1) EFT and Surge Transient Waveform Equations

1.0

5 / 50 ns, EFT waveform:

0.8 - t/τ1 - t/τ2
V(t) = A·VP·(1- e )·e
0.6 τ1 = 3.5 ns
V(t) / VP

τ2 = 55.6 ns
0.4
A = 1.27
0.2

0.0
0 20 40 60 80 100
Time – ns

1.0

1.2 / 50 μs, Surge open-circuit waveform :

0.8 - t/τ1 - t/τ2
V(t) = A·VP·(1- e )·e
0.6 τ1 = 0.4074 μs
V(t) / VP

τ2 = 68.22 μs
0.4
A = 1.037
0.2

0.0
0 20 40 60 80 100
Time – μs

1.0

8 / 20 μs, Surge short-circuit waveform:

0.8 - t/τ
k
I(t) = A·IP·t ·e
-k
0.6
A = 0.1405 (μs)
I(t) / IP

0.4
k = 2.93
τ = 3.977 μs
0.2

0.0
0 10 20 30 40 50
Time – μs

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2) Simulation Models for EFT and Surge Generators
Because of the significantly higher energy content of an EFT transient versus an ESD transient, I have focused
on the simulation of the EFT generator. Although slightly modified from the standard (I added a 2nd switch as
charge switch, Sc) the output transient is in alignment with the EFT standard waveform.
The charge switch, Sc, and
Vsc Vsd discharge switch, Sd, operate
alternately. When Sc is closed,
+ + Sd is open, and the 6 μF
capacitor (C1) is charged by the
+

+
-

-
Sc 0 Sd 0 C2 1u
high-voltage dc-supply (V1).



R2 50
Vout When Sc is open, Sd is closed,
and C1 discharges via the R-C
output network. The 12 mΩ R1
R1 12m

R3 50k
serves as pulse-shaping resistor.
C1 6u

V1 4k
The 50 Ω R2 provides
impedance matching with the
coaxial output, and the 1uF C2
blocks dc voltages. R3 is the
actual load impedance, which is
EFT Generator made 50 Ω during generator
calibration only.

T 1.98k T 3.96k

Vout Vout

0.00 0.00
1.00 1.00

Vsc Vsc

-1.00 -1.00
1.00 1.00

Vsd Vsd

-1.00 -1.00
0.00 500.00u 1.00m 0.00 500.00u 1.00m
Time (s) Time (s)

Output transients and switching cycles of Sc and Sd for R3 = 50 Ω (left) and R3 = 50 kΩ (right)

EFT waveform for R3 = 50 Ω (left) and R3 = 50 kΩ (right). The output peak voltage halfs when terminated with
50 ohms. The time between the red and blue cursor lines at half the peak output voltage = 49 ns (left) and 50 ns
(right). The IEC 61000-4-4 standard allows for a variation of 50 ns ± 30 %.

2
The IEC 61000-4-5 specified surge generator is a combination waveform generator (CWG) because under
open-circuit conditions it provides an output voltage transient with 1.2 μs front time and a time-to-half-value (0.5
VPK) of 50 μs, while under short-circuit conditions the output provides an output current transient with 8 μs front
time and a time-to-half-value (0.5 IPK) of 20 μs.
The following graphs show the CWG configurations and their corresponding output transient waveforms.

VG1 VG1
+ +

SW1 0 SW1 0

+
+

-
-

Lr 10.4u


Lr 10.4u


Rc 1k Rm 940m Rc 1k Rm 940m
Vout
+
V2 1.07k Cc 6.04u Rs1 25.1 Rs2 19.8 V2 1.07k Cc 6.04u Rs1 25.1 Rs2 19.8 A Iout

CWG with RL = ∞ for measuring the 1.2/50 μs open- CWG with RL = 0 Ω for measuring the 8/20 μs short-circuit
circuit output voltage transient output current transient

1.2/50 μs open-circuit output voltage transient 8/20 μs short-circuit output current transient
The cursor lines of the 1.2/50 μs open-circuit output voltage transient show a time-to-half-value of 49.5 μs and
thus sit perfectly in the middle of the 50 μs ± 20 % specified in the IEC 61000-4-5 standard.
The cursor lines of the 8/20 μs short-circuit output current transient show a time-to-half-value of 19.5 μs and
thus sit perfectly in the middle of the 20 μs ± 20 % specified in the IEC 61000-4-5 standard. Also, the negative
overshoot of - 27.6 % is well within the standard-specified maximum of - 30 %.