Computer System

Organization
Course Code: INITCO7
Semester: 3
Section: ITNS, 1
 UNIT 2:
MICROPROGRAMMED
CONTROL
Control Memory
• The function of the control unit in a digital computer is to initiate
sequences of microoperations.
• When the control signals are generated by hardware using
conventional logic design techniques, the control unit is said to be
hardwired.
• Microprogramming is a second alternative for designing the control
unit of a digital computer.
• The principle of microprogramming is an elegant and systematic
method for controlling the microoperation sequences in a digital
computer.
• The control function that specifies a microoperation is a binary
variable.
• When it is in one binary state, the corresponding microoperation is
executed.
• A control variable in the opposite binary state does not change the
state of the registers in the system.
• The active state of a control variable may be either the 1 state or the 0
state, depending on the application.
• The control variables at any given time can be represented by a string
of 1's and 0's called a control word.
• Control words can be programmed to perform various operations on
the components of the system.
• A control unit whose binary control variables are stored in memory is
called a microprogrammed control unit.
• Each word in control memory contains within it a microinstruction .
• The microinstruction specifies one or more microoperations for the
system.
• A sequence of microinstructions constitutes a microprogram.
• The control memory address register specifies the address o f the
microinstruction, and the control data register holds the
microinstruction read from memory.
• The microinstruction contains a control word that specifies one or
more microoperations for the data processor.
• The next address generator is sometimes called a microprogram
sequencer, as it determines the address sequence that is read from
control memory.
• The address of the next microinstruction can be specified in several
ways, depending on the sequencer inputs.
• The control data register holds the present microinstruction while the
next address is computed and read from memory.
• The data register is sometimes called a pipeline register.
• The main advantage of the microprogrammed control is the fact that
once the hardware configuration is established, there should be no
need for further hardware or wiring changes.
• If we want to establish a different control sequence for the system, all
we need to do is specify a different set of microinstructions for control
memory.
 Address Sequencing
• Microinstructions are stored in control memory in groups, with each group
specifying a routine.
• Each computer instruction has its own microprogram routine in control
memory to generate the microoperations that execute the instruction.
• An initial address is loaded into the control address register when power is
turned on in the computer.
• This address is usually the address of the first microinstruction that activates
the instruction fetch routine.
• The fetch routine may be sequenced by incrementing the control address
register through the rest of its microinstructions.
• At the end of the fetch routine, the instruction is in the instruction register of
the computer.
• The address sequencing capabilities required in a control memory are:
1. Incrementing of the control address register.
2. Unconditional branch or conditional branch, depending on
status bit conditions.
3. A mapping process from the bits of the instruction to an
address for control memory.
4. A facility for subroutine call and return.
Conditional Branching
• The status conditions are special bits in the system that provide
parameter information such as the carry-out of an adder, the sign bit of
a number, the mode bits of an instruction, and input or output status
conditions.
• The branch logic hardware may be implemented in a variety of ways.
The simplest way is to test the specified condition and branch to the
indicated address if the condition is met; otherwise, the address
register is incremented.
Mapping of Instructions
Subroutines
• Subroutines are programs that are used by other routines to accomplish
a particular task.
• A subroutine can be called from any point within the main body of the
microprogram.
• Frequently, many microprograms contain identical sections of code.
• Microinstructions can be saved by employing subroutines that use
common sections of microcode.
• Microprograms that use subroutines must have a provision for storing
the return address during a subroutine call and restoring the address
during a subroutine return.
Example:
• Each line of the assembly language microprogram defines a symbolic
microinstruction.
• Each symbolic microinstruction is divided into five fields: label,
microoperations, CD, BR, and AD.
• The fields specify the following information.
1. The label field may be empty or it may specify a symbolic
address. A label is terminated with a colon (:).
2. The microoperations field consists of one, two, or three
symbols, separated by commas. There may be no more than one
symbol from each F field. The NOP symbol is used when the
microinstruction has no microoperations. This will be translated
by the assembler to nine zeros.
3. The CD field has one of the letters U, I, S, or Z.
4. The BR field contains one of the four symbols defined.
5. The A D field specifies a value for the address field of the
microinstruction in one of three possible ways:
a. With a symbolic address, which must also appear as a label.
b. With the symbol NEXT to designate the next address in
sequence.
c. When the BR field contains a RET or MAP symbol, the AD
field is left empty and is converted to seven zeros by the
assembler.
Fetch Instruction
Design of Control Unit
• The bits of the microinstruction are usually divided into fields, with
each field defining a distinct, separate function.
• Each field requires a decoder to produce the corresponding control
signals.
• This method reduces the size of the microinstruction bits but requires
additional hardware external to the control memory.
• The nine bits of the microoperation field are divided into three
subfields of three bits each.
• The control memory output of each subfield must be decoded to
provide the distinct microoperations.
Central Processing Unit
• Major components of CPU
General Register Organization
 Control Word
• For example, to perform the operation R 1 <--R2 + R3 the control must
provide binary selection variables to the following selector inputs:
1. MUX A selector (SELA): to place the content of R2 into bus A .
2 . MUX B selector (SELB): to place the content o f R 3 into bus B .
3 . ALU operation selector (OPR): to provide the arithmetic addition
A+B.
4. Decoder destination selector (SELD): t o transfer the content of
the output bus into R 1 .
• There are 14 binary selection inputs in the unit, and their combined
value specifies a control word.
• The 14-bit control word consists of four fields.
• Three fields contain three bits each, and one field has five bits.
• The three bits of SELA select a source register for the A input of the
ALU.
• The three bits of SELB select a register for the B input of the ALU.
• The three bits of SELD select a destination register using the decoder
and its seven load outputs.
• The five bits of OPR select one of the operations in the ALU.
• The 14-bit control word when applied to the selection inputs specify a
particular
• microoperation.
Encoding of Register Selection Fields
Encoding of ALU operations
Examples of Microoperations for CPU
 Stack Organization
• A useful feature that is included in the CPU of most computers is a
stack or last-in, first-out (UFO) list.
• A stack is a storage device that stores information in such a manner
that the item stored last is the first item retrieved.
• The stack in digital computers is essentially a memory unit with an
address register that can count only (after an initial value is loaded into
it).
• The register that holds the address for the stack is called a stack
pointer (SP) because its value always points at the top item in the
stack.
• The two operations of a stack are the insertion and deletion of items.
Register
Stack
PUSH

POP
Memory Stack
Reverse Polish Notation
• A*B+C*D
Evaluation of mathematic expressions
Instruction Formats
• The most common fields found in instruction formats are:
1. An operation code field that specifies the operation to be
performed.
2. An address field that designates a memory address or a
processor register.
3. A mode field that specifies the way the operand or the effective
address is determined.
• The number of address fields in the instruction format of a computer
depends on the internal organization of its registers.
• Most computers fall into one of three types of CPU organizations:
1. Single accumulator organization.
2. General register organization.
3. Stack organization.
• Example of an accumulator-type organization: ADD X
• An example of a general register type of organization: ADD R1, R2,
R3
• An example of stack organization: PUSH X
ADD
Example:

• Three Address Instructions

• Two Address Instructions
• Single Address Instructions
• Zero Address Instructions
• RISC Instructions
Addressing Modes
• The operation field of an instruction specifies the operation to be performed.
• This operation must be executed on some data stored in computer registers or
memory words.
• The way the operands are chosen during program execution is dependent on
the addressing mode of the instruction.
• The addressing mode specifies a rule for interpreting or modifying the address
field of the instruction before the operand is actually referenced.
• Computers use addressing mode techniques for the purpose of accommodating
one or both of the following provisions:
1. To give programming versatility to the user by providing such facilities
as pointers to memory, counters for loop control, indexing of data, and
program relocation.
2. To reduce the number of bits in the addressing field of the instruction.
Implied Mode:
• In this mode the operands are specified implicitly in the definition of
the instruction.
• For example, the instruction "complement accumulator“ is an implied-
mode instruction because the operand in the accumulator register is
implied in the definition of the instruction.
• In fact, all register reference instructions that use an accumulator are
implied-mode instructions.
• Zero-address instructions in a stack-organized computer are implied-
mode instructions since the operands are implied to be on top of the
stack.
Immediate Mode:
• In this mode the operand is specified in the instruction itself.
• In other words, an immediate-mode instruction has an operand field
rather than an address field.
• The operand field contains the actual operand to be used in
conjunction with the operation specified in the instruction.
• Immediate- mode instructions are useful for initializing registers to a
constant value.
• It was mentioned previously that the address field of an instruction
may specify either a memory word or a processor register.
• When the address field specifies a processor register, the instruction is
said to be in the register mode.
Register Mode:
• In this mode the operands are in registers that reside within the CPU.
• The particular register is selected from a register field in the
instruction.
• A k-bit field can specify any one of 2 (raise to the power of k)
registers.
 Register Indirect Mode:
• In this mode the instruction specifies a register in the CPU whose
contents give the address of the operand in memory.
• In other words, the selected register contains the address of the operand
rather than the operand itself.
• Before using a register indirect mode instruction, the programmer must
ensure that the memory address of the operand is placed in the processor
register with a previous instruction.
• A reference to the register is then equivalent to specifying a memory
address.
• The advantage of a register indirect mode instruction is that the address
field of the instruction uses fewer bits to select a register than would have
been required to specify a memory address directly.
Autoincrement or Autodecrement
Mode:
• This is similar to the register indirect mode except that the register is
incremented or decremented after (or before) its value is used to
access memory.
• When the address stored in the register refers to a table of data in
memory, it is necessary to increment or decrement the register after
every access to the table.
• This can be achieved by using the increment or decrement instruction.
• However, because it is such a common requirement, some computers
incorporate a special mode that automatically increments or
decrements the content of the register after data access.
Direct Address Mode:
• In this mode the effective address is equal to the address part of the
instruction.
• The operand resides in memory and its address is given directly by the
address field of the instruction.
• In a branch-type instruction the address field specifies the actual
branch address.
Indirect Address Mode:
• In this mode the address field of the instruction gives the address
where the effective address is stored in memory.
• Control fetches the instruction from memory and uses its address part
to access memory again to read the effective address.
• A few addressing modes require that the address field of the
instruction be added to the content of a specific register in the CPU.
• The effective address in these modes is obtained from the following
computation:
effective address = address part of instruction + content of CPU
register
Relative Address Mode:
• In this mode the content of the program counter is added to the address
part of the instruction in order to obtain the effective address.
• The address part of the instruction is usually a signed number (in 2’ s
complement representation) which can be either positive or negative.
• When this number is added to the content of the program counter, the
result produces an effective address whose position in memory is
relative to the address of the next instruction.
 Indexed Addressing Mode:
• In this mode the content of an index register is added to the address part of the
instruction to obtain the effective address.
• The index register is a special CPU register that contains an index value.
• The address field of the instruction defines the beginning address of a data
array in memory.
• Each operand in the array is stored in memory relative to the beginning
address.
• The distance between the beginning address and the address of the operand is
the index value stored in the index register.
• Any operand in the array can be accessed with the same instruction provided
that the index register contains the correct index value.
• The index register can be incremented to facilitate access to consecutive
operands.
Base Register Addressing Mode:
• In this mode the content of a base register is added to the address part
of the instruction to obtain the effective address.
• This is similar to the indexed addressing mode except that the register
is now called a base register instead of an index register.
• The difference between the two modes is in the way they are used
rather than in the way that they are computed.
• An index register is assumed to hold an index number that is relative
to the address part of the instruction.
• A base register is assumed to hold a base address and the address field
of the instruction gives a displacement relative to this base address.