0% found this document useful (0 votes)
519 views9 pages

Calculation of VIL - .

This document provides instructions for simulating a simple inverter design in Tanner Tools to calculate various voltage parameters. The steps include adding a capacitor to the output, setting up the simulation with library paths and parameters, adding SPICE commands to the netlist, running the simulation, and measuring VIL, VIH, VOH, VOL, and noise margins from the results. Waveforms can also be viewed in W-Edit to verify the output.

Uploaded by

bipin1025
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
519 views9 pages

Calculation of VIL - .

This document provides instructions for simulating a simple inverter design in Tanner Tools to calculate various voltage parameters. The steps include adding a capacitor to the output, setting up the simulation with library paths and parameters, adding SPICE commands to the netlist, running the simulation, and measuring VIL, VIH, VOH, VOL, and noise margins from the results. Waveforms can also be viewed in W-Edit to verify the output.

Uploaded by

bipin1025
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 9

 

Calculation of VIL, VIH, VOH, VOL, NoiseMarginLow (VIL-


VOL), & NoiseMarginHigh (VOH-VIH) of Simple Inverter

Add a Capacitor across the output end of the design by selecting it from the Devices Library.

Follow the Schematic Design(simple_inverter) process explained in the inverter_generic pdf.

For simulation of design go to Setup-> Spice Simulation

 
Select ‘General’ option:

Set Accuracy and Performance parameter “Accurate”.

Set Enable Waveform Voltage Probing parameter “True”. 

Set Enable Waveform Current Probing parameter “True”. 

Set Enable Waveform Charge Probing parameter “True”. 

Add Library path parameter in the ‘General’ option:

C:\Documents and Settings\admin\My Documents\Tanner EDA\Tanner Tools


v15.0\Process\Generic_250nm\Generic_250nm_Tech\Generic_250nm.lib TT

Add ‘TT’ at the end of library path “it is compulsory”. 

Select Parameters option


Click on at the corner of this window to add the parameter.

Vpwr = 3

Wn = 1.5u

Wp = 1.5u

Add all three parameters mentioned above one by one. Click ‘ok’

 
Select Additional SPICE Commands option & write the spice code in the box as follows:

Vdd Vdd GND Vpwr


V1 In Gnd dc Vpwr BIT ({0 1} pw=10n lt=10n ht=10n on=Vpwr off=0)

.SUBCKT Inv In Out Gnd Vdd


M_M1 Out In Gnd Gnd T_NMOS W=Wn L=250n
+M=1 AS='Wn*250n*3' AD='Wn*250n*3'
+PS='4*(Wn+250n)' PD='4*(Wn+250n)'
M_M2 Vdd In Out Vdd T_PMOS W=Wp L=250n
+M=3 AS='Wp*250n*3' AD='Wp*250n*3'
+PS='4*(Wp+250n)' PD='4*(Wp+250n)'
.ENDS

.PARAM CLoad1 = 50fF


.PARAM CLoad2 = 1pF

X1 In Out1 Gnd Vdd Inv


C1 Out1 Gnd C=CLoad1
X2 In Out2 Gnd Vdd Inv
C2 Out2 Gnd C=CLoad2
********* Simulation Settings - Analysis section *********
.DC LIN V1 0.0 'Vpwr' 'Vpwr/100'
.PRINT DC V(In) V(Out1)

.MEASURE DC VIL FIND v(In) WHEN 'DDX(V(Out1),V(In))'=-1


.MEASURE DC VIH FIND v(In) WHEN 'DDX(V(Out1),V(In))'=-1 CROSS=LAST

.MEASURE DC VOH FIND v(Out1) AT=0


.MEASURE DC VOL FIND v(Out1) AT='Vpwr'

.MEASURE DC NoiseMarginLow PARAM='VIL-VOL'


.MEASURE DC NoiseMarginHigh PARAM='VOH-VIH'

 
Select SPICE Options (analysis) then define time parameter

Click OK, then Select Tools-> Start Simulation

It will automatically invoke T-Spice software

Right click on finished simulation report and click on ‘Open Netlist’ to get Spice Netlist.  

 
 

Remove below given lines from the spice netlist in between .SUBCKT & ENDS

M_M1 Out In Gnd Gnd T_NMOS W=Wn L=250n

+M=1 AS='Wn*250n*3' AD='Wn*250n*3'

+PS='4*(Wn+250n)' PD='4*(Wn+250n)'

M_M2 Vdd In Out Vdd T_PMOS W=Wp L=250n

+M=3 AS='Wp*250n*3' AD='Wp*250n*3'

+PS='4*(Wp+250n)' PD='4*(Wp+250n)'

Paste simple inverter spice generated after simulation of inverter schematic in between
.SUBCKT & ENDS.

MNMOS_2_5v_1 Out In Gnd 0 NMOS25 W=1.5u L=250n AS=975f PS=4.3u AD=975f


PD=4.3u $ $x=4293 $y=3900 $w=414 $h=600

MPMOS_2_5v_1 Out In Vdd Vdd PMOS25 W=3u L=250n AS=1.95p PS=7.3u AD=1.95p
PD=7.3u $ $x=4293 $y=5000 $w=414 $h=600

CCapacitor_1 Out Gnd 1p $ $x=5600 $y=4000 $w=400 $h=600


Remove these below given lines also from the netlist because they create Voltage
source/inductor loop.

VVoltageSource_1 Vdd Gnd DC 5 $ $x=800 $y=2200 $w=400 $h=600

VVoltageSource_2 In Gnd PULSE (0 5 0 5n 5n 95n 200n) $ $x=3200 $y=3900 $w=400 $h=600

Select simulation-> Run Simulation

Simulation Status shows that the “Measurement result summary” in the above window, which
contains the information about VIL, VIH, VOH, VOL, NoiseMarginLow & NoiseMarginHigh
of an inverter.
 

Waveform can be checked Using W-Edit; It will automatically invoked at the time of running T-
spice.

Waveform:

Click on Chart & select Expand Traces

Final input and output waveform

 
 

THANK YOU
 
                              PRAKASH KUMAR DWIJ
Application Engineer (E.D.A)
Email:[email protected]
 

TRIDENT TECHLABS PVT LTD


WHITE HOUSE, 1/18-20,RANI JHANSI ROAD
NEW DELHI-110055
www.tridenttechlabs.com 
 

You might also like