Electronics with Discrete Components

Solutions to Exercises and Problems

Enrique J. Galvez
Department of Physics and Astronomy
Colgate University

July 2012
ii
Contents

1 The Basics 3
1.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Introduction to Digital Electronics 15

2.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

3 Combinational Logic 27
3.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

4 Advanced Combinational Devices 47

4.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
4.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

5 Sequential Logic 59
5.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

6 AC Signals 89
6.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
6.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

7 Filters and the Frequency Domain 103

7.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
7.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

8 Diodes 115
8.1 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

iii
iv CONTENTS

9 Transistors 129
9.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
9.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

10 Operational Amplifiers 141

10.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
10.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

11 Connecting Digital to Analog and to the World 159

11.1 Exercises . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
11.2 Problems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
CONTENTS 1

Preface

The present document gives the solutions to all the problems and exercises in the
textbook Electronics with Discrete Components, authored by myself. As instructor,
you are entitled to these solutions. I have tried to give the rationale behind the solu-
tions. I believe that students should work hard and struggle to find the solution to a
problem, but at some point see what they did wrong, if that is the case. So instruc-
tors are encouraged to share individual solutions to problems with their students. It
would not be wise to post the entire document, or give students entire chapters, as
these can easily find their way to the web, rendering these solutions unsuitable as
homework assignments.
Many of the solutions are not unique. This is because some involve creativity in
the design, where there is no clear-cut answer; and many electronic conditions are
inequalities rather than equalities. Therefore, the instructor should use judgment
when grading student work, as students’ solutions may be correct but different than
mine.
Finally, textbook solutions are a good way to learn out of the textbook, but the
real learning is done in the electronics workbench, wiring circuits and trying them
out. Electronics has many details, and many components (diodes, transistors) whose
characteristics (IV curves, for example) are not the textbook’s. So the paper solution
may not be the solution obtained by wiring with real components. Students should
be encouraged to try the circuits for themselves, because as they do, they will find a
way to play, and there is no better way to learn than that.
E.J. “Kiko” Galvez
2 CONTENTS
Chapter 1

The Basics

1.1 Exercises
Exercise 1.1 Calculate the equivalent resistance of the network in Figure 1.9 (in the
textbook, shown below). All resistors have a resistance R.

Solution: The middle branch is a straight wire, so it nullifies the two resistors
in series that it shorts. We are then left with two branches in parallel: one with
resistance R and the other with resistance 2R. The equivalent resistance is then
Req = (1/R + 1/2R)−1 = 2R/3.

Exercise 1.2 Use the concepts of resistors in series and parallel with a voltage di-
vider to calculate the voltage across each resistor in the circuit of Figure 1.14 (in the
textbook, shown next). Each resistor has a value of 1 kΩ.

Soution: There are two junctions in the circuit. The equivalent resistance between
them is Rjunc = (1/R + 1/2R)−1 = 2R/3. Using the voltage divider Eq., the voltage
between the two junctions is Vjunc = [2R/3] · V0 /[R + 2R/3] = 2V0 /5 = 4 V. One of

3
4 CHAPTER 1. THE BASICS

the branches between the two junctions has two resistors in series. Since they have
the same resistance value, the voltage across each is 2 V. The resistors between the
junctions are, as a whole, in series with a resistance R. The voltage across the latter
is 6 V, because the sum of voltages in series has to be 10 V.

Exercise 1.3 A capacitor is charged to 200 V.

1. What capacitance does it have if it stores a charge of 10 mC?

2. If we connect a 1 kΩ resistor across the capacitor, what is the maximum current

that will flow as the capacitor discharges?

Solution: (a) The capacitance is C = q/VC = 50µF. (b) The current decays expo-
nentially as the capacitor discharges, so maximum current occurs when the capacitor
has its maximum voltage, or VC /R = 0.2 A.

1.2 Problems
1. Two capacitors with capacitances 3 µF and 2 µF are initially discharged. They
are connected in series, and then the two ends of the combination are connected
to a 10-V battery, as shown in Figure 1.24 (in the textbook, shown next). The
negative end of the battery is at zero potential.

(a) How much charge does the battery deliver? You can get started by figuring
out the relationship between the charges in each capacitor and the voltage
across each of them.
Solution: Because the two capacitors are in series, they have the same
charge Q. The source delivers Q. The voltages across each capacitor add
up to the source voltage V0 = 10 V. Therefore Q/Ctop + Q/Cbot = V0 , or
Q = 12 µC.
(b) If we connect a single capacitor to the same battery, what would be the
capacitance of the capacitor so that it draws the same charge from the
battery?
1.2. PROBLEMS 5

Solution: C = Q/V0 = 12µC/10V = 1.2 µF, or using equivalent capaci-

tance: Ceq = (1/Ctop + 1/Cbot )−1 = 1.2 µF.
(c) Find the charges on each capacitor.
Solution: The charge on each capacitor is Q = 12 µC.
(d) Find the voltage across each capacitor.
Solution: For the top capacitor: Vtop = Q/Ctop = 4 V; and for the bottom
capacitor, Vbot = Q/Cbot = 6 V.
(e) If point B is at zero potential, what is the potential at point A between
the two capacitors?
Solution: VA = VB + 6 V = 6 V.

2. A battery with potential V0 is connected to a capacitor C. We label the charge

in the top plate as q1 and the charge in the bottom plate as q2 . Which statement
is correct?
(a) q1 = q2 = CV0
(b) q1 = −q2 = CV0
(c) q1 + q2 = CV0
(d) q1 = −q2 = 2CV0
(e) q1 = q2 = CV0 /2
Solution: Answer is (b), because the capacitor’s top plate has a charge Q, and
the bottom plate has a charge −Q. Their absolute value is equal to CV0 .
3. Suppose that we have two capacitors with capacitances 0.1 µF and 0.2 µF. We
connect them in parallel and apply a voltage of 10 V to their ends.
(a) What is the charge on each capacitor?
Solution: Because the capacitors are in parallel, the voltage across them
is the same. If C1 = 0.1 µF and C2 = 0.2 µF, then q1 = C1 V0 = 1 µC and
q2 = C2 V0 = 2 µC.
(b) What is the total amount of charge that the source has to supply to charge
the two capacitors?
Solution: The source has to supply charge to both capacitors: q = q1 +q2 =
3 µC.
(c) If we replaced both capacitors with one so that it draws the same amount
of charge from the supply, what capacitance would it have?
Solution: Ceq = (q1 + q2 )/V0 = 0.3µF.
6 CHAPTER 1. THE BASICS

(d) Can you generalize the previous situation for finding the equivalent capac-
itance of any two capacitors connected in parallel?
Solution: Ceq = C1 + C2 .

4. In the circuit of Figure 1.25 (in the textbook, shown below), C1 = 0.2 µF and
C2 = 0.15 µF. When a voltage of 10 V is applied to the system of capacitors,
we find that the charge of capacitor 1 is 1 µC.

(a) Find the value of C3 , and the charge on it.

Solution: The voltage across capacitor 1 is V1 = q1 /C1 = 5 V, so the
voltage across capacitors 2 and 3 must also be 5 V (to add to the supply
voltage). The charge on capacitor 1 must be split onto capacitors 2 and 3
because they are in parallel (i.e., the wire that connects the bottom plate
of 1 to the top plates of 2 and 3 is initially neutral, so q2 +q3 −q1 = 0). The
charge on capacitor 2 is q2 = (5V)(0.15µF) = 0.75 µC. Thus q3 = 0.25 µC.
The capacitance of 3 is then C3 = (0.25µC)/(5V) = 0.05 µF.

(b) What is the equivalent capacitance of the arrangement?

Solution: The capacitance of 2 and 3 in parallel is the sum of the two:
C23 = C2 + C3 = 0.2 µF. They are in series with capacitor 1, so Ceq =
(1/C1 + 1/C23 )−1 = 0.1 µF. Check: The source must deliver the charge
Q = Ceq V0 = 1 µC, which is also equal to the charge on capacitor 1.

5. We apply 1.2 V to the 0.5 µF capacitor of Figure 1.26 (in the textbook, shown
next). We then disconnect the capacitor from the power supply. Subsequently,
we connect an uncharged 1-µF capacitor in parallel with the other capacitor.
Find the charge on the 1-µF capacitor. (Note that the voltage across it is not
1.2 V.)
1.2. PROBLEMS 7

Solution: When we connect the supply to the first capacitor, it gets a charge
q1 = (0.5µF)(1.2V) = 0.6 µC. We then disconnect it from the supply and
connect it to the second capacitor. The charges rearrange so that the two
capacitors have the same voltage across them. We can also think that the two
capacitors now act as a single capacitor of capacitance C ′ = C1 + C2 = 1.5 µF.
The charge on it is the initial one, so the new voltage across the capacitors is
V ′ = q1 /C ′ = 0.4 V. The charges on each capacitor are then q1′ = C1 V ′ = 0.2 µC
and q2 = C2 V ′ = 0.4 µC. Check: The two charges indeed add to the original
charge.

6. The potential of point A in Figure 1.27 (in the textbook, shown below) is 0 V.
Find the potential of point B.

Solution: We have a single loop. The sum of voltages must add to zero. The
total supply voltage is 20V − 4V = 16 V. The voltage drops across the resistors,
their value times the current, must be equal to this voltage. Since the resistors
are in series in the loop, then their combined resistance is 8 kΩ. The current is
then I = (16V)/(8kΩ) = 2 mA. The potential of B is the potential on A plus the
drops on the 5-kΩ and 2-kΩ resistors, (5kΩ)(2mA) = 10 V and (2kΩ)(2mA) = 4
V, respectively. Therefore VB = 14 V.

7. The colors of the bands of the resistors of Figure 1.4 (in the textbook, shown
next) are: (a) Orange, orange, red, white; (b) Brown, black, red, gold; (c)
Brown, red, blue, orange, green.
8 CHAPTER 1. THE BASICS

(a) Determine their value and tolerance.

Solution: (a) 33 × 102 Ω = 3.3kΩ, 20%; (b) 10 × 102 Ω = 1kΩ, 5%; and (c)
126 × 103 Ω = 126kΩ, 0.5%.
(b) A measurement of the actual resistance of (b) gave 992 Ω. Should we
return it as defective? Explain.
Solution: No, because the difference between the expected and measured
is 0.8%, which is within the 5% tolerance of the resistor.

8. Calculate the equivalent resistance of the network in Figure 1.28 (in the text-
book, shown below).

Solution: In the upper-right side of the circuit is a wire oriented diagonally.

Notice that it meets with another wire to short a resistor. The potential of that
wire is the same. Let us call this potential, VC . Between the wire at potential
A and the one at C there is only one resistor. Between C and B there are three
resistors in parallel. Therefore we can reduce the arrangement as two resistors
in series: R between A and C, and R/3 between C and B. The equivalent
resistance between A and B is 4R/3.

9. If point A is at zero potential in Figure 1.29 Figure 1.28 (in the textbook, shown
next), what is the potential at points B and C?
1.2. PROBLEMS 9

Solution: We can calculate the current flowing through the loop by adding the
voltage sources, 16 V, and dividing that by the equivalent resistance of three
resistors in series, or 8 kΩ. We get I = 2 mA. The potential of the positive
side of the battery above A is 8 V. The potential of point B is one resistor drop
below: VB = 8V − (1kΩ)(2mA) = 6 V. Point C is another resistor drop below
B: VC = VB − (5kΩ)(2mA) = −4 V. Check: The potential of the negative side
of the battery below A is −8 V. The potential of point C is one resistor drop
above this: VC = −8V + (2kΩ)(2mA) = −4 V.

10. Many of the circuits that you will use in the lab will be powered by +12 V
power supplies. What is the smallest value 1/8-W resistor that we can apply
the full voltage of the power supply without burning it?

Solution: Given are: V0 = 12 V, and Pmax = 0.125 W. We know that P = V 2 /R,

so Rmin = V 2 /Pmax = 1152Ω.

11. Be aware of the dangers of electricity. Human skin can exhibit large variations
in electrical resistance. Although dry skin may have a resistance of 100 kΩ, wet
and tender skin may have resistances as low as 1 kΩ. If electrocution is caused
by currents above 50 mA, what applied voltages would cause electrocution for
(a) dry and (b) wet skin?

Solution: Lethal current is Ileth = 50 mA. (a) For dry skin Vleth = (50mA)(100kΩ) =
5000 V. (b) For wet skin Vleth = (50mA)(1kΩ) = 50 V.

12. Using only the concepts of equivalent resistance and voltage divider, calculate
the voltage between points A and B of Figure 1.30 (in the textbook, shown
below). Hint: First find the voltage drop across the 8 k resistor, but do not
ignore the resistor ladder to the right of it.
10 CHAPTER 1. THE BASICS

Solution: The two resistors of branch CAB are in parallel with the 4 kΩ resistor,
so the resistance between C and B is RCB = 2kΩ (see the figure above). The
resistance between D and B is the resistance in the branch DCB in parallel
with the 8 kΩ resistor. The equivalent resistance between D and B is then
RDB = 4kΩ (see the figure above). Applying the voltage divider argument in the
reduced one-loop circuit, we get VDB = (4/6)V0 = 6.67 V. Applying the voltage
divider argument between D and B, we get VCB = (2/8)VDB = (1/6)V0 = 1.67
V. Finally, Applying the voltage divider argument between C and B, we get
VAB = (3/4)VCB = (1/8)V0 = 1.25 V.
13. Find the value of R in the circuit of Figure 1.31 (in the textbook, shown below)
if points A and B are at the same potential.

Solution: The ratio of the resistance on the two branches must be the same:
1kΩ 2kΩ
=
5kΩ R
1.2. PROBLEMS 11

or R = 10 kΩ.

14. Two resistors are connected in series to a 20-V battery. The ratio of their
resistances is 1:4.

(a) Find the voltage across the larger resistor.

Solution: If one resistor has a resistance R and the other one 4R, then the
voltage across the larger one is V = (4R/5R)(20V) = 16 V.
(b) If the total current flowing through the resistors is 10 mA, what is the
value of the smaller resistor?
Solution: The voltage across the smaller resistor (of resistance R) is 4 V.
Then R = (4V)/(10mA) = 400 Ω.

15. Find the current flowing through each resistor, and the voltage drop across the
resistor in the middle branch of the circuit of Figure 1.32 (in the textbook,
shown on the left below).

Solution: Let us assume that the currents are given in mA, resistances in kΩ
and voltages in V. The equations for the left-hand and right-hand loops are:
10−I1 −I3 = 0 and 5−I3 −2I2 = 0. The equation for the currents is I1 = I2 +I3 .
Solving the system of equations, we get I1 = 7 mA, I2 = 4 mA and I3 = 3 mA.
The voltage drops across the middle resistor is (1kΩ)(3mA) = 3 V.

16. Find the current flowing through the 4-kΩ resistor in Figure 1.33 (in the text-
book, shown below).
12 CHAPTER 1. THE BASICS

Solution: The 6-V supply is straight across the 2-kΩ resistor, so the voltage
across the 4-kΩ resistor is 2 V. The current is then (2V)/(4kΩ) = 0.5 mA.
17. Find the value of the resistors R1 and R2 in Figure 1.34 (in the textbook, shown
below with solution).

Solution: We can calculate the voltage across the right branch (of total resis-
tance 2.5 kΩ): (4mA)(2.5kΩ) = 10 V. Next we focus on the two resistors in
parallel in the left-most vertical branch. The resistors have the same resistance,
so if the current on the left resistor is 1 mA, then the right resistor carries the
same current. The voltage drop across them is 2 V. Up to this point we know
all the drops on the left loop, so we can find the voltage across R2 : 18 V. Its
value is then R1 = 9 kΩ. From the sum of currents at the joints we get that
I2 = 2 mA. The voltage across R2 is 20 V, so R2 = 10 kΩ.
18. The capacitor in the circuit of Figure 1.36 (in the textbook, shown below) is
discharged.

(a) Switch 1 is closed at t = 0. At what time will the voltage across the
capacitor reach 6 V?
Solution: The equation for charging the capacitor is: VC = (9V)(1 −
e−t/RC ), where RC = (8kΩ)(1000µF) = 8 s. We solve for t when VC = 6
V: t = −(8s) ln(1 − 6/9) = 8.8 s.
1.2. PROBLEMS 13

(b) Switch 1 is opened when the voltage across the capacitor reaches 6 V.
What was the current flowing through the circuit before the switch was
opened?
Solution: The drop across each resistor is 1.5 V, so the current flowing
through them is I = (1.5V)/(4kΩ) = 0.375 mA.
(c) We close switch 2. At what time after closing the switch is the voltage
across the capacitor equal to 3 V?
Solution: The time constant for the discharge of the capacitor is 4 s. The
time is: t = −(4s) ln(3/6) = 2.8 s.

19. At t = 0, the switch of Figure 1.36 (in the textbook, shown below) is closed.
At t = 80 ms, the voltage across the capacitor is 5 V. Calculate V0 .

Solution: The time constant for discharging the capacitor is

τ = RC = (2kΩ + 2kΩ)(10µF) = 40ms

The discharge equation is Vt = V0 e−t/τ . The condition of the problem is Vt = 5

V at t = 80 ms, so 5V = V0 e−2 . Solving for V0 we get V0 = 36.9 V.

20. In Figure 1.37 (in the textbook, shown below), the capacitors are initially
charged. As soon as the switch is closed the current is 0.5 mA. After 14 ms the
current has dropped to 0.25 mA. Find C.
14 CHAPTER 1. THE BASICS

Solution: As soon as the switch is closed, the voltage across the capacitors,
V0 , is applied to the resistors, so the current flowing through them at that
initial time is I = V0 /Rtotal . The problem gives I0 = 0.5 mA at t = 0, and
Rtotal = (3kΩ + 1kΩ) = 4kΩ. Therefore, V0 = I0 Rtotal = 2 V. At t = 14
ms the current is It = 0.25 mA. Therefore, the voltage across the capacitors
at that time is Vt = It Rtotal = 1 V. So from the discharge of the capacitor
we have Vt = V0 e−t/τ . Solving for τ we get τ = −t/ ln(1/2) = 20 ms. Since
τ = Rtotal Ctotal , then Ctotal = 5µF. The answer will be C = Ctotal − 3µF = 2µF.
Chapter 2

Introduction to Digital Electronics

2.1 Exercises
Exercise 2.1 What are the decimal representations of 338 and 3316 ?

Solution: 338 = 3 × 8 + 3 = 27, and 3316 = 3 × 16 + 3 = 51.

Exercise 2.2 What is the value of 1F16 in decimal?

Solution: 1F16 = 1 × 16 + 15 = 31.

Exercise 2.3 Convert B3F16 to binary.

Solution: We know: B = 10112 , 3 = 00112 , F = 11112 . So B3F16 = 1011001111112 .

Exercise 2.4 Convert 1011011102 to hexadecimal.

Solution: 1011011102 = 1 0110 11102 = 16E16 .

Exercise 2.5 Calculate the sum and difference of 1011012 and 0011102 .

Solution: 1011012 + 0011102 = 1110112 , 1011012 − 0011102 = 0111112 .

Exercise 2.6 What character does the ASCII code 0101 1101 represent?

Solution: 010111012 = 5D =]

Exercise 2.7 Verify the relationship between the OR gate and NAND gates of Fig-
ure ?? (in the textbook, shown next) using the truth table.

15
16 CHAPTER 2. INTRODUCTION TO DIGITAL ELECTRONICS

N O T

A N D

O R

Solution:
A B A↑B A↑B AB A′ B′ A′ ↑B′ A+B
0 0 1 0 0 1 1 0 0
0 1 1 0 0 1 0 1 1
1 0 1 0 0 0 1 1 1
1 1 0 1 1 0 0 1 1
Exercise 2.8 Find the matrix for the AND gate.
Solution: ( )
1 1 1 0
AND =
0 0 0 1

Exercise 2.9 Suppose we have a gate G where one input, |A⟩, goes through a NOT
gate and then into an AND gate, and the other input, |B⟩, goes straight into the AND
gate.
1. Find the matrix for G.
2. Fill in the truth table for gate G by calculating its output using matrix operations.
Solution: (1)
 
( ) ( ) 0 0 1 0
0 1 1 0  0 0 0 1 
(NOT) ⊗ (I) = ⊗ =



1 0 0 1  1 0 0 0 
0 1 0 0
( )
1 1 1 0
AND =
0 0 0 1
2.2. PROBLEMS 17

( )
1 0 1 1
G = AND · (NOT ⊗ I) ==
0 1 0 0

(2)
A B G
0 0 0
0 1 1
1 0 0
1 1 0

2.2 Problems
1. Explain the difference between analog and digital signals.
Solution: In analog electronics the information is encoded in the amplitude (or
the frequency) of the signals. In digital electronics the information is encoded
in the combination of binary signals, which have only two values.

2. Convert the following binary numbers to decimals:

(a) 11101
Solution: 111012 = 16 + 8 + 4 + 1 = 29
(b) 10111.11
Solution: 10111.112 = 16 + 4 + 2 + 1 + 0.5 + 0.25 = 23.75

3. Ancient Mayans, prolific astronomers and time keepers who lived in Yucatan
around 1000 AD (and who did not predict the end of the world in 2012), used the
vigesimal number system (base 20). For calendars, they modified the number
system slightly so that the digits would be close to multiples of a year (360
days). The meaning of a four-digit number in a Mayan calendar is:

A3 .A2 .A1 .A0 = A3 × 18 × 202 + A2 × 18 × 20 + A1 × 20 + A0

Here, all the digits except for A1 can range from 0 to 19, but A1 can range
only from 0 to 17. For example, the number 1.0.0 is 360 days (we separate
here the digits with a period), and 1.0.2.5 is 7, 200 + 40 + 5 = 7, 245. The
Mayans had 20 characters, including zero. These were elaborate, mean-looking
anthropomorphic figures, but apparently also used a simpler system of three
characters and positions: a bar = 5, a dot = 1, and a shell =0. Each “digit”
18 CHAPTER 2. INTRODUCTION TO DIGITAL ELECTRONICS

was a grouped combination of bars and dots, or a shell. The positions were
oriented vertically, with the least significant position lowest and most significant
position the highest. The lowest position (least significant place) was the units,
the second position had the 20s , the third position were the 360s (18 × 20),
the fourth position were the 7,200s (18 × 400), and so on. Figure 2.5 (in the
textbook, which is incorrect, the correct figure is shown on the left below, the
one on the right is modified for the solution) is a reproduction of a section of
the Eclipse table of a Mayan document (the Dresden Codex) used to predict
eclipses.1 It gives several groupings of numbers denoting partial and cumulative
days between lunar months. We have selected several numbers. For example
number A is read (vertically) as 1.6.0.0 or (dot = 1) × 7, 200+(dot plus bar =
6)×360 = 9, 360.

(a) What are the decimal equivalents of the numbers labeled B, C, and E?
Solution: B= 8.17 = 8 · 20 + 17 = 177
C= 1.6.8.17 = 1 · 7200 + 6 · 360 + 8 · 20 + 17 = 9537
E= 1.6.17.14 = 1 · 7200 + 6 · 360 + 17 · 20 + 14 = 9714
A= 9360, A + B = 9537 = C.
1
For more information see A.F. Aveni, in Stairways to the Stars (New York: Wiley, 1997), 105ff.
2.2. PROBLEMS 19

(b) It is trivial to see that A + B = C (it is a cumulative table, so the top

numbers are the totals and the bottom ones are the increments) and that
B = D. Show C + D = E. Do the addition within the Mayan number
system (do not convert to decimal to do the addition).
Solution: C + D = 1.6.8.17 + 8.17 = 1.6.17.14 = E. Note that for the least
significant digit: 17 + 17 = 1.14.
(c) Deduce the value F . It represents the predicted number of days between
two eclipses. Explain your reasoning and calculation.
Solution: F = 1.7.15.19 = 1·7200+7·360+15·20+19 = 10039. A different
way: Let us call G the number between E and F (see previous figure on the
right). We read G = 1.7.8.11 from the codex. Let us call H the number
under G (H = 8.17). It is easy to see that E + H = G: 1.6.17.14 + 8.17 =
1.7.8.11. Note that for the least significant digit: 14 + 17 = 1.11. For
the next digit: 17 + 8 + 1 = 1.8. Note also that J = 7.8. The sum
G + J = 1.7.8.11 + 7.8 = 1.7.15.19 = F.

4. The IP addresses used for Internet networks consist of four 8-bit binary numbers
separated by periods. A valid IP is, for example, 149.43.164.45, where the
displayed numbers are in decimal. In Internet networks, the MSB of the left-
most number has a special meaning. If it is a 0, the IP address is from a Class
A (large) network like one of a major international company or a government.
If the MSB is 1 and the binary digit next to it is a 0, then it is a Class B
(medium) network, like those of a university campus. If the binary number
starts with 110, then it is a Class C (small) network, such as one of a small
business. Convert the IP address given earlier to hexadecimal and state what
type of network it corresponds to.
Solution: The IP address is 10010101.00101011.10100100.00101101 in binary,
and 95.2B.A4.2D in hexadecimal. It is class B.

5. For the number 45, give the following information:

(a) Convert it to binary.

Solution: 45 = 1011012 .
(b) Based on the previous part, convert the number to hexadecimal.
Solution: 0010 11012 = 2D16 .
(c) Give its BCD representation in a BCD file.
Solution: 45 → 0100 01012 .
20 CHAPTER 2. INTRODUCTION TO DIGITAL ELECTRONICS

(d) If the two-digit number were to be stored in an ASCII (text) file as char-
acter 4 followed by character 5, what ASCII codes would represent those
characters?
Solution: ASCII= 34 35.
(e) If 4516 were an ASCII code, what character would it represent?
Solution: 45 = E.

6. Assuming that we are working with 8-bit numbers, consider the number N =
101011012 .

(a) Give its one’s complement.

Solution: 010100102 .
(b) Give its two’s complement.
Solution: 010100112 .
(c) Is N a positive or negative number? Why?
Solution: Negative because MSB=1.

7. Give the negative of 5716 in the following:

(a) Sign and magnitude.

Solution: 110101112 .
(b) One’s complement.
Solution: 101010002
(c) Two’s complement.
Solution:101010012

8. Subtract 4716 from 6616 in binary by adding the two’s complement of the sub-
trahend to the minuend.
Solution: 011001102 + (−010001112 ) = 011001102 + 101110012 = 1 000111112
We drop the MSB, so answer is 000111112 . In hexadecimal: 6616 + (−4716 ) =
6616 + B916 = 11F16 .

9. If A = 011011012 and B = 110000112

(a) Calculate A plus B in binary.

Solution: 1001100002 = 13016
(b) Calculate B minus A in binary.
Solution: 010101102 = 5616
2.2. PROBLEMS 21

(c) Check the previous result by adding B to the two’s complement of A.

Solution: −A = 100100112 , so 110000112 + 100100112 = 1 010101102 and
drop MSB, so answer is 010101102 = 5616
(d) Convert A to hexadecimal.
Solution: 01102 = 616 , 11012 = D16 , so A = 6D16 .
(e) Convert B to hexadecimal.
Solution: 11002 = C16 , 00113 = 316 , so B = C316 .
(f) Without a calculator, convert A to decimal.
Solution: 6 × 16 + 13 = 109.
(g) Without a calculator, convert B to decimal.
Solution: 12 × 16 + 3 = 195.
We can also verify that 195 − 109 = 86 = 5616 .

10. Use truth tables to help you construct NOT, two-input OR and two-input AND
gates using purely NOR gates.
Solution:
A B A↓B A+B AB A′ B′ (A + B)′ A′ ↓B′
0 0 1 0 0 1 1 1 0
0 1 0 1 0 1 0 1 0
1 0 0 1 0 0 1 1 0
1 1 0 1 1 0 0 0 1
We see then that A ↓ A = A′ , (A ↓ B)′ = A + B, and A′ ↓B′ =A+B.

11. Use truth tables to show that the complement of the XOR of three variables,
(A ⊕ B) ⊕ C, is a 1 only when an even number of inputs is 1.
Solution:
A B C A⊕B (A ⊕ B) ⊕ C [(A ⊕ B) ⊕ C]′ Parity
0 0 0 0 0 1 Even
0 0 1 0 1 0 Odd
0 1 0 1 1 0 Odd
0 1 1 1 0 1 Even
1 0 0 1 1 0 Odd
1 0 1 1 0 1 Even
1 1 0 0 0 1 Even
1 1 1 0 1 0 Odd

12. Do the following gate-matrix operations:

22 CHAPTER 2. INTRODUCTION TO DIGITAL ELECTRONICS

(a) Find the matrix for the XOR gate.

Solution: ( )
1 0 0 1
XOR =
0 1 1 0
(b) Find the matrix for the XNOR gate by multiplying the matrices of the
XOR gate and the NOT gate.
Solution:
( )( ) ( )
0 1 1 0 0 1 0 1 1 0
=
1 0 0 1 1 0 1 0 0 1

(c) Find the matrix for the gate G = (A′ B ′ )′ .

Solution: G = (NOT)(AND)[(NOT) ⊗ (NOT)]
 
( )( ) 0 0 1 0 ( )
0 1 1 1 1 0  0 0 0 1  1 0 0 0
 
G=  =
1 0 0 0 0 1  1 0 0 0  0 1 1 1
0 1 0 0

(d) Find the entries for the truth table for G using matrix operations.
Solution:
A B A′ B′ A′ B′ (A′ B′ )′
0 0 1 1 1 0
0 1 1 0 0 1
1 0 0 1 0 1
1 1 0 0 0 1
13. In the partial circuit diagram of Figure 2.6 (of the textbook), two different
digital lines must be connected to a common line. Tristate gates help us avoid
conflicts where one line puts a logic 0 and another puts a logic 1. We then define
a protocol where a third-line ENABLE controls traffic. When ENABLE = 1,
it allows the first input to go through and disables the second one; conversely,
when ENABLE = 0, it allows the second one to go through, disabling the first
one. Using any gates that you deem necessary complete the circuit so that it
enables the desired protocol.
Solution: The inputs to the tristate buffers, T1 and T2 have to be controlled by
ENABLE line following the table below.

ENABLE T1 T2
0 0 1
1 1 0
2.2. PROBLEMS 23

So the tristate inputs have to be wired following T1 = ENABLE and T2 =

(ENABLE)′ , as shown in the figure below.

14. In the circuit of Figure 2.7 (of the textbook), we want to implement a bi-
directional transceiver. The idea is that two devices need to communicate with
each other over a single line. Each device has input and output capabilities.
For simplicity, we call the devices “left” and “right” in the figure. To avoid
conflicts, then, we need to use tristate gates in conjunction with a line that
establishes the direction in which the data goes: 1 for left to right and 0 for
right to left. Suppose that, in addition, we want to implement an enable line so
that when it is 1, it allows the transceiver to work normally, but when it is 0,
it disables any data transfer. Use any gates you deem necessary to implement
this communication protocol.
Solution: The function of the transceiver is summarized in the truth table below,
for the inputs to the “ right-to-left” and “left-to-right” tristate gates, TRL and
TLR , respectively, as a function of the enable and direction inputs, E and D,
respectively.

E D TRL TLR
0 0 0 0
0 1 0 0
1 0 1 0
1 1 0 1

From the table it can be deduced that TRL = ED′ and TLR = ED. The
completed diagram is shown in the next figure.
24 CHAPTER 2. INTRODUCTION TO DIGITAL ELECTRONICS

15. In serial communications the data bits are preceded by a “start bit,” which is
a high-voltage (5 V) bit. The data then follows the start bit. After the data
comes the parity bit. The parity bit is set according to the following protocol:
If it is even (odd), then the total number of 1’s in the data plus the parity bit
is even (odd). Suppose that we decide to send the sequence 1011001. If a logic
1 is encoded with 5 V (H) and a logic 0 is encoded by 0 V (L), then the data
stream will be HHLHHLLHP, where P stands for the parity bit and the first
bit is the start bit.

(a) If the parity protocol is odd, what logic level (H/L) should the parity have?
Justify your answer.
Solution: The data has an even number of 1’s. If the set parity is odd,
then the parity bit must be 1.
(b) Baud rate is the number of bits per second sent in serial communications.
If the baud rate is 19,200, what it the temporal width of each bit being
transmitted?
Solution: The unit of baud rate is bits/s. The time between bits is tB =
1/(19200bits/s) = 5.2 · 10−5 s.
(c) Draw the waveform for sending the data stream 0110110 with even parity.
Label your axes.
Solution: The answer is shown in the figure below. Since the parity is even
and there is an even number of data bits, then the parity bit is P= 0. S is
start bit.
2.2. PROBLEMS 25

(d) The USB communications protocol is different from the usual serial com-
munications protocol. It uses the Non Return to Zero Invert (NRZI) en-
coding. In this protocol, the logic information is encoded via changes of
voltage levels. A logic 0 corresponds to a change in the input voltage while
a logic 1 corresponds to no change in the voltage level. For example, 0110
is encoded by Start(H)-L-L-L-H, where we have used (H for high voltage
and L for low voltage). In the NRZI encoding, there is no parity bit. In-
stead, the one’s complement of the data is sent immediately after the data.
Redraw the waveform of the previous part (c) using NRZI encoding.
Solution: Every time there is a 0 the level changes, and when there is a 1
the level does not change. The parity is 0, so there is a change with the
parity bit. The waveform is shown in the figure below.

16. In table of Problem 16 (see textbook), fill in the logic level interpreted by the
gate of a given type for the voltages listed in the column on the left.

Solution: The filled table is shown below. Note that“x” represents an undefined
value.

Input Voltage (V) TTL-LS CMOS-HC CMOS-HCT

3.6 1 1 1
0.2 0 0 0
4.5 1 1 1
-0.1 0 x 0
1.4 x 0 x
2.6 1 x 1

17. In table of Problem 17, fill in the table with a “yes” or “no” depending on
whether the gates of the type listed can output the voltage given in the column
on the left.

Solution: The filled table is shown next.

26 CHAPTER 2. INTRODUCTION TO DIGITAL ELECTRONICS

Output Voltage (V) TTL-LS CMOS-HC CMOS-HCT

0.1 yes no no
3.6 yes no no
2.1 no no no
5.0 yes yes yes
0 yes yes yes
0.5 no no no
Chapter 3

Combinational Logic

3.1 Exercises
Exercise 3.1 Use truth tables to verify the theorems of Equations 3.9—3.16.

Solution:
A A′ (A′ )′ A·A A′ + A A′ · A A+0 A+1 A·0 A·1
0 1 0 0 1 0 0 1 0 0
1 0 1 1 1 0 1 1 0 1
Eq. 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Exercise 3.2 Convert the information in the table below into an SOP function.

x y z F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1

Solution: F = x′ y ′ z + x′ yz ′ + xy ′ z ′ + xyz ′ + xyz.

Exercise 3.3 Simplify the following function: F = xyz + x′ y + xyz ′ .

Solution: F = x′ y + xy(z + z ′ ) = x′ y + xy = (x′ + x)y = y.

Exercise 3.4 For function F = zx + zx′ y,

27
28 CHAPTER 3. COMBINATIONAL LOGIC

1. Simplify it algebraically (if out of ideas try a Venn diagram).

Solution: F = zx + zx′ y = z(x + x′ y) = z(x[y + y + y ′ ] + x′ y)
= z(xy + xy + xy ′ + x′ y) = z(x[y + y ′ ] + [x + x′ ]y) = zx + zy.
2. Draw a circuit diagram using AND and OR gates.
Solution:

3. Draw a circuit diagram using only NAND gates.

Solution:

Exercise 3.5 Write the truth table for the function F = x′ yz + xy ′ z + xyz.
Solution:
x y z F
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Exercise 3.6 Simplify the function F = xy + x′ y + x′ y ′ .
Solution:
3.1. EXERCISES 29

Exercise 3.7 Show that the function given by Equation 3.19 reduces to z ′ + xy. By
simplifying the function, we now need only three gates to implement it.

Solution: We load the Karnaugh map directly from the Boolean expression, F =
x′ y ′ z ′ + x′ yz ′ + xy ′ z ′ + xyz ′ + xyz, and then group contiguous boxes.

The groupings indeed show that F = z ′ + xy

Exercise 3.8 Simplify F = w′ x′ y ′ z ′ + wx′ + x′ y + xyz.

Solution: First we load the Karnaugh map and group the boxes in the simplest
form:

From grouping we get: F = wx′ + x′ z ′ + yz.

Exercise 3.9 A function F is true when the 4-bit binary-coded decimal input is a 3
or a 5. Find the simplest expression for F.

Solution: First we need to set up a truth table following the conditions of the
problem. Since the problem specifies that the input variables represent a binary-
coded decimal, then 4-bit binary values from 10102 to 11112 will never occur, and so
we load don’t care symbols “×” in the table. Secondly, we load the Karnaugh map
from the truth table. Shown below are the truth table and the Karnaugh map.
30 CHAPTER 3. COMBINATIONAL LOGIC

w x y z F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 ×
1 0 1 1 ×
1 1 0 0 ×
1 1 0 1 ×
1 1 1 0 ×
1 1 1 1 ×

3.2 Problems
1. Consider the following functions:

(a) F = x′ y ′ + xy + x′ y
(b) F = (x + y)(x + y ′ )
(c) F = x′ + xy + xz ′ + xy ′ z ′

• Reduce them to the simplest expression using the postulates of Boolean

algebra.
• Check your results using a Venn diagram.
• Draw a circuit diagram of the simplest expression of the function.

Solution: Will do only the analytical solutions.

(a) F = x′ y ′ + xy + x′ y = x′ y ′ + xy + x′ y + x′ y
= x′ (y ′ + y) + (x + x′ )y = x′ + y.
3.2. PROBLEMS 31

(b) F = (x + y)(x + y ′ ) = x + xy ′ + xy + yy ′ = x(1 + y ′ + y) = x.

(c) F = x′ + xy + xz ′ + xy ′ z ′ = x′ + x′ (y + y ′ ) + xy + xz ′ (1 + y ′ ) = x′ + x′ y +
x′ y ′ + xy + xz ′ =
= x′ + (x′ + x)y + x′ y ′ + xz ′ = x′ (1 + x′ y ′ ) + y + xz ′ = x′ + y + xz ′ =
= x′ (1 + z ′ ) + y + xz ′ = x′ + y + (x′ + x)z ′ = x′ + y + z ′

2. Find a simplified expression for F = a ⊙ (a ⊙ b).

Solution: F = a ⊙ (a ⊙ b) = a(a ⊙ b)′ + a′ (a ⊙ b) = a(a ⊕ b) + a′ (a ⊕ b) =
= a(ab + a′ b′ ) + a′ (ab′ + a′ b) = ab + a′ b = b

3. Verify De Morgan’s theorem using a truth table: Make a table with two columns
listing all the possible combinations of the two inputs, A and B. Fill additional
columns with the result of the operations of each side of Equations 3.17 and
3.18 (in the textbook) for each combination of A and B.
Solution: The truth table is shown below. notice that the columns for (A + B)′
and A′ B′ , and (AB)′ and A′ + B′ , are the same, as predicted by De Morgan’s
theorem.
A B A′ B′ (A + B)′ A ′ B′ (AB)′ A ′ + B′
0 0 1 1 1 1 1 1
0 1 1 0 0 0 1 1
1 0 0 1 0 0 1 1
1 1 0 0 0 0 0 0

4. In negative logic, a logic 1 is a low voltage and a logic 0 is a high voltage. Use
De Morgan’s theorem to show that in negative logic an AND gate based on
positive logic behaves as an OR gate, and vice versa.
Solution: We denote low electronic level by “L” and high electronic level by
“H.” In positive logic L = 0 and H = 1. So the electronic output of the AND
gate is consistent with F = AP BP . However, in negative logic L = 1 and H = 0,
so the input levels, recognized AN and BN , produce an output consistent with
F = AN + BN . That is, the gate performs the AND function in positive logic
and the OR function in negative logic. This is shown in the truth table below.
A B AP BP A P BP F AN BN AN + BN
L L 0 0 0 L 1 1 1
L H 0 1 0 L 1 0 1
H L 1 0 0 L 0 1 1
H H 1 1 1 H 0 0 0
32 CHAPTER 3. COMBINATIONAL LOGIC

5. A CNOT gate has two inputs, a and b, and two outputs, a and a ⊕ b. The
right part of Figure 3.12 (in the textbook, shown below) shows the symbolic
representation, and the one on the left side shows the wiring diagram. Briefly,
one of the outputs is the same as one of the inputs (a). The other output is the
XOR operation between the two inputs (c = a ⊕ b). This gate is the inverse of
itself.

(a) Use a truth table to show this property by proving that (CNOT)2 = I,
where I is the identity operation (the outputs are the same as the inputs).
Solution: The table below shows the results: the outputs of CNOT2 are
equal to the inputs, and thus constitute the identity operation.
a b CNOT CNOT2
0 0 0 0 0 0
0 1 0 1 0 1
1 0 1 1 1 0
1 1 1 0 1 1
(b) The CNOT gate has two inputs and two outputs. Find the 4 × 4 matrix
that represents it.
Solution:  
1 0 0 0
 0 1 0 0 
 
 
 0 0 0 1 
0 0 1 0

(c) Show by matrix multiplication that (CNOT)2 = I.

Solution:
    
1 0 0 0 1 0 0 0 1 0 0 0
 0 1 0 0  0 1 0 0   0 1 0 0 
    
  = 
 0 0 0 1  0 0 0 1   0 0 1 0 
0 0 1 0 0 0 1 0 0 0 0 1

6. A Toffoli gate is said to be a universal gate. It has three inputs and three
outputs. Figure 3.13 (in the textbook) shows its circuit diagram. If the three
inputs are a, b, and c, the three outputs are a, b, and t = (ab) ⊕ c. Design an
3.2. PROBLEMS 33

arrangement of input/output connections so that the Toffoli gate can be used

as follows:

(a) An AND gate (two inputs, x and y, and an output, xy)

Solution:

(b) A NAND gate

Solution:

(c) An OR gate
Solution: Below we show a NOT gate generated from a Toffoli gate. Since
x + y = x′ ↑ y ′ , then we can make an OR gate using previously defined
NOT and NAND gates.

7. A 1-bit memory cell consists of a latch and a tristate buffer, as shown in Fig-
ure 3.14 (in the textbook). It uses a line for both input and output. When
SEL = 0, the latch captures the logic level of the line at IN and transfers it to
OUT. When SEL = 1, The logic value of OUT remains the same regardless of
the value on IN. The value at OUT can be connected to the INPUT/OUTPUT
34 CHAPTER 3. COMBINATIONAL LOGIC

line by making T = 1 in the tristate buffer, enabling it. When T = 0, the tris-
tate buffer is disabled and isolates OUT from the INPUT/OUTPUT line. We
control the memory cell via two control lines: EN ABLE and READ/W RIT E.
The communications protocol is then the following:

• When we wish to communicate with the memory cell we make EN ABLE =

0. In addition,
– When we want to write to the memory cell, we make READ/W RIT E =
0. When this occurs, we need to enable the latch and disable the buffer.
– When we want to read the value stored in the memory cell, we make
READ/W RIT E = 1. Then we need to disable the latch and enable
the buffer.
• When we do not want to communicate with the memory cell, we need
to disable the buffer but still make sure that the memory remembers its
stored value (keeping OUT from changing).

(a) Based on the specified protocol, fill in a truth that has EN ABLE and
READ/W RIT E as inputs and SEL and T as outputs.
Solution:
E R/W SEL T
0 0 1 1
0 1 0 0
1 0 1 0
1 1 1 0
(b) Find simplified expressions for SEL and T using Karnaugh maps.
Solution: From the Karnaugh maps of SEL and T we get:
SEL = E + (R/W)′ and T = (E)′ (R/W)′ .

(c) Implement the memory cell by completing the circuit of Figure 3.14 (in
the textbook). Use any gates you deem appropriate.
Solution: The completed circuit is shown next.
3.2. PROBLEMS 35

8. A three-member congressional board, made of members A, B, and C, is to vote

on resolutions. A and B are with the ruling party, and C is with the opposition.
C shares some interests with A and B, but not both. The board decided to
save taxpayers money by using a voting machine that makes legislating more
efficient.

(a) Write a truth table for the function F implemented by the voting machine,
which has the following rules:
• When A and B vote yes and C votes no, the resolution passes.
• A, B, and C never all agree on anything (they never all vote yes). (Of
course!)
• On certain environmental issues, A and C agree, but B disagrees. If
A and C vote yes and B votes no, the resolution passes.
• On abortion rights, B and C agree, but A disagrees. If B and C vote
yes and A votes no, then the resolution passes.
• The inputs are low active, so a yes is a logic 0 and a no is a logic 1.
• The output is high active: If the resolution passes, the output is a
logic 1.
A B C F Explanation
0 0 0 × They never all vote yes
0 0 1 1 A,B yes, C no
0 1 0 1 A, C yes, B no
Solution: 0 1 1 0 No pass
1 0 0 1 B, C yes, A no
1 0 1 0 No pass
1 1 0 0 No pass
1 1 1 0 They all vote no
36 CHAPTER 3. COMBINATIONAL LOGIC

(b) Simplify F using Karnaugh maps.

Solution: The Karnaugh map is shown below.

The simplified function is F = B′ C′ + A′ B′ + A′ C′ .

(c) Draw a simplified circuit using only NAND gates.
Solution:

9. Simplify the circuit of Fgure 3.15 (in the textbook) and redraw it using AND,
NOT and OR gates.
Solution: F = ABC + BC + CD + BC(A + D)′ = ABC + BC + CD + A′ BCD.
From the Karnaugh map simplification we have: F = BC + CD.

10. Table 3.5 (in the textbook) shows the truth table for a “4-to-2 priority encoder.”
3.2. PROBLEMS 37

(a) Write the complete truth table for S1 and S0 (all 16 combinations of D3 ,
D2 , D1 , and D0 ).
(b) Draw the corresponding Karnaugh map.
(c) Obtain simplified Boolean expressions for them.

Solution: The truth table and Karhaugh map simplifications are given below.
The final solutions are: S1 = D2 + D3 and S0 = D3 + D2′ D1 .

D3 D2 D1 D0 S1 S0
0 0 0 0 0 0
0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 0 0
0 1 1 1 0 0
1 0 0 0 1 1
1 0 0 1 1 1
1 0 1 0 1 1
1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1
38 CHAPTER 3. COMBINATIONAL LOGIC

11. We want to generate the circuit of the seven-segment display decoder, the 7447.
It has four inputs representing a BCD number. The outputs to the LEDs are
low active. That is, they are 0 if we want to turn on the segment. Eventually,
we want the seven segments to display the decimal digits from 0 to 9. For each
segment:
(a) Write the truth table. Remember that a 0 turns on the segment light. For
example, if F= 0101, we want to display a 5, which means that a = c =
d = f = g = 0 and b = e = 1.
F3 F2 F1 F0 a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 0 0
0 1 0 0 1 0 0 1 1 0 0
0 1 0 1 0 1 0 0 1 0 0
0 1 1 0 0 1 0 0 0 0 0
Solution: 0 1 1 1 0 0 0 1 1 1 1
1 0 0 0 0 0 0 0 0 0 0
1 0 0 1 0 0 0 1 1 0 0
1 0 1 0 × × × × × × ×
1 0 1 1 × × × × × × ×
1 1 0 0 × × × × × × ×
1 1 0 1 × × × × × × ×
1 1 1 0 × × × × × × ×
1 1 1 1 × × × × × × ×
(b) Draw the K-maps and obtain the simplest expression.

a = F2 F1′ F0′ + F3′ F2′ F1′ F0 b = F2 F1′ F0 + F2 F1 F0′ .

3.2. PROBLEMS 39

c = F2′ F1 F0′ d = F2 F1′ F0′ + F2 F1 F0 + F2′ F1′ F0 .

e = F0 + F2 F1′ f = F1 F0 + F2′ F1 + F3′ F2′ F0 .

g = F2 F1 F0 + F3′ F2′ F1′ .

(c) Draw the circuit diagram using NAND gates.
40 CHAPTER 3. COMBINATIONAL LOGIC

Solutions:

12. We want to design a BCD-to-XS3 binary code converter. A number in XS3

(excess 3) code, NXS3 , is related to a BCD number, NBCD , by:
NXS3 = NBCD plus 3. For example, the BCD number 1000 is 1011 in XS3.
The converter we want to design will have the digits of the BCD number (B3 ,
3.2. PROBLEMS 41

B2 , B1 , and B0 ) as inputs, and the digits of the XS3 number (X3 , X2 , X1 and
X0 ) as outputs. It will work in such a way that when we input a BCD number
at the Bi ’s, we get its XS3 equivalent at the outputs Xi ’s.

(a) Write the truth table for X3 , X2 , X1 , and X0 as a function of B3 , B2 , B1 ,

and B0 .
Solution:
B3 B2 B1 B0 X3 X2 X1 X0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 × × × ×
1 0 1 1 × × × ×
1 1 0 0 × × × ×
1 1 0 1 × × × ×
1 1 1 0 × × × ×
1 1 1 1 × × × ×
(b) Find a simplified Boolean expression for X2 and X1 .
Solution: The simplified functions are:
X2 = B2 B1′ B0′ + B2′ B0 + B2 B1′ B0′ and X1 = B1′ B0′ + B1 B0 .
42 CHAPTER 3. COMBINATIONAL LOGIC

(c) Draw a circuit diagram for X2 and X1 in terms of NAND gates.

13. Design a combinational circuit that has as inputs the 4-bit (binary) month
count from a “month” counter, and as outputs: (a)The 8 bits of the BCD
representing the month (for example, for December the input is 11002 , and the
output is 000100102 ). (b) Two functions, F30 and F31 , whose output is a 1 when
the month count corresponds to a month with 30 and 31 days, respectively. The
design should include the following:
(a) Truth tables reflecting the statement of the problem.
Solution:
B3 B2 B1 B0 M7 M6 M5 M4 M3 M2 M1 M0 F31 F30
0 0 0 0 × × × × × × × × × ×
0 0 0 1 0 0 0 0 0 0 0 1 1 0
0 0 1 0 0 0 0 0 0 0 1 0 0 0
0 0 1 1 0 0 0 0 0 0 1 1 1 0
0 1 0 0 0 0 0 0 0 1 0 0 0 1
0 1 0 1 0 0 0 0 0 1 0 1 1 0
0 1 1 0 0 0 0 0 0 1 1 0 0 1
0 1 1 1 0 0 0 0 0 1 1 1 1 0
1 0 0 0 0 0 0 0 1 0 0 0 1 0
1 0 0 1 0 0 0 0 1 0 0 1 0 1
1 0 1 0 0 0 0 1 1 0 0 1 1 0
1 0 1 1 0 0 0 1 1 0 0 1 0 1
1 1 0 0 0 0 0 1 1 0 0 1 1 0
1 1 0 1 × × × × × × × × × ×
1 1 1 0 × × × × × × × × × ×
1 1 1 1 × × × × × × × × × ×
(b) Karnaugh maps for each of the outputs.
3.2. PROBLEMS 43

Solution: It is trivial to show that M7 = M6 = M5 = 0.

M4 = B3 B2 + B3 B1 M3 = B3 B1′ B0 + B2′ B1′ B0′

M2 = B3′ B2 M1 = B3 B2 + B3′ B1

M0 = B0 F31 = B3 B0′ + B3′ B0

44 CHAPTER 3. COMBINATIONAL LOGIC

B3 B0 + B3′ B2 B0′

(c) Circuit diagram using NAND gates.

3.2. PROBLEMS 45

14. One of the computer’s most important parts is the device that performs all the
arithmetic and logical operations: the arithmetic logical unit (ALU). The ALU
is a large combinational circuit that has control inputs, data inputs, and data
outputs. In this exercise, we use the 74LS181 4-bit ALU. The functional details
are described shortly. The data inputs are B = B3 B2 B1 B0 and A = A3 A2 A1 A0 ,
and the data outputs are F = F3 F2 F1 F0 . They represent 4-bit binary variables,
with F being the result of an operation between A and B. The control inputs
S3 , S2 , S1 , S0 , M , and Cn specify the operation as given in Table 3.6 (of the
textbook). Note that the functions under “M = 1” are independent of the
input Cn .

(a) Complete Table 3.7 (in the textbook). Solution:

x y z ALU OPERATION S3 S2 S1 S0 M Cn
0 0 0 F=A+B 1 1 1 0 1 ×
0 0 1 F=A·B 1 0 1 1 1 ×
0 1 0 F=A′ 0 0 0 0 1 ×
0 1 1 F=B′ 0 1 0 1 1 ×
1 0 0 F=A⊕B 0 1 1 0 1 ×
1 0 1 F=A⊙B 1 0 0 1 1 ×
1 1 0 F=A minus B 0 1 1 0 0 0
1 1 1 F=A plus B 1 0 0 1 0 1
(b) Get a simplified functional form for each of the ALU control inputs, as a
function of x, y, and z, using the Karnaugh map method.
Solutions:

S3 = x′ y ′ + xz S2 = y ′ z ′ + x′ yz + xz ′
46 CHAPTER 3. COMBINATIONAL LOGIC

S1 = x′ y ′ + xz ′ S0 = z

M = y ′ x′ Cn = z
(c) Express each circuit in terms of NAND gates.
Solution:
Chapter 4

Advanced Combinational Devices

4.1 Exercises
Exercise 4.1 We have two 3-bit numbers, A=A2 A1 A0 and B=B2 B1 B0 . Each bit is
represented by a digital input line. Find a function G that is a 1 when A ̸= B.

Solution: G = A2 ⊕ B2 + A1 ⊕ B1 + A0 ⊕ B0 .

Exercise 4.2 Implement the function F = x′ y ′ z + x′ yz + xy ′ z + xyz ′ using a 3×8

decoder.

Solution: x′ y ′ z = D1 , x′ yz = D2 , xy ′ z = D5 , xyz ′ = D6

Exercise 4.3 Fill in the remainder of Table 4.4 (in the textbook) according to the
setting of the fuses of the PROM in Figure 4.3 (in the textbook).

47
48 CHAPTER 4. ADVANCED COMBINATIONAL DEVICES

Solution:
A1 A0 O3 O2 O1 O0
0 0 1 1 0 1
0 1 1 0 0 1
1 0 0 0 1 1
1 1 1 1 0 1

Exercise 4.4 We can also use the enable line for a different purpose: To expand the
decoding space. Design a circuit that uses two 2×4 decoders with enable to make a
3×8 decoder. The circuit should have three lines as inputs: the address lines A2 , A1 ,
and A0 ; and eight lines as outputs: the data lines D0 , D1 , D2 , D3 , D4 , D5 , D6 , and
D7 .

Solution: Two address lines are the inputs to each 2×4 decoder. The third address
line uses the enable input in each multiplexer to select either one appropriately.

Exercise 4.5 Implement the function F = y + x′ y ′ using a 4 × 1 multiplexer and a

2 × 1 multiplexer.

Solution: The truth table for F in terms of x and y is shown below on the left.
We implement it with a 4 × 1 multiplexer in a straightforward way, as shown in the
next figure. Notice that when y = 0, F = x′ , and when y = 1, F = 1, as shown in the
reduced truth table, below on the right. The implementation with a 2 × 1 multiplexer
is shown in the next figure on the right.
x y F
0 0 1 y F
0 1 1 0 x′
1 0 0 1 1
1 1 1
4.2. PROBLEMS 49

4.2 Problems
1. We have two 4-bit numbers A=A3 A2 A1 A0 and B=B3 B2 B1 B0 . Find a circuit
diagram that generates a 1 when A is greater than or equal to B.

Solution:

F = A3 B3′ + (A3 ⊙ B3 )A2 B2′ + (A3 ⊙ B3 )(A2 ⊙ B2 )A1 B1′

+(A3 ⊙ B3 )(A2 ⊙ B2 )(A1 ⊙ B1 )A0 B0′ + (A3 ⊙ B3 )(A2 ⊙ B2 )(A1 ⊙ B1 )(A0 ⊙ B0 )

2. In a full adder, each digit has three inputs (Ai , Bi , and Cini ) and two outputs
(Si and Couti ).

(a) Using the standard logic minimization procedure, find Boolean expressions
for Si and Couti .
Solution: We begin by writing the truth table, and then use Karnaugh
maps to obtained simplified expressions.
A1 Bi Cini Couti Si
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
50 CHAPTER 4. ADVANCED COMBINATIONAL DEVICES

Couti = Bi Cini + Ai Cini + Ai Bi ,

Si = Ai B′i C′ini + Ai Bi Cini + A′i B′i Cini + A′i Bi C′ini
(b) What is the maximum number of gate delays in arriving at the two out-
puts?
Solution: Three levels of gates are involved, and so three delays: the com-
plements of the inputs, the AND operations, and the OR operation.
(c) Now consider a 3-bit full adder. How many gate delays are involved in
getting the adder to settle into its final value? Show your work.
Solution: The first-bit output, Cout1 , is the second-bit input, Cin2 . It is
arrived after three gate delays. The second-bit outputs then appear after
six gate delays. Finally, the three-bit outputs appear after nine gate delays.
(d) We want to shorten the time by adding “look ahead” carry circuits. A
carry Couti = 1 is generated if either: both Ai and Bi are 1, OR if Ai
or Bi (or both) are 1 AND Cini is 1. State this condition in a Boolean
expression for each digit i, where i = 1, 2, 3. Let us also call Cin1 = C0 ,
Cout1 = Cin2 = C1 , Cout2 = Cin3 = C2 , and Cout3 = C3 .
Solution: For each digit we know: Couti = Ai Bi + (Ai + Bi )Cini
C1 = A1 B1 + (A1 + B1 )C0
= A1 B1 + A1 C0 + B1 C0
C2 = A2 B2 + (A2 + B2 )C1
= A2 B2 + (A2 + B2 )(A1 B1 + A1 C0 + B1 C0 )
= A2 B2 + A2 A1 B1 + A2 A1 C0 + A2 B1 C0 + B2 A1 B1 + B2 A1 C0 + B2 B1 C0
C3 = A3 B3 + (A3 + B3 )C2
= A3 B3 + A3 A2 B2 + A3 A2 A1 B1 + A3 A2 A1 C0 + A3 A2 B1 C0 + A3 B2 A1 B1
+ A3 B2 A1 C0 + A3 B2 B1 C0 + B3 A2 B2 + B3 A2 A1 B1 + B3 A2 A1 C0
+ B3 A2 B1 C0 + B3 B2 A1 B1 + B3 B2 A1 C0 + B3 B2 B1 C0

3. We have two 4-bit lines representing two BCD variables. We want to design a
4-bit BCD adder. That is, the output of the circuit must be the BCD number
4.2. PROBLEMS 51

that results from adding the two BCD numbers. We have at our disposal one
or more 4-bit binary adders. Using any gates that you need and the binary
adder(s), design the circuit that will do the job. Hint: Start by looking at the
output of the 4-bit binary adder that has the two BCD variables as inputs, and
compare that to the output that BCD adder should have.
Solution: Decimal digits vary between 0 and 9, so the sum of two decimal digits
can vary between 0 and 18. If we add carry, this range includes 19. If these are
added in binary, then the sum varies from 0 to 1316 . Thus, after 9 (10012 ) we
get 10102 instead of the desired 1000 00002 . In the truth table below we list the
outputs of a binary adder. We also list the outputs we would desire for a BCD
adder.
Cout S3 S2 S1 S0 Mout X3 X2 X1 X0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1
0 0 0 1 0 0 0 0 1 0
0 0 0 1 1 0 0 0 1 1
0 0 1 0 0 0 0 1 0 0
0 0 1 0 1 0 0 1 0 1
0 0 1 1 0 0 0 1 1 0
0 0 1 1 1 0 0 1 1 1
0 1 0 0 0 0 1 0 0 0
0 1 0 0 1 0 1 0 0 1
0 1 0 1 0 1 0 0 0 0
0 1 0 1 1 1 0 0 0 1
0 1 1 0 0 1 0 0 1 0
0 1 1 0 1 1 0 0 1 1
0 1 1 1 0 1 0 1 0 0
0 1 1 1 1 1 0 1 0 1
1 0 0 0 0 1 0 1 1 0
1 0 0 0 1 1 0 1 1 1
1 0 0 1 0 1 1 0 0 0
1 0 0 1 1 1 1 0 0 1
Here one might compare the two and notice that the output for 10 and above
can be obtained by adding 6 to the output of the binary adder. That is, below
10, X = S, and for 10 and above, X = S + 6. So we could use a binary adder,
and feed its output to another adder, where we add 6 when the output of the
first adder is greater than 10, or when Mout = 1. Thus, we can implement this
via the following operation: X = S + 6 · Mout . When is Mout = 1? We can see
that we can implement it as Mout = Cout + S3 S2 + S3 S1 . The final circuit is
52 CHAPTER 4. ADVANCED COMBINATIONAL DEVICES

shown below.

4. Write down the gate-level circuit of the decoder with low-active enable and
low-active outputs.
′ ′ ′
Solution: For such a device D0 = x′ y ′ z ′ E , D1 = x′ y ′ zE ,D2 = x′ yz ′ E , D3 =
′ ′ ′ ′ ′
x′ yzE ,D4 = x′ yzE , D5 = x′ yz ′ E , D6 = xyz ′ E and D7 = xyzE
4.2. PROBLEMS 53

5. How would you make a 3x8 decoder using two 2×4 decoders with enable (all
high-active)? (Hint: You can use the third input to enable/disable the de-
coders.)

Solution: Same solution as Exercise 4.4.

6. Draw a circuit diagram of a PROM similar to Figure 4.3 (in the textbook) that
follows table below with the requirements given here.

A1 A0 O3 O2 O1 O0
0 0 1 1 0 1
0 1 0 1 1 0
1 0 0 1 0 0
1 1 1 1 1 1

(a) Using a decoder.

(b) Using a low-active input enable line such that when enable is true the
PROM works as planned, but when false, all the outputs of the PROM
are a logic 0.

(c) Using a low-active enable so that, when false, the outputs are in a high-
impedance state.
54 CHAPTER 4. ADVANCED COMBINATIONAL DEVICES

7. Design a 1 × 8 demultiplexer using two 1 × 4 demultiplexers (74LS139). Make

a diagram.
Solution: The 74LS139 has only one enable input and two address inputs. It
can function as a decoder with enable or as a demultiplexer. For a 1 × 8
demultiplexer we need an extra address line A2 and the data input (D). When
A2 = 0 we want to enable one IC and when A2 = 1 we want to enable the other
IC. However, we want the selected output to display data, given by D. Thus
we need to enable the IC in an appropriate manner. We summarize this by the
truth table below:
A2 D E1 E2
0 0 0 1
0 1 1 1 E1 = (D′ A′2 )′ , E2 = (D′ A2 )′
1 0 1 0
1 1 1 1
The final circuit is:

8. Use the data sheet of the 74LS148 to explain the role that EI , E0 , and GS play
in the circuit of Figure 4.8 (in the textbook).
Solution: The 74LS148 is a priority encoder with low-active inputs and outputs.
4.2. PROBLEMS 55

From the datasheet of the IC we gather the operation of the IC. Since data sheets
do not have subscripts, will use EI and EO instead of EI and EO .

(a) When EI is high (1 in positive logic), the encoder is disabled and all of the
outputs (data A2, A1, A0; control GS EO) are high.

(b) When EI is low, the encoder data outputs will output the binary value of
the highest-value data input (0 to 7) that is low. For example, if 2 and 4
are low, (A2,A1,A0) are 1002 , decoding a 4 in binary. The encoder gave
input-4 priority over input-2.

(c) When EI is low and any of the data inputs is held low, output EO is high.
If none of the inputs is low (and EI is low), then EO is low. This feature
allows one to connect encoders together: EO would go to the EI of the
following encoder. GS has the opposite output as EO, except when EI is
high, and can be used as a low-active indicator that a data input is active.

9. Implement the function F = x′ y ′ z + x′ yz + xy ′ z + xyz ′ using:

(a) A decoder

(b) An 8 × 1 multiplexer

(c) A 4 × 1 multiplexer

Solution: First we fill in the truth table:

x y z F
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

The diagrams for each case are:

56 CHAPTER 4. ADVANCED COMBINATIONAL DEVICES

10. A full subtractor subtracts two numbers, such as X − Y = Z, where X is the

minuend, Y is the subtrahend, and Z is the difference.

(a) Check your binary subtracting skills by verifying that 10011011−01011101 =

00111110.
Solution: Best is to put it in the conventional form:
1 0 0 1 1 0 1 1
− 0 1 0 1 1 1 0 1
0 0 1 1 1 1 1 0
(b) A 1-bit full subtractor has as inputs the minuend xi , the subtrahend yi , and
a borrow-in Bin . A borrow-in arises when the operation for the previous
least significant digit needs to borrow. Its outputs are the difference zi and
borrow-out Bout . The borrow out is generated when the minuend has to
borrow. Write the truth table of a 1-bit full subtractor.
Solution:
Bin xi yi zi Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1
(c) Implement circuits for zi and Bout using:
i. An 8 × 1 multiplexer.
Solution:
4.2. PROBLEMS 57

ii. A 4 × 1 multiplexer.
Solution:
58 CHAPTER 4. ADVANCED COMBINATIONAL DEVICES
Chapter 5

Sequential Logic

5.1 Exercises
Exercise 5.1 The circuit of the previous example works for positive-edge transitions.
Design one that works for negative-edge transitions.

Solution: Let us use a gate with inputs x and y. In the steady state, y = x′ . That
is, the signal from x goes through a NOT gate that inserts a delay. We want the gate
to output 0 for this case. When x goes from 0 to 1, temporarily x = y = 1, but we
want the gate output to be 0 for this case too. Finally, when x goes from 1 to 0 (that
is, what we want to detect), temporarily x = y = 0. Therefore we want the gate to
be 1 for this case. If we fill in the truth table of possible values of x and y (below),
we find that the desired output is that of a NOR gate.
x y F
0 0 1
0 1 0
1 0 0
1 1 0

Exercise 5.2 Continue where we left off in the previous circuit for the changes men-
tioned and fill in Table 5.1.

1. Find the value of Q and Q′ when we make R = 0.

2. Find the value of Q and Q′ when we make S = 1.

3. Find the value of Q and Q′ when we make S = 0.

4. Find the value of Q and Q′ when we make R = 1.

59
60 CHAPTER 5. SEQUENTIAL LOGIC

5. Find the value of Q and Q′ when we make R = 0 and S = 1.

6. Generalize the function of the circuit but without considering the S = 1, R = 1

state.
Question S R Q Q′
0 0 1 0
0 1 0 1
(1) 0 0 0 1
(2) 1 0 1 0
(3) 0 0 1 0
(4) 0 1 0 1
(5) 1 0 1 0
(6) 0 0 1 0

Exercise 5.3 Draw the timing diagram that corresponds to the input signals of the
D flip-flop with enable shown in Figure 5.5 (in the textbook).

Solution: The output Q is a snapshot of the input D while E is high.

Exercise 5.4 As a preview of our next section, consider the circuit of Figure 5.6 (in
the textbook). It consists of two flip-flops connected in a peculiar way. The method of
triggering is called the master-slave method. If we use the timing diagram of Figure 5.3
for D and E, draw the timing diagram for X and Y . Draw your conclusions.

Solution: The final output Y effectively is a snapshot of the input D on the

negative transition of E. This is shown in the timing diagram (right below).
5.1. EXERCISES 61

Exercise 5.5 Complete the timing diagram of Figure 5.9 (in the textbook) for a D
flip-flop with a negative edge-trigger (enabling the operation at the low-going edge of
the enable input).

Solution: Transfer of state from D to Q occurs at the negative transition of E.

Exercise 5.6 The JK flip-flop in Figure 5.5 (in the textbook) is in toggle mode.
Complete the timing diagram adjacent to it. Assume that the output Q is a 0 at the
start of the diagram.

Solution:

Exercise 5.7 Design an asynchronous up-counter using JK flip-flops with negative

edge-trigger. Verify its operation with a timing diagram.

Solution: The counters are triggered by Qs, which also serve as counter outputs.
62 CHAPTER 5. SEQUENTIAL LOGIC

Exercise 5.8 Complete Table 5.8 (in the textbook), listing all the possible variations
of inputs for an asynchronous counter that uses T flip-flops (JK flip-flops with inputs
tied).

Solution: The completed table is shown below.

Trigger Trigger Comes From Count Up Count Down
Positive Q Q′ Q
Positive Q′ Q Q′
Negative Q Q Q′
′
Negative Q Q′ Q

Exercise 5.9 Design a 2-bit asynchronous up-counter using D flip-flops.

Solution: The change on a binary digit must occur in the negative transition of
the previous digit.

Exercise 5.10 For the circuit of Figure 5.21 (in the textbook) make a timing diagram
of the clock, and the outputs Q and Q′ of each flip-flop, for nine cycles of the clock.
Make the propagation delays noticeably large in your diagram. Do the S outputs count
up or down?

Solution: The counter counts down.

Exercise 5.11 If the first state of the 3-bit LSFR is 0012 the next state can be cal-
culated with Equation 5.1: 1002 .

1. Calculate the remaining states in the sequence.

Solution: The sequence is 0012 , 1002 , 0102 , 1012 , 1102 , 1112 , 0112 .
5.2. PROBLEMS 63

2. Explain why we should avoid state 0002 .

Solution: State 0002 should be avoided because the LSFR does not change state
once it is in it.
Exercise 5.12 Wire four TMM2114 (1024 × 4) memory chips using a DMUX.
Solution:

Exercise 5.13 Wire a 2048 × 8 memory with TMM2114 chips.

Solution:

5.2 Problems
1. A second type of RS flip-flop uses NAND gates, as shown in Figure 5.35 (in the
textbook, shown below). This flip-flop differs from the NOR-based flip-flop, in
that the inputs are low-active. Write the truth table for the flip-flop.
64 CHAPTER 5. SEQUENTIAL LOGIC

Solution: On the left table shown next, we show the outputs for a sequence of
inputs. The sequence does not include 0-0 because the outputs are unstable.
The table on the right has the summary truth table for the flip-flop.
S R Q Q′
1 1 1 0
S R Q Q′
0 1 1 0
0 0 Qt−1 Unstable
1 1 1 0
0 1 1 Set
1 0 0 1
1 0 0 Reset
1 1 0 1
1 1 ? No change
0 1 1 0
1 1 1 0

2. Flip flops can be represented by a functional form.

(a) Show that the output of the RS flip-flop can be represented by the function
Qt = R′ · (Qt−1 + S). (NOTE THE CHANGE: R′ INSTEAD OF R.)
Solution: Assume NOR-based flip flop (not mentioned, but implicit). We
begin with an equation for Qt . From one of the NOR gates we get:

Qt = (S + Qt−1 )′ (5.1)

For the other NOR gate we have:

Qt = (R + Qt )′

or
′
Qt = R′ · Qt (5.2)
Replacing Eq. 5.1 into Eq. 5.2 we get

Qt = R′ (S + Qt−1 )

(b) Find the functional form of the NAND-based flip-flop of Problem 1.

5.2. PROBLEMS 65

Solution: Similarly we begin with Qt :

Qt = (R · Qt−1 )′ (5.3)
and continue with Qt :
Qt = (S · Qt )′
or
′ ′
Qt = S + Qt (5.4)
Replacing Eq. 5.3 into Eq. 5.4, we get
′
Qt = S + R · Qt−1

3. Using positive edge-triggered T flip-flops with clear and preset inputs, design
an asynchronous decade counter (it counts up to nine and then resets to zero).
Make a diagram.
Solution: The counter should reset after 10012 , or as soon as the count reaches
10102 . Thus we need to generate (S3 S1 )′ to be sent to the clear inputs (low
active).

4. Using T flip-flops with clear and preset inputs, design an asynchronous decade
count-down counter (it counts down to zero and resets to nine after zero). Make
a diagram.
Solution: When count goes to 11112 the counter should be reset to 10012 .
66 CHAPTER 5. SEQUENTIAL LOGIC

5. Show that the circuit of page 37 works as an edge-triggered D flip-flop. Do this

the following way.

(a) Fill in Table 5.15 (in the textbook) for S and R. Note that we must assume
initial values for Q and Q in the first line. We will assume they are “1”
and “0”, respectively.
(b) Complete the truth table ?? for Q and Q. You may want to do Problem 1
if you have not done so already.
(c) Make a summary statement describing how the circuit works.

Solution: (a,b). We assume that initially Q = 1 and Q = 0.

D E S R Q Q
0 0 1 1 1 0
0 1 1 0 0 1
0 0 1 1 0 1
1 0 1 1 0 1
1 1 0 1 1 0
1 0 1 1 1 0
(c) When E goes from 0 to 1, Q and Q take on new values, and these depend
on D: if D = 0, Q = 0 and Q = 1; and if D = 1, Q = 1 and Q = 0.

6. Using a 4-bit binary counter IC, shown in Figure 5.36 (in the textbook), design
a circuit that outputs a pulse for every six input pulses. Draw a timing diagram
of the input clock, counter outputs, and circuit output.
Solution: Will assume that it is an up-counter. The count sequence 00002 →
01012 → 00002 has six states, so we reset when the counter reaches 01102 . The
reset pulse can be used as a divide-by-6 pulse.

7. Design a synchronous counter that counts to six and resets to zero after that
state. Any unused states should go to zero. Make a diagram. Your design
should use JK flip-flops, with J and K not tied together as in a T flip-flop.
Solution: We must do first the excitation table for the JK flip-flop:
5.2. PROBLEMS 67

Qt Qt+1 J K Comment
0 0 0 × Q=0→ Q=0 when J = 0, K = 0 or J = 0, K =1
0 1 1 × Q=0→ Q=1 when J = 1, K = 0 or J = 1, K =1
1 0 × 1 Q=1→ Q=0 when J = 0, K = 1 or J = 1, K =1
1 1 × 0 Q=1→ Q=1 when J = 1, K = 0 or J = 0, K =0
The the excitation table for the counter is shown below.
Q2,t Q1,t Q0,t Q2,t+1 Q1,t+1 Q0,t+1 J2 K2 J1 K1 J0 K0
0 0 0 0 0 1 0 × 0 × 1 ×
0 0 1 0 1 0 0 × 1 × × 1
0 1 0 0 1 1 0 × × 0 1 ×
0 1 1 1 0 0 1 × × 1 × 1
1 0 0 1 0 1 × 0 0 × 1 ×
1 0 1 1 1 0 × 0 1 × × 1
1 1 0 0 0 0 × 1 × 1 0 ×
1 1 1 0 0 0 × 1 × 1 × 1
We then find expressions for the flip-flop inputs by using Karnaugh maps (not
shown) and find: J2 = Q1 Q0 , K2 = Q1 , J1 = Q0 , K1 = Q2 + Q0 , J0 = Q′1 + Q′2
and K0 = 1.

8. We are to design a state machine that consists of three negative edge-trigger

D-type flip-flops, all synchronously triggered by the same clock pulse. The
three outputs of the machine form the digital number S2 S1 S0 . An incomplete
schematic of the circuit is shown in Figure ??.
When input x = 0, the circuit makes the outputs change in the following se-
quence after each clock pulse: 1 → 3 → 5 → 7 → 0 → 2 → 4 → 6 → 1. When
the external input is x = 1, the circuit should follow the reverse sequence.
(a) Fill in Table 5.16 (in the textbook) with the values that the outputs S2 (t +
1), S1 (t + 1), and S0 (t + 1) should have after a clock pulse. Two rows of
68 CHAPTER 5. SEQUENTIAL LOGIC

entries have been filled in as an example.

(b) Fill in Table 5.16 (in the textbook) with the values that the D inputs
of the flip-flops should have so that the outputs change according to the
prescribed sequence.

(c) If the flip-flop inputs D2 , D1 , and D0 are Boolean functions of x, S2 (t),

S1 (t), and S0 (t), find the corresponding Karnaugh map and simplified
Boolean expressions for each of them.

(d) Complete the circuit of the figure by adding any gates and connections
that feed into D2 , D1 , and D0 .

Solution: (a) We follow the requirements for Si (t + 1). (b) Because of the way
D-flip-flops work, Di = Si (t + 1). The full table is shown below.

x S2 (t) S1 (t) S0 (t) S2 (t + 1) S1 (t + 1) S0 (t + 1) D2 D1 D0

0 0 0 0 0 1 0 0 1 0
0 0 0 1 0 1 1 0 1 1
0 0 1 0 1 0 0 1 0 0
0 0 1 1 1 0 1 1 0 1
0 1 0 0 1 1 0 1 1 0
0 1 0 1 1 1 1 1 1 1
0 1 1 0 0 0 1 0 0 1
0 1 1 1 0 0 0 0 0 0
1 0 0 0 1 1 1 1 1 1
1 0 0 1 1 1 0 1 1 0
1 0 1 0 0 0 0 0 0 0
1 0 1 1 0 0 1 0 0 1
1 1 0 0 0 1 0 0 1 0
1 1 0 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 1 1 0 1

(c) Karnaugh maps:

5.2. PROBLEMS 69

D2 = xS2′ S1′ + xS2 S1 + x′ S2 S1′ + x′ S2′ S1 D1 = S1′

D0 = x′ S2′ S0 + S2 S1′ S0 + xS1 S0 + x′ S2 S1 S0′ + xS2′ S1′ S0′

(d) The completed diagram:

70 CHAPTER 5. SEQUENTIAL LOGIC

9. Design a programmable four-digit combination lock.

Solution: Just like in the textbook:

10. Design the circuit of a digital clock.

(a) Design a 1 Hz clock signal using an LM555 timer chip.
Solution: The clock period is T = ln 2(RA + 2RB )C. If we pick C = 1 µF
then RA + 2RB ≃ 1443 kΩ.

(b) Using the 74LS190 decade counter ICs, design the circuitry for driving
seven segments for minutes and hours starting from the 1 Hz signal.
Solution: First we need to generate pulses for the minute counter, so we
need to divide the 1 Hz frequency by 60. We do this with the 74LS190 as
5.2. PROBLEMS 71

shown below. First we divide by 10 and then we divide by 6. The ICs reset
after 10, producing a ripple carry output, which serves as clock input for
the next IC. When the count on the second IC reaches 01102 , the counter
resets to 00002 via the low-active LOAD input of the counter. That signal
also serves as the minute input clock for the next stage.

The hi-minutes digit goes from 0 to 5, so counter resets at 6. Hours go

from 01 to 12, so must reset at 13. from 9 to 10 we use the automatic reset
of the low-hour digit.

(c) Design the circuitry to turn an AM/PM LED.

Solution: It is straightforward. We reset when the hours counter is at 13,
and send that to a toggle JK flip-flop that drives an AM/PM light.
11. We want to design a safety circuit for a laser lab. The output of the circuit is
a shutter line SH that commands an electronic shutter to block a high-power
laser. When SH = 1 the shutter blocks the laser beam. One logic input to the
circuit is the “lab-door” (LD) line. When the door of the lab is open, a sensor in
the door frame generates the logic signal LD = 1. It is set to LD = 0 otherwise.
An override (OV) line coming from a push button is 1 while the pushbutton is
pressed, 0 otherwise.
(a) Design a logic circuit for the following conditions: (i) When the lab door
72 CHAPTER 5. SEQUENTIAL LOGIC

is closed, the laser beam remains unblocked; (ii) when the door is opened
and the push button is not pushed, the laser is blocked; and (iii) when
the door is opened and the push button is pressed, the laser is unblocked.
Write a truth table and design the circuit.
Solution: We first draw a truth table for SH in terms of LD and OV.
LD OV SH Situation
0 0 0 Lab door closed
0 1 0 Lab door closed
1 0 1 Lab door open, no override,
laser blocked
1 1 0 Lab door open, override
For the circuit we use an AND gate. Let us assume that the switch is
debounced.

(b) When the lab door is opened, the laser shutter is activated and the beam
is blocked. Modify the circuit so that when the laser beam is blocked, it
remains so even if the door is closed or the push button is pressed. Add a
new push button input that, when pressed, resets the circuit to its normal
operating conditions.
Solution: There are many possibilities to do this, but basically we need to
latch a change. Here we show one that uses a D-flip-flop as shown in the
figure below. The shutter output feeds to the clock of a D flip-flop, which
sets the Q output high. It stays high unless the flip-flop is reset through
the clear input.
5.2. PROBLEMS 73

(c) Modify the push-button circuit so that OV = 1 for 15 seconds after the
push button is pushed, independently of when it is released. (This is so
that the laser operator can leave the lab without blocking the laser.)
Solution: For the delay we need a counter. Thus, we use a counter that
is run by 1 Hz, and resets itself after 15 clock pulses. The reset is done
in combination with a latch that enables and disables the counter. This
way, when OV=1, it triggers a flip-flop that enables a counter. This enable
line is also OV′ , which disables the laser shutter in case the door opens.
Once the counter count reaches 15, the counter resets itself (by loading 0
to the count), and the flip-flop that enables the counter, setting OV’=1
and enabling the laser shutter mechanism. The diagram is given below.

(d) Design a four-digit combination lock that provides an alternative way of

generating OV = 1 for 15 seconds. (This keypad will be put outside the
lab and will allow the operator to get back into the lab without blocking
the laser.)
Solution: This is the same solution as that of problem 9. Its output would
be the new OV signal.
12. A student wants to redesign the stop light at the intersection College Street
and Broad Street. It is the only stop light between campus and off-campus
apartments.
(a) Using a 4-bit counter, draw the diagram of a circuit that will turn the
lights of the College Street stop-light in the following repetitive sequence:
green light for 20 seconds, yellow light for 5 seconds, and red light for 40
seconds. Assume that the input clock frequency is 1 Hz. Assume also that
the stop light will take three high-active inputs, one for each light, that
when true, will turn on the corresponding light.
Solution: The light times are in multiples of 5 s, so we can divide the 1 Hz
clock by 5. That would give us a total of 13 states: 4 for green, 1 for yellow
and 8 for red. To go through 13 states we need at least a 4-bit counter. We
74 CHAPTER 5. SEQUENTIAL LOGIC

can use the counter lines as input variables of three functions, one for each
color. Below we draw a truth table, with the states corresponding to each
light color. Once we do the corresponding Karnaugh-map simplification
we get

G = C3′ C2′

Y = C3′ C2 C1′ C0′

R = C3 + C2 C0 + C2 C1

The circuit will have 13 states (0 to 12). The circuit resets at 13, but we
want the light to stay red in the brief time that 13 is reached, so we force
13 to stay red. It will help in the design of the next section (see below).
Because states 14 and 15 are never reached, we put don’t cares for them
in the truth table.
C3 C2 (t) C1 (t) C0 (t) G Y R
0 0 0 0 1 0 0
0 0 0 1 1 0 0
0 0 1 0 1 0 0
0 0 1 1 1 0 0
0 1 0 0 0 1 0
0 1 0 1 0 0 1
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 0 0 1
1 0 0 1 0 0 1
1 0 1 0 0 0 1
1 0 1 1 0 0 1
1 1 0 0 0 0 1
1 1 0 1 0 0 1
1 1 1 0 × × ×
1 1 1 1 × × ×
In the circuit we also reset the counter when it reaches 13. We draw only a
box for a divide-by-5 circuit, but it can be implemented by another, 3-bit,
counter that resets when the count reaches 5. The reset pulse can be used
as the divided signal.
5.2. PROBLEMS 75

(b) During summer, when College Street has very low traffic, the stop light
switches into the following mode of operation: After finishing the red-light
cycle, it will not change to green unless an external input (coming from a
car-sensing coil underneath the pavement) is high. Modify the circuit so
that it operates in this mode.
Solution: We have a signal that resets the stop light when the counter
reaches 13. Instead of resetting the stop light, we inhibit the input clock
through an AND gate. Therefore the counter will stay at 13, leaving the
light red indefinitely. The car sensing coil clears the counter so the light
turns green and the cycle restarts.

(c) A second car-sensing coil is located upstream from the first one so that if
the light is green and a car activates it, the green light remains unchanged
for at least 5 seconds after the car activates it. This way, the car gets a
chance to make it through the intersection.
Solution: In this section, we want a green light to stay green. Therefore a
combination of count 3 (last state of the green light) and a 1 from the car
sensing coil (all conditions enforced a NAND gate), produces a low-going
signal into the load input of the counter, which loads count 2, giving the
green light 5 more seconds. If we want more we could load counts 1 or 0.
76 CHAPTER 5. SEQUENTIAL LOGIC

The rest of the circuit remains the same.

(d) This semester, you have a late-night activity (academic of course) that
gives you real trouble getting up in the morning. As a consequence, you are
always rushing to campus so that you are not late to class. But that College
Street stop light always gets in the way. In a very minor transgression
from an otherwise fine law-abiding citizen, you decided to add a secret
component to the College Street stop light circuit. It gets activated by
remote control so that when you are coming toward the intersection in
your car, the light turns to or stays green while you are rushing through
the intersection, ensuring the perfect timing of your trip to class. Set
your own conditions for this to happen and draw a circuit diagram. Note:
Your design has to be clear and well explained. Unreadable diagrams and
algorithms will be marked wrong even if they work!
Solution: Here we have a number of possibilities. Here is one solution: we
generate a signal that is 1 when the button is pushed. This signal can be
ORed to the signal from the second coil so that when the counter reaches
3 (green) it gets reset to 2, keeping the light green. If the signal is left on,
the counter will remain in this “green loop.” If the light is red, we can use
the signal from R to either reset the counter or load 2.

13. Design an asynchronous 4-bit binary “down counter” with positive edge-trigger
JK flip-flops, with count outputs C0 , C1 , C2 , and C3 .

(a) Draw an accurate timing diagram of the input clock pulse CLK, Q0 , Q′0 ,
Q1 , and Q′1 for six periods of CLK.
Solution: The design has a couple of possibilities. Here we use one where
the trigger comes from the Q′ output, and so the count-down digits are also
the Q′ s. The alternative with positive edge-trigger flip-flops is to trigger
with the Qs, in which case the Qs are also the count-down outputs (see
5.2. PROBLEMS 77

Exercise 5.8). The circuit and corresponding timing diagrams are shown
below.

(b) Add the necessary wiring to the circuit so that it loads 1100 when it reaches
0000. Assume that the flip-flops have clear and preset (low-active) inputs.
(c) Add the necessary wiring to the circuit such that when an external input
START/STOP is 1, the counter counts, and when it is 0, it stops.
(d) Using 2 × 1 multiplexers modify the wiring so that when an external input
U/D is 1, the outputs of the circuit C3 , C2 , C1 , and C0 count up, and when
the input is 0, the outputs count down.
Solutions (b), (c), (d): The solutions for the different parts are shown below
in the same circuit. The last one, where the counter counts up needs the
additional circuitry from the U/D to prevent it from looping between 12
and 15 when it counts up.
78 CHAPTER 5. SEQUENTIAL LOGIC

14. A calendar clock has a 4-bit month counter. Design a synchronous counter with
the following specifications:

(a) The month count should increase with the rising edge of a TTL pulse that
is an input to the circuit.
(b) The circuit should output a pulse every time the month count goes from
month 12 to month 01 (every year, so that it increments a year counter,
which is not part of your design).
(c) The circuit should have four binary outputs that represent the month
count.
(d) You can use only positive edge-trigger JK flip-flops that do not have preset
or clear inputs.

Solution: First we need to write the excitation table. To simplify the design,
we will use T flip-flops (JK with their inputs tied together). There are several
unused states: 00002 , 11012 , 11102 and 11112 . We force the next state for these
states to be 00012 .
Q3,t Q2,t Q1,t Q0,t S3,t+1 S2,t+1 S1,t+1 S0,t+1 T3 T2 T1 T0
0 0 0 0 0 0 0 1 0 0 0 1
0 0 0 1 0 0 1 0 0 0 1 1
0 0 1 0 0 0 1 1 0 0 0 1
0 0 1 1 0 1 0 0 0 1 1 1
0 1 0 0 0 1 0 1 0 0 0 1
0 1 0 1 0 1 1 0 0 0 1 1
0 1 1 0 0 1 1 1 0 0 0 1
0 1 1 1 1 0 0 0 1 1 1 1
1 0 0 0 1 0 0 1 0 0 0 1
1 0 0 1 1 0 1 0 0 0 1 1
1 0 1 0 1 0 1 1 0 0 0 1
1 0 1 1 1 1 0 0 0 1 1 1
1 1 0 0 0 0 0 1 1 1 0 1
1 1 0 1 0 0 0 1 1 1 0 0
1 1 1 0 0 0 0 1 1 1 1 1
1 1 1 1 0 0 0 1 1 1 1 0
The flip-flop inputs Ti ’s are functions of the Qi,t ’s. The month-digits are the
Qi ’s. The next step is to do the Karnaugh maps for each input (not shown),
and obtain simplified expressions for each. They are:

T3 = M3 M2 + M2 M1 M0
5.2. PROBLEMS 79

T2 = M3 M2 + M1 M0
T1 = M3′ M0 + M2′ M0 + M1 M0 + M3 M2 M1
T0 = M3′ + M2′ + M0′
The output to the year counter is:

Y = M3′ M2′ M1′ M0

Following we show the circuit.

15. We want to drive a stepper motor in high-torque mode. A stepper motor (see
Figure 5.38 in the textbook) has four coils.
The motor operates in high-torque mode when its coils are energized consec-
utively following a four-step cycle that repeats continuously. Each cycle step
corresponds to a motor step. Table 5.17 (in the textbook, shown below) lists
the four-step sequence in which the coil must be energized. A logic 1 denotes
that the coil is energized.
Step Coil 1 Coil 2 Coil 3 Coil 4
1 1 0 0 1
2 1 1 0 0
3 0 1 1 0
4 0 0 1 1
80 CHAPTER 5. SEQUENTIAL LOGIC

The circuit must take an input digital pulse to step a 4-bit synchronous counter
circuit through the sequence specified in the table. The counter must use T-flip
flops. Assume that the unused states never occur. Each of the counter lines
enables a motor coil.

Solution: First we write the excitation table. Notice that there are many unused
states.

C1,t C2,t C3,t C4,t C1,t+1 C2,t+1 C3,t+1 C4,t+1 T3 T2 T1 T0

0 0 0 0 × × × × × × × ×
0 0 0 1 × × × × × × × ×
0 0 1 0 × × × × × × × ×
0 0 1 1 1 0 0 1 1 0 1 0
0 1 0 0 × × × × × × × ×
0 1 0 1 × × × × × × × ×
0 1 1 0 0 0 1 1 0 1 0 1
0 1 1 1 × × × × × × × ×
1 0 0 0 × × × × × × × ×
1 0 0 1 1 1 0 0 0 1 0 1
1 0 1 0 × × × × × × × ×
1 0 1 1 × × × × × × × ×
1 1 0 0 0 1 1 0 1 0 1 0
1 1 0 1 × × × × × × × ×
1 1 1 0 × × × × × × × ×
1 1 1 1 × × × × × × × ×

Then we simplify the corresponding Karnaugh maps and obtain several possible
solutions: T1 = T3 = C1 C2 + C3 C4 = C4′ C3′ + C1′ C2′ , T2 = T4 = C4 C1 + C3 C2 =
C4 C3′ + C2 C1′ . The circuit follows.
5.2. PROBLEMS 81

16. Design a circuit that generates the timing cycle of a washing machine.
(a) Using 4-bit counters, design a circuit that generates a pulse every minute
(1/60 Hz) when the input clock has a 60 Hz frequency. You can use several
frequency dividers in tandem if you want.
Solution: The circuit shown below is a divide by 60 circuit consisting of
two decade counters. We can use two of these in a row to divide by 3600.

(b) Suppose that the analog electrical hardware of the washing machine has
four low-active inputs: F ILL, W ASH, RIN SE, and DRAIN . These
inputs consecutively activate their respective mechanical functions for the
times given in Table 5.18 (shown below).
Function Time (min)

F ILL 2
W ASH 4
RIN SE 4
DRAIN 2
82 CHAPTER 5. SEQUENTIAL LOGIC

Design a circuit that has outputs for each of the washing machine cycles.
The outputs should be activated consecutively and should last the time
given by the table. The input to the circuit is the 1/60 Hz signal of part
(a). Figure 5.39 (in the textbook) shows the block diagram of the circuit.
Solution: The times of the table are divisible by 2, so we can further divide
by two and end up with a cycle requiring 6 steps. This can be implemented
with a 3-bit counter. The table below generates the signals that implement
each of the functions of the washing cycle. One technicality is that we turn
all functions off when we reach count 1102 (that is, the seventh state). This
function will be used later. The count 1112 is never reached and so we use
don’t cares for it.
w2 w1 w0 F W R D
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 0 1 1
0 1 1 1 1 0 1
1 0 0 1 1 0 1
1 0 1 1 1 1 0
1 1 0 1 1 1 1
1 1 1 × × × ×
Simplifying with Karnaugh maps:
5.2. PROBLEMS 83

The simplified functions are:

F = w2 + w1 + w0

W = w1 w0 + w2 + w1′ w0′

R = w1 w0′ + w1′ w0 + w2′ w1′

D = w2′ + w0′

The circuit is straightforward. We have a 3-bit binary counter, and its

output generates the functions specified above. We could build this with
three individual flip-flops via an asynchronous counter, or we could use a
counter IC.
(c) Modify the circuit of the previous part to generate an output every time the
washing machine cycle is completed. Use this pulse to reset the washing
cycle.
Solution: Here we NAND the outputs of the counter when it reaches 1102 .
That pulse is used to reset the counter.

(d) Design a circuit that inhibits the 60 Hz input when the cycle is finished
(otherwise, the washing machine will continue washing forever). Include an
additional input to restart the cycle (see the block diagram in Figure 5.40
of textbook).
Solution: We use a flip-flop to generate a 0 with the low-going transition
of the resetting signal. This 0 is ANDed with the input clock, stopping the
counter from moving forward. The cycle starts when a puchbutton resets
the clock-inhibiting flip-flop.
84 CHAPTER 5. SEQUENTIAL LOGIC

17. Verify that the 4-bit LFSR goes through all 15 states. Pick any starting value
except zero.
Solution: The sequence that follows starts with 00012 . The first column gives
the bit to be shifted to the right into the number, which is generated by the XOR
operation of the two least significant bits of the number. All fifteen non-zero
numbers are cycled through.
Shift in N3 N2 N1 N0 N (base 10)
1 0 0 0 1 1
0 1 0 0 0 8
0 0 1 0 0 4
1 0 0 1 0 2
1 1 0 0 1 9
0 1 1 0 0 12
1 0 1 1 0 6
0 1 0 1 1 11
1 0 1 0 1 5
1 1 0 1 0 10
1 1 1 0 1 13
1 1 1 1 0 14
0 1 1 1 1 15
0 0 1 1 1 7
0 0 0 1 1 3
1 0 0 0 1 1

18. Using memory-cell blocks like the one shown on the left side of Figure 5.41 (in
the textbook), construct the internal wiring of a 8 × 2 memory chip shown on
the right side of Figure 5.41. Make a diagram.
Solution:
5.2. PROBLEMS 85

19. Draw the circuit diagram for a section of memory that contains four 2048 × 4
memory chips connected to a 16-bit address bus and an 8-bit data bus. Make
the proper connections with all the address and data lines so that the starting
address is 200016 .

Solution:
86 CHAPTER 5. SEQUENTIAL LOGIC

20. For the circuit of Figure 5.42 (in the textbook):

(a) What is the memory capacity of the chip?

Solution: 12 bits correspond to 212 = 4096 memory locations.
(b) What are the starting and ending addresses?
Solution: Starting: 500016 . Ending: 5FFF16 . The decoding of the IC
should look like:

(c) By adding another identical memory chip, modify the circuit so that the
new circuit has twice the memory capacity as before. Arrange it so that
the second chip occupies the memory space following the one of the first
chip.
Solution: The memory IC contains an address space that is accessed by
address lines A0 to A11 . The decoding circuitry must enable the IC when
5.2. PROBLEMS 87

A15 A14 A13 A12 = 516 , and rmSEL = 0 (memory select). If we want to
expand the memory the new address space will decode from 600016 to
6FFFF16 . Thus the address decoding for the second IC must enable the
IC when A15 A14 A13 A12 = 616 , as shown below.

21. The circuit of Figure 5.43 (in the textbook) uses an 8-bit comparator chip as
part of the address decoding. Determine the memory space of each memory
chip in the circuit shown. Explain your reasoning.
Solution: Each IC has 9 address inputs. Thus, it stores 29 = 512 memory
locations of 4 bits each. The table below shows the beginning and ending
addresses of each IC.
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hex
Chip-1 start 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 5800
Chip-1 end 0 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 59FF
Chip-2 start 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 5C00
Chip-2 end 0 1 0 1 1 1 0 1 1 1 1 1 1 1 1 1 5DFF
22. A memory board addressed by a computer using a 16-bit bus has three memory
chips. Use a 4-to-16 line-decoder chip to do the address decoding with the
following conditions:
(a) The first chip has 12 address lines and a starting address A00016 .
(b) The second chip has 13 address lines and a starting address C00016 .
(c) The third chip’s memory space starts at 680016 and ends at 6FFF16 .
Solution: The summary of the address spaces is:
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Hex
Chip-1 start 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 A000
Chip-1 end 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 AFFF
Chip-2 start 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5C00
Chip-2 end 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 5DFF
Chip-3 start 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 6800
Chip-3 end 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 6FFF
The decoding circuit is shown below.
88 CHAPTER 5. SEQUENTIAL LOGIC
Chapter 6

AC Signals

6.1 Exercises
Exercise 6.1 Verify the following relationships:

1. zz ∗ = a2 + b2
Solution: zz ∗ = (a + jb)(a − jb) = a2 − ajb + jba + b2 = a2 + b2 .

2. z + z ∗ = 2a
Solution: z + z ∗ = (a + jb) + (a − jb) = 2a.

3. z − z ∗ = j2b
Solution: z + z ∗ = (a + jb) − (a − jb) = 2jb.

4. (z ∗ )∗ = z
Solution: (z ∗ )∗ = (a − jb)∗ = (a + jb) = z.

Exercise 6.2 Show that the complex impedance of the inductor is given by Equa-
tion 6.38. Assume that the current through the inductor is I = I0 exp[jωt].

Solution:
dI d
V =L = L (I0 ejωt ) = LI0 jωejωt = jωLI
dt dt
Therefore ZL = jωL.

89
90 CHAPTER 6. AC SIGNALS

6.2 Problems
1. An electrical signal oscillates between 0 and V. Find the RMS value of the wave
if the wave is

(a) Square
Solution: The RMS voltage is defined as:
√
1
VRMS = (Sum of V 2 over a period)
T

For a square signal, where V (t) = 0 for 0 ≤ t < T /2 and V (t) = V for
T /2 ≤ t < T , it is: √
1 2T V
VRM S = V =√
T 2 2
.
(b) Sinusoidal
Solution: The voltage is given by
V V
V (t) = sin ωt +
2 2
The RMS voltage is
[ ]1/2
1∫T 2
VRMS = V (t) dt
T 0
[ ]1/2
V2 ∫ T 2
= (sin ωt + 1) dt
4T 0
[ ( ∫ T )]1/2
V2 ∫ T 2
∫ T
= sin ωt dt + 2 sin ωt dt + dt
4T 0 0 0
[ ( )]1/2
V2 T
= +0+T
4T 2
[ ]1/2
3V 2
=
8
√
3V
= √
2 2

(c) Triangular
6.2. PROBLEMS 91

Solution: The triangular wave between 0 and T /2

2V
V (t) = t
T
So we will calculate the area for half a period and multiply it by 2.
[ ( ∫ )]1/2
1 T /2 4V 2 2
VRMS = 2 t dt
T 0 T2
[ ( )]1/2
1 4V 2 T 3
= 2 2
T T 24
[ ]1/2
V2
=
3
V
= √
3
2. If z1 = 1 + j, z2 = 1 − j, and z3 = −2j, calculate the magnitude and phase (in
radians) of
(a) z1
√
Solution: |z1 | = 2, ϕ = tan−1 1 = π/4.
(b) z2
√
Solution: |z2 | = 2, ϕ = tan−1 (−1) = −π/4.
(c) z3
Solution: |z3 | = 2, ϕ = tan−1 (−2/0) = −π/2 = 3π/3.
(d) z1 + z2
Solution: z1 + z2 = 2, |z1 + z2 | = 2, ϕ = tan−1 (0/2) = 0.
(e) z1 − z3
√
Solution: z1 − z3 = 1 + 3j, |z1 − z3 | = 10, ϕ = tan−1 (3) = 1.25 rad.
(f) z1 z2
Solution: z1 z2 = 2, |z1 z2 | = 2, ϕ = tan−1 (0/2) = 0.
z1 +z2
(g) z2
Solution:
z1 + z2 2
=
z3 1−j
,  
 z1 + z2  √
 = 2
 
z3
ϕ = tan−1 (1) = π/4
92 CHAPTER 6. AC SIGNALS

z1
(h) z3
Solution:
√ jπ/4
z1 1+j 2e
= = −jπ/2
z3 −2j 2e
 
 z1  1
 = √
 
z3 2

ϕ = π/4 + π/2 = 3π/4

z2
(i) z1 −z3
Solution:
√ −jπ/4
z2 1−j 2e
= = √ j tan−1 3
z1 − z3 1 + 3j 10e
  √
 z2  2 1
 = √ =√
 
z1 − z3 10 5

ϕ = π/4 − tan−1 3

z3
(j) z1
+ z2
Solution:

z3 −2j
+ z2 = + 1 − j = −j(1 − j) + 1 − j = −2j
z1 1+j
 
 z3 
 + z2  = 2

z1

ϕ = tan−1 (−0/2) = −π/2

3. If the angular frequency of the source is 105 rad/s, calculate the equivalent
impedance between A and B in Figure 6.18 (in the textbook, shown below).
6.2. PROBLEMS 93

Solution: Zeq = R − j/(ωC1 ) + jωL1 + (jωC2 + jωC3 − j/(ωL2 ))−1 , where

R = 4 kΩ, C1 = 5000 pF, C2 = 1000 pF, C3 = 4000 pF. The answer is
Zeq = (4000 + 37050j) Ω.

4. Consider the circuit of Figure 6.19 (in the textbook, shown below). The AC
supply has a peak voltage of 10 V and a frequency of 1 kHz. The resistor has
a value of 1 kΩ, and the capacitor has a capacitance of 0.1 µF.

(a) Find the peak value of the current through the circuit.
Solution: The impedance of the circuit is z = R − j/(ωC), so replacing
values, we get |z| = 1.88 kΩ. The amplitude of the current is I = V /z =
5.32 mA.
(b) Explain how the current “flows” through the capacitor.
Solution: Current flows by charging one capacitor plate and discharging
the other one.
(c) What is the peak voltage between points A and B?
Solution: The voltage drop at the capacitor is VAB = I[−j/(ωC)]. The
peak value is VAB = 8.47 V.
94 CHAPTER 6. AC SIGNALS

(d) We change the frequency of the source so that the peak voltage through
the capacitor is the same as the peak voltage through the resistor
i. What is the value of the frequency?
Solution: The condition is 1/(ωC) = R, so ω = 104 rad/s, and f =
ω/2π = 1.59 kHz.
ii. What are the peak voltages across the resistor and capacitor?
Solution: With the new frequency z ′ = 1.414 kΩ, so I ′ = 7.07 mA.
Therefore, VR = 7.07 V and VAB = 7.07 V.
iii. Explain why they are not 5 V.
Solution: They are not 5V because the voltages across R and C are
90 degrees out of phase, so the voltages add in quadrature.

5. Consider the circuit of Figure 6.20 (in the textbook, shown below). A capacitor
with C = 0.25 µF is in series with two resistors, R1 = 1500 Ω and R2 = 3500 Ω.
The peak current through the circuit is I0 = 2 mA, and its angular frequency
is ω = 180 rad/s.

(a) Find the voltages on each component (amplitude and phase).

Solution: We take the phase of the current to be zero. The voltages across
the components are:
V1 = I0 R1 = 3V, ϕ = 0

V2 = I0 R2 = 7V, ϕ = 0
I0 j
V3 = − R1 = −44.4j V, |V3 | = 44.4 V, ϕ = −π/2
ωC
(b) Find the amplitude of the voltage of the source.
Solution: VS = V1 + V2 + V3 = (10 − 44.4j) V, V0 = |VS | = 45.56 V,
6.2. PROBLEMS 95

(c) Find the impedance of the circuit.

Solution:
j
Z = R1 + R2 − = (5 + 22.2) kΩ, |Z| = 22.8 kΩ
ωC
(d) Find the phase between the source voltage and the current.
Solution: ϕ = tan−1 (−44.4/10) = −77.3◦ .
(e) Write the expressions for the voltage and current as a function of time
(amplitudes and phases all included explicitly).
Solution: I = 2 cos ωt mA, VS = 45.6 cos(ωt − 77.3◦ ) V.
(f) What is the average power dissipated by the resistors?
Solution: PR = V1 I0 + V2 I0 = 0.02 W.
(g) What is the average power dissipated by the source?
Solution: PS = 0.02 W
(h) Explain the relationship between the results in (f) and (g).
Solution: The capacitor does not dissipate any power, so the power dissi-
pated by the source is the same as the power dissipated by the resistors.

6. In the circuit of Figure 6.21 (in the textbook, shown below), the voltage source
is VG = 10 sin ωt V, where the frequency of the source is 20 kHz.

(a) Find the current through the resistor.

Solution: IR = VG /R = 5 mA.
(b) Find the current through the inductor.
Solution: IL = VG /(jωL) = −2.5 mA.
(c) Find the amplitude of the total current flowing out of the source.
Solution: IT = IR + IL = (5 − 2.5j) mA, |IT | = 5.6 mA.
(d) Find the phase between the voltage of the source and the current flowing
through it.
Solution: Assuming that the phase of the source is zero, ϕ = tan−1 (−2.5/5) =
−26.4◦ .
96 CHAPTER 6. AC SIGNALS

7. The input voltage for the circuit shown in Figure 6.22 (in the textbook, shown
below) is given by VG (t) = V0 cos ωt.

(a) Find the equivalent impedance of all three components in the complex
notation.
Solution: Z = R + jωL − j/(ωC) = R + j(ωL − 1/(ωC)).

(b) What is the expression for amplitude of the current?

Solution:
V0 V0
I0 = =√ ( )2
|Z|
R2 + ωL − 1
ωC

(c) What is the expression for the phase difference between the current and
the voltage of the source?
Solution:
( )
ωL − 1
ϕ = tan−1  
ωC
R

(d) If V0 =10 V, R=10 kΩ, L=2.5 H, and C=0.01 µF, make a plot (using Excel
or your favorite software) of the amplitude of the current vs. frequency (f
not ω).

(e) Make a plot of the amplitude of the voltage across the resistor as a function
of frequency.
Solution: The√graph of the current has a maximum at the resonance con-
dition ω = 1/ LC = 1 kHz.
6.2. PROBLEMS 97

(f) If we assume V is an input voltage and VR is the output voltage, what

utility can you find for this circuit?
Solution: Since the voltage across the resistor is proportional to the cur-
rent, the circuit could be used as a band-pass filter.

8. In the circuit of Figure 6.23 (in the textbook, shown below):

(a) If the amplitude of the voltage is 20 V, calculate the current flowing

through each element when the angular frequency is 100 rad/s.
Solution: IR = V0 /R = 10 mA, IL = V0 /(jωL) = −100j A, IC = V0 jωC =
4j mA.
(b) Calculate the frequency at which the current leaving the supply is maxi-
mum.
Solution: [ ( )]−1
1 1
Zeq = + j ωC −
R ωL
When ω → 0, Zeq ∼ jωL, so I has a maximum.
When ω → ∞, Zeq ∼ −j/(ωC), so I has a maximum here too.
98 CHAPTER 6. AC SIGNALS

(c) Calculate the phase between the current and voltage for parts 8a and 8b.
Solution: In the first case, the current is dominated by the current flowing
through the inductor: I = (0.01 + 99.99j) A. The phase is ϕ = −89.99◦ .
At the two extremes: for ω → 0, ϕ →√−90◦ ; and for ω → ∞, ϕ → 90◦ .
(The resonance condition is at ωc = 1/ LC = 15.8 k-rad/s, much higher
than 100 rad/s.)

9. In the circuit of Figure 6.19 (in the textbook, shown below), the supply has a
peak voltage of 10 V and a frequency of 1 kHz. The resistor has a value of 1
kΩ, and the capacitor has a capacitance of 0.1 µF.

(a) Find the Thevenin equivalent circuit.

Solution:
−j
VAB = ωC
V0 = (7.17 − 4.5j) V
R− j
ωC

|VThev | = |VAB | = 8.5 V

( −1 )
1
ZThev = + jωC = (717 − 450j) Ω
R
|ZThev | = 847 Ω
(b) If we varied the frequency of the source, at what frequency would the
output impedance be:
i. Maximum
Solution: When ω → 0, ZThev ∼ R = 1 kΩ.
ii. Minimum
Solution: When ω → ∞, ZThev ∼ 0.
iii. What are the impedances for cases 9(b)i and 9(b)ii?
Solution: Given above, 1 kΩ and 0.
6.2. PROBLEMS 99

(c) We now connect a resistor R in series with a 0.02 µF as a load connected

to points A and B.

i. What value of resistor R will not load the circuit when the frequency
is 1 kHz?
Solution: The impedance of the load is ZL = R − j/ωC. At ω = 1
kHz 1/ωC = 7.96 kΩ, so no value of R will load the circuit.
ii. What value of resistor R will not load the circuit regardless of fre-
quency?
Solution: Let us call C ′ = 0.02µF. Note that C ′ = C/5. When ω → ∞
ZThev ∼ 1/ωC. So, if R = 0 the source will be loaded (VAB−loaded =
(5/6)VAB−unloaded - 5/6=0.833). For example, if ω = 5 · 105 rad/s,
1/ωC = 20 Ω and 1/ωC ′ = 200 Ω. A numerical solution of the
problem yields: for ω ≤ 8700 rad/s, no value of R loads the circuit.
Above that value, there are values of R that load the circuit. A safe
value for R would be 5 times 1000 Ω, or 5000 Ω, and the circuit will
not be loaded regardless of the frequency.

10. Suppose we want to apply a voltage of 2 V (± 10%) to a 10 kΩ resistor, but

we have only a 10 V power supply. Design a voltage divider that will give 2 V
from the 10 V power supply. Choose the resistors of the divider so that: (a)
the maximum current put out by the supply does not exceed 100 mA, and (b)
when the divider is connected to the 10 kΩ resistor, the voltage does not drop
below 1.8 V (a 10% loading of the divider).

Solution: A divider that gives us 2 V from a 10 V is one that has resistors R

and 4R, with the load connected to the resistor R. The Thevenin resistance will
be ZThev = 4R/5. The loading condition is RThev < 0.1Rload , so if Rload = 10
kΩ, then R ≤ 1.25 kΩ. If we want the current to be below 100 mA, then
the total impedance cannot be below 100 Ω. If the divider is not loaded, then
R ≥ 100Ω/5 = 20 Ω. If we include the load, then R ≥ 20.008 Ω.

11. Find the Thevenin equivalent circuit between points A and B for the circuit
shown in Figure 6.24 (in the textbook, shown below).
100 CHAPTER 6. AC SIGNALS

Solution: VThev = 2V0 /5 = 4 V, ZThev = 2kΩ/5 = 400 Ω.

12. For the circuit of Figure 6.25 (in the textbook, shown below):

(a) Find the Thevenin equivalent circuit between A and B.

Solution: VThev = 2 V, ZThev = 667 Ω.
(b) Determine what value of load resistance applied to A and B will not load
the circuit.
Solution: Applying the 10% rule, Zload = 6.67 kΩ.
(c) Find the Norton equivalent circuit.
Solution: INorton = VThev /ZThev = 3 mA, ZNorton = ZThev = 667 Ω.
(d) What load maximizes the delivered power?
Solution: ZL = ZThev = 667 Ω.

13. Use the Thevenin equivalent of the circuit of Figure 6.26 (in the textbook, shown
below) to find the voltage that is applied to a 3 kΩ load connected across A
and B.
6.2. PROBLEMS 101

Solution: VThev = 2 V, ZThev = 1500 Ω.

102 CHAPTER 6. AC SIGNALS
Chapter 7

Filters and the Frequency Domain

7.1 Exercises
Exercise 7.1 The -3 dB frequency of the n-stage filter is not ωc . Find an expression
for the -3 dB frequency as a function of n and ωc .

Solution: The transfer function of the n-stage filter is

 n
1
T = √ 
1 + (ω/ωc )2

The transfer function in dB is:

( ) ( )
n
20 log T3dB = 20 log 1 + (ω3dB /ωc )2
2
= −3dB
ω
1+ = 103/10n
ωc
√
ω3dB = ωc 100.3/n − 1

Exercise 7.2 Derive Equation 7.28 (in the textbook) using Zin = V1 /I1 and V2 /I2 =
ZL .
V1 V2
Solution: The definitions for input and load impedance are: Zin = I1
and I2
= ZL
N1
The transformer equations are V1 = N 2
V2 and I1 = N 2
N1 2
I
Combining these equations we get:
N1
V ( )2
N2 2 N1
Zin = N2 = ZL
I
N1 2
N2

103
104 CHAPTER 7. FILTERS AND THE FREQUENCY DOMAIN

Exercise 7.3 Sketch the square wave that would give b0 = −V0 /2.

Solution: The waveform is:

Exercise 7.4 Sketch on the previous graph of the square wave:

2V0
1. π
sin( 2πt
T
)

2V0
2. 3π
sin( 6πt
T
)

2V0
3. 2π
sin( 4πt
T
)

4. Use those sketches to explain why terms (1) and (2) are part of the Fourier
decomposition and not term (3).

Solution: The mentioned “previous graph” refers to Fig. 7.21 in the textbook.
The answers to parts 1 to 3 are given in the same graph, below.

Terms (1) and (2) are solutions because they are symmetric about the square wave.
Term (3) would not contribute to a building up a square wave because it contributes
equally to both high and low sections of the square wave.
7.2. PROBLEMS 105

7.2 Problems
1. For the filter of Figure 7.24 (in the textbook, shown below:

(a) Identify the type of filter.

Solution: Low-pass filter.
(b) Find the cutoff frequency.
Solution: ωc = 1/RC = 1 · 104 rad/s.
(c) Attach a second stage with the same cutoff frequency that does not load
the first one.
Solution: This is shown in the figure below. Note that the product of the
resistor and capacitor in each stage is the same, and equal to the reciprocal
of the cutoff frequency.

2. Design an RC low-pass filter with a cutoff frequency at 2 kHz, using a capacitor

of 0.1 µF.

(a) Show a circuit diagram, and your calculations in obtaining R.

Solution: The circuit is shown below. R = 1/(2πf C) = 796 Ω.
106 CHAPTER 7. FILTERS AND THE FREQUENCY DOMAIN

(b) Make a sketch of the absolute value of the input impedance |Zin | of the
filter vs. frequency. What are the limiting values of |Zin |?
Solution: Zin = R − j/(ωC),
√ √
1 ωc
|Zin | = R2 + 2 2 =R 1+
ω C ω

When ω → 0, |Zin | → ∞; and when ω → ∞, |Zin → R.

(c) Make a similar sketch of the output impedance of the filter.

Solution: Zout = (1/R + iωC)−1 .

1 R
|Zout | ( )1/2 = ( )1/2
1 ω2
R2
+ ω2C 2 1+ ωc2

When ω → 0, Zout = R; and when ω → ∞, Zout → 0. The graph of the

output impedance is given next.
7.2. PROBLEMS 107

(d) If we connect the filter to a load resistance RL , what minimum value should
it have in order to not load the filter?
Solution: 10R = 8 kΩ.
(e) Design two more filter stages to sharpen the filter curve (with the same
cutoff frequency). Your design should address the problem of loading.
Make a log-log plot of the filter curve using the software of your preference.
108 CHAPTER 7. FILTERS AND THE FREQUENCY DOMAIN

3. An audio source has an output impedance of 200 Ω. Design a filter that trans-
mits more than 90% of frequencies above 15 kHz, but less than 10% of fre-
quencies below 0.2 kHz (CORRECTION). Draw a complete circuit diagram,
including resistor and capacitor values.
Solution: ERRATUM: The lower frequency must be 0.2 kHz, or the solution is
not possible. The filter must be a high-pass filter. If the audio source has an
output impedance of 200Ω, then using our factor-of-10 rule we conclude that the
input impedance of the filter must be 2 kΩ. The absolute value of the transfer
function of the filter is
R
|T | = √
R2 + ω21C 2

We solve for C when |T | = 0.9, R = 2kΩ and f = 15 kHz, and get C = 0.011µF.
At 0.2 kHz |T | = 0.028, which is less than 0.1 (it would be 0.27 with f = 2
kHz). We can also calculate the value of the capacitor when f = 0.2 kHz and
|T | = 0.1 and get C = 0.04µF. With this value of C we get 0.991. Therefore,
our capacitor must have values between 0.011 and 0.04 µF.

4. Design a band-pass filter with the following specifications.

(a) Its first stage is a high-pass filter with a cutoff frequency of 1 kHz. The
input impedance of the first stage should be at least 500 Ω.
Solution: If fl = 1 kHz and RHP = 500Ω, then CHP = 0.032 µF.
(b) A second stage that follows should be a low-pass filter with a cutoff fre-
quency of 10 kHz. The second stage should not load the first stage.
Solution: Taking then RLP = 5kΩ, and f = 10 kHz, then we get CLP =
0.0032 µF.
(c) If we use a transformer to impedance-match the filter to a 10-Ω load, find
a ratio of primary to secondary windings in the transformer that will do
the job.
Solution: √
N1 5000Ω
= = 71
N2 10Ω
.

5. A 12-V DC power supply that gets its power from the 110-V (RMS) wall outlet
needs a transformer as a first step in generating its output. The rectification
and regulation stage of the power supply needs an input voltage of 15 V (peak).
7.2. PROBLEMS 109

(a) What winding ratio should the transformer have?

√
Solution: The input voltage has a peak value of 110 · 2 = 155 V. The
winding ratio of the transformer should be 156/15 = 10.4 ∼ 10 (we want
to transform to higher, not lower, voltage).
(b) If the power supply has an effective impedance of 100 Ω (i.e., the load
impedance that the transformer sees), what impedance does the primary
of the transformer see?
Solution: Z = 100Ω · 102 = 10 kΩ.

6. Design a series LRC filter for 10 kHz using a 0.01 µF capacitor. CORRECTION:
ADD “R = 1000 Ω.”

(a) What is the Q of the filter?

√
Solution: The resonance frequency of the filter is fc = 1/(2π LC), so if
fc = 10 kHz then L = 1/(4π 2 fc2 C) = 25 mH. Q = ωc L/R = 1592Ω/R. If
we use the addition R = 10 Ω, then Q = 1.592.
(b) Redesign the filter with a new Q that is 10 times larger.
Solution: We can do this by either increasing L by 10 and decreasing C
by 10, or by decreasing R by 10.
(c) Make a log-log plot of the two filter curves vs. frequency.

7. The circuit of Figure 7.25 (in the textbook, shown below) is supposed to be a
band-pass filter, but it has design flaws.
110 CHAPTER 7. FILTERS AND THE FREQUENCY DOMAIN

(a) Identify the problems (more than one).

Solution: There are two errors. First, it is not a band-pass filter because
the low-pass frequency cutoff is 159 Hz, which is lower than the high-pass
frequency cutoff, 15.9 lHz (it should be all the way around). The second
error is that the second stage loads the first stage (the resistor for the
second stage should be at least 100 kΩ).
(b) Correct the problems, but keep the same cutoff frequencies.
Solution: There are several ways to do this. One is to switch the compo-
nents of the first stage, making it a high-pass filter. The resistor of the
second stage should then be 100 kΩ. This is a factor of 20 higher. To keep
the same cutoff frequency we make the capacitor to be a factor of 20 lower,
or 0.0001 µF.

8. The circuit of Figure 7.26 (in the textbook, shown next) is a one-stage Butter-
worth filter. The load is also shown.

(a) Find an analytical expression for the voltage on the load as a function of
the frequency and the input voltage.
7.2. PROBLEMS 111

(b) Make a graph of the filter curve with your favorite software.
(c) Describe the type of filter and find a cutoff frequency.
(d) Graph an equivalent RC filter curve and compare it to the previous graph.

Solution: (a) First we get the Thevenin equivalent of the filter. The voltage
applied to the load is:

− ωC
j
1
VThev = j V0 = V0
jωL − ωC 1 − ω 2 LC

The output impedance of the filter (assuming zero output impedance of the
source) is:
( )−1
j −jωL
Zout = − + jωC = 2
ωL ω LC − 1
The voltage on the load is obtained applying the voltage divider argument:
R
VL = VThev
R + Zout

R(ω 2 LC − 1) −R
VL = V0 = V0
[R(ω LC − 1) − jωL][1 − ω LC]
2 2 R(ω LC − 1) − jωL
2

(c) It is a low-pass filter.

√ From the curve, the cutoff frequency is 10,000 rad/s.
This is also equal to 1/ LC.
112 CHAPTER 7. FILTERS AND THE FREQUENCY DOMAIN

(b), (d) We can see that the Butterworth filter has a much sharper cutoff.

9. Calculate the Fourier coefficients of a square wave defined by:

{
V0 /2 −T /4 < t ≤ T /4
V (t) =
−V0 /2 T /4 < |t| ≤ T /2

Solution: Since the function is even, an = 0. For the b0 coefficient:

[∫ ∫ ∫ ]
1 −T /4 −V0 T /4 V0 T /2 −V0
b0 = dt + dt + dt
T −T /2 2 −T /4 2 T /4 2

1
b0 = (−V0 /8 + V0 /4 − V0 /8) = 0
T

Because the arguments of the integrals are even we can integrate over half a
period and multiply that by 2:
[ ( ) ( ) ]
4 ∫ T /4 V0 2πnt ∫ T /2
V0 2πnt
bn = cos dt − cos dt
T 0 2 T T /4 2 T

2V0
bn = sin(nπ/2)
πn
with n odd.
7.2. PROBLEMS 113

10. Calculate the Fourier coefficients for a triangular wave defined by:
{
V0 (1 − 2t/T ) 0 ≤ t ≤ T /2
V (t) =
V0 (1 + 2t/T ) −T /2 ≤ t ≤ 0
Solution: Because the function is even, an = 0. That can also be shown by
direct integration.
[ ]
V0 ∫ 0 ∫ T /2
V0
b0 = (1 + 2t/T )dt + (1 − 2t/T )dt =
T −T /2 0 2
It makes sense because the triangular wave oscillates symmetrically about V0 /2.
[ ( ) ( ) ]
2V0 ∫ 0 2πt ∫ T /2
2πt
b0 = (1 + 2t/T ) cos dt + (1 − 2t/T ) cos dt
T −T /2 T 0 T
[ ( ) ( ) ( ) ]
2V0 ∫ T /2 2πt 2∫0 2πt 2 ∫ T /2 2πt
b0 = cos dt + t cos dt − t cos dt
T −T /2 T T −T /2 T T 0 T
After a few integration steps, we get:
4V0
bn = 2 2
π n
with n odd.
11. For the previous problems, make plots using your favorite software of the first
term (n = 1) and the sum of the first five terms vs. t. Assume that T = V0 = 1.
114 CHAPTER 7. FILTERS AND THE FREQUENCY DOMAIN

12. Suppose that we connect a function generator, set to 1 kHz square waveform
with an amplitude of 1 V, to an RC low-pass filter with a frequency cutoff of
2 kHz. Calculate the absolute value of the first five Fourier components (an or
bn ) of the waveform at the output of the filter.
Solution:
∞
∑ 2V0 nπ 2πnt
V (t) = sin cos n odd
n=1 πn 2 T
2V0 2πt 2V0 6πt 2V0 10πt 2V0 14πt 2V0 18πt
V (t) ≃ cos − cos + cos − cos + cos
π T 3π T 5π T 7π T 9π T
If we make ω0 = 2π/2
2V0 2V0 2V0 2V0 2V0
V (t) ≃ cos ω0 t − cos 3ω0 t + cos 5ω0 t − cos 7ω0 t + cos 9ω0 t
π 3π 5π 7π 9π
√
The filter transfer function 1/ 1 + (ω/ωc )2 . If ωc = ω0 , then after the filter the
amplitudes of the different terms are:
2V0 2 2V 2 2V 2 2V 2 2V 2
V1 = √ , V3 = 0 √ , V5 = 0 √ , V7 = 0 √ , V9 = 0 √
π 5 3π 13 5π 29 7π 53 9π 85
We can see that the greater the frequency, the greater the attenuation effected
by the filter: ω0 by 0.89, 3ω0 by 0.55, 5ω0 by 0.37, 7ω0 by 0.27, and 9ω0 by 0.21.
Chapter 8

Diodes

8.1 Problems
1. Consider the diamond structure of Figure 8.2 (in the textbook). The coordinates
of the nearest neighbors to atom 5 in pane (b) of the previous figure are R1 =
(0, 0, 0), R2 = ( a2 , 0, a2 ), R3 = ( a2 , a2 , 0), and R4 = (0, a2 , a2 ). Find the coordinates
of atoms 1, 2, 3, 4 relative to atom 5, and show that the four distances are the
same.

Solution:
( )
a a a
R5 = , ,
4 4 4

( ) ( )
a a a a a a
R1 − R5 = (0, 0, 0) − , , = − ,− ,−
( ) (
4 4 4 ) (4 4 ) 4
a a a a a a a a
R2 − R5 = , 0, − , , = ,− ,
(
2 2 ) (
4 4 4 ) (
4 4 4)
a a a a a a a a
R3 − R5 = , ,0 − , , = , ,−
(
2 2 ) (
4 4 4 ) (
4 4 4)
a a a a a a a a
R4 − R5 = 0, , − , , = − , ,
2 2 4 4 4 4 4 4

2. Consider the p–n junction of Figure 8.4 (in the textbook).

(a) What is the direction of the electric field in the p–n junction? Redraw it
and label it.

115
116 CHAPTER 8. DIODES

(b) Since there is an electric field, there is an electric potential across the
semiconductor. Which side is at higher potential?
Positive side.

(c) Assume that on either side of the interface the charge density is uniform
from the interface to the end of the depletion region, positive on the n-
side, and negative on the p-side. Is the potential a linear function of the
distance along the axis of the device? Justify your answer.
The electric field is a linear function, being maximum at the center and
zero at the end of the depletion regions. Since the field is the derivative
of the potential, the latter is a curve with slope equal to the field. This is
shown in the graph below.

3. An LED has the I–V curve shown in Figure 8.30 (corrected below).

CORRECTION: Figure:
8.1. PROBLEMS 117

(a) If this LED lights well at 10 mA, use the load line method to determine
the biasing circuit using a 4-V battery.
Solution: Using the load line (see figure below) we get an intercept of 18
mA, which implies a series resistor with value 4V/18mA = 220 Ω.

(b) Repeat the design using the “quick-and-dirty” method.

Solution: (4 − 2)/0.01 = 200 Ω.
(c) If we use a forward bias of 3 V and a 500-Ω resistor, find the current flowing
through the diode.
Solution: Using the load line we find that the current flowing is about 2
mA (see figure above).

4. A 15-V DC power supply is connected to a diode in series with a 750 Ω resistor.

The I–V curve of the diode is shown in Figure 8.31 (in the textbook). If the
diode is forward biased, answer the following questions:

(a) How much current is flowing through the diode?

Solution: To answer this we draw the load line. The intercepts are 15 V
and (15V)/(750Ω) = 20 mA. The operating point is the crossing of the
118 CHAPTER 8. DIODES

load line and the diode curve. The y-coordinate of the operating point is
the current flowing through the diode, which is 10 mA (see graph below).

(b) What is the voltage drop at the diode?

Solution: From the previous graph, the x-coordinate of the operating point
is the potential drop at the diode, which comes out to be 7.5 V.
(c) How much power is dissipated by the resistor?
Solution: PR = I 2 R = (10mA)2 (750Ω) = 75 mW.
(d) How much power is dissipated by the diode?
Solution: The power dissipated by the source is PS = IV0 = (10mA)(15V) =
150 mW. So the difference with the power dissipated by the resistor is
75 mW. We can verify this by calculating it directly: PD = IVD =
(10mA)(7.5V) = 75 mW.

5. A 10-W source (AC) that has a peak voltage Vp = 10 V. The source is connected
to a full-wave bridge with diodes that have a forward drop Vd = 0.7 V and a
power rating Pmax = 1 W. The load resistor is 1 kΩ. The output waveform is
similar to the one of Figure 8.17 (in the textbook, shown below).
V R

(a) Explain the small flat regions of zero voltage in the waveform of the figure.
Solution: In these regions the voltage of the source is less than 1.4 V (two
diode drops), and so no current flows.
(b) What is the maximum voltage across the load resistor?
Solution: Vpeak − 1.4V = 8.6 V.
8.1. PROBLEMS 119

(c) If one (either) end of the AC supply is connected to one (either) end of the
resistor some part of the circuit will go up in smoke (literally!). Identify
the part and explain why.

Solution: The full voltage of the supply will be applied to a diode. We will
assume that 10-W is the maximum power it delivers, which is when the load
impedance matches the source impedance, and the output voltage is half
the open-circuit voltage. Thus we assume that a current (10W)/(5V) = 2
A will flow, or that the output impedance is 2.5 Ω. A quick and dirty
calculation is that when we plug the diode directly to the 10-V source, a
current (10V − 0.7V)/(2.5Ω) = 3.72 A. The power dissipated by the diode
is (0.7V)(3.72A) = 2.6 W. An average rectifier diode can dissipate no more
than 1 W. If we exceed that, it will overheat and burn.

6. In the circuit of 8.32 (in the textbook), the input is a 60-Hz voltage (AC) with
an RMS value of 8.5 V. The bridge has diodes with a forward drop of 0.7 V.
The capacitor has a value of 20 µF and is connected to a load resistor shown.

(a) What is the minimum value of the load resistor RL so that the ripple
voltage does not exceed 10 percent of the peak output voltage?
√
Solution: The peak voltage is (8.5V) 2 = 12 V. The peak voltage after the
bridge is 12V−1.4V = 10.6 V. Using Eq. 8.10, RL = 1/(0.1·2·60Hz·20µF =
4.2 kΩ.

(b) Make a careful sketch of the voltage across the load when it is 600 Ω. Label
your axes.

Solution: We note that the new load is significantly lower than the load
for a 10% ripple. The time constant of the rectifier is τ = RL C =
(600Ω)(20µF) = 12 ms. Half a period of the source is t1/2 = 1/(2 · 60Hz) =
8.3 ms. In half a period the voltage decays by exp(−t1/2 /τ ) = 0.5, so the
with that load the ripple is significant, almost 50%.
120 CHAPTER 8. DIODES

7. Design a +12V power supply:

(a) What should be the RMS voltage of the output of the transformer?
Solution: It must be: 12 V (objective) + 1.2 (10% ripple) + 1.4 V (two
diode drops)
√ = 14.6 V. The RMS value would then need to be at least
14.6V/ 2 = 10.3 V.
(b) If the maximum output current is 0.5 A, what is the value of the capacitor?
Solution: We assume a 10% ripple. The minimum load is RL−min =
12V/0.5A = 24Ω, so C = 1/(0.1 · 2 · f · RL−min ) = 3500 µF.
(c) Make a full diagram of the power supply (include a regulator).
Solution: Same as Figure 8.20 of the textbook.

8. Consider the circuit shown in Figure 8.33 (in the textbook, shown below). The
input voltage is sinusoidal (AC), with a peak amplitude of 3 V. The resistor has
a value of 1 kΩ. When conducting, the two diodes have a forward drop of 0.7
V. Make a sketch of the output voltage. Carefully label your axes.
8.1. PROBLEMS 121

Solution: The circuit clips the positive swing of the voltage above 1.4 V, as
shown next.

9. Design a clipping circuit that limits the voltage of an input signal to within the
range −5 V to +5 V.
Solution:

10. Consider the clamping circuits of Figure 8.34 (in the textbook, shown below).
Assume a steady state and neglect the diode drops.

(a) What would be the output waveform in the circuit (a)?

122 CHAPTER 8. DIODES

Solution: The capacitor is charged acquiring a potential Vp + V0 on the

negative swing of the source. Thereafter it cannot discharge (unless there
is a load). Thus, the waveform gets a positive DC shift of Vp + V0 . The
waveform is shown below.

A more explicit explanation is this: Suppose that the potential of the

lower side of the source is 0. That is VB . On the most positive swing, the
potential of the top end of the source is Vp . The potential of point A is
that plus the potential of the capacitor. Thus VA = 2Vp + V0 . In the most
negative swing the top end od the source is −Vp , so VA = V0 . At any given
time VAB = V (t) + Vp + V0 .

(b) What would be the output waveform in the circuit (b)?

Solution: The solution is similar to the previous one only that there is no
V0 and the diode is reversed. The capacitor gets charged on the positive
swing of the source. Thus, point A is at lower potential than the top side
of the source. If we consider VB = 0, then VAB = VA = V (t) − Vp . Thus,
it gets shifted to lower voltage by an amount equal to the peak voltage, as
shown below.
8.1. PROBLEMS 123

11. In the circuit of Figure 8.35 (in the textbook), the input voltage is sinusoidal
and has a peak voltage of 5 V. The diode has a drop Vd = 0.7 V.

(a) Make a sketch of Vout as a function of time, neglecting Vd . Carefully label

your axes.

Solution: This is identical to the part (b) of the previous problem. Since
the peak voltage is 5 V, the signal source gets a negative DC offset of 5 V.
The graph is shown below.

(b) Make a sketch of Vout as a function of time, accounting for Vd . Carefully

label your axes.

Solution: The answer to this question is subtle. The signal source gets a
DC shift by the amount that the capacitor is charged. How much is this?
It is not exactly Vp −Vd = 4.3 V. This is because the diode still conducts at
a voltage below the forward drop, but less so. It depends on the diode and
the diode curve. This is an excellent problem where the student should
just try it out in the lab. In conclusion, the signal source gets shifted to
lower potential by Vp − Vd′ , where Vd′ is a fraction of the diode forward
drop, but not zero, and depends on the diode.
124 CHAPTER 8. DIODES

12. In the circuit of Figure 8.36 (in the textbook, shown below), the power source
has a peak voltage of 10 V. Find the output voltage. Assume for simplicity that
the diode drops are zero. Find Vout . Make a sketch, if necessary.
Solution: On the negative swing, capacitor 1 gets charged acquiring a potential
Vp = 10 V. Because of the diode, once the capacitor is charged, it stays that
way. Let us assume that Point B has potential 0. On the peak of the positive
swing, Point A is at potential 2Vp = 20 V. At this point capacitor 2 gets charged
to a potential of 20 V, which becomes the output voltage. Thus, the circuit acts
as a voltage doubler. In the next figure we sketch the solution.

13. The circuit of Figure 8.37 (in the textbook, shown below as part of the solution)
is a Cockroft-Walton multiplier. The input signal is a square wave with a high
voltage Vp and a low voltage of zero volts.

(a) What is the output voltage? (Neglect diode drops.)

Solution: the output voltage is 7.5 V. When the source is +5 it charges the
two capacitors adjacent to it (2.5 V potential for each). When the voltage is
zero the top capacitor gets discharged and the bottom one shares is charge
8.1. PROBLEMS 125

with the second top one, charging is to 1.25 V. At the next swing the first
two get charged to 2.5 V, also charging the second one from the bottom. At
the next zero voltage of the source, 1st-bottom capacitor shares its charge
with 2nd-top capacitor, and 2nd-bottom capacitor with 3rd-top capacitor.
This way, on every swing the capacitors get charged to leave the bottom
three capacitors each charged to a potential of 2.5 V. The total is 7.5 V.

(b) If Vp = 5 V, find the output voltage, including diode drops of 0.6 V.

Solution: The final voltage will be 7.5 V minus 5 diode drops (∼ 0.2 V),
or 6.5 V.
14. Consider a touch sensor of Section 8.5.7. Assume TTL gates.
(a) The pad is untouched (neglecting Csens ). If C = 0.22 µF and R = 10 kΩ,
what is the minimum value of the input frequency for the output to be
always low?
Solution: The output of the NOT gate is low if the input is high. For
TTL, the input voltage has to be grater than 2 V. (see pages 54-56 of the
textbook). The input to the NOT gate has a capacitor and resistor in
parallel, connected to ground. This way, when the capacitor discharges, it
does so with a time constant τ = RC = 2.2 ms. If we want the input to the
NOT gate to be always high, then we do not want it to go below 2 V. The
input to the capacitor comes from a gate through a diode. If the input
to the circuit is a square wave, because of the diode, the peak voltage
charging the capacitor C is 4.4 V. (Since there is a resistor to ground,
current is flowing even when the capacitor is charged, so there is a 0.6
V diode drop.) When the input is low, on half the period, the capacitor
discharges. Therefore, we want 2V = (4.4V) exp(−t/2ms), which gives
t = 1.74 ms. Being this half a period, the frequency is f = 1/2t = 288 Hz.
(b) If R′ = 512 kΩ, what is the minimum value of Csens so that, with the
frequency of the previous part, the output of the first NOR is always low?
126 CHAPTER 8. DIODES

Solution: The sensing capacitor gets charged through the diode when the
input is high, and discharged through R′ when the input is low. The gate
is a NOR, whose output is 1 only if both inputs are low. When the sensing
capacitor is very small, the time constant Csens R′ is low enough that the
input to the NOR gate is the same as the other input, which makes the
output of the gate oscillate between 1 and 0 at the input signal times.
When the touchpad is touched, the value of Csens increases. The output of
the NOR will be 0 if the sensing capacitor does not discharge below 2 V in
the half a period when the input is low (during 1.74 ms). Thus, we want
2 = 5 exp(−(1.74ms)/τ ′ ), which gives τ ′ = −t/ ln(2/5) = 1.9 ms. (Here we
ignore the diode drop, because when the capacitor is charged, no current
flows through the diode, and so there is no drop.) The sensing capacitor
is then Csens = τ ′ /R′ = 0.0037 µF.
(c) Make a sketch of the waveforms of the inputs and outputs of both NOR
and AND gates for the two cases: when the pad is untouched and when
the pad is touched. ERRATUM: added “and AND” above.
Solution: The waveforms of for the NOR gate are shown below.

The input for the NOT gate, untouched (zero otherwise), and output of
the NOT gate touched (zero otherwise) are graphed below.
8.1. PROBLEMS 127

15. Consider the circuit of Figure 8.38 (in the textbook, shown below). The OR
gate accepts any voltage greater than or equal to 2.5 V as a logic 1 and anything
below 2.5 V as a logic 0. Its logic 1 output is 5 V and logic 0 output is 0 V. The
input voltage is a TTL square wave with a frequency of 1 kHz. The resistor is
1 kΩ, and the capacitor is 0.5 µF. Neglect the forward drop across the diode.

(a) Make a sketch of the voltages of points A, B, and C as a function of time.

128 CHAPTER 8. DIODES

(b) Find the range of frequencies for which the output of the gate is a logic 1
permanently.
Solution: We want the B input to always be high, or VB > 2.5. We find
the time it takes to drop from 5 V to 2.5 V is t = 0.347 ms. The frequency
should be at least 1/2t = 1.443 kHz.
Chapter 9

Transistors

9.1 Exercises
Exercise 9.1 Use the transistor curves of Figure 9.5 (in the textbook, shown below
as part of the solution) to design a transistor switch when Vcc = 3 V and RL = 1000
Ω. Find RB .
Solution: The load line has intercepts 3 V and IC = VCC /RL = 3 mA. The
operating point is the intersection of the transistor curve and the load line (see below).
For a switch we need the intersection point to be such that the value of VCE is as
low as possible. We pick the curve with IB = 50µA. To get such a value of IB
we bias the transistor base with a current limiting resistor RB = (VCC − VB )/IB =
(3V − 0.6V)/50µA = 50kΩ.

Exercise 9.2 Suppose that we apply an input voltage Vin = 2 cos 2πf t, with f = 1
kHz, Vcc = 12 V, and RL = 10 Ω. Make a sketch of Vout as a function of time. Label
your axes accurately.

129
130 CHAPTER 9. TRANSISTORS

Solution: Once the base voltage exceeds 0.6 V, the transistor conducts, and the
emitter voltage is VB − 0.6 V.

Exercise 9.3 For the previous exercise, find the impedance seen by the source.

Solution: If β = 100, then R = 1 kΩ.

Exercise 9.4 If RS = 50 Ω, what source impedance will the load see?

Solution: RS /100 = 0.5Ω.

Exercise 9.5 Suppose that we apply an input voltage Vin = 2 cos 2πf t to the previous
circuit (Figure 9.12, a transistor push-pull), with f = 1 kHz, Vcc = 12 V, RL = 10 Ω.
Make a sketch of Vout as a function of time. Label your axes accurately.
9.2. PROBLEMS 131

Exercise 9.6 Use Equation 9.27 to show that the drain current becomes
( )
Vin
ID = 2k − VT VD .
2
Vin
ERRATUM: Equation must have 2
(as shown above, corrected), instead of Vin (as
currently in the textbook).

The two resistors R2 linearize the relationship between ID and VD , making the FET
behave exactly like a resistor.
Solution: The drain current is (Equation 9.27):

ID = 2k(VG − VT )VD − kVD2

We find an expression for the gate voltage using the voltage divider argument between
the drain and the input:
1
VG − Vin = (VD − Vin )
2
Solving for VG :
VD Vin VD Vin
VG = − + Vin = +
2 2 2 2
Replacing VG into the expression for ID , we get
( ) ( )
VD Vin Vin
ID = 2k + − VT VD − kVD2 = 2k − VT VD
2 2 2

This way, from Equation 9.30 we get

[( ) ] [ ]
1 VD Vin Vin
= 2k + − VT − VD = 2k − VT
RDS 2 2 2

9.2 Problems
1. Calculate the value of RB for the circuit of Figure 9.26 (in the textbook, shown
below) so that it behaves as a transistor switch.
Solution: The load-line intercepts are VCC = 5 V and ICmax = VCC /RC = 10
mA. The base current that intersects the load line at a low value is VCE (and
act like a switch) is one with IB ∼ 10ICmax /β = 1 mA. The base resistor must
be RB ≤ (5V − 0.6V)/(1mA) = 4.4 kΩ.
132 CHAPTER 9. TRANSISTORS

+ 5 V

5 0 0 W
R B

2. Figure 9.5 (in the textbook) gives the I–V curve of the transistor in the circuit
of Figure 9.27 (in the textbook, shown below). What is the current flowing
through the load?
+ 6 V

2 k W

5 0 k W

+ 3 .6 V

Solution: From the load line we have ICmax = (6V)/(2kΩ) = 3 mA. From
the circuit we deduce IB = (3.6V − 0.6V)/(50kΩ) = 60 µA. Because IB >
ICmax /β ∼ 30 µA, the transistor must act like a switch. The current flowing
through the load would be IC ∼ (6V − 0.2V)/(2kΩ) = 2.9 mA.

3. The input waveform in the circuit of Figure 9.28 (in the textbook, shown below)
is Vin = V0 cos ωt, with V0 = 3 V and a frequency f = 10 kHz.
+ 1 0 V

V in
R E

(a) Make a sketch of VE .

9.2. PROBLEMS 133

Solution: The input signal gets clipped at 0.6 V, the forward base-emitter
diode drop.

(b) If RE = 100 Ω, sketch the current flowing through it. Label your axes.
Solution:

(c) Suppose that we now add a DC component to the input so that

Vin = V0 cos ωt + VDC
Sketch the output waveform of VE for the following values of VDC : 1 V, 3
V, and 5 V.
Solution: As we add a DC voltage to the input more of the input signal
gets through.
134 CHAPTER 9. TRANSISTORS

(d) With VDC = 5 V, attach a filter to the output, with a resistor RL = 1 kΩ

and a capacitor C2 . If we want to suppress only the DC part of VE , with
at least 90 percent of the 10-kHz waveform coming out, what value of C2
should we use? Draw a circuit diagram.
Solution: If we equate the high-pass filter equation (7.9 in the textbook)
to 0.9, we get ωc = 3 · 104 rad/s. We pick a load resistor that is 10
times larger than RE , or RL = 1 kΩ, then find that the capacitor is
C = 1/ωc RL = 0.033 µF.

4. For the circuit of Figure 9.29 (in the textbook, shown below):
+ 1 5 V

L O A D

V B = 3 .2 V

(a) Determine the value of the resistor R so that a current of 0.5 A flows
through the load.
Solution: VE = 3.2V − 0.6V = 2.6 V, so R = VE /IC = 2.6V/0.5A = 5.2 Ω.
(b) What is the maximum value of the load resistor?
Solution: At saturation, the transistor has VCE ∼ 0.2V, so VC =≃ 2.8V.
The maximum load is one where the voltage drop across it is the remaining
voltage: VLmax = 15V − 2.8V = 12.2 V. RLmax = VLmax /0.5A = 24.4 Ω.
9.2. PROBLEMS 135

(c) If the load resistor is 10 Ω, what value of VB will put the transistor into
saturation?
Solution: We know that IC RL + VCEmin + VE = 15 V, where IC = VE /R,
VCEmin = 0.2 V, and VE = VB − 0.6 V. Solving for VB , we get VB = 5.7 V.

5. What is the relationship between the input voltage VB and IC in the current
source circuit shown in Figure 9.30 (in the textbook, shown below)? What is
the maximum current that can flow?
+ 1 5 V

2 0 0 W

V B

8 0 0 W

Solution: IC = (VB − 0.6V)/RE . ICmax (RC + RE ) + 0.2V = 15 V. ICmax = 14.8

mA.
6. Design a 0–10 mA current source.
(a) If the load is 1 kΩ, what is the maximum drop across the load?
Solution: VLmax = (1kΩ)(10mA) = 10 V.
(b) Pick a value of Vcc that is greater than the voltage you calculated in the
previous part.
Solution: VCC = 12 V.
(c) Explain why we should do the latter.
Solution: Otherwise, the transistor will reach saturation (VCE ∼ 0.2 V)
before reaching the maximum current.
(d) What value of RE would you pick?
Solution: 12V − 10.2V = 1.8 V. RE = 1.8V/10mA = 180 Ω.
(e) Give a relationship between VB and the current flowing through the load.
Solution: IC = VE /RE = (VB − 0.6V)/RE .
7. Design a current source that can put out a current of up to 50 mA to a maximum
load of 500 Ω. Assume that VCC = 30 V.
136 CHAPTER 9. TRANSISTORS

Solution: RLmax = 500 Ω. VLmax = (500Ω)(50VmA) = 25 V. So VCC must

be greater than this. For example, VCC = 30 V would do. At maximum
load VE = 30V − 25V − 0.2V = 4.8 V. The emitter resistor would then be
RE = (4.8V)/(50mA) = 96 Ω. IC = (VB − 0.6V)/(96Ω).

8. We apply 2 V to the base of the transistor, as shown in Figure 9.31 (in the
textbook, shown below). If RE = 1,000 Ω and RC = 2,000 Ω, what is the
voltage of the collector of the transistor relative to ground?

Solution: VE = VB −0.6V = 1.4 V, so IC = 1.4 mA. VC = 12V−(2000Ω)(1.4mA) =

9.2 V.

9. The transistors shown in Figure 9.32 (in the textbook, shown below) have β =
100.

(a) Find the current flowing through the 4-Ω resistor.

Solution: VE = 6V − 0.6V − 0.6V = 4.8 V. Then IC = (4.8V)/(4Ω) = 1.2
A.
9.2. PROBLEMS 137

(b) Find the current flowing out of the 6-V source.

Solution: IB = 1.2A/10000 = 0.12 mA.
(c) The output impedance of the 6-V source is 10 Ω. Is the circuit loading the
source? Explain.
Solution: No, because the load appears 10000 larger than it is, at 40 kΩ,
which is much larger than 10 Ω. Another way to put it is that the voltage
drop at the output impedance is (0.12mA)(10Ω) = 1.2 mV.

10. An n-channel MOSFET has the following operating parameters: VT = 4 V and

k = 2.8 A/V2 .
(a) Design a transistor switch that applies 500-V to a 1 kΩ load.
Solution: The maximum current is then Imax = (500V)/(1kΩ) = 0.5 A. For
a MOSFET switch Imax ≪ IDsat . For convenience let us make IDsat = 2.8
A. Then VDsat = 1V = VGS − VT , which results in VGS = 5 V. Thus, we
trigger the MOSFET as a switch with a gate-source voltage of 5 V.
(b) What is the resistance of the MOSFET when VGS = 6 V and VDS = 1 V?
Solution: If VGS = 6 V, then VDsat = 2 V. If VDS = 1 V, then we are
in the linear region of the MOSFET. Then, using Equation 9.25, RDS =
1/[2k(VGS − VT )] = 0.089 Ω.
11. The circuit of Figure 9.33 (in the textbook, shown below) is a simple MOSFET
NOT gate. The MOSFET parameters are k = 0.2 mA/V2 and VT = 0.8 V.

(a) If the input is Vin = 5 V, find IDsat .

Solution: VGS = Vin , so VDSsat = VGS − VT = 4.2 V. IDsat = kVDSsat
2
= 3.5
mA
(b) Is the MOSFET in the linear region? Justify your answer.
Solution: IDmax = 5V/10kΩ = 0.5 mA. Because IDsat > IDmax , the tran-
sistor is in the linear region.
138 CHAPTER 9. TRANSISTORS

(c) Find Vout .

Solution: RDS = 1/(2kVDSsat ) = 600 Ω. The drain current: ID = (VCC −
Vout )/RD = Vout /RDS . So Vout = VCC /(1 + RD /RDS ) = 0.3 V

12. Consider a JFET that has the curves shown in Figure 9.34 (in the textbook,
shown below).
ID (m A )
V G S

0 .3 V
6

0 V
4

2 -0 .4 V

V D S
1 2

(a) Estimate the value of the threshold voltage VT . Justify your answer.
Solution: From the lowest curve, IDSsat = 2.1 mA. Then −0.4V − VT =
√
2.1mA/k. But we do not know k. From the next higher curve, −VT =
√
4.3mA/k. Dividing these two we get
√
−VT 4.3V
= = 1.43
−0.4V − VT 2.1V
which gives us VT ∼ −1.3 V.
(b) For what value of the gate-source voltage is the current 2.2 mA?
Solution: VGS ∼ −0.4 V.
(c) For what values of the drain-source voltage is the current 2.2 mA?
Solution: For values above VDSsat = VGS − VT ∼ 0.9 V.
(d) What current flows through the circuit of Figure 9.35 (in the textbook,
shown below) when it is in the flat (FET saturation) region?
Solution: VGS = 0, so ID = 4.3 mA.
(e) If the FET is in the circuit of Figure 9.35 (in the textbook, shown below),
for what values of the drain-source voltage is the FET in the flat region?
Justify.
Solution: VDS > VDSsat = 0.6 V.
9.2. PROBLEMS 139

(f) If the supply voltage is 3 V, and the load is 375 Ω, use the load-line method
to determine whether the FET is in the flat region.
Solution: We draw a load line with intercepts ID = 3V/375Ω = 8 mA, and
VCC = 3 V. That line intercepts the VGS = 0 curve in the flat region.
(g) Suppose that the supply voltage is set to a value for which the FET is
in the linear region. In this region, it acts like a resistor. What is its
resistance?
Solution: For VGS = 0, IDSsat ∼ 4.3 mA and VDSsat ∼ 0.6 V. The resistance
is RDS ∼ VDSsat /IDSsat ∼ 140 Ω.

lo a d

13. For the MOSFET of Figure 9.36 (in the textbook),

(a) Find the threshold voltage.

Solution: VT = VGS − VDSsat = 6V − 10V = −12 V.
(b) If we have a 100-V power supply, for what range of loads can the MOSFET
be used as a switch with VGS = 6 V?
Solution: Once we are low in the linear region, where ID < 3 A, for
example. Then RL > 100V/3A = 33 Ω.
(c) Estimate the ON resistance for VGS = 6 V.
Solution: RDS ∼ VDSsat /IDSsat ∼ 10V/10mA = 1 Ω.
140 CHAPTER 9. TRANSISTORS
Chapter 10

Operational Amplifiers

10.1 Exercises
Exercise 10.1 The transistors in the previous circuit act as a current-supply exten-
sion of the op-amp. Without adding another op-amp, modify the circuit so that it also
amplifies by a factor of five.

Solution: We wire it as shown in the figure below. Using voltage division and
op-amp properties we have
R1
Vin = Vout
R1 + R2
which can be turned around to
( ) ( )
R1 + R2 R2
Vout = Vin = 1 + Vin
R1 R1
If we want Vout = 5Vin , then we make R2 /R1 = 4.

141
142 CHAPTER 10. OPERATIONAL AMPLIFIERS

Exercise 10.2 Derive an expression for Vout when the noninverting input of the pre-
vious circuit (see below) is connected to a potential V0 (do not underestimate this
calculation!).

Solution: Applying the voltage divider method, and making V+ = V− = V0 , we

have
R1
V0 − Vin = (Vout − Vin )
R1 + R2
Solving for Vout : [ ( ) ]
R2 R2
Vout = − Vin − 1 + V0
R1 R1
Exercise 10.3 Derive the equation for the circuit of Figure 10.11 (in the textbook,
shown below) in the following steps:
1. Find an expression for V− in terms of V1 , Vout , R1 ,and R2 .

2. Find an expression for V+ in terms of V2 , R1 , and R2 .

3. Using the previous results, show that

R2
Vout = (V2 − V1 ) (10.1)
R1

R 2

R 1
V 1

V 2
V o u t
R 1
R 2

Solution: (1) The input current goes through the feedback resistor:
V1 − V− V− Vout
I− = =
R1 R2
10.1. EXERCISES 143

and solving for V− ,

R2 R1
V− = V1 + Vout
R1 + R2 R1 + R2
We could also have used the voltage divider argument:
R1
V− V1 = (Vout − V1 )
R1 + R2

(2) Using the voltage division argument again,

R2
V+ = V2
R1 + R2

(3) Equating the expressions for V− and V+ and multiplying both sides by (R1 +
R2 ):
R2 V2 = R1 (Vout − V1 ) + (R1 + R2 )V1
and solving for Vout we get indeed:
R2
Vout = (V2 − V1 )
R1

Exercise 10.4 Show that the current flowing through the load in the circuit of Fig-
ure 10.14 is given by
R2
I= Vin (10.2)
R1 R3

+ V c c

R 3
R 2
V in

I L o a d

R 1

Solution: The current through the load is given by

VCC − V+
Iload =
R3
144 CHAPTER 10. OPERATIONAL AMPLIFIERS

In the second op-amp we have V− = V+ = VCC −I21 R2 , but we also have I21 = Vin /R1 .
Putting these two relations together we get an expression for V+ :
R2
V+ = VCC − Vin
R1
which we can replace into the first expression to get
R2
Iload = Vin
R3 R1
Exercise 10.5 By now, we have all the tools to understand the circuit of Figure 10.20
(in the textbook, shown below).
R 1

V in
V o u t

R 2
Z

1. Find an expression for Vin in terms of Z, R2 , and Vout .

2. Find an expression for I, the current flowing through R1 , in terms of Z, R1 ,
R2 , and Vout .
3. Show that
R1
Zin = − Z (10.3)
R2
Solution: (1)
Z
Vin = V+ = Vout
R2 + Z
(2) ( )
Vin − Vout 1 Z R2
I= = − 1 Vout = − Vout
R1 R1 R2 + Z R1 (R2 + Z)
(3) Zin = Vin /I, so replacing the expressions for Vin and I, and simplifying, we get:
R1 Z
Zin = −
R2
10.1. EXERCISES 145

Exercise 10.6 Figure out the circuit of Figure 10.21 (in the textbook, shown below).
R '

R '
V in
V o u t

C
R

1. Get expressions for V+ and V− . Keep all complex numbers in the a+ib form—do
not use exponential notation yet.

2. Express Vout in terms of Vin . A bit of algebra is involved here, including complex-
number manipulations (nobody said it would be easy). When you get to the
final relation between Vin and Vout , convert the final complex number to the
exponential notation.

3. What does the circuit do? (Psst: You get to the answer if you can answer the
following two questions: What is the relationship between the amplitudes of Vin
and Vout ? What is the relation between the phases of Vin and Vout ? How does it
behave as a function of ω? What are the extreme cases?)

Solution: (1) Using voltage divider arguments we get:

R
V+ =
R − ωC
j

R′ Vin + Vout
V− = ′
(Vout − Vin ) + Vin =
2R 2
(2) We now equate V− and V+ and then crunch through some algebra, and get
j
R+
Vout = ωC
Vin = ej2ϕ Vin
R− J
ωC

where ϕ = tan−1 (1/(ωRC)).

(3) It is a phase shifter. When ω → 0, 2ϕ → π; and when ω → ∞, 2ϕ → 0.

Exercise 10.7 Find the transfer function for the inverting high-pass active filter of
the previous figure (10.23 in the textbook, shown below).
146 CHAPTER 10. OPERATIONAL AMPLIFIERS

Solution:
R1 − ωC
j
0 − Vin = j (Vout − Vin )
R1 + R2 − ωC
Simplifying, we get
Vout R2
=−
Vin R1 − ωC
j

When ω → 0, Vout /Vin → 0; and when ω → ∞, Vout /Vin → −R2 /R1 .

Exercise 10.8 Show that the period of the relaxation oscillator of Figure 10.35 (in
the textbook, shown below) is 2.2RC.

V o u t

R '
R '

Solution: As soon as V+ > V− , Vout = VCC and V+ = VCC /2, and the capacitor
charges. Once the voltage on the capacitor (V− ) exceeds VCC /2 the output swings to
−VCC , and V+ = −VCC /2 The capacitor then discharges until V− goes below −VCC /2
at which point the output swings back to VCC and the cycle repeats. We note that
when V− = VCC /2 and Vout switches to −VCC . The voltage of the capacitor decays
exponentially as:
( )
VCC 3VCC −t/RC
V− + VCC = + VCC e−t/RC = e
2 2
10.2. PROBLEMS 147

The capacitor stops discharging and starts charging when V− = −VCC /2. Note that
the previous equation simplifies to e−tdischarge /RC = 1/3 and from that we get tdischarge =
RC ln 3 = 1.1RC. The charging process is similar:
( )
VCC VCC ( )
V− + = VCC + 1 − e−t/RC
2 2
Solving for the charging time when V− = VCC /2 yields to the same time: tcharge =
tdischarge = 1.1RC. The period of the oscillation is then T = 2.2RC. The waveform is
shown below.

10.2 Problems
1. In the circuit of Figure 10.44 (in the textbook, shown below), find Vout in terms
of the input voltages.
R
R
V 1
R
V 2
R V
V 3 o u t
R
V 4
R
148 CHAPTER 10. OPERATIONAL AMPLIFIERS

Solution: The current in the inverting branch is

V1 − V− V2 − V− V− − Vout
+ =
R R R
and in the noninverting branch,
V3 − V+ V4 − V+ V+
+ =
R R R
Solving for V−
1
V− = (V1 + V2 + Vout )
3
and for V+ ,
1
V+ = (V3 + V4 )
3
Equating the two we get:

Vout = V3 + V4 − V1 − V2

2. Find the output voltage in the circuit of Figure 10.45 (in the textbook, shown
below).
2 0 0 k W

1 0 0 k W

V o u t
V in

1 0 0 k W
2 0 0 k W

Solution: Using voltage divider arguments in the inverting branch we find:

100kΩ 1
V− = Vout = Vout
300kΩ 3
In the noninverting branch we find
2
V+ = Vin
3
Equating the two, we find Vout = 2Vin .
10.2. PROBLEMS 149

3. A siren alarm is based on an integrator circuit, shown in Figure 10.46 (WHICH

IS INCORRECT-inverting and noninverting labels switched, the correct figure
is shown below), with a capacitor of 2 µF. When the input is a logic value of 1
(5 V), the output of the integrator feeds onto a siren whose frequency depends
on the voltage input to it. Thus, the integrator must:

• Output a voltage that rises linearly with time from 0 to 10 V in 2 s.

• Have a capacitor that must be reset to zero when the integrator voltage
reaches 10 V. We do this with a MOSFET switch driven by a comparator.
• You must find:
(a) The way to connect the digital input to the integrator so that the
output of the integrator rises when the digital input is 5 V.
(b) The value of R.
(c) The way to wire the comparator. You have only +5 V, +15 V and -15
V available.

Solution: (a,b) The central component of the circuit is an integrator, giving

1 ∫ tsiren Vin tsiren

Vout = − Vin dt = −
RC 0 RC
Note that there is a negative sign, so Vin must be negative for Vout to be positive.
Suppose we make Vin = −5 V, to get Vout = 10 V in 2 s we can make tsiren = 2
s, so RC = 1 s. Since C = 2 µF, then R = 500 kΩ. Therefore, the circuit in
the box is an inverting amplifier with a gain of 1.
(c) The comparator must compare Vout to 10 V. Since we only have one voltage
above 10 V (+15 V), we can voltage divide it to get 10 V, as shown below in
the completed circuit.
150 CHAPTER 10. OPERATIONAL AMPLIFIERS

4. Design a circuit that has Vout = (2/3)Vin + 5 V.

Solution: We can do this intwo steps: deamplify Vin and then add 5V to it, as
shown below.

We can also do this more elegantly in one step with a differential amplifier,
shown below: V+ = (1/3)Vin = (1/2)[Vout + (−5V )].
10.2. PROBLEMS 151

5. Design a circuit that amplifies the 0.8 V (peak-to-peak) audio signal from an
audio circuit that has a 100 kΩ output impedance. The output should be about
10 V (peak-to-peak), and applied to an 8 Ω speaker load.
Solution: The audio circuit has high output impedance, so we need a circuit
with an even higher input impedance, such as a noninverting amplifier. Then
we need to drive a speaker, so we need push-pull power transistors. The output
is expected to be the input amplified by 10V/0.8V = 12.5. Therefore R2 /R1 =
11.5. The circuit is shown below.

6. Determine how the circuit of Figure 10.13 (in the textbook, shown below) works.
+ V

R
a ls o
V D
in
G
I S
L o a d

(a) Find an expression for the current flowing through R in terms of Vin and
R.
Solution: I = (VCC − Vin )/R.
(b) For what value of Vin do we have I = 0?
Solution: Vin = VCC .
152 CHAPTER 10. OPERATIONAL AMPLIFIERS

7. Draw the complete circuit diagram to generate a reference voltage using the
method of Figure ??. Use a 3-V Zener diode with a current of 5 mA going
through it.
Solution: The circuit takes an input voltage of 2.5 V, amplifies it by a factor
of 2. Since the Zener has an reverse drop of 3 V, the current flowing through
the resistor R after the op-amp. Since we want the current to be 5 mA, R =
(5V − 3V)/(5mA) = 400 Ω.

8. A photodiode with a responsivity of 0.9 A/W is to be used to detect light at

the 1 mW level. Design a circuit that outputs 3 V/mW.
Solution: The photodiode acts like a current source, generative a reverse current
proportional to the light it receives. Therefore we need a current amplifier,
shown below. The output voltage is Vout = −Iphoto R = −(0.9mA/mW)R =
−3V/mW. Therefore R = 3.3 kΩ.

9. The circuit of page 147 (of textbook, shown below) is an instrumentation am-
plifier.

(a) Find an expression for Vout in terms of Vout−1 and Vout−2 . The values of
the resistors are given.
10.2. PROBLEMS 153

Solution: On the right-most op-amp,

R3
Vout = (Vout−2 − Vout−1 )
R2

(b) Find expressions for Vout−1 and Vout−2 in terms of V1 and V2 .

Solution: The current flowing through the two resistors R1 and RG is
Vout−1 − V1 V2 − Vout−2 V1 − V2
= =
R1 R1 RG
From these relations we find
R1
Vout−1 = (V1 − V2 ) + V1
RG
and
R1
Vout−2 = − (V1 − V2 ) + V2
RG
(c) Show that ( )
R3 2R1
Vout = 1+ (V2 − V1 ) (10.4)
R2 Rg
Solution: Replacing Vout−1 and Vout−2 from part (b) in to the expression
for Vout in part (a),
[ ]
R3 R1 R1
Vout = − (V1 − V2 ) + V2 − (V1 − V2 ) − V1
R2 RG RG
154 CHAPTER 10. OPERATIONAL AMPLIFIERS

Simplifying,
[ ]
R3 R1
Vout = −2 (V1 − V2 ) − (V1 − V2 )
R2 RG
which simplifies further to the desired result (Eq. 10.4 in this Manual).

10. For each of the circuits of Figures 10.47-10.51 explain what is wrong with it and
modify it so that it works. Be particularly observant of connections, component
values, loading, and any detail that looks odd. Note that the circuit may have
more than one problem.

(a) The circuit of Figure 10.47 (in the textbook, shown below) is a ×10 am-
plifier.
V in
V o u t

2 0 k W

2 k W

Solution: A first error is that the gain of the noninverting amplifier of the
figure is 1 + R2 /R1 = 11. For the gain to be 10 we must make R2 /R1 = 9.
A second error is that the feedback is connected to the noninverting input
instead of the inverting one. The correct circuit is shown below.

(b) The circuit of Figure 10.48 (in the textbook, shown below) outputs −5 V.
Solution: This circuit has a serious design flaw: the amplifier loads the
voltage divider. The output impedance of the voltage divider is 0.5 kΩ,
and the input impedance of the op-amp is 2 kΩ, which is only a factor
of 4. As a consequence the op-amps sees a 5-V source connected to the
10.2. PROBLEMS 155

inverting input through a 0.5kΩ + 2kΩ = 2.5 kΩ resistor. The output is

then Vout = −(2kΩ/2.5kΩ)(5V) = −4 V.

+ 1 0 V
2 k W
1 k W

2 k W
1 k W V o u t

This can be remedied easily by changing the feedback resistor to 2.5 kΩ.

(c) The circuit of Figure 10.49 (in the textbook, shown below) uses a 4-V
source to drive a 10-Ω load with 6 V.

4 V

6 V
1 k W
2 k W 1 0 W

1 k W 1 k W

Solution: The design would fine if the op-amp could drive the 10-Ω load
with 6 V, but the op-amp cannot source 0.6 A. We remedy this by connect-
ing a power booster at the output of the op-amp. Note how the feedback
is connected to avoid any junction drops of the transistor.
156 CHAPTER 10. OPERATIONAL AMPLIFIERS

(d) The circuit of Figure 10.50 (in the textbook, shown below) is a ×4 amplifier
that suppresses the DC component.

V o u t

3 0 k W

1 k W

Solution: The circuit has two errors. A first error is that the circuit am-
plifies by a factor of 31 instead of 4. We solve that by switching the 30-kΩ
resistor for a 3-kΩ one. The second error is that the capacitor feeds straight
into the noninverting input of the op-amp. For it to work as a filter, the
capacitor needs to charge and discharge, but the op-amp input cannot do
that. We fix it by adding a resistor to ground after the capacitor. We pick
a large value for the resistor so that the frequency cutoff is low.
10.2. PROBLEMS 157

(e) The circuit of Figure 10.51 (in the textbook, shown below) is a microphone
to 8-Ω speaker.

3 0 0 k W

1 0 k W

Solution: There are two errors. First, the microphone is capacitive, so,
like in the previous solution, we need to provide a path to ground via a
resistor. The second error is that the npn transistor only conducts in the
same direction. To fix this we need to add a pnp transistor in a push-pull
configuration after the op-amp.
11. Explain how the circuit of Figure 10.52 (in the textbook, shown below) works.
Suggestion: Analyze the value of Vout when Vin > V+ and Vin < V+ .

1 0 k W
1 k W V o u t

V in

5 k W

Solution: V+ = VCC /3. When Vin > V+ the output of the op-amp is going
to draw a current to create a drop across the resistor in the inverting input.
158 CHAPTER 10. OPERATIONAL AMPLIFIERS

This to keep V− = V+ . Thus, the output is one diode drop below VCC /3. When
Vin < V+ the current has to flow the other way to raise the potential of V− to the
same value as V+ . However, the diode will prevent this, and the feedback loop
will be broken and the output will be VCC . The circuit then gives a digital-type
output depending on where the value of Vin is relative to V+ .
Chapter 11

Connecting Digital to Analog and

to the World

11.1 Exercises
Exercise 11.1 What is the step voltage in the previous example (Figure 11.12 in the
textbook, shown below)?
V N
1 0 1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 t (m s )

1 0 1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 t (m s )

1 0 1 1 1
1 1 0
1 0 1
1 0 0
0 1 1
0 1 0
0 0 1
0 0 0
1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 t (m s )

159
160CHAPTER 11. CONNECTING DIGITAL TO ANALOG AND TO THE WORLD

Solution:
10V
Vstep = = 1.42 V
23 − 1

Exercise 11.2 What is the sampling rate in the previous example (Figure 11.13 in
the textbook, shown below)?

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 t (m s )

1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 t (m s )
Solution: Sampling time is ts = 1 ms, so the rate is 1/ts = 1 kHz.

Exercise 11.3 List all the possible sensing transducers in a car.

Solution: Temperature (thermostat, climate control, engine temperature), accel-

eration (anti-lock brakes), pressure (tire pressure, oil pressure), fuel and liquid-level
sensors, speed sensor.

Exercise 11.4 Describe a system controlled by a computer that uses transducers.

Describe also the role of the computer in relation to the signal received or sent to the
transducer.

Solution: There are many sophisticated systems that do this. One with high
visibility is the system that helps navigate launch vehicles, especially sophisticated
ones, like the space shuttle, and phased out recently. It was common for launches to
be scrubbed, because at critical countdown times the on-board computers, which read
sensors critical to the launching process, find that there is a problem. The sensors
measure temperature, pressure, position (valves that must open or close), and other
quantities to make sure that once the launch begins, the astronauts sitting on top of
a fireball get sent safely into space.
11.2. PROBLEMS 161

11.2 Problems
1. Suppose that both the inputs of the plain TTL NAND circuit of Figure 11.1
(ERRATUM: the textbook incorrectly says 11.3; the circuit is shown below) are
logic 1’s.

R 1 =
R 2 = R 3 =
4 k W 1 .6 k W 4 k W

A
Q 1 Q 2

B F
Q 4
R 4 =
1 k W

(a) As we mentioned earlier, a consequence is that transistor Q1 is off, but

current goes into the collector from the base of Q1 . As a result, Q2 is on
and Q4 is on. Although we have not demonstrated it, let us assume this is
correct. Find the potential of the base of Q2 . (Hint: What is the voltage
drop at p–n junctions?)
Solution: Since Q2 and Q4 are on, the base of Q2 is two diode drops above
ground: 0.6V + 0.6V = 1.2 V.
(b) The base of Q2 receives current that comes from the base of Q1 . Thus, the
B-C junction of Q1 is forward-biased. What is the base current on Q1 ?
Solution: The base of Q1 is a diode drop above the base of Q2 , or 1.8 V. The
current into Q1 is the current through R1 , or IB1 = (5V − 1.8V)/(4kΩ) =
0.8 mA.
(c) If Q2 is in saturation, what is the collector current of Q2 ? (Hint: What is
VCE in a transistor that is saturated?)
Solution: The collector of Q2 is at potential VC2 = 0.6V + 0.2V = 0.8
V. The collector current is the current through R2 , or IC2 = (5V −
0.8V)/1.6kΩ = 2.6 mA.
(d) How much current flows through R4 ?
Solution VE2 = 0.6 V, so I4 = (0.6V)/(1kΩ) = 0.6 mA.
(e) Now let us assume that the base current of Q2 is the base current of Q1
(part (b)) plus 0.1 mA. What is the base current of Q4 ?
162CHAPTER 11. CONNECTING DIGITAL TO ANALOG AND TO THE WORLD

Solution: The base current of Q4 is

IB4 = IB1 +0.1mA+IC2 −I4 = 0.8mA+0.1mA+2.6mA−0.6mA = 2.9 mA

(f) If Q4 is in saturation, how much current flows into Q4 from the collector
when the output of the gate is not connected to anything?
Solution: The collector of Q4 is at a potential VC4 = 0.2 V, so the current
flowing through R3 is IC4 = (5V − 0.2V)/(4kΩ) = 1.2 mA.
(g) Fanout is the capability of a gate to drive other gates. It is typically the
number of gates it can drive. In this case, driving means sinking 1.1 mA
per gate (see Equation 11.1 of the textbook). If the transistor Q4 has
β = 25, what is a reasonable fanout keeping in mind that we need to keep
Q4 saturated. (Hint: What is the saturation condition?)
Solution: The saturation condition is IC4 < βIB4 . βIB4 = 25 · 2.9mA =
72.5 mA. From a previous part, IC4max = 1.2 mA. So, βIB4 − IC = 71.3
mA. The latter is the most collector current that the transistor can have
without saturating Q4 . (71.3mA)/(1.1mA) = 64.8 would be the number
of gates we can drive. Prudently, we can cut that by a factor of 2 and then
be safe.

2. Find the function of the CMOS gate shown in Figure 11.16 (shown below).

Solution: Filling the truth table (below), we find it is a NOR gate.

11.2. PROBLEMS 163

A B F
0 0 1
0 1 0
1 0 0
1 1 0

3. A motor with an impedance of 25 Ω must be powered with the 5 V from a (1)

digital TTL gate or (2) CMOS gate. One input to the motor should be 5 V
, and the other motor input must be at ground potential. Draw the diagram
that is needed to energize the motor. Justify the components that you use.
Solution: 5V/25Ω = 0.2A is too much for a gate to put out. We can use a
power booster buffer, as shown below.

4. For the cases shown, explain in detail which of the circuits is better than the
other.

(a) TTL digital input I/O:

R = 1 k W

O R
R = 1 k W

Solution: The left one is good because it drives the gate well. The one on
the right is not good because the input to the gate is always connected to
+5 V.
(b) TTL digital output I/O:
164CHAPTER 11. CONNECTING DIGITAL TO ANALOG AND TO THE WORLD

O R

Solution: The one on the left is good because the gate can sink the current
that is needed to drive the LED. The one on the right is not good because
the gate cannot source the current that is needed (tens of mA).

5. Your current employer hires you to design the alarm system of an ultra-secure
vault to store secret disks sought by none other than Ethan Hunt (Mission
Impossible). The alarm system has two parts: a sensor unit and logic unit.
Your employer gives you the specifications outlined. However, Dr. Evil is
blackmailing you to provide him with a back-door entry that he will give to
Ethan Hunt as part of another blackmail scheme. The specifications are the
following:

(a) Sensors. Four sensors must produce a logic 1 (5 V) when: (1) weight on
the floor inside the vault, on a special slab, detects a person’s weight, (2)
the temperature of the vault exceeds some low value (that is, detects a
person’s body temperature), (3) the sound level inside the sound-proof
vault exceeds a minimum (pin-drop sound) level, and (4) the path of a
laser beam reflected by an elaborate set of mirrors and ending on a light
detector is broken. The sensors work the following way:
• The weight sensor is a switch that closes when a person steps on the
floor slab of the vault.

• The temperature sensor is a resistor (thermistor) whose resistance

value decreases as the temperature increases. The trip point for body
temperature is 10 kΩ.
11.2. PROBLEMS 165

• The sound sensor is a microphone that puts out an AC signal. The

trip sound level has an amplitude of 50 mV (peak).

• The light sensor is a phototransistor that, when illuminated by the

laser, puts the transistor into saturation.

You must devise a circuit for each of these sensors. That is, each circuit
takes the input in the form specified and translates it to a digital logic
value of 1 (5 V) when the trip point is exceeded (for temperature and
sound), or the condition is met (person on the floor or laser-beam path
interrupted).

(b) The logic of the alarm system must include:

• If the weight sensor circuit puts a 1, then the alarm gets turned on.
• If two or more of the other sensors put a 1, then the alarm gets turned
on. This is to avoid fluke trips produced by a bug.
• For the back-door entry, if all the sensors get triggered at the same
time, the alarm does not get turned on. That is, if Ethan steps on the
floor of the vault and turns on a hair dryer, flips on a boom-box, and
blocks the laser beam simultaneously, he is safe to get the disks.
• The output of this logic circuit must switch a 10-V 70-Ω relay that
turns on the alarm system.

Design a circuit that implements the alarm system. It has the sensor logic
outputs as inputs, and must drive the relay to turn on the alarm system.

Solution: The circuits of the various components follow:

(i) Weight sensor: Since it is a switch, we just bias it properly.

166CHAPTER 11. CONNECTING DIGITAL TO ANALOG AND TO THE WORLD

(ii) Temperature sensor: Since there is a tripping point we make a comparator

that drives a logic signal when the temperature exceeds the tripping point. In
our case, at low temperature the resistance is above 10 kΩ, and so V+ > V− =
2.5 V, so the output of the comparator is low. When the temperature increases
above the tripping point V+ < V− = 2.5 V and the output of the comparator is
high (logic 1).

(iii) Sound sensor: We amplify the signal, then rectify it with a peak detector,
and compare it to 5 V. The circuit is shown below.
11.2. PROBLEMS 167

(iv) Light sensor: This is another switch. When the laser beam is incident on
the phototransistor, it is saturated, and grounds the input of the first NOT
gate, making the output of the second NOT be 0. When interrupted, the
phototransistor is an open circuit so the input of the first NOT gate is a logic
1. The second NOT gate inverts the output of the first one to give a logic 1.

Finally we need to do the logic. First we need to fill a truth table, with the
sensor outputs labeled A, B, C and D.
168CHAPTER 11. CONNECTING DIGITAL TO ANALOG AND TO THE WORLD

A B C D F
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 0
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
Then we simplify using Karnaugh maps, and get
F = AC ′ + AD′ + BDC ′ + A′ BC + B ′ CD
When F = 1 we drive a transistor switch that turns the load on.

6. If we have a digitizing scope that has a 10 V, 6-bit, 10 ns conversion time A/D

at its input, what are the minimum requirements on the input signal such that
the scope is able to measure it?
Solution: The minimum detectable variations must be greater than
10V
Vstep = = 0.156 V
26 − 1
11.2. PROBLEMS 169

The maximum frequency should be fmax = 1/tc = 5 · 107 MHz.

7. Suppose that we are designing a computer-automated temperature controller.

(a) The temperature gauge gives an output voltage given by Vg = 0.1T , where
T is the temperature in degrees Celsius. For temperatures between 0 and
100◦ C, a 1-10 V A/D can be used. What is the minimum number of bits
the A/D converter must have to be sensitive to temperature variations of
0.2 ◦ C? Justify your answer.
Solution Vstep < 0.1 · 0.2◦ C = 0.02 V. If we equate this to (10V)/(2n − 1),
we get n = 8.97 ∼ 9.
(b) A digital circuit compares the digitized number to a number that represents
a set temperature. If the reading is below this temperature, the comparator
outputs a logic 1, otherwise it outputs a logic 0. Design a circuit that will
drive a 15 V 1 A heater when this happens. Assume that the digital output
comes from a typical TTL gate. Draw the circuit diagram and explain its
operation.
Solution: We connect the output of the comparator, inverted or not, such
that we get 5 V to drive the heater. We connect the 5-V signal to a resistor,
and the other end to a transistor switch, shown below. The load resistance
is RL = 15V/1A = 15 Ω. We use a power transistor with β = 100. The
estimated base current that puts the transistor in normal operation at 1 A
is IB = ICmax /β = 10 mA. The base resistor for making this a transistor
switch requires IB > 10 mA, say 50 mA. The base resistor will then be
RB = (5V − 0.6V)/(50mA = 167 Ω.

8. In a modern type of telephone, the signal generated by the speaker is filtered

such that audio above the highest human voice’s frequency of 4 kHz is sup-
pressed. After the filter, there is an amplifier followed by an 6-bit A/D con-
verter.
170CHAPTER 11. CONNECTING DIGITAL TO ANALOG AND TO THE WORLD

(a) What is the maximum conversion time of the A/D?

Solution: tc = 1/(2 · 4kHz) = 0.125 ms.
(b) If the maximum voltage for the A/D is 10V, what is the minimum de-
tectable voltage change in the amplified audio signal.
Solution: Vstep = 10V/(26 − 1) = 0.159 V.