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Create New Coal Id

The document provides instructions for a simple hypothetical machine. It includes performing two steps - instruction fetch and instruction execute - for three sample instructions individually. The instruction fetch step involves loading the instruction from memory into registers. The instruction execute step involves performing the operation specified by the opcode and updating register and memory values accordingly. Flags are also set after arithmetic operations in the execute step.

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Hassaan Ahmad Khawaja
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© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
143 views

Create New Coal Id

The document provides instructions for a simple hypothetical machine. It includes performing two steps - instruction fetch and instruction execute - for three sample instructions individually. The instruction fetch step involves loading the instruction from memory into registers. The instruction execute step involves performing the operation specified by the opcode and updating register and memory values accordingly. Flags are also set after arithmetic operations in the execute step.

Uploaded by

Hassaan Ahmad Khawaja
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 27

ID: ___________

NAME: _____________________________________

SECTION: _________

Consider last four digits of your ID and ADD 5555H to all digits and create your new COAL ID in HEX as
shown in example below

Example ID
1 2 8 9
+ Added Value
5 5 5 5
Example COAL ID
6 7 D E
0110 0111 1101 1110

CREATE NEW COAL ID

Your ID

Added Value
5 5 5 5
COAL NEW ID

Binary

MS-BCD LS-BCD
ASSIGNMENT 4 (EE-204)

1. Consider the following code and fill given registers and memory accordingly?
NOTE: Multiplicand is last digit of your NEW COAL ID to it whereas Multiplier is second last digital of your
New COAL ID?

al bl
CF multiplicand Multiplier CF result

Page 2 of 27
ASSIGNMENT 4 (EE-204)

2. Consider the following code and fill given registers and memory accordingly?
NOTE: Where Multiplicand is your NEW ID whereas Multiplier is given in declaration.

Page 3 of 27
ASSIGNMENT 4 (EE-204)

Page 4 of 27
ASSIGNMENT 4 (EE-204)

Page 5 of 27
ASSIGNMENT 4 (EE-204)

3. Change above given code for following data declaration?

Page 6 of 27
ASSIGNMENT 4 (EE-204)

4. Perform unsigned binary multiplication using following given flow chart?


NOTE: Your computer width is 8-bit, Multiplicand is last 2 digits of your NEW ID, Multiplier is 0A5H

Page 7 of 27
ASSIGNMENT 4 (EE-204)

5. Write code in assembly language to implement the above mentioned flow chart. (Attach sheet for
code here).

Page 8 of 27
ASSIGNMENT 4 (EE-204)

6. Perform Multiplication using Booth’s algorithm?


NOTE: Your computer width is 10-bit, Multiplicand is 2’s complement of last 2 digits of your NEW ID
(Means it’s a signed and negative number), Multiplier is 0A5H

Page 9 of 27
ASSIGNMENT 4 (EE-204)

7. Write code in assembly language to implement the above mentioned flow chart. (Attach sheet for
code here).

Page 10 of 27
ASSIGNMENT 4 (EE-204)

8. Perform Unsigned binary division?


NOTE: Your computer width is 8-bit, where dividend is last 2 digits of your NEW ID, Divisor is 003H

9. Write code in assembly language to implement the above mentioned flow chart. (Attach sheet for
code here).

Page 11 of 27
ASSIGNMENT 4 (EE-204)

10. Apply following peace of code and update register accordingly?

Page 12 of 27
ASSIGNMENT 4 (EE-204)

11. Save your NEW ID in BX register and calculate number of one’s in your ID

12. Find number of odd numbers in following array?

NOTE: Using shifting to find whether number is odd/ or even

Page 13 of 27
ASSIGNMENT 4 (EE-204)

13. Write a program that take 4 digits of your NEW ID and save them in separate memory
location of size byte?
NOTE: Supposed to use rotate and shift instructions

Page 14 of 27
ASSIGNMENT 4 (EE-204)

INSTRUCTIONS: (Question 14) Consider a simple hypothetical machine that includes a


single data register, called an accumulator (AC), 16-bits long instructions and data. Memory
is organized using 16-bit words. The instruction format provides 4 bits for the opcode and 12
bits for the memory address.
Following Figure is showing the relevant portions of memory:
Address Memory Registers
400 2900 PC 400
401 0901 AC
402 5005 IR
403 4006 MAR
404 6902 MBR
405 9500 I/OAR
406 5006 I/OMR
407 2902
…... I/O Devices
500 3901 …
…. 005 867E
900 80EF 006 7AEE
901 90FF 007 FFFF
902 FFFF ….

PC = Program counter
IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Instruction Format:
16-bit instructions
Bits 0-3 is Operation Code (Op Code)
Bits 4-15 is Address

Operation Codes (Op Code)


0000 Add to AC from memory AC = AC + [Address]
0010 Load AC from memory AC = [Address]
0011 Store AC to memory [Address] = AC
0100 Load AC from I/O AC = [Device_Address]
0101 Load I/O from AC [Device Address] = AC
0110 Subtract memory from AC AC = AC – [Address]
1001 Jump to the address PC = Address

Page 15 of 27
ASSIGNMENT 4 (EE-204)

Perform two steps individually for each instruction:


Instruction Fetch
Instruction Execute
(Fill corresponding tables)
After execution of arithmetic operations, set the values of the flags as well after the execution
step.

Fetch Step 1 Execute Step 1


Memory Registers Memory Registers
400 2900 PC 400 400 2900 PC
401 0901 AC 401 0901 AC
402 5005 IR 402 5005 IR
403 4006 MAR 403 4006 MAR
404 6902 MBR 404 6902 MBR
405 9500 I/OAR 405 9500 I/OAR
406 5006 I/OMR 406 5006 I/OMR
407 2902 407 2902
…... I/O Device …... I/O Device
500 3901 … 500 3901 …
…. 005 867E …. 005 867E
900 80EF 006 7AEE 900 80EF 006 7AEE
901 90FF 007 FFFF 901 90FF 007 FFFF
902 FFFF …. 902 FFFF ….

Fetch Step 2 Execute Step 2


Memory Registers Memory Registers
400 2900 PC 400 2900 PC
401 0901 AC 401 0901 AC
402 5005 IR 402 5005 IR
403 4006 MAR 403 4006 MAR
404 6902 MBR 404 6902 MBR
405 9500 I/OAR 405 9500 I/OAR
406 5006 I/OMR 406 5006 I/OMR
407 2902 407 2902
…... I/O Device …... I/O Device
500 3901 … 500 3901 …
…. 005 867E …. 005
900 80EF 006 7AEE 900 80EF 006 7AEE
901 90FF 007 FFFF 901 90FF 007 FFFF
902 FFFF …. 902 FFFF ….

Page 16 of 27
ASSIGNMENT 4 (EE-204)

Fetch Step 3 Execute Step 3


Memory Registers Memory Registers
400 2900 PC 400 2900 PC
401 0901 AC 401 0901 AC
402 5005 IR 402 5005 IR
403 4006 MAR 403 4006 MAR
404 6902 MBR 404 6902 MBR
405 9500 I/OAR 405 9500 I/OAR
406 5006 I/OMR 406 5006 I/OMR
407 2902 407 2902
…... I/O Device …... I/O Device
500 3901 … 500 3901 …
…. 005 867E …. 005 867E
900 80EF 006 7AEE 900 80EF 006 7AEE
901 90FF 007 FFFF 901 90FF 007 FFFF
902 FFFF …. 902 FFFF ….

Fetch Step 4 Execute Step 4


Memory Registers Memory Registers
400 2900 PC 400 2900 PC
401 0901 AC 401 0901 AC
402 5005 IR 402 5005 IR
403 4006 MAR 403 4006 MAR
404 6902 MBR 404 6902 MBR
405 9500 I/OAR 405 9500 I/OAR
406 5006 I/OMR 406 5006 I/OMR
407 2902 407 2902
…... I/O Device …... I/O Device
500 3901 … 500 3901 …
…. 005 867E …. 005 867E
900 80EF 006 7AEE 900 80EF 006 7AEE
901 90FF 007 FFFF 901 90FF 007 FFFF
902 FFFF …. 902 FFFF ….

Page 17 of 27
ASSIGNMENT 4 (EE-204)

Fetch step 5 Execute step 5


Memory Registers Memory Registers
400 2900 PC 402 400 2900 PC 403
401 0901 AC 11EE 401 0901 AC
402 5005 IR 5005 402 5005 IR
403 4006 MAR 402 403 4006 MAR
404 6902 MBR 5005 404 6902 MBR
405 9500 I/OAR 405 9500 I/OAR
406 5006 I/OMR 406 5006 I/OMR
407 2902 407 2902
…... I/O Device …... I/O Device
500 3901 … 500 3901 …
…. 005 867E …. 005 11EE
900 80EF 006 7AEE 900 80EF 006 7AEE
901 90FF 007 FFFF 901 90FF 007 FFFF
902 FFFF …. 902 FFFF ….

Fetch step 6 Execute step 7


Memory Registers Memory Registers
400 2900 PC 403 400 2900 PC 404
401 0901 AC 11EE 401 0901 AC
402 5005 IR 5005 402 5005 IR
403 4006 MAR 403 4006 MAR
404 6902 MBR 404 6902 MBR
405 9500 I/OAR 005 405 9500 I/OAR
406 5006 I/OMR 11EE 406 5006 I/OMR
407 2902 407 2902
…... I/O Device …... I/O Device
500 3901 … 500 3901 …
…. 005 867E …. 005 11EE
900 80EF 006 7AEE 900 80EF 006 7AEE
901 90FF 007 FFFF 901 90FF 007 FFFF
902 FFFF …. 902 FFFF ….

Page 18 of 27
ASSIGNMENT 4 (EE-204)

Fetch Step 7 Execute Step 7


Memory Registers Memory Registers
400 2900 PC 403 400 2900 PC 404
401 0901 AC 11EE 401 0901 AC
402 5005 IR 4006 402 5005 IR
403 4006 MAR 403 403 4006 MAR
404 6902 MBR 4006 404 6902 MBR
405 9500 I/OAR 405 9500 I/OAR
406 5006 I/OMR 406 5006 I/OMR
407 2902 407 2902
…... I/O Devices …... I/O Devices
500 3901 … 500 3901 …
…. 005 11EE …. 005 11EE
900 80EF 006 7AEE 900 80EF 006 7AEE
901 90FF 007 FFFF 901 90FF 007 FFFF
902 FFFF …. 902 FFFF ….

INSTRUCTIONS: (Question 15) Consider a simple hypothetical machine that includes a


single data register, called an accumulator (AC), 16-bits long instructions and data. Memory
is organized using 16-bit words. The instruction format provides 4 bits for the opcode and 12
bits for the memory address.
Following Figure is showing the relevant portions of memory:
Address Memory Registers
840 2900 PC 840
841 7901 AC
842 5005 IR
843 4006 MAR
844 6902 MBR
845 2840 I/OAR
846 7006 I/OMR
847 3902
--- I/O Devices
850 3901 …
--- 005 8675
900 80EF 006 7A33
901 2305 007 8414
902 1214 ….

Page 19 of 27
ASSIGNMENT 4 (EE-204)

PC = Program counter
IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Instruction Format:
16-bit instructions
Bits 0-3 is Operation Code (Op Code)
Bits 4-15 is Address

Operation Codes (Op Code)


0111 Add to AC from memory AC = AC + [Address]
0010 Load AC from memory AC = [Address]
0011 Store AC to memory [Address] = AC
0100 Load AC from I/O AC = [Device_Address]
0101 Load I/O from AC [Device Address] = AC
0110 Subtract memory from AC AC = AC – [Address]

Perform two steps individually for each instruction:


Instruction Fetch
Instruction Execute
(Fill corresponding tables)
After execution of arithmetic operations, set the values of the flags as well after the execution
step.

Fetch Step 1 Execute Step 1


Memory Registers Memory Registers
840 2900 PC 840 840 2900 PC
841 7901 AC 841 7901 AC
842 5005 IR 842 5005 IR
843 4006 MAR 843 4006 MAR
844 6902 MBR 844 6902 MBR
845 2840 I/OAR 845 2840 I/OAR
846 7006 I/OMR 846 7006 I/OMR
847 3902 847 3902
--- I/O Devices --- I/O Devices
850 3901 … 850 3901 …
--- 005 8675 --- 005 8675
900 80EF 006 7A33 900 80EF 006 7A33
901 2305 007 8414 901 2305 007 8414
902 1214 …. 902 1214 ….

Page 20 of 27
ASSIGNMENT 4 (EE-204)

Fetch Step 2 Execute Step 2


Memory Registers Memory Registers
840 2900 PC 840 840 2900 PC 840
841 7901 AC 841 7901 AC
842 5005 IR 842 5005 IR
843 4006 MAR 843 4006 MAR
844 6902 MBR 844 6902 MBR
845 2840 I/OAR 845 2840 I/OAR
846 7006 I/OMR 846 7006 I/OMR
847 3902 847 3902
--- I/O Devices --- I/O Devices
850 3901 … 850 3901 …
--- 005 8675 --- 005 8675
900 80EF 006 7A33 900 80EF 006 7A33
901 2305 007 8414 901 2305 007 8414
902 1214 …. 902 1214 ….

Fetch Step 3 Execute Step 3


Memory Registers Memory Registers
840 2900 PC 840 2900 PC
841 7901 AC 841 7901 AC
842 5005 IR 842 5005 IR
843 4006 MAR 843 4006 MAR
844 6902 MBR 844 6902 MBR
845 2840 I/OAR 845 2840 I/OAR
846 7006 I/OMR 846 7006 I/OMR
847 3902 847 3902
--- I/O Devices --- I/O Devices
850 3901 … 850 3901 …
--- 005 8675 --- 005 8675
900 80EF 006 7A33 900 80EF 006 7A33
901 2305 007 8414 901 2305 007 8414
902 1214 …. 902 1214 ….

Page 21 of 27
ASSIGNMENT 4 (EE-204)

Fetch step 4 Execute step 4


Memory Registers Memory Registers
840 2900 PC 840 2900 PC
841 7901 AC 841 7901 AC
842 5005 IR 842 5005 IR
843 4006 MAR 843 4006 MAR
844 6902 MBR 844 6902 MBR
845 2840 I/OAR 845 2840 I/OAR
846 7006 I/OMR 846 7006 I/OMR
847 3902 847 3902
--- I/O Devices --- I/O Devices
850 3901 … 850 3901 …
--- 005 8675 --- 005 8675
900 80EF 006 7A33 900 80EF 006 7A33
901 2305 007 8414 901 2305 007 8414
902 1214 …. 902 1214 ….

Fetch step 5 Execute step 5


Memory Registers Memory Registers
840 2900 PC 840 2900 PC
841 7901 AC 841 7901 AC
842 5005 IR 842 5005 IR
843 4006 MAR 843 4006 MAR
844 6902 MBR 844 6902 MBR
845 2840 I/OAR 845 2840 I/OAR
846 7006 I/OMR 846 7006 I/OMR
847 3902 847 3902
--- I/O Devices --- I/O Devices
850 3901 … 850 3901 …
--- 005 8675 --- 005 8675
900 80EF 006 7A33 900 80EF 006 7A33
901 2305 007 8414 901 2305 007 8414
902 1214 …. 902 1214 ….

Page 22 of 27
ASSIGNMENT 4 (EE-204)

Fetch Step 6 Execute Step 6


Memory Registers Memory Registers
840 2900 PC 840 2900 PC
841 7901 AC 841 7901 AC
842 5005 IR 842 5005 IR
843 4006 MAR 843 4006 MAR
844 6902 MBR 844 6902 MBR
845 2840 I/OAR 845 2840 I/OAR
846 7006 I/OMR 846 7006 I/OMR
847 3902 847 3902
--- I/O Devices --- I/O Devices
850 3901 … 850 3901 …
--- 005 8675 --- 005 8675
900 80EF 006 7A33 900 80EF 006 7A33
901 2305 007 8414 901 2305 007 8414
902 1214 …. 902 1214 ….

Fetch Step 7 Execute Step 7


Memory Registers Memory Registers
840 2900 PC 840 2900 PC
841 7901 AC 841 7901 AC
842 5005 IR 842 5005 IR
843 4006 MAR 843 4006 MAR
844 6902 MBR 844 6902 MBR
845 2840 I/OAR 845 2840 I/OAR
846 7006 I/OMR 846 7006 I/OMR
847 3902 847 3902
--- I/O Devices --- I/O Devices
850 3901 … 850 3901 …
--- 005 8675 --- 005 8675
900 80EF 006 7A33 900 80EF 006 7A33
901 2305 007 8414 901 2305 007 8414
902 1214 …. 902 1214 ….

Page 23 of 27
ASSIGNMENT 4 (EE-204)

INSTRUCTIONS: (Question 16) Consider a simple hypothetical machine that includes a


single data register, called an accumulator (AC), 16-bits long instructions and data. Memory
is organized using 16-bit words. The instruction format provides 4 bits for the opcode and 12
bits for the memory address.
Following Figure is showing the relevant portions of memory:
Address Memory Registers
400 Last 4 digits of PC 400
your ID
401 2901 AC
402 4005 IR
403 6006 MAR
404 0902 MBR
405 2900 I/OAR
406 4006 I/OMR
407 3902
…... I/O Device
500 5901 …
…. 005 1214
900 3527 006 0512
901 1392 007 0132
902 1514 ….

PC = Program counter
IR = Instruction register
MAR = Memory address register
MBR = Memory buffer register
I/O AR = Input/output address register
I/O BR = Input/output buffer register
Instruction Format:
16-bit instructions
Bits 0-3 is Operation Code (Op Code)
Bits 4-15 is Address

Operation Codes (Op Code)


0010 Add to AC from memory AC = AC + [Address]
0011 Load AC from memory AC = [Address]
0101 Store AC to memory [Address] = AC
0110 Load AC from I/O AC = [Device_Address]
0100 Load I/O from AC [Device Address] = AC
0000 Subtract memory from AC AC = AC – [Address]

Page 24 of 27
ASSIGNMENT 4 (EE-204)

Fetch Step 1 Execute Step 1


Memory Registers Memory Registers
400 ID PC 400 400 ID PC 400
401 2901 AC 401 2901 AC
402 4005 IR 402 4005 IR
403 6006 MAR 403 6006 MAR
404 0902 MBR 404 0902 MBR
405 2900 I/OAR 405 2900 I/OAR
406 4006 I/OMR 406 4006 I/OMR
407 3902 407 3902
…... I/O Device …... I/O Device
500 5901 … 500 5901 …
…. 005 1214 …. 005 1214
900 3527 006 0512 900 3527 006 0512
901 1392 007 0132 901 1392 007 0132
902 1514 …. 902 1514 ….

Fetch Step 2 Execute Step 2


Memory Registers Memory Registers
400 ID PC 400 400 ID PC 400
401 2901 AC 401 2901 AC
402 4005 IR 402 4005 IR
403 6006 MAR 403 6006 MAR
404 0902 MBR 404 0902 MBR
405 2900 I/OAR 405 2900 I/OAR
406 4006 I/OMR 406 4006 I/OMR
407 3902 407 3902
…... I/O Device …... I/O Device
500 5901 … 500 5901 …
…. 005 1214 …. 005 1214
900 3527 006 0512 900 3527 006 0512
901 1392 007 0132 901 1392 007 0132
902 1514 …. 902 1514 ….

Page 25 of 27
ASSIGNMENT 4 (EE-204)

Fetch Step 3 Execute Step 3


Memory Registers Memory Registers
400 ID PC 400 400 ID PC 400
401 2901 AC 401 2901 AC
402 4005 IR 402 4005 IR
403 6006 MAR 403 6006 MAR
404 0902 MBR 404 0902 MBR
405 2900 I/OAR 405 2900 I/OAR
406 4006 I/OMR 406 4006 I/OMR
407 3902 407 3902
…... I/O Device …... I/O Device
500 5901 … 500 5901 …
…. 005 1214 …. 005 1214
900 3527 006 0512 900 3527 006 0512
901 1392 007 0132 901 1392 007 0132
902 1514 …. 902 1514 ….

Fetch Step 4 Execute Step 4


Memory Registers Memory Registers
400 ID PC 400 400 ID PC 400
401 2901 AC 401 2901 AC
402 4005 IR 402 4005 IR
403 6006 MAR 403 6006 MAR
404 0902 MBR 404 0902 MBR
405 2900 I/OAR 405 2900 I/OAR
406 4006 I/OMR 406 4006 I/OMR
407 3902 407 3902
…... I/O Device …... I/O Device
500 5901 … 500 5901 …
…. 005 1214 …. 005 1214
900 3527 006 0512 900 3527 006 0512
901 1392 007 0132 901 1392 007 0132
902 1514 …. 902 1514 ….

Page 26 of 27
ASSIGNMENT 4 (EE-204)

Fetch Step 5 Execute Step 5


Memory Registers Memory Registers
400 ID PC 400 400 ID PC 400
401 2901 AC 401 2901 AC
402 4005 IR 402 4005 IR
403 6006 MAR 403 6006 MAR
404 0902 MBR 404 0902 MBR
405 2900 I/OAR 405 2900 I/OAR
406 4006 I/OMR 406 4006 I/OMR
407 3902 407 3902
…... I/O Device …... I/O Device
500 5901 … 500 5901 …
…. 005 1214 …. 005 1214
900 3527 006 0512 900 3527 006 0512
901 1392 007 0132 901 1392 007 0132
902 1514 …. 902 1514 ….

Fetch Step 6 Execute Step 6


Memory Registers Memory Registers
400 ID PC 400 400 ID PC 400
401 2901 AC 401 2901 AC
402 4005 IR 402 4005 IR
403 6006 MAR 403 6006 MAR
404 0902 MBR 404 0902 MBR
405 2900 I/OAR 405 2900 I/OAR
406 4006 I/OMR 406 4006 I/OMR
407 3902 407 3902
…... I/O Device …... I/O Device
500 5901 … 500 5901 …
…. 005 1214 …. 005 1214
900 3527 006 0512 900 3527 006 0512
901 1392 007 0132 901 1392 007 0132
902 1514 …. 902 1514 ….

Page 27 of 27

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