Synthesis Training
Synthesis Training
Open-Silicon, Inc
June 25, 2007
Open-Silicon Confidential
Session Goals
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Different Levels of Abstraction
Idea Conceptual idea about a functionality, that is thought through in the mind.
Functional A functional representation of the idea, in the form of a flow chart or other
text information. (specification).
Behavioral A model that can be verified by a concept simulation. This may be written
using a HDL or other high level languages like C.
RTL Register Transfer Level, which is the architectural HDL that can be
converted into a logical representation.
Logical RTL mapped into an equivalent gate level netlist using a target library.
Physical Physical specification that will help realize the device in silicon.
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What is Synthesis?
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Synthesis Process
HDL Description
Verilog / VHDL
Generic Boolean
Gtech
Target Tech
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Libraries… (for now)
Technology Library:
► Contains vendor specific set of technology specific
cells, their electrical parameters, physical
parameters, operating conditions, wlm, and their
units of measure.
► This is supplied by the vendor, and mostly delivered
in the complied form.
DW Library:
These are architectural libraries of technology independent
functions like adders, multipliers, comparators, FIFOs, etc.
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Libraries
►Link Library:
► The technology library which
provides complete information
(functional, wlm, operating conditions,
area, etc.) about the cells instantiated in
the design.
► set link_library [ ]
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Libraries
►Target Library:
► The technology library to which the
synthesis engine maps the design to
perform a specific function described by
the design.
► set target_library [ ]
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Libraries
►DW Library:
► These are architectural libraries of
technology independent functions like
adders, multipliers, comparators,
FIFOs, etc.
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Control Synthesis
process (clk)
begin B
x
if (clk’event and clk = ‘1’)
then - A
E
A <= B - (C + D); C
‘0’
if (x = ‘1’) then
400ps 150ps
E <= A;
+
Clk
else 400ps
D
E <= ‘0’;
800ps 400ps
end if;
400ps 550ps
end if;
end process;
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DataPath Synthesis: Resource sharing
C
x
+
B A
if (x = ‘1’) then
A <= B + C; +
‘1’
else
A <= B +
B
‘1’;
end if; x
+ A
C
‘1’
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Logic Synthesis
► Example: x
y
y
e
a g
f
b
x
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Logic Optimization
► Two-level optimization
― forPLAs g = y’ . (y. x’ + a . x) + y . (b . x)
― minimize the number of = y’ . a . x + y . b . x
minterms (K-maps,
Quinn-McKluskey)
► Multi-level optimization
― for standard cells, g = x . (a . y’ + b . y)
FPGAs
― minimize the number of
literals (kernel
extraction)
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Technology independent mapping
b x g
x b
g
y y
a a
x
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Technology Mapping
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Role of DC in Synthesis
Design Compiler
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Design Objects
Design – A logic circuit that performs a specified logic function
Reference – The design that a cell refers to. (so, there can be many cells pointing to the same
reference)
Net – The object that connects ports and/or pins of a design or cell.
Clock – A periodic waveform applied to the port or pin that functions as the clock source
to a sequential element in the design.
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Design Partitioning
It is a method used to divide the design into smaller functional elements, so that a very
complex design is split into simpler inner level modules.
Advantages:
► Better results
► Faster churning in tools (run time)
► Easier top level integration
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Typical Synchronous Design
To be Synthesized
C3 C4 C5
D Q C1 C2 D Q D Q D Q
FF1 FF2 FF3 FF4
CLK
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Design Constraints
► Clock constraints (Control performance of the design)
― Clock period
― Duty cycle 0 2.5 5
― Uncertainty (same as skew)
― Latency (same as insertion delay)
― Port (clock source)
Period
► Example
― create_clock -period 5.0 -waveform {0 2.5} find(port *CLK) D Q D Q
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Design constraints …
► Input Constraints
― Applied to input pins of design
― Arrival time of the input signal wrt to clock
― Driving strength (drive resistance / drive cell)
0 2.5 5
D Q C1 C2 D Q
FF1 FF2
Stable Stable
min delay
max delay
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Design constraints …
► Examples
― set_input_delay -min 1.2 -clock CLK all_inputs() -find(port,
*CLK)
― set_input_delay -max 2.0 -clock CLK all_inputs() -find(port,
*CLK)
― set_driving_cell -cell BUFX2 -pin Y all_inputs() - find(port,
*CLK)
― Specified the library cell or pin that drives the input/inout
port
― set_drive 2.0 all_inputs() -find(port, *CLK)
― Smaller the value => higher is the drive (sets the drive
resistance (Kohms) of the input/inout port)
Setting the driving cell is preferable, since the drive cell’s various characteristics will get reflected
at the input port at the time of synthesis.
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Design Constraints ...
► Output Constraints
― Applied to output pins of the design
― Output signal required time wrt to clock
― Load
0 2.5 5 C4 C5
D Q D Q
FF3
Stable CLK
min delay
max delay
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Design Constraints
► Example
― set_output_delay -min -0.5 -clock CLK
all_outputs()
― set_output_delay -max 2.0 -clock CLK
all_outputs()
― set_load load_of (lib/cell/pin) all_outputs()
― set_load load_of (lib/cell/pin)*4 find (port, OUT)
― set_load 2.0 all_outputs()
― Sets a load of 2 units at the output ports.
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Exceptions
► False paths
► Multicycle paths
► Constant propagation
► Modes of operation
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Design Rules
set_max_transition v
(sets a max transition time value on ports or design)
90%
set_max_fanout
10%
t
Transition time
set_max_capacitance
(sets a max capacitance on ports or designs)
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Operating Conditions
Best
Typical
Worst
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Hierarchical synthesis
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Standard Cell Library
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Standard Cell Library ...
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Standard Cell Library ...
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Transition Time
90%
10%
t
Transition time
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Cell Delay
vin
50%
vout
Delay
50%
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.Lib Format
Cell (NAND2X1) Pin(Y)
Cell_footprint : nand2 ; direction : input ;
Area : 9.9792 ; capacitance : 0.0 ;
Pin(A) { function : “(!(A B))” ;
direction : input ; timing() {
capacitance : .00396 ; related pin : “A”;
} cell_rise (template_name)
{
Pin(B) { Index1(.. , .. , ..)
direction : input ; Index2(.. , .. , ..)
capacitance : .00375 ; values (table)
} cell_fall
rise_transition
fall_transition
}
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Standard Cell library ...
Cap .00035 0.021 0.0385 0.084 0.147 0.231 0.3115
Trans
0.05 .0445 0.1841 0.3005 0.6020 1.0190 1.5750 2.1070
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Wire load models
► Why?
― Synthesis need to model interconnect parasitic information
► What?
― WLM is based upon the characteristics of a statistically average net
for a given fanout contained within a given area of the die.
― The synthesis tool used WLM to estimate capacitance, resistance
and area of the nets connecting two cells/ports.
― Standard and custom WLMs.
► Issues
― Fanout based interconnect modeling is very inaccurate for today’s
technology (0.25, 0.18, 0.13)
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Sample wire load model
wire_load(“10x10") {
capacitance : 0.000060
resistance : 0.000034
area : 0.28
slope : 0.5
fanout_length(1, 2.493685)
fanout_length(2, 2.987365)
fanout_length(3, 3.481050)
fanout_length(4, 3.974750)
fanout_length(5, 4.962100)
fanout_length(6, 5.949450)
fanout_length(7, 7.936850)
}
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Wire load modes
20x20
► Top 10x10
5x5 7x7
10x10
5x5 7x7
► Segmented 10x10
20x20
10x10
5x5 7x7
7x7
5x5
10x10
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Report Generation
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Coding for Successful Synthesis
► Think in hardware
► Think HW reuse
► Follow proven coding guidelines
► Complete sensitivity list
► Blocking and non-blocking statements with care
► Priority encoder Vs parallel logic
► parallel_case and full_case
► State machine designs
► Avoid unintentional latches
► Multiple drivers to a flop
► Reset scheme for flops
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Recipe for Successful Synthesis
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Physical synthesis
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Topographical synthesis
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The End
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