0% found this document useful (0 votes)
444 views45 pages

Synthesis Training

The document discusses an introduction to synthesis training provided by Open-Silicon. It covers the goals of the training which are to introduce synthesis, define inputs and outputs, apply constraints, analyze strategies, and coding for successful synthesis. It also discusses different levels of abstraction from ideas to physical implementation. The synthesis process and use of libraries is explained.

Uploaded by

Pinky Nahar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
444 views45 pages

Synthesis Training

The document discusses an introduction to synthesis training provided by Open-Silicon. It covers the goals of the training which are to introduce synthesis, define inputs and outputs, apply constraints, analyze strategies, and coding for successful synthesis. It also discusses different levels of abstraction from ideas to physical implementation. The synthesis process and use of libraries is explained.

Uploaded by

Pinky Nahar
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 45

Synthesis Training

Open-Silicon, Inc
June 25, 2007
Open-Silicon Confidential
Session Goals

► Introduction to synthesis and the basic idea behind


the process.
► Synthesis inputs and outputs.
► Defining and applying constraints to drive synthesis.
► Synthesis strategies.
► Analyze the results of synthesis.
► RTL coding for successful synthesis
► New trends in synthesis

Open-Silicon Confidential
Different Levels of Abstraction

Idea Conceptual idea about a functionality, that is thought through in the mind.

Functional A functional representation of the idea, in the form of a flow chart or other
text information. (specification).

Behavioral A model that can be verified by a concept simulation. This may be written
using a HDL or other high level languages like C.

RTL Register Transfer Level, which is the architectural HDL that can be
converted into a logical representation.

Logical RTL mapped into an equivalent gate level netlist using a target library.

Physical Physical specification that will help realize the device in silicon.

Open-Silicon Confidential
What is Synthesis?

Synthesis is the process of translating a design idea


described in HDL, into a form that is optimized for
performance (timing and area) and that is
manufacturable into a device.
In the various levels of abstraction, the synthesis
process focuses on the RTL and the Logic Level
abstractions.

Open-Silicon Confidential
Synthesis Process

HDL Description
Verilog / VHDL

Generic Boolean

Gtech

Optimize while Mapping

Target Tech

Open-Silicon Confidential
Libraries… (for now)

Technology Library:
► Contains vendor specific set of technology specific
cells, their electrical parameters, physical
parameters, operating conditions, wlm, and their
units of measure.
► This is supplied by the vendor, and mostly delivered
in the complied form.

DW Library:
These are architectural libraries of technology independent
functions like adders, multipliers, comparators, FIFOs, etc.

Open-Silicon Confidential
Libraries

►Link Library:
► The technology library which
provides complete information
(functional, wlm, operating conditions,
area, etc.) about the cells instantiated in
the design.
► set link_library [ ]

Open-Silicon Confidential
Libraries

►Target Library:
► The technology library to which the
synthesis engine maps the design to
perform a specific function described by
the design.
► set target_library [ ]

Open-Silicon Confidential
Libraries

►DW Library:
► These are architectural libraries of
technology independent functions like
adders, multipliers, comparators,
FIFOs, etc.

Open-Silicon Confidential
Control Synthesis

► ROM based Control signals


ROM
― tryto minimize the width State
of memory word Next state

► FSM based start


10x S0, 01
― PLA or combinational S0, 10
logic based next state
00x
generation 01x
x01 x
1xx x10
― One-hot or minimal code 11x
length encoding
S0, 00 S0, 11
► Counter 0xx
based x11, x00
― stateassignment is
predefined
Open-Silicon Confidential 1
DataPath Synthesis: Retiming

process (clk)
begin B
x
if (clk’event and clk = ‘1’)
then - A
E
A <= B - (C + D); C
‘0’
if (x = ‘1’) then
400ps 150ps
E <= A;
+
Clk
else 400ps
D
E <= ‘0’;
800ps 400ps
end if;
400ps 550ps
end if;
end process;
Open-Silicon Confidential 1
DataPath Synthesis: Resource sharing

C
x
+
B A
if (x = ‘1’) then
A <= B + C; +
‘1’
else
A <= B +
B
‘1’;
end if; x
+ A
C

‘1’

Open-Silicon Confidential 1
Logic Synthesis

► Input: Synthesizable RTL


► Output: Interconnected abstract gates
► Operations:
― Two-level logic optimization
― Multi-level logic optimization
― Technology independent mapping

► Example: x
y
y
e
a g

f
b
x

Open-Silicon Confidential 1
Logic Optimization

► Two-level optimization
― forPLAs g = y’ . (y. x’ + a . x) + y . (b . x)
― minimize the number of = y’ . a . x + y . b . x
minterms (K-maps,
Quinn-McKluskey)

► Multi-level optimization
― for standard cells, g = x . (a . y’ + b . y)
FPGAs
― minimize the number of
literals (kernel
extraction)

Open-Silicon Confidential 1
Technology independent mapping

► Generic gates: AND, OR, NAND, NOR, NOT, XOR


etc
► No concept of power levels
► No timing, area model
Example: Two-level logic Example: Multi-level logic

b x g
x b
g
y y
a a
x

Open-Silicon Confidential 1
Technology Mapping

► Input: Technology independent logic


► Output: Interconnected library cells
► Operations:
― Structuring,flattening, grouping, boundary optimization
― Optimization for power, timing and/or area

Example: 2 input NOR implementation


b x
g
y

Open-Silicon Confidential 1
Role of DC in Synthesis

Design Constraints RTL Std Cell Libraries

Design Compiler

Mapped & Optimized Design

Open-Silicon Confidential 1
Design Objects
Design – A logic circuit that performs a specified logic function

Cell – An instance of the design, placed inside a design to for a hierarchy.

Reference – The design that a cell refers to. (so, there can be many cells pointing to the same
reference)

Port – Input or output of a design.

Pin – Input or output of a cell.

Net – The object that connects ports and/or pins of a design or cell.

Clock – A periodic waveform applied to the port or pin that functions as the clock source
to a sequential element in the design.

Open-Silicon Confidential 1
Design Partitioning
It is a method used to divide the design into smaller functional elements, so that a very
complex design is split into simpler inner level modules.

What is the need for partitioning?


► Divide and conquer idea.
► Separate distinct functional blocks.
► Focused verification efforts.
► Reuse of a module across various designs and projects.
► Workable size of a design for a set of tools.
► Parallelizing work among team members.
► Need to meet physical design challenges/constraints.

Advantages:
► Better results
► Faster churning in tools (run time)
► Easier top level integration

Open-Silicon Confidential 1
Typical Synchronous Design

To be Synthesized

C3 C4 C5
D Q C1 C2 D Q D Q D Q
FF1 FF2 FF3 FF4

CLK

* How do we constrain this design?

Open-Silicon Confidential 2
Design Constraints
► Clock constraints (Control performance of the design)
― Clock period
― Duty cycle 0 2.5 5
― Uncertainty (same as skew)
― Latency (same as insertion delay)
― Port (clock source)
Period
► Example
― create_clock -period 5.0 -waveform {0 2.5} find(port *CLK) D Q D Q

― set_clock_skew -ideal -delay 1.0 -uncertainty 0.5


all_clocks()
― set_clock_uncertainty
― set_clock_latency To be Synthesized
― set_dont_touch_network find (clock, CLK)

Open-Silicon Confidential 2
Design constraints …
► Input Constraints
― Applied to input pins of design
― Arrival time of the input signal wrt to clock
― Driving strength (drive resistance / drive cell)

0 2.5 5

D Q C1 C2 D Q
FF1 FF2

Stable Stable

min delay
max delay

Open-Silicon Confidential 2
Design constraints …

► Examples
― set_input_delay -min 1.2 -clock CLK all_inputs() -find(port,
*CLK)
― set_input_delay -max 2.0 -clock CLK all_inputs() -find(port,
*CLK)
― set_driving_cell -cell BUFX2 -pin Y all_inputs() - find(port,
*CLK)
― Specified the library cell or pin that drives the input/inout
port
― set_drive 2.0 all_inputs() -find(port, *CLK)
― Smaller the value => higher is the drive (sets the drive
resistance (Kohms) of the input/inout port)

Setting the driving cell is preferable, since the drive cell’s various characteristics will get reflected
at the input port at the time of synthesis.

Open-Silicon Confidential 2
Design Constraints ...

► Output Constraints
― Applied to output pins of the design
― Output signal required time wrt to clock
― Load

0 2.5 5 C4 C5
D Q D Q
FF3

Stable CLK
min delay

max delay

Open-Silicon Confidential 2
Design Constraints

► Example
― set_output_delay -min -0.5 -clock CLK
all_outputs()
― set_output_delay -max 2.0 -clock CLK
all_outputs()
― set_load load_of (lib/cell/pin) all_outputs()
― set_load load_of (lib/cell/pin)*4 find (port, OUT)
― set_load 2.0 all_outputs()
― Sets a load of 2 units at the output ports.

Open-Silicon Confidential 2
Exceptions

► False paths
► Multicycle paths
► Constant propagation
► Modes of operation

Open-Silicon Confidential 2
Design Rules
set_max_transition v
(sets a max transition time value on ports or design)
90%

set_max_fanout
10%
t
Transition time

set_max_capacitance
(sets a max capacitance on ports or designs)

* Can be found in lib also

Open-Silicon Confidential 2
Operating Conditions

These are the PVT conditions for which the synthesis


tool optimizes the paths in the design.
Cells delays and wire delays scale based on these
conditions.
Delay Delay Delay

Process Voltage Temp

Best
Typical
Worst

Open-Silicon Confidential 2
Hierarchical synthesis

► Top Down hier compile


― Read in the entire design
+ kind of push button, though it is actually
not!
― Resolve multiple instances
+ inter-module dependencies are
(uniquify) automatically taken care.
― Apply the constraints and - Heavy run time for the tools
attributes
- Does not work for huge designs
― Compile
― Preserve hier

► Bottom Up hier compile (divide and conquer)


+ better handling of the design
― Read in the sub-blocks independently
― Apply constraints from time budgeting + allows time budgeting among blocks
― Apply drive and load models and compile + managing in a team is easy
― Read in the compiled designs and apply top - Multiple iterations
level constraints - Needs good coordination to get the
― Check results
final netlist.

Open-Silicon Confidential 2
Standard Cell Library

► Library of predefined cells


― Covers most of the functions required for synthesis
― Each function is implemented for multiple driving strengths
― Cells follow same layout architecture
― Many different views of cells are available for different tasks during design cycle
― timing view, layout view etc.

Open-Silicon Confidential 3
Standard Cell Library ...

►.libview of std cell library is used for


synthesis (compiled view is .db)
►Contains
―Cellfunctionality
―Detailed timing and power information
about cells
― Look-up table format
―Cell Area

Open-Silicon Confidential 3
Standard Cell Library ...

► Cell Delay / Transition


― Depends on
― Transition time of inputs
― Load at the output
― .lib has lookup tables to specify delay/transition
― One axis is output load
― Other is input transition time
― Tables for each input output pair of pins
― rise delay, fall delay, rise transition, fall transition
― Special format for sequential elements

Open-Silicon Confidential 3
Transition Time

90%

10%
t
Transition time

Open-Silicon Confidential 3
Cell Delay
vin

50%

vout

Delay

50%

Open-Silicon Confidential 3
.Lib Format
Cell (NAND2X1) Pin(Y)
Cell_footprint : nand2 ; direction : input ;
Area : 9.9792 ; capacitance : 0.0 ;
Pin(A) { function : “(!(A B))” ;
direction : input ; timing() {
capacitance : .00396 ; related pin : “A”;
} cell_rise (template_name)
{
Pin(B) { Index1(.. , .. , ..)
direction : input ; Index2(.. , .. , ..)
capacitance : .00375 ; values (table)
} cell_fall
rise_transition
fall_transition
}

Open-Silicon Confidential 3
Standard Cell library ...
Cap .00035 0.021 0.0385 0.084 0.147 0.231 0.3115
Trans
0.05 .0445 0.1841 0.3005 0.6020 1.0190 1.5750 2.1070

0.15 0.0665 0.2103 0.3270 0.6289 1.0460 1.6020 2.1350

0.60 0.1269 0.3366 0.4540 0.7543 1.1710 1.7270 2.2590

1.40 0.2050 0.4980 0.6630 0.9850 1.3990 1.9520 2.4840

2.30 0.2797 0.6344 0.8364 1.2350 1.6600 2.2110 2.7400

3.30 0.3553 0.7647 0.9960 1.4610 1.9500 2.5010 3.0290

4.50 0.4405 0.9051 1.1650 1.6910 2.2530 2.8530 3.3780

Open-Silicon Confidential 3
Wire load models
► Why?
― Synthesis need to model interconnect parasitic information

► What?
― WLM is based upon the characteristics of a statistically average net
for a given fanout contained within a given area of the die.
― The synthesis tool used WLM to estimate capacitance, resistance
and area of the nets connecting two cells/ports.
― Standard and custom WLMs.

► Issues
― Fanout based interconnect modeling is very inaccurate for today’s
technology (0.25, 0.18, 0.13)

Open-Silicon Confidential 3
Sample wire load model
wire_load(“10x10") {
capacitance : 0.000060
resistance : 0.000034
area : 0.28
slope : 0.5
fanout_length(1, 2.493685)
fanout_length(2, 2.987365)
fanout_length(3, 3.481050)
fanout_length(4, 3.974750)
fanout_length(5, 4.962100)
fanout_length(6, 5.949450)
fanout_length(7, 7.936850)
}

Open-Silicon Confidential 3
Wire load modes
20x20
► Top 10x10
5x5 7x7

► Enclosed 20x20 20x20

10x10
5x5 7x7

► Segmented 10x10
20x20
10x10
5x5 7x7

7x7
5x5
10x10
Open-Silicon Confidential 3
Report Generation

- Timing path report


- qor reports
- area reports

Open-Silicon Confidential 4
Coding for Successful Synthesis

► Think in hardware
► Think HW reuse
► Follow proven coding guidelines
► Complete sensitivity list
► Blocking and non-blocking statements with care
► Priority encoder Vs parallel logic
► parallel_case and full_case
► State machine designs
► Avoid unintentional latches
► Multiple drivers to a flop
► Reset scheme for flops

Open-Silicon Confidential 4
Recipe for Successful Synthesis

► Good coding practice


► Hierarchical design
► Reasonable and good constraints
► If WLM, use custom WLM
► Bottom up block synthesis with time budget
► Top down compile
► characterize, write_script, bottom up compile (debatable)
► Report timing
► Revisit code, script
► Synthesize or incremental synthesis
► Hold fix ( to be done along with placement+routing state)

Open-Silicon Confidential 4
Physical synthesis

► Wire loads are imperfect


― Too pessimistic, too optimistic
► Ideal way is to get exact wiring parasitic
► Input: Netlist, SDC and floorplan
► Flow
― Place the standard cells
― Global routing
― Extract parasitics

Open-Silicon Confidential 4
Topographical synthesis

► Another form of physical synthesis


► Input is RTL not netlist
► Does two passes
― RTL to netlist maping
― Physical syntheis

Open-Silicon Confidential 4
The End

Open-Silicon Confidential 4

You might also like