4-bit Carry Look Ahead Adder

li Md. Shahriar Mahmud line Md. Shahriar Mahmud

line 1: Md. Shahriar Mahmud
Id. 18-38023-2 Id. 18-38023-2
Id. 18-38023-2
Computer Engineering Computer Engineering
Computer Engineering
American International University American International University
American International University
Bangladesh Bangladesh
Bangladesh
Dhaka, Bangladesh Dhaka, Bangladesh
Dhaka, Bangladesh
[email protected] [email protected]
[email protected]
ine 5: email address or ORCID 5: email address or ORCID
Md. Shahriar Mahmud
Md. Shahriar Mahmud
Id. 18-38023-2 line 1: Md. Shahriar Mahmud
Id. 18-38023-2
Computer Engineering
Computer Engineering Id. 18-38023-2
American International University
American International University Computer Engineering
Bangladesh
Bangladesh American International University
Dhaka, Bangladesh
Dhaka, Bangladesh Bangladesh
[email protected]
[email protected] Dhaka, Bangladesh
[email protected]
line Md. Shahriar Mahmud
li Md. Shahriar Mahmud
line 5: email address or ORCID
Id. 18-38023-2
Id. 18-38023-2
Computer Engineering ORCID
Computer Engineering
American International University
American International University
Bangladesh
Bangladesh
Dhaka, Bangladesh
Dhaka, Bangladesh
[email protected]
[email protected]
5: email address or ORCID
ne 5: email address or ORCID

Abstract— An adder is an essential part of the central adder. Traditional CLA is constructed by XOR, AND, and OR
processing unit (CPU) of any microprocessor and all other gates. The proposed circuit uses NAND gates to replace the
computing devices. Generally, carry propagate adders are AND and NOT gates in CLA, it can decrease the cost of CLA
employed in realizing such an arithmetic circuit. While there and increase the speed of CLA. Carry Look Ahead (CLA)
exist several designs of carry propagate adders, the carry Addder (also known as Carry Look Ahead Generator) is one
lookahead adder (CLA) is popular for its characteristic speed of the digital circuits used to implement addition of binary
relative to other designs like the carry ripple adder. This report numbers. It is an improvement over ’Ripple carry adder’
captures the principle behind CLAs and a schematic level design
circuit. In Ripple Carry adders, carry propagation time is the
along with delay analysis by hand calculation and Dsch
major speed limiting factor as it works on the basic
simulation methods.in this project Dsch3.5 simulation software
is use.
mechanism to generate carries as we generally do while
adding two numbers using pen and paper. A ripple carry adder
Keywords— CPU, carry lookahead adder (CLA), Dsch3.5. may be supposed to be built of a series of 1-bit adders
(generally known as a full adder in digital electronics). Thus,
the speed of ripple carry adder is a direct function of number
I. INTRODUCTION of bits. On the other hand, Carry Look Ahead adder solves this
Adder as we know is used widely in a computer as adding problem by calculating carry signals in advance based upon
data is an important task in a processor. Arithmetic operations input bits and does not wait for the input signal to propagate
such as addition, subtraction, multiplication and division are through different adder stages. Hence, it implements the adder
widely used and play an important role in various digital with reduced delay at the cost of more area.
systems such as Very Large Scale Integration(VLSI)
architecture, microprocessor and microcontroller and data II. THEORY AND METHODOLOGY
process unit. The speed of execution is the most important
factor in fast computing devices to meet our performance A carry look-ahead adder (CLA) is an electronic adder
expectations. The simplest binary adder is ripple carry adder. used for binary addition. Due to the quick additions
It is easy to be understood and implemented. To reduce the performed, it is also known as a fast adder. The CLA logic
delay caused by the eect of carry propagation through the uses the concepts of generating and propagating carries. We
ripple-carry adder, we can attempt to evaluate quickly for each can say that the CLA adder is the successor of the Ripple
stage whether the carry-in from the previous stage will have a Carry Adder.
value 0 or 1. If a correct evaluation can be made in a relatively In parallel adders, we can perform the addition operation when
short time, then the performance of the complete adder will be both values required to perform addition, i.e., the augend and
improved. Such concept is commonly called carry-lookahead. the addend are present at the same time. In parallel adder
A more complex binary adder is carry lookahead adder circuits, the carry output of one stage serves as the carry input
(abbreviated as CLA) [3, 4]. It uses the same carry lookahead of the succeeding stage, thus being called the ‘ripple’ carry
circuits to construct the higher-bit CLA recursively. It is adder.
widely used due to its superior performance over ripple carry
To begin with, when we consider a 4-bit ripple carry adder,
we see that the augend and the addend are readily available.
All that is left for the full adder to begin working is the input
carry. This carry is given as an input to the first full adder. But
the remaining full adders require the carry-output of the
previous adder to be input in their systems. In other words, a
full adder can’t generate the sum and carry of the respective
block unless the input carry is known.

Fig-2: Truth Table of Full Adder

On analyzing the truth table, we see that the Carry is 1 when
• Either the value of A or B is one, as well as Cin, is 1,
or
Fig-1: 4-bit Ripple Carry Adder
• Both A and B have the value 1.
Consider block 1, block 2, and so on. In general, let us
represent these blocks with variables i, i+1, ….. Let us now consider two new variables, Carry Generate (Gi)
and Carry Propagate (Pi).
If we analyze the system carefully, the (i+1)th block waits for
the ith block to generate a carry. The sum S3 generated on the For case 1, we see that an output carry is propagated, when
availability of input signals A3 and B3, but the Carry C4 does we give an input carry. We will refer to this with Pi. So, the
not get generated until the previous carry C3 is available, mathematical expression of Pi can we represented as :
which in turn cannot be present without the presence of C2, Pi = Ai ⊕ Bi
which is again dependent on the previous carries C1 and Cin.
As a result, the entire operation has a lot of delay within the While considering case 2, we see that an output carry is
system, which can be called as the carry propagation delay. generated when both inputs, A and B, are high, regardless of
The total propagation time is equal to the sum of all the the value of the input carry. We will refer to this output carry
individual propagation delays of each Full Adder block as Gi. Thus, we can mathematically express Gi as :
present in the system. Undeniably, the propagation time of the Gi = Ai . Bi
system increases if the number of Full Adder blocks (i, in this
case) increases, i.e., if we perform the addition of larger Originally, for a full adder we have the following equations:
numbers (4-bit to 16-bit). Sum = A⊕B⊕Ci
How can we overcome this issue? We have two solutions to Carry = Ci(A+B) + AB
this.
Thus, we can rewrite the equations of the full adder in terms
1. Introduce faster gates in the system with smaller of Carry Propagate (Pi) and Carry Generate (Gi) as :
delays. But we cannot keep adding more and more
gates in the circuit; this would increase the size of the Sum = Pi ⊕ Ci
overall prototype and, in turn, cause more power Carry = Gi + Pi . Ci
dissipation and lead to faster damage of the system.
The equations of Sum and Carry can be represented by a logic
2. Modify the circuit in such a way that, even though circuit given below.
the complexity increases by a small degree, it
performs the same function more efficiently and does
not depend on the carry of the previous system. Thus
came the Carry Look Ahead Adder, which solved the
problem faced by the Ripple Carry Adder’s
dependency on the prior carry inputs.
Thus came the Carry Look Ahead Adder, which solved the
problem faced by the Ripple Carry Adder’s dependency on the
prior carry inputs.
Working of a Carry Look Ahead Adder:
Fig-3: Logic Circuit
Let us consider a full adder. We have the inputs signals A, B,
and Cin. If we consider the addition of these three variables in
every possible case, we get a truth table like the one below.
III. CIRCUIT DIAGRAM
The circuit for the above equations can be constructed as
shown below.
 We can calculate the output carry C1, C2, C3, and C4 IV. APPARATUS
using the above derived equations as: Computer and DSCH3.5 software installed in the
C1 = (Cin . P0) + G0 Computer
C2 = ( C1 . P1 ) + G1 = ((( Cin . P0 ) + G0 ) . P1) + G1
V. SIMULATION
= (Cin . P0 . P1) + ( G0 . P1 ) + G1
Component heads identify the different components of
C3 = ( C2 . P2 ) + G2 = ((( C1 . P1 ) + G1 ) . P2 ) + G2 your paper and are not topically subordinate to each other.
Examples include Acknowledgments and References and, for
= G2 + ( P2 . G1 ) + ( P2 . P1 . G0 ) + (P2 . P1 . P0 . Cin ) these,
C4 = ( C3 . P3 ) + G3
= (Cin . P0 . P1 . P2 . P3) + ( P3 . P2 . P1 . G0 ) + ( P3 .
P2 . G1 ) + ( G2 . P3 ) + G3

Fig-4: Circuit Diagram of 4-bit Carry-Lookahead Adder Fig-6: Simulation Circuit Diagram of the entire 4-bit CLA
Adder
Entire 4-bit CLA Adder:

Fig-5: Circuit Diagram of the entire 4-bit CLA Adder

We can see that there is no dependency on any intermediate
Carry values in any of the equations. On solving the equations,
we see that only the input Carry Cin is required to calculate all
the Sum and Output Carry values. This resolves the issue
faced by the Ripple Carry Adder’s dependency on the Fig-7: Timing Diagram 4-bit CLA Adder
intermediate carry values. Thus, the entire operation works
faster for higher-order bits, when compared to the Ripple
Carry Adder. This is the reason why the CLA Adder is also
called as a Fast Adder.
 VII. ADVANTAGES OF CARRY LOOK AHEAD ADDERS

• CLA Adders generate the carry-in for each full adder

simultaneously, by using simplified equations
involving Pi, Gi, and Cin.
• This system reduces the propagation delay. This is
because the output carry at any stage is dependent
only on the first Carry signal given at the input.
• It is the fastest adder when compared to other
addition mechanisms.

VIII. DISSADVANTAGES OF CARRY LOOK AHEAD ADDERS

• The carry-lookahead adder circuit gets more
complicated as the number of variables increase.
• The circuit for a carry-lookahead adder is expensive
as it involves more hardware.
• As the number of variables increases, the circuit
implements more hardware. Thus, when the carry-
lookahead adder is implemented as an IC, the area is
bound to increase.

REFERENCES

[1] G. Eason, B. Noble, and I. N. Sneddon, “On certain integrals of

Lipschitz-Hankel type involving products of Bessel functions,” Phil.
Fig-8: Schema Symbol of 4-bit CLA Adder Trans. Roy. Soc. London, vol. A247, pp. 529–551, April 1955.
(references)
VI. RESULTS & DISCUSSION [2] J. Clerk Maxwell, A Treatise on Electricity and Magnetism, 3rd ed.,
vol. 2. Oxford: Clarendon, 1892, pp.68–73.
In this project, we learn about CLA adder what is it ?, how
[3] I. S. Jacobs and C. P. Bean, “Fine particles, thin films and exchange
does it work? We use Dsch3.5 software to simulate the circuit anisotropy,” in Magnetism, vol. III, G. T. Rado and H. Suhl, Eds. New
of 4-bit CLA-adder. In this circuit we use basically NOT, York: Academic, 1963, pp. 271–350.
NOR & AND mostly basic gate. We face some difficultly to [4] K. Elissa, “Title of paper if known,” unpublished.
add VDD. We use 5V for VDD. After build the circuit we run [5] R. Nicole, “Title of paper with only first word capitalized,” J. Name
this and after that we get value according the truth. Here we Stand. Abbrev., in press.
don’t get the output properly as shown as in timing diagram. [6] Y. Yorozu, M. Hirano, K. Oka, and Y. Tagawa, “Electron spectroscopy
Q5 doesn’t work. Other wise the circuit is perfectly work. studies on magneto-optical media and plastic substrate interface,” IEEE
Different bit-adder configurations of the fast-response carry- Transl. J. Magn. Japan, vol. 2, pp. 740–741, August 1987 [Digests 9th
Annual Conf. Magnetics Japan, p. 301, 1982].
lookahead adders are manufactured on integrated circuitry
nowadays. Apart from the circuits, there are also individual [7] M. Young, The Technical Writer’s Handbook. Mill Valley, CA:
University Science, 1989.
carry generator ICs that are manufactured, and we need to
make the required connections to perform the quick addition
function