APPLICATION NOTE

Application information for

change-over
TDA935X/6X/8X N1 -> N2

AN200XX

Version 1.6
March 2001

DRAFT

Philips
Semiconductors
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

INTRODUCTION

This report describes the differences between the TDA935X/6X/8X N1 and N2 version.
First the functionality differences are briefly given (chapter 1)
Next, the hardware differences, software differences and development tool differences are given
(chapter 2, 3, 4)
The following chapter shortly describes the software changes (chapter 5).

For reference, the last two chapters give more detailed information about the new features, changed
items and the new peak white limiter function. (chapter 6 and 7).

Finally in chapter 8 errata are given from the User Manual of the N1 version (AN98093).

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

CONTENT

1 Brief overview of new features........................................................................................................ 5

1.1 Microprocessor part ..................................................................................................................... 5
1.2 Video processor part .................................................................................................................... 5
2 Compatibility hardware ................................................................................................................... 6
2.1 Compatibility TDA935X/6X/8X N1 and N2............................................................................... 6
2.2 Compatibility TDA935X/6X/8X N2 and the new TDA955X/6X/8X family ............................. 8
3 Compatibility software .................................................................................................................... 9
3.1 Compatibility TDA935X/6X/8X N1 and N2............................................................................... 9
3.2 Compatibility TDA935X/6X/8X N2 and the new TDA955X/6X/8X family ............................. 9
4 Compatibility development tools................................................................................................... 10
4.1 Emulator..................................................................................................................................... 10
4.2 Display Development Studio (DDS) ......................................................................................... 11
4.3 GTV development tool .............................................................................................................. 11
4.4 Bench programmer..................................................................................................................... 11
4.5 TV Demo boards........................................................................................................................ 11
4.6 WIC software ............................................................................................................................. 11
5 Software Changes .......................................................................................................................... 12
5.1 Added / Changed SFR registers in the microcontroller part of the TDA935X/6X/8X N2 ....... 12
5.2 I2C Control table video processor part of the TDA953X/6X/8X N2. ....................................... 13
5.2.1 Survey of added bits / bits with changed functionality:..................................................... 14
5.2.2 Bits, moved from position.................................................................................................. 15
5.3 Software adaptation, a short overview....................................................................................... 15
6 Extended description of the new / adapted functionality .............................................................. 17
6.1 Microprocessor .......................................................................................................................... 17
6.1.1 I2C communication speed .................................................................................................. 17
6.1.2 Standby mode..................................................................................................................... 17
6.1.3 Watch Dog Timer .............................................................................................................. 17
6.1.4 Extra 16 bit timer with 8 bit prescaler ............................................................................... 18
6.2 Video processor general............................................................................................................. 19
6.2.1 Hardware compatibility bit N1 / N2 .................................................................................. 19
6.3 IF ................................................................................................................................................ 19
6.3.1 IF PLL Offset adjustment .................................................................................................. 19
6.3.2 Changed AGC speed settings............................................................................................. 20
6.4 Sound ......................................................................................................................................... 21
6.4.1 Sound bandpass.................................................................................................................. 21
6.4.2 + 6 dB amplifier ................................................................................................................. 22
6.5 Synchronisation, Geometry and Deflection............................................................................... 22
6.5.1 Adapted range of upper/lower corner correction / S-correction........................................ 22
6.6 Filters and switches.................................................................................................................... 23
6.6.1 Independent video and audio source selection .................................................................. 23
6.6.2 Depeaking included in peaking range................................................................................ 24
6.6.3 Selection Peaking frequency.............................................................................................. 24
6.6.4 Adjustable ratio of pre- and overshoot for peaking ........................................................... 25
6.7 RGB processing ......................................................................................................................... 25
6.7.1 Blanking of RGB outputs under all supply conditions ...................................................... 25
6.7.2 Extended range of Black Level offset adjustment ............................................................. 26
6.7.3 Soft Clipper function ......................................................................................................... 26
6.7.4 Vg2 alignment bits can be read out via OSD..................................................................... 26

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx
7 Info when adapting for the new peak white limiter function......................................................... 28
7.1 Hardware changes for the new peak white limiter function ...................................................... 28
7.2 Beam current limiting and Peak white Limiter function ........................................................... 30
8 Errata Application Note TDA935X/6X/8X N1 (AN98093) ......................................................... 31
8.1 RGB / YUV inputs..................................................................................................................... 32

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

1 BRIEF OVERVIEW OF NEW FEATURES

1.1 Microprocessor part

− Internal reset for microprocessor and video processor part. No external reset circuit needed any
more (but is still allowed for compatibility reasons)
− The I2C communication speed is increased to 400 kHz (previous maximum 200 kHz)
− The Stand-by mode (display and acquisition disabled, 30% supply current saving) is now also
available in the 10 page TXT versions
− The 8 bit watch-dog timer has now a 16 bit prescaler (previous 11 bits) to allow longer times
between interrupts
− An extra 16 bit timer with 8 bit prescaler is added

1.2 Video processor part

− The DC offset of the IF PLL can be adjusted via I2C to fine-tune the performance
− The AGC speed can now be set faster (3x and 6x i.s.o. 2x and 4x) for better airplane flutter
performance
− FM sound selectivity improved by implementation of an internal sound bandpass filter.
No external sound bandpass needed for more critical conditions. In combination with other circuit
optimisation the performance of PAL-I sound (6.0 MHz) now close to BG (5.5 MHz) and DK (6.5
MHz) sound
− The peaking range is adapted to include depeaking for noisy signal conditions
− The peaking centre frequency can be selected from three different values
− The ratio of pre- and overshoot of peaking can be selected from 1:1.8 to 1:1.
− The high output level of pin 32 has been lowered from 8 Volt to 4.5 Volt for better compatibility
with 5 Volt logic
− Range of upper / lower corner correction and vertical S correction are adapted for use with real
flat picture tubes
− Extended range and increased resolution for the Black level offset, now 6 bits in stead of 4 bits
adjustment register
− Improved Switch-on / Switch-off behaviour by blanking the RGB outputs with new I2C bit
RGBL.
− Soft clipper function to limit short peaks in the RGB output signal
− The Vg2 alignment method is improved, now the measured current can be displayed via OSD
− Hardware compatibility modes with TDA935X/6X/8X N1 and the new TDA955X/6X/8X family,
selectable by I2C bus bit

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

2 COMPATIBILITY HARDWARE

2.1 Compatibility TDA935X/6X/8X N1 and N2

For easy change-over, the N2 family is pin to pin compatible with the N1 version when the
compatibility bit IVG (reg. 2B bit D6) is set to 1.
Selecting for hardware compatibility disables the new Peak White Limiter function of the N2. The
absence of the peak white limiter function is compensated with the new Soft Clipper function.
No layout changes are needed in the board for applying the N2 and most likely no component changes
with only few exceptions, which will only be relevant for some of the applications.

1. Change of the DC voltage levels of pin 32 in two modes:

1. High voltage level when pin 32 is used as I2C controlled control output (CMB1..0 = 1 1)
The "high" level of this output is for the N1 8 Volts
The "high" level of this output is for the N2 lowered to 4.5 Volts (better 5V logic interface)
This might effect the interface circuit component values when this pin is used for switching
purposes.
2. When pin 32 is used as subcarrier reference (CMB1..0 = 0 1), the DC voltage has changed
from 4 V in the N1 to 2.3 V in the N2.
When this pin also was used to switch a transistor for switching the combfilter TDA9181 on
and off, it might be needed to change the interface component values.

2. Internal reset function

The N2 has an internal reset for the device, but the reset is compatible with the N1 version and it
remains possible to use an external reset circuit.
To save components, it is possible to remove the external reset circuit. In that case, we advice to
connect the external reset pin 61 direct to ground to increase robustness for unwanted reset due to
flash or ESD.

3. Lower capacitor value needed on sound decoupling pin (DECSDEM, pin 29) in FM types
The value of this capacitor determines the low corner frequency of the FM demodulated baseband
audio. Compared to the N1, the now needed value is about 4 times lower.
The low corner frequency is dependent on the use of the +6 dB amplifier in the deemphasis path.
This amplifier is normally enabled for 4.5 MHz sound carriers with 25 kHz deviation (see for
details 6.4.2 + 6 dB amplifier)
The low corner frequency (- 3 dB) can be calculated with the following formula:
+ 6 dB amplifier off: Flow corner = 1/(2*π*500)
+ 6 dB amplifier on : Flow corner = 1/(2*π*250)
A 10 µF capacitor has a Flow corner of 32 Hz (no + 6 dB ampl) and 64 Hz (with + 6 dB ampl)
Note that capacitor values larger than 22 µF lead to long settling times before the FM sound
is available (> 3 –4 seconds after +8 Volt is applied)

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx
4. Improved H-out start-up
The difference in Hout start-up is given in the figures below.

100

Ton
(%)

50

50 100 150 200 250

TIME (MS)

Figure 1: H-out Start-up N1

During start-up of the N1, the off-time of the H-out was fixed to 28.8 µs while the on-time
increased linear in 100 ms from 0 to 35.2 µs. This already resulted in smooth increase of the EHT
build-up and lower stress on the rectifiers on the secondary side of the FBT.

In the N2, this start-up has been refined to further lower the stress and enable application of large
picture tubes with DAF (Dynamic Astigmatism Focus).

100

75
Ton Soft start
(%)

50

57 73 1045
12

50 100 150 TIME (MS)

Figure 2: H-out Start-up N2

The growth of the on-time of the H-out from 0 to 100 % is now divided in three parts:
1. Extra slow increase from 0 to 12 %, lasting 57 msec.
The purpose is to further lower the stress of the rectifiers on the secondary side of the Fly
Back Transformer (FBT). This is important for applications with high secondary power.
2. Normal increase from 12 to 75 % lasting 73 msec., comparable to N1

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx
3. Very slow increase from 75 to 100% lasting 1045 msec.
This last part is related to enable the use of large picture tubes with DAF. These tubes tend to
flash when the EHT rise from around 75% to 100% is too fast. It has been proven in High End
concepts that by slowing down the EHT build-up in this region this flash problem does not
occur.

The total start-up time becomes now 1175 msec. for the N2 compared to 100 msec. for the N1.
For most applications there will be no consequence. It might be needed to change the timing of
checks, which are done after the soft start of H-out is finished, because the soft start takes more
time.

5. Position change of RGB measuring lines

To improve the commonality between 50 and 60 Hz, the position of the RGB measuring lines has
been made identical for both vertical frequencies.

The position of the 4 measuring lines (leakage, R, G, B) was for the N1:
50 Hz line 19 – 22 (Odd field) line 331 – 334 (Even field)
60 Hz: line 15 – 18 (Odd field) line 277 – 280 (Even field)

For the N2 this becomes:

50 Hz line 17 – 20 (Odd field) line 329 – 332 (Even field)
60 Hz: line 17 – 20 (Odd field) line 279 – 282 (Even field)*

* The number of lines from vertical flyback to the measuring lines in the even field is identical
for 50 and 60 Hz, but due to the lower line count per field for 60 Hz the line numbers differ.

We do not expect consequences for the repositioning of these measuring lines unless they are used
for alignment of Vg2 in production.

For new designs we advice to set the compatibility bit IVG (reg. 2B D6) to 0. The hardware is only
slightly different from N1 to accommodate the changed vertical guard application on pins 49 / 50.
For details on the hardware adaptation needed, see chapter 7.1 Hardware changes for the new peak
white limiter function
This adaptation adds to the exceptions as described above.
The advantage is that it is possible to use the improved peak white limiter function of the N2 and that
the device is pin to pin compatible with the TDA95XX family for upgrading.
It is of course possible to adapt also the hardware for this improved peak white limiter function when
changing from N1 to N2.

2.2 Compatibility TDA935X/6X/8X N2 and the new TDA955X/6X/8X family

When the compatibility bit IVG is set to 0, the N2 is pin to pin compatible with the new
TDA955X/6X/8X family.
Note that the new TDA95XX family has no TDA93XX N1 compatibility bit, so for new designs we
advice to adapt the hardware for the changed functionality of 2 pins to allow future upgrading to the
TDA95XX family.

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

3 COMPATIBILITY SOFTWARE

Software written for the N1 family needs to be adapted and re-compiled for the N2 family.
It is of fundamental importance to use the Driver and Platform libraries vers. 3.0.2 or above.

Correct directives needs to be used for re-compiling the software, after adaptation, by taking in
account of the new / improved resources available in the N2 device, e.g. timer 2, watchdog, etc.

For details on using the new libraries, please refer to the LMR Analog TV Microcontrollers Drivers &
Platform ver 1.7. User’s Manual.

For more details on the both manual and libraries, please contact the BL-Video Systems Application
Department in Southampton, [email protected]..

3.1 Compatibility TDA935X/6X/8X N1 and N2

When the watch dog timer is used, the timing period must be adapted because the prescaler of the
watch dog timer is increased from 11 bits to 16 bits. Further all software, related to the
microprocessor part (SFR) is compatible between N1 and N2. The SFR registers are backwards
compatible with the N1. Software code for OSD, TXT, CC, I/O pins remain all working correct when
applied in the N2.
Because the I2C table of the video processor part has changed on a number of points, this part of the
software needs to be adapted.
Some bits are added for the new functionality, some bits are moved to group the bits more logical
together. For new feature bits, extra registers (05 and 2E) had to be added which implies writing two
more I2C register to release the H-out
See chapter 5 Software Changes for more info.

3.2 Compatibility TDA935X/6X/8X N2 and the new TDA955X/6X/8X family

Software, written for the N2 will run also on the TDA95XX family. In that case, the features and
behaviour will also be identical to the N2.
To use the extra functionality and features, the software must be adapted.

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

4 COMPATIBILITY DEVELOPMENT TOOLS

To design with the TDA935X/6X/8XPS/N2 family, the tools, listed below, need to be
adapted/upgraded. To order the necessary upgrades, please contact your local marketing
representative.

4.1 Emulator
Depending on the emulator brand used, the following adaptations are necessary:

HITEX
The HITEX with the existing PXSAA55xx probe for emulation of the TDA935X/6X/8X N1 consists
of the following PCBs:

1. Main probe PCB, ref. 7313-903-0027-2 or ref. 7313-903-0027-3

2. QFP120 Daughter board PCB, ref. 7313-903-0033-2
3. UOC Interface board, ref. 7313-903-0007-2.

In order to emulate the new UOC–N2 family devices, the following boards have to be upgraded:

1. new Main probe PCB, ref. 7313-903-0027-3 (Only in case version is ref. 7313-903-0027-2)
2. new QFP120 Daughter board (ref. 7313-903-2641)
3. new UOC interface board (ref. 7313-903-03171)

The new Daughter board (ref. 7313-903-2641) plugs into the main probe PCB (ref. 7313-903-0027-3)
via an array of connectors, SK1..SK8. It replaces the existing Daughter board (ref. 7313-903-0033-2).

The new Daughter board can accommodate the new µprocessor bondout. The new UOC interface
board can accommodate the new video processor bondout.

This new set of boards supports the internal reset feature.

Before using the probe, a set of jumpers on the Daughter board needs to be set as described below:

J1: HI
J2: HI
J3: OPEN (not used)
J4: OPEN (not used)

A brochure with information about the new probe heads and bondouts is attached to this document.

BL-Video Systems Application Southampton supplies the necessary µprocessor and video processor
bondouts for emulation.

ASHLING ULTRA 51
Ashling announced to quit support for the existing CTS51 system. They offer full support for the
TDA935X/6X/8X N2 with their new Ultra Ashling system.
These new Ultra Ashling emulators need a new developed probe head and bondouts of the µprocessor
part and video processor part for emulation.
Information about the new probe head can be found in the attached brochure.

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

4.2 Display Development Studio (DDS)

The DDS is needed to generate the proper character sets and the matching with the type number of the
device.

The new version DDS 2.2 supports the new UOC–N2. The original PAT/PROMT tool is out of date.

It is recommended to use the latest version of DDS and Service packs, which can be downloaded from
our Support area on the Semiconductor Internet Site located at :

http://download.semiconductors.com/protected/video/.

4.3 GTV development tool

GTV release 2.0 supports the TDA93xx-N2 family. Older releases are not suitable for the N2 devices.

4.4 Bench programmer

For programming the TDA935X/6X/8XPS/N2 the bench programmer must be a recent version. These
versions can be easily recognised because they have a blue PCB (serial number 3-xxx and onwards).
Some of older bench programmer versions, with green PCB (serial number 2-xxx), cannot be used
with the N2, unless they are upgraded.

Please contact the BL-Video Systems Application Southampton for more details.

4.5 TV Demo boards

The TV demo boards are compatible provided the compatibility bit IVG (reg. 2B D6) is set to 1.
When evaluation of the new peak white limiter function is wanted, the board needs a small
modification as described in chapter 7 Info when adapting for the new peak white limiter function

4.6 WIC software

For evaluation on the TV demo board, a new WIC software version is available for the N2 version.

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

5 SOFTWARE CHANGES

In the software, some bits are added or moved to have all related bits logically grouped together and
for new functinality an extra registers are added (05 and 2E).

5.1 Added / Changed SFR registers in the microcontroller part of the TDA935X/6X/8X N2

Add R/W Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
r
84 R/W IEN1 ET2

85 R/W IP1 PT2

91 R/W TP2L TP2L7 TP2L6 TP2L5 TP2L4 TP2L3 TP2L2 TP2L1 TP2L0

92 R/W TP2H TP2H7 TP2H6 TP2H5 TP2H4 TP2H3 TP2H2 TP2H1 TP2H0

93 R/W TP2PR TP2PR7 TP2PR6 TP2PR5 TP2PR4 TP2PR3 TP2PR2 TP2PR1 TP2PR0

94 R/W TP2CRL TP2CRL1 TP2CRL

9C R/W TP2CL TP2CL7 TP2CL6 TP2CL5 TP2CL4 TP2CL3 TP2CL2 TP2CL1 TP2CL0

9D R/W TP2CH TP2CH7 TP2CH6 TP2CH5 TP2CH4 TP2CH3 TP2CH2 TP2CH1 TP2CH0

FB R/W ROMBK STANDBY IIC_LUT1 IIC_LUT2 0 0 0 ROMBK1 ROMBK

0

The new bits or bits with changed functionality are indicated in BOLD and blue.

For details, see chapter 6.1.1 I2C communication speed, chapter 6.1.4 Extra 16 bit timer with 8
bit prescaler and the specification.

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 Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

5.2 I2C Control table video processor part of the TDA953X/6X/8X N2.

FUNCTION SUBADDR DATA BYTE POR

(HEX) D7 D6 D5 D4 D3 D2 D1 D0 Value
Offset IF demodulator IFO 05 0 0 A5 A4 A3 A2 A1 A0 20
Horizontal parallelogram HP 06 0 0 A5 A4 A3 A2 A1 A0 20
Horizontal Bow HB 07 0 0 A5 A4 A3 A2 A1 A0 20
Hue HUE 08 0 0 A5 A4 A3 A2 A1 A0 20
Horizontal shift HS 09 0 0 A5 A4 A3 A2 A1 A0 20
EW width1 EW 0A 0 0 A5 A4 A3 A2 A1 A0 20
EW parabola/width1 PW 0B 0 0 A5 A4 A3 A2 A1 A0 20
EW uppercorner parabola1 UCP 0C 0 0 A5 A4 A3 A2 A1 A0 20
EW lowercorner parabola1 BCP 0D 0 0 A5 A4 A3 A2 A1 A0 20
EW trapezium1 TC 0E 0 0 A5 A4 A3 A2 A1 A0 20
Vertical slope VS 0F 0 0 A5 A4 A3 A2 A1 A0 20
Vertical amplitude VA 10 0 0 A5 A4 A3 A2 A1 A0 20
S-correction SC 11 0 0 A5 A4 A3 A2 A1 A0 20
Vertical shift VSH 12 0 0 A5 A4 A3 A2 A1 A0 20
Vertical zoom VX 13 0 0 A5 A4 A3 A2 A1 A0 20
Black level offset R BLOR 14 0 0 A5 A4 A3 A2 A1 A0 20
Black level offset G BLOG 15 0 0 A5 A4 A3 A2 A1 A0 20
White point R WPR 16 0 0 A5 A4 A3 A2 A1 A0 20
White point G WPG 17 0 0 A5 A4 A3 A2 A1 A0 20
White point B WPB 18 0 0 A5 A4 A3 A2 A1 A0 20
Peaking PEAK 19 PF1 PF0 A5 A4 A3 A2 A1 A0 20
Luminance delay time YD3..0 1A 0 0 0 0 YD3 YD2 YD1 YD0 00
Brightness BRIGHT 1B 0 0 A5 A4 A3 A2 A1 A0 20
Saturation SAT 1C 0 0 A5 A4 A3 A2 A1 A0 20
Contrast CON 1D 0 0 A5 A4 A3 A2 A1 A0 20
AGC take-over TOP 1E 0 0 A5 A4 A3 A2 A1 A0 20
Volume control VOL 1F 0 0 A5 A4 A3 A2 A1 A0 20
Colour decoder 0 20 CM3 CM2 CM1 CM0 MAT MUS ACL CB 00
Colour decoder 1 21 0 0 0 0 0 0 BPS FCO 00
AV-switch 0 22 0 0 SVO CMB1 CMB0 INA INB 0 00
AV-switch 1 23 0 0 0 0 0 0 0 RGBL 00
Synchronization 0 24 0 HP2 FOA FOB POC STB VIM VID 00
Synchronization 1 25 0 0 FSL OSO FORF FORS DL NCIN 00
Deflection 26 0 AFN DFL XDT SBL AVG EVG HCO 00
Vision IF 0 27 IFA IFB IFC VSW MOD AFW IFS STM 00
Vision IF 1 28 SIF 0 0 IFLH 0 AGC1 AGC0 FFI 00
Sound 29 AGN SM1 FMWS AM SM0 0 FMB FMA 00
Control 0 2A 0 IE2 RBL AKB CL3 CL2 CL1 CL0 00
Control 1 2B 0 IVG 0 0 0 YUV 0 HBL 00
Sound 1 2C 0 0 ADX 0 0 AVL 0 0 00
Features 0 2D 0 0 0 0 0 0 0 BKS 00
Features 1 2E 0 BPB RPO1 RPO0 0 0 0 0 00

FUNCTION SUBADDR DATA BYTE

(HEX) D7 D6 D5 D4 D3 D2 D1 D0
Output status bytes 00 POR IFI LOCK SL CD3 CD2 CD1 CD0
01 XPR NDF FSI IVW WBC HBC BCF IN2
02 SUP X X QSS AFA AFB FMW FML

Note: Differences between TDA935X/6X/8X N1 and TDA935X/6X/8X N2 are indicated as follows:

- New bits or bits with changed functionality are indicated in BOLD and blue
- Bits which changed from position are indicated in BOLD, Italic and violet

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Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

5.2.1 Survey of added bits / bits with changed functionality:

CONTROL FUNCTION REG BIT I/O MACRO FU

BITS
ADX AuDio internal / eXternal switch 2C 5 I Filt/Sw SC
0 = internal audio input selected
1 = external audio input selected
AGN Audio GaiN, 0 = 0 dB, 1 = +6 dB 29 7 I Sound SC
AVG Alignment VG2, 1 = enabled 26 2 I RGB SC
AGC1..0 AGC time constant (changed spec) 28 2..1 I IF SC
0 0 0.7 x norm
0 1 norm
1 0 3 x norm (was 2 x)
1 1 6 x norm (was 4 x)
BPB ByPass sound Bandpass 2E 6 I Sound SC
0 = Sound bandpass active
1 = Sound bandpass bypassed
INA..B Video Input source selection 22 2..1 I Filt/Sw UC
Selects only video source, audio source
to be selected using ADX
AB
0 0 CVBS1 (pin 40)
0 1 CVBS2 (pin 42)
1 0 Y/C (pin 42/43)
IVG Interchange Vertical Guard, 2B 6 I RGB SU
N1 compatibility bit
0 Vertical guard at pin 50 (IBL)
Compatibility with new TDA95XX
1 Vertical guard on pin 49 (BCL) and
Peak White Limiter swiched off
Compatibility with N1 version
RGBL RGB outputs Low 23 0 I RGB SC
Pulls the RGB outputs below 1.5 Volts
Meant to prevent RGB drive at start-up
and black switch-off.
When active, the black current loop does
not function!! (use RBL for video
blanking during normal operation)
1 = enable
PF1..0 Peaking Frequency 19 7..6 I Filt/Sw SC
0 0 2.7 MHz
0 1 3.1 MHz (same as N1)
1 0 3.5 MHz
RPO1..0 Ratio Pre / Overshoot peaking 2E 5..4 I Filt/Sw SC
Overshoot white : overshoot black
00 1:1
0 1 1 : 1.25
1 0 1 : 1.5
1 1 1 : 1.8 (same as N1)

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TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

Analogue control bits:

CONTROL FUNCTION REG BIT STEPS RANGE MACRO FU

BITS
IFO IF PLL DC Offset 05 5..0 63 tbf. IF AL
BLOG Black Level Off-set Green 15 5..0 63 -160..+160 mV RGB AL
BLOR Black Level Off-set Red 14 5..0 63 -160..+160 mV RGB AL

5.2.2 Bits, moved from position

CONTROL FUNCTION I/O REG BIT REG BIT

BITS New new Old Old
AFN AFC Not active, 0 = normal, 1 = off O 26 6 28 4
AVL Automatic Volume Leveling, 1=on O 2C 2 29 2
DFL Disable Flash protection, 1=disabled O 26 5 21 5
FMA FM sound carrrier selection O 29 0 29 1
FMB FM sound carrrier selection O 29 1 29 0
FMA and FMB changed position in the
table, but the table remains unchanged:
FMB FMA
0 0 5.5 MHz
0 1 6.0 MHz
1 0 4.5 MHz
1 1 6.5 MHz
IFLH IFLockHold, 0 = auto calibration O 28 4 21 2
1 = no auto PLL-calibration
IN2 Reflects the level of the fast blanking I 01 0 02 5
INput of RGB 2 input, 1 = active
SIF Sound IF Input, selects pin 32 as sound O 28 7 21 7
IF input, 1 = selected
XDT X-ray DeTection O 26 4 21 4
0 = XPR + slow stop
1 = XPR only
YUV YUV / RGB input selection O 2B 2 2B 1

5.3 Software adaptation, a short overview

For software adaptation, of course the new bits and the moved bits must be implemented.
Please take care that all places filled with 0’s indicated in blue and bold (normal and italic) have to be
set to 0 for proper functioning!
Do not forget to write up till including register 2E because else the H-out will not start when
activated.

Below, a short summary of the changes is given to adapt the software for N2 with identical behaviour
as N1. All registers and bit positions refer to the N2 I2C table, unless clearly N1 is stated.

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− When using the Watch Dog Timer, adapt the Watch Dog Timer interval, see paragraph 6.1.3
Watch Dog Timer
− Adapt the position of the bits that moved in the I2C table:
AFN, AVL, DFL, FMA, FMB, IFLH, IN2, SIF, XDT and YUV, see paragraph 5.2.2 Bits,
moved from position for the details.
− Set (if wanted) the compatibility bit IVG (reg 2B D6) to 1 when hardware compatibility is
required for pin 49 (BCL) and 50 (Black Current Input).
See paragraph 6.2.1 Hardware compatibility bit N1 / N2
− Start writing at register 05 (IFO ) in stead of 06 and write to this register 20 hex
This sets IFO, the IF PLL offset, to neutral position.
See further 6.3.1 IF PLL Offset adjustment
− Check that BPB (reg 2E D6) is set to 0 for better FM sound selectivity. Set temporarily BPB to 1
when performing a sound carrier search, using FML and FMW.
See further 6.4.1 Sound bandpass
− Implement that AGN (reg 29 D7) is set to 1 when FMB..A = 1 0 and AGN is set to 0 in all other
conditions.
If for N1 BTSC (N1 reg 29 D7) was used, now set AGN = 0 when for N1 BTSC was set to 1.
See further paragraph 6.4.2 + 6 dB amplifier
− Adapt (if wanted) the neutral position for Peaking in reg. 19 from 00 hex to 10 hex.
See further paragraph 6.6.2 Depeaking included in peaking range
− Set reg. 19 bit D7..6 to 0 1
In this way PF1..0 will select the same peaking frequency of 3.1 MHz as in the N1.
See further paragraph 6.6.3 Selection Peaking frequency
− Adapt (when used) the preset values of UCP, BCP and SC to comply with the adapted range.
See further paragraph 6.5.1 Adapted range of upper/lower corner correction / S-correction
− Implement that ADX (reg 2C D5) is set to 0 when INA..B = 0 0 and ADX = 1 for INA..B = 0 1 or
1 0.
When with N1 the bits ADX (N1 reg 21 D3) and ADS (N1 reg 28 D5) are used for indpendent
selection of the audio source, then applies
N1 ADX, ADS = 0 1 --> N2 ADX = 0
N1 ADX, ADS = 1 0 --> N2 ADX = 1
Note that the adress from the control bit ADX is different for N1 and N2!
See further paragraph 6.6.1 Independent video and audio source selection
− Add register 2E to the I2C register list and write to this register 30 hex.
This sets the bits RPO1..0 to 1 1, which gives identical behaviour to N1.
See further paragraph 6.6.4 Adjustable ratio of pre- and overshoot for peaking
− Write RGBL (reg 23 D0) to 0 for same behaviour as N1.
See further paragraph 6.7.1 Blanking of RGB outputs under all supply conditions
− Change the registers BLOR and BLOG from 4 to 6 bits and from position:
N1 BLOR (N1 reg 15 D7..4) --> N2 BLOR (reg 14 D5..0), neutral position 20 hex
N1 BLOG (N1 reg 15 D3..0) --> N2 BLOG (reg 15 D5..0), neutral position 20 hex
See further paragraph 6.7.2 Extended range of Black Level offset adjustment
− When used, replace in the type definition the Vg2 alignment bit of the N1 VSD (N1 reg 26 D2) by
the N2 Vg2 alignemnt bit AVG (reg 26 D2)
See further paragraph 6.7.4 Vg2 alignment bits can be read out via OSD
− Write 0 to the following bit locations (these were not 0 in the N1):
Reg 21 D7..2
Reg 28 D5
Reg 2B D1

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6 EXTENDED DESCRIPTION OF THE NEW / ADAPTED FUNCTIONALITY

6.1 Microprocessor

6.1.1 I2C communication speed

The maximum allowed I2C communication speed is increased from 200 kHz to 400 kHz. This allows
for faster transfer times of high amounts of data, e.g. with digital sound decoders.
To enable this high speed, setting bits IIC_LUT<1:0> in SFR ROMBNK (FB, D6..5) to 0 1 a high
speed 558 mode can be selected.
Setting the bits CR<2:0> in SFR S1CON (D8, D7,D1..0) to 0 1 1 selects then 400 kHz
communication speed.

Addr R/W Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FB R/W ROMBK STANDBY IIC_LUT1 IIC_LUT2 0 0 0 ROMBK1 ROMBK0

D8 R/W S1CON CR2 ENSI STA STO SI AA CR1 CR0

Refer to the specification for all other possible settings.

Software consequences
None, provided no I2C speed change is required.

6.1.2 Standby mode

The STANDBY mode, which allows for 30% supply current saving, is now also available for the 10
page TXT devices. This mode was already available for the 1 page and OSD versions of the N1.
This allows for a simplified stand-by configuration with less software overhead which can be used for
the whole family.
Previous when lower power was required in TV receiver stand-by, for the 10 page TXT device the
IDLE mode had to be used which is more complex from software point of view while the supply
current is almost identical to the STANDBY mode.

6.1.3 Watch Dog Timer

The prescaler of the Watch Dog Timer is increased from 11 bits to 16 bits.

This changes the adjustable timing intervals

WDV7..0
Version 00 FF
N1, 11 bit prescaler 0.524 sec 0.002048 sec
N2, 16 bit prescaler 16.777 sec 0.065536 sec

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The timing interval can be calculated using:

Watch Dog Interval = (256 - <WDV7..0>) * t

with t = 0.002048 sec. for N1
t = 0.065536 sec. for N2

For details about setting and using the Watch Dog timer, see the specification.

Software consequences
When the Watch Dog Timer is used in the software, the setting for the Watch Dog Timer period has to
be changed to achieve the same period. The setting of WDV7..0 in SFR WDT (FF D7..0) has to be
increased. Because the resolution is different, it is possible that not exact the same timing can be
achieved.
When the original timing interval was smaller than 0.065536 sec, then the software must be adapted to
work with the new timing range

6.1.4 Extra 16 bit timer with 8 bit prescaler

This timer offers extra flexibility. Because the maximum time interval can be very long (16.777 sec),
it can be used for functions like software clocks.
The timer has the following functionality:
− Setting the 16 bit timer period (SFR TP2L for lower byte and TP2H for higher byte)
Reading TP2L and TP2H returns the written timer period.
− Setting the 8 bit prescaler (SFR TP2PR)
− Reading the current counter value (SFR TP2CL for lower byte and TP2CH for higher byte)
− Overflow flag TP2CRL1 when the counter value reaches zero (SFR TP2CRL, D1, 1 = overflow)
− In addition, an interrupt can be generated upon raeching counter value zero (SFR IEN1, D0, when
ET2 is set to 1 the interrupt is enabled). The interrupt priority is set via PT2 (SFR IP1, D0)
The interrupt vector is 003BH.
− Enabling/disabling the timer is set using TP2CRL0 (SFR TP2CRL, D0). 1 is enable.

The relevant SFR's are given in the table below.

Add R/W Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
84 R/W IEN1 ET2

85 R/W IP1 PT2

91 R/W TP2L TP2L7 TP2L6 TP2L5 TP2L4 TP2L3 TP2L2 TP2L1 TP2L0

92 R/W TP2H TP2H7 TP2H6 TP2H5 TP2H4 TP2H3 TP2H2 TP2H1 TP2H0

93 R/W TP2PR TP2PR7 TP2PR6 TP2PR5 TP2PR4 TP2PR3 TP2PR2 TP2PR1 TP2PR0

94 R/W TP2CRL TP2CRL1 TP2CRL

9C R/W TP2CL TP2CL7 TP2CL6 TP2CL5 TP2CL4 TP2CL3 TP2CL2 TP2CL1 TP2CL0

9D R/W TP2CH TP2CH7 TP2CH6 TP2CH5 TP2CH4 TP2CH3 TP2CH2 TP2CH1 TP2CH0

For further details, please refer to the specification.

Software consequences
None. All Timer 2 related SFR register positions were not used in the N1.

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6.2 Video processor general

6.2.1 Hardware compatibility bit N1 / N2

To ease the implementation of the N2, the hardware on pin 49 / 50 can be made compatible with the
N1 version. See for details paragraph 2.1 Compatibility TDA935X/6X/8X N1 and N2,
Note that selecting for hardware compatibility disables the peak white limiter of the N2. The absence
of this function is compensated by the new soft clipper function.

IVG
Reg. 2B D6 Hardware functionality pin 49 / 50
0 N2 compatible with new TDA95XX family
1 N2 compatible with N1

Software consequences
When hardware compatibility with N1 is required, IVG (reg. 2B D6) has to be set to 1

6.3 IF

6.3.1 IF PLL Offset adjustment

This function is added to finetune the performance of the IF PLL

Function Reg Bit Steps Neutral (Hex)

IF offset 05 D5..0 63 20

The IF-PLL offset can be adjusted in +/- 32 steps. In previous concepts this typical offset was
achieved via an external high ohmic resistor connected to the IF-PLL filter pin.
This offset feature now gives more flexibility in optimising the performance.
Below three options are given for the PLL-offset:

1. No PLL offset
For standard application/requirements we recommend to preset to
mid-range D5-D0=001000.

2. Fixed PLL offset

Preset to a determined value. It’s recommended to have two different settings; one optimal for
positive modulation and one optimal for negative modulation. Of course one is free to determine
1-preset value as compromise for both (this than is similar to previous concepts when an external
resistor was used).

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3. Align for optimal PLL offset:

Negative modulation:
Apply a video signal with a 6kHz video component and a non-modulated sound FM carrier.
Monitor the audio SCART output signal or listen to the loudspeaker. Align the offset for a
minimal audible 6kHz component.

Positive modulation:
Have high modulated video signal. Monitor:
- the video SCART output signal and adjust offset for minimal V-sync disturbance.
- or align for correct Canal+ decoder behaviour.

Next a list is given of most important parameters that are effected by the PLL-offset.
Special attention is required for using the offset adjust as it requires a compromise on video and sound
performance.
Performance Negative modulation Positive modulation
parameters Offset setting -1 Offset setting -2
Video
Option 1 - sync and colour catching behaviour at weak RF signals.
Important for both pos/neg modulation

Video
Option 2 - video response (white->black) of - vertical sync distortion at high modulation depth *)
horizontal white line - video response (black->white) of horizontal
white line

Sound
- 6kHz video cross talk into sound *) - no issue: AM sound has different signal path

*) most sensitive parameters

Software consequences
When not used, just write the neutral position (20 hex) in register 05.
It is also possible to still start with writing register 06, register 05 will contain the value at power on
reset, which is also 20 hex.

6.3.2 Changed AGC speed settings

The AGC speed can now be set higher for better air plane flutter performance See table below.

AGC1 AGC0 Setting N2 Setting N1

reg 28 D2 reg 28 D1
0 0 0.7 x 0.7 x
0 1 Normal Normal
1 0 3x 2x
1 1 6x 4x

Software consequences
We do not expect it is needed to change the software for this change.

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6.4 Sound

6.4.1 Sound bandpass

The selectivity for FM sound carriers is improved by implementing an internal bandpass filter in the
2nd SIF path. The filter bandpass characteristic is adapted to the sound carrier (4.5, 5.5, 6.0 or 6.5
MHz), selected by the control bits FMA..B.

For more critical reception conditions, some setmakers used an external sound bandpass filter with the
N1 between pin 38 (IF out) and pin 32 (multi-functional pin, configured as 2nd SIF input by setting
SIF = 1). The internal bandpass improves the FM sound selectivity enough to omit this external
bandpass filter.

The internal sound bandpass and other circuit optimisations have improved the PAL-I FM sound
performance almost to the level of BG and DK performance

The sound bandpass filter can be bypassed by setting BPB (ByPass Bandpass, reg. 2E D6) to 1.
We advice to bypass the sound bandpass filter when searching for a sound carrier, e.g during search
tuning or automatic sound carrier detection after channel change.
Sound carrier search uses the read out bits FML (reg 02 D0, FM Lock, indicating lock to a carrier)
and FMW (Reg 02 D1, FM Window, indicating a carrier within +/- 225 kHz from the selected carrier
frequency) to detect whether a sound carrier is present.
Our investigations have shown that the reliablility of FML and FMW is better when the sound
bandpass filter is bypassed.
Do not forget to switch the sound bandpass filter on again after the sound carrier is found to benefit
from the improved sound selectivity.

Situation N1
No internal sound bandpass filter. For critical reception conditions some setmakers applied an
external sound bandpass filter.

Situation N2
Internal bandpass filter improves the FM sound selectivity. No need for applying an external sound
bandpass filter for more critical reception conditions.
Sound bandpass must be switched off during sound carrier search to improve the reliability of FML
and FMW.

Software consequences
When performing a sound carrier search e.g. during search tuning or automatic sound carier detection
after channel change, switch off the sound bandpass filter setting BPB = 1 to improve the reliablility
of the FML and FMW readout bits.
For all other conditions, enable the sound bandpass by setting BPB = 0 for improved sound
selectivity.

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6.4.2 + 6 dB amplifier

The N1 contained a + 6 dB amplifier, which was only switched on with 4.5 MHz sound carrier.
In the N2, the 6 dB amplifier after the FM demodulator can now be controlled independent of the
sound standard by the I2C bit AGN. This offers the opportunity for sets without the need for 4.5 MHz
sound carrier, to use the + 6 dB amplifier with 5.5 - 6.0 - 6.5 MHz sound carriers increasing the sound
output level at the deemphasis pin to a level which can be fed direct to SCART out without additional
amplification (only buffer needed). Note that the distortion figures of the audio signal can be outside
specification when this +6 dB amplifier is used with carriers with 50 kHz deviation and also the
reserve for overmodulation is decreased.

Situation in the N1
In the N1, the + 6 dB amplifier was switched on automatically when a 4.5 MHz sound carrier was
selected. This took care that the signal output level at 4.5 MHz sound carrier with 25 kHz deviation
had the same amplitude as the other carriers (5.5 - 6.0 - 6.5 MHz) with 50 kHz deviation.
For distortion free reception of a 4.5 MHz BTSC stereo signal with high deviation (100 kHz), the 6
dB amplifier could be switched off using the bit BTSC (only working when 4.5 Mhz carrier was
selected).

Situation in the N2
In the N2, the BTSC bit is replaced by AGN (Audio GaiN, reg. 29 D7), which switches the + 6 dB
amplifier on (AGN = 1) and off (AGN = 0) independent of the sound standard.

Software consequences
To have the same functionality in N2 as in the N1, the software should set AGN = 0 for 5.5 - 6.0 - 6.5
MHz carrier and AGN = 1 when 4.5 Mhz (mono) carrier is selected.
For BTSC stereo signal, AGN must be kept 0. (For N1, bit BTSC must be set 1 in this condition)

6.5 Synchronisation, Geometry and Deflection

6.5.1 Adapted range of upper/lower corner correction / S-correction

The range of these registers is changed to fulfil the requirements of real flat picture tubes.

Function Reg Bit Range N1 Range N2

Upper / Lower corner parabola 0C / 0D D5..0 -43 % ..... 0 % -46 % ..... + 17 %
Vertical S-correction 11 D5..0 0 % .....+30 % -10 % ..... + 25 %

Software consequences
When for manufacturing a pre-setting is used to load these registers with a value, close to the
alignment value, it is possible that the preset value must be adapted.
We do not expect any alignment problems with the new range.

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6.6 Filters and switches

6.6.1 Independent video and audio source selection

The selection of video source and sound source is made independent. This increases the flexibility for
external sound insertion and comb filter applications.(video: INA..B, audio: ADX)

Situation N1
In the N1, audio selection followed the switching of the video inputs (when ADX and ADS were 0).
It was posible to select the audio source indpendent of the video source when ADX or ADS was set
to 1. See table below.

Row INA INB ADX ADS Selected video Selected audio

reg 22 D2 reg 22 D1 reg 21 D3 Reg 28 D5
1 0 0 0 0 CVBS internal Internal audio
2 0 1 0 0 CVBS external External audio
3 1 0 0 0 Y/C external External audio
4 X X 0 1 See INA..B row 1..3 Internal audio
for selected video
5 X X 1 0 See INA..B row 1..3 External audio
for selected video

Situation N2
In the N2, the selection of video inputs and audio inputs is complete independent, see tables below

INA INB Selected video

reg 22 D2 reg 22 D1
0 0 CVBS internal
0 1 CVBS external
1 0 Y/C external

ADX Selected audio

reg 22 D5
0 Internal audio
1 External audio

Note that the bit ADX in the N2 has another position in the I2C table than in the N1!

Software consequences
When in the N1 no use was made of the bits ADX, ADS (both bits 0), for the N2 the software has to
write ADX = 0 when the internal video source is selected (INA..B = 0 0) and ADX = 1 when an
external video source is selected (INA..B = 0 1 or 1 0)
When using ADX and ADS in N1, the setting for ADX in N2 becomes:
ADX, ADS N1 = 0 1 --> ADX N2 = 0
ADX, ADS N1 = 1 0 --> ADX N2 = 1
Note that the position of the bit ADX in the I2C table is different for N1 and N2.

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6.6.2 Depeaking included in peaking range

To improve the picture under noise conditions, the peaking range is extended with depeaking.
By decreasing the bandwidth of the Y signal using depeaking, the picture impression will improve
when much noise is present.

Peaking setting N1 N2
Reg. 19 D5..0
00 Neutral (No peaking) Depeaking (overshoot -22 %)
10 Overshoot 20% Neutral (No peaking)
20 Overshoot 40% Overshoot 27%
3F Overshoot 80% Overshoot 80%
Note: Overshoot in direction black

Software consequences
The neutral position for peaking (no peaking) should be adapted from 00 hex to 10 hex.
When in standard setting peaking is already set at 20 hex, one could consider to leave the peaking
software "as is" and accept that at 20 hex the overshoot decreases from 40% to 27%.

6.6.3 Selection Peaking frequency

The peaking frequency ca nnow be selcted from three values. Previous, the peaking frequency had to
be a compromise to work well for both NTSC and PAL systems. Now optimal performance can be
achieved pending on the system received.

PF1 PF0 Peaking centre frequency

reg 19 D7 reg 19 D6
0 0 2.7 MHz
0 1 3.1 MHz
1 0 3.5 MHz
1 1 spare

Situation N1
The peaking frequency in the N1 is fixes to 3.1 MHz.

Software consequences
To get the same performance, set PF1..0 = 0 1.

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6.6.4 Adjustable ratio of pre- and overshoot for peaking

The ratio of overshoot in black direction and white direction for the peaking can be set to 4 different
positions using RPO1..0.

RPO1 RPO0 Ratio pre- and overshoot peaking

reg 2E D5 reg 2E D4
0 0 1:1
0 1 1 : 1.25
1 0 1 : 1.5
1 1 1 : 1.8

Situation N1
This feature was not available in the N1, the ratio pre- and overshoot of peaking was fixed
to 1 : 1,8.

Software consequences
To have the same setting for pre- and overshoot in the N2, write RPO1..0 = 1 1

6.7 RGB processing

6.7.1 Blanking of RGB outputs under all supply conditions

To avoid unwanted RGB drive at switch-on and switch-off, the RGB outputs have been modified.
The change consists of a hardware and software part.
In hardware, when the 8 Volt supply is below 6.4 volts, the RGB outputs are pulled below 1.5 Volts
internally.
In addition, the RGB outputs can be pulled low by setting the new bit RGBL (reg.23, D0) to 1.

Switch-on
For start-up, we advice to set RGBL to 1 and RBL to 1 as soon as the 3.3 Volt is present and the 8
Volt supply is still switched off. When the 8 Volt supply rises at the same time as the 3.3 Volt supply,
we advice to set RGBL = 1 and RBL to 1 when writing for the first time the I2C registers.
About one second after H-out is enabled (setting STB = 1) RGBL must be set to 0, because the black
current loop is also disabled when RGBL is set to 1.
The blanking of the screen is maintained as long as RBL remains 1, allowing the black current loop to
stabilize. Pending on the used start-up algorithm, usually RBL is set back to 0 when the loop is
stabilized (1.5 to 2 seconds after BCF reads 0).
This procedure ensures no flashes or retrace lines at start-up under any condition, also when the set is
switched off and immediately on again.

Switch-off
When the device is switched off by using the mains switch, the RGB outputs are pulled low as soon as
the +8 Volt supply drops below 6.4 Volts. Because the H-out also stops below 6.4 volts, this avoids
RGB drive when no deflection is present. This minimizes the risk for a white spot on the screen.

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When in bleeder applications also RGBL in combination with RBL is used to blank the RGB outputs
when switching to stand-by, perfect black switch-off is achieved indenpendent of the +8 Volt supply
behaviour.

Situation N1
This bit was not available in N1

Software consequences
No changes needed when the start-up / switch-off behaviour of the N1 is acceptable. Just write RGBL
= 0. The switch-off is already improved by the hardware provision which pulls the RGB outputs low
when the +8 Volt supply drops below 6.4 volts.

6.7.2 Extended range of Black Level offset adjustment

The range of the Black Level offset (BLOG/BLOR) has been doubled while the resolution is also
doubled.
The DAC’s are increased to 6 bit, and Black Level Offset Red and Green have now there own
subadress (formally they were 4 bits and combined in one 8 bit register)

Software consequences
In the N1, BLOR is positioned reg 15 D7..4 and BLOG is positioned reg 15 D3..0
In the N2, BLOR is positioned reg 14 D5..0 and BLOG is positioned reg 15 D5..0
Neutral position:
N1: reg. 15, 88 hex
N2: reg 14 and 15, 20 hex

6.7.3 Soft Clipper function

The built-in soft slipper function compresses peaks in the video signal. The function is quite simular
to the peak white limiter of the N1.
The compression gives a better impression than hard limiting of short peaks.

6.7.4 Vg2 alignment bits can be read out via OSD

The Vg2 alignment option is improved. When enabling the alignment with the bit AVG, the vertical
deflection remains running and the current measurement is done in a few lines in the top of the screen,
allowing to indicate on another part of the screen via OSD the status using bit HBC and WBC.
The adjustment of Vg2 using this method is very accurate. Therefore the best results are obtained
when the Vg2 potmeter range is chosen not to wide to have sufficient adjustment accuracy when
turning the Vg2 potmeter
Note: Vg2 alignment using only a horizontal line and turning up Vg2 until the line just becomes
visible is not possible any more with the N2.

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Situation N1
In the N1, the vertical deflection was switched off when the bit VSD (Vertical Scan Disable) was set
to 1. Readout of HBC and WBC had to be done via external controller or indication by LED in the
set.

Situation N2
In the N2, the name of the bit VSD has been changed to AVG (Alignment VG2) but the bit position
remained the same. When AVG is set to 1, the vertical deflection remains running, close to the top of
the screen a black bar is visable where the beam current is measured. In the lower half of the screen,
OSD can be positioned to indicate the status of HBC and WBC.

Software consequences
When in the N1 the bit VSD was used together with HBC and WBC for Vg2 alignment, it is not
needed to adapt the software, the adjustment procedure of the N1 will remain working.
If readout of the bits HBC and WBC via OSD is preferred, the software must write the status in the
lower half of the screen.
If Vg2 alignment was done setting VSD = 1 and turning up the Vg2 until a horizontal line just
becomes visable, the Vg2 alignment procedure has to be adapted to use HBC and WBC.

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TDA935X/6X/8X: Changeover N1 -> N2
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7 INFO WHEN ADAPTING FOR THE NEW PEAK WHITE LIMITER FUNCTION

The changed functionality of the new peak white limiter requires to bring the Vertical Guard function
from the BCL pin 49 to Black Current pin 50. The needed hardware changes are listed below.
This adaptation is only needed when the bit IVG (reg. 2B D6) is set to 0.

7.1 Hardware changes for the new peak white limiter function

When preferring to use the changed peak white limiter of N2 or wanting to adapt for compatibility
with the new TDA95XX family, only a small adaptation of the hardware is needed to use the N2
version in an existing N1 layout.
Note that in this case the bit IVG (reg. 2B D6) has to be set to 0

When no vertical guard is used, even no layout adaptation is needed.

vertical guard vertical guard
from from
TDA835X TDA835X

.
R3

10K

D1

50 R2 R2
50
BLKIN BLKIN
1K 1K
C2 C2

1nF

R1
49 49
BCLIN BCLIN
4K7

C1 C1
>4u7 >4u7

TDA935X/6X/8X N1 or N2 application (IVG = 1) TDA953X/6X/8X N2 application (IVG = 0)

Figure 3: Hardware changes for TDA953X/6X/8X N1 -> N2 when IVG = 0

28
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

The changes are:

For applications not using the vertical guard:

Pin 49, Beam Current Limiting input:

- Replace R1 by a jumper or a low ohmic resistor (equal or smaller than 1 Ohm)

For applications, using vertical guard:

Pin 49, Beam Current Limiting input

- Omit R1 (short-circuit by layout or replace by a jumper / resistor (equal or smaller than 1 Ohm)
- Disconnect the connection with the vertical guard output from the vertical deflection

Pin 50, black current input:

- Connect the vertical guard output of the vertical deflection via a schottky diode to pin 50. The
diode should be put as short as possible to pin 50.
- To prevent injection of picked up disturbance by the long track running from the vertical guard
output to pin 50, add a high ohmic resistor (10 kOhm) to ground in the track from the vertical
guard output.
- To further reduce possible disturbance add a capacitor of 560 pF from pin 50 to the ground pin of
the RGB connector for the wire to the RGB panel. In some applications, this capacitor was
already present

Some background for these changes:

The peak white limiter function in the N2 is improved. When the RGB outputs are driven too high, the
contrast wil be reduced for the total picture for the N2. This is achieved by discharging the capacitor
C1 with a large current.
When R1 is not replaced by a low ohmic path, the large current will cause a voltage drop across R1
when trying to discharge C1. The result is a much too slow discharge of C1, leading to incorrect
behaviour of the peak white limiter
Therefore it is needed to remove R1 for correct working of the new peak white limiter.
Without this resistor, the vertical guard function is not possible on pin 49 any more because the large
capacitor now direct connected to pin 49 prohibits the lifting of the voltage at pin 49 above detection
level during the guard pulse.
Therefore, the vertical guard function is moved to the black current loop pin 50.

In the application must be checked that the vertical guard pulse is ended before start of the RGB
measurement lines, see table below. The hardware checks for a falling edge of the vertical guard pulse
and expects this falling edge before the start of the RGB measuring lines.

Start vertical flyback // Position RGB measuring lines (leakage, R, G,

B)
Field 50 Hz field frequency 60 Hz field frequency
Odd Line 1.5 // 17, 18, 19, 20 Line 1.5 // 17, 18, 19, 20
Even Line 314 // 329, 330, 331, 332 Line 264 // 279, 280, 281, 282

With the above data the maximum duration of the vertical guard pulse becomes 14 lines, i.e.
maximum 900 µs. This value is valid for 50 and 60 Hz applications.

29
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

7.2 Beam current limiting and Peak white Limiter function

The peak white limiting function is improved. It now will reduce the contrast of the total picture when
the drive level at the RGB outputs is too high.

The level the peak white limiter starts working is set at 0.5 volts Black to White of a nominal CVBS
input signal with 0.7 Black to White amplitude (1 Vpp including sync).
However, this is only valid when contrast is set to maximum, when the contrast is decreased by e.g. 6
dB, the acting level of the peak white limiter referring to the CVBS input level is increased by 6 dB.
Only under extreme conditions the peak white limiter will be activated to ensure a proper picture.

To prevent that the peak white limiter acts on short peaks from e.g. subtitling, the peak white limiter
only will act when the duration of the peak exceeds 2 µs. In this way, the Soft Clipper takes care of
the short peaks while the peak white limiter acts on the peaks with longer duration.

Only under extreme conditions the peak white limiter will be activated to ensure a proper picture.
The reduction of the contrast in these extreme conditions improves the stability of the beam current
limiting because excessive RGB overdrive is already limited before reaching the cathodes.

Of course the behaviour for several pictures can slightly differ from the previous beam current limiter
circuit.

Usually by adapting the values of the different components used in the existing beam current limiting
circuit, a proper performance can be achieved.

30
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

8 ERRATA APPLICATION NOTE TDA935X/6X/8X N1 (AN98093)

These errata apply for the N1 but are also valid for the N2 version.

Errata:

Page 176:
YUV inputs must be AC coupled, identical to the RGB inputs

Page 178:
Interface circuit Y Pr Pb -> Y U V optimised in performance and corrected for AC coupling.

The modified pages are attached for reference.

There is also an updated version of the Application Note AN98093 (version 1.1) containing this
corrected information.

31
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

8.1 RGB / YUV inputs

*R2/V, G2/Y, and B2/U (external) inputs pin 46, 47, 48

The external R2,G2,B2 inputs and the external YUV inputs share only three pins therefore there must
be chosen to use these pins as external R2,G2,B2 inputs OR external YUV inputs. The selection is
done by I2 C bit YUV.
If I2C bit YUV=0 the external inputs pin 46, 47 and 48 behave as external RGB inputs. In case the
YUV bit is set to 1 the external inputs can be used as external YUV inputs.

The nominal amplitude of the R2, G2, B2 inputs is 700 mV.

The levels of the YUV inputs for a 100% colour bar are:
Y = 1.4 Vpp ( 1 Vblack-white)
U = -(B-Y ) = 1.78 Vpp
V = -(R-Y ) = 1.4 Vpp

The external R2 G2, B2 or YUV input signals must be AC coupled to pin 46, 47 and 48 according the
table below.

Pin number RGB input YUV input

46 R2 V = -(B-Y)
47 G2 Y
48 B2 U = -(R-Y)

The input signals are clamped to 2 Volt during burstkey period. The coupling capacitors chosen are a
compromise between fast clamping action and minimum line sag. Capacitors of 10nF or greater can
be used . The source impedance of the R2, G2 B2 or YUV signals should be minimised for correct
clamping operation. On the external R2G2B2 signals and the YUV signals the saturation control and
the black stretcher will function.
It is advised to minimise the track length to the YUV input pins. Adequate ground shielding of the
YUV signal tracks is advised for good interference immunity.

Note : When using the RGB or YUV input, the synchronisation into has to be connected to the
external CVBS/Y input pin!

* Insertion switch input 2 pin 45

Via a voltage on the insertion switch input pin 45 and the I2C bit IE2 a selection between the internal
YUV signals and the external R2G2B2/YUV signals can be made.
In 2 tables below a survey is given of the several modes which can be selected (also the relation to the
YUV bit is given.)

I2C bit YUV=0

BLKIN pin 45 I²C function Selected sources:
BLKIN< 0.4V IE2= * Internal YUV signals
0.9V<BLKIN< 3V IE2 = 0 Internal YUV signals
0.9V<BLKIN<3V IE2 = 1 R2;G2;B2 signals (via pin 46,47 and 48)

32
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

I2C bit YUV=1

BLKIN pin 45 I²C function selected sources:
BLKIN < 0.4V IE2= * Internal YUV signals
0.9V<BLKIN< 3V IE2 = 0 Internal YUV signals
0.9V<BLKIN<3V IE2 = 1 external YUV signals (via pin 46,47 and 48)

Internal YUV signals are always selected whenever the voltage at pin 45 is below the 0.4V and is
independent of the status of the IC control bit IE2.
With the I2C control bit IN2 it is possible to sense the voltage on the RGB insertion switch input pin
45 continuously even if the I2C bit IE2 is disabled.
At the input pin of the RGB insertion switch a low (source) impedance (< 560Ω) should be connected
for driving this pin.

DVD input (Y PB PR) using the YUV input

The signal on the YUV input must have the “Philips” amplitudes and sign to obtain the correct YUV
output signals. Note that this input is actually a Y, -(B-Y), -(R-Y) input.
For a 100% colour bar the signal amplitudes are:
Y = 1.4 Vpp ( 1 Vblack-white)
U = -(B-Y ) = 1.78 Vpp
V = -(R-Y ) = 1.4 Vpp

DVD players that are sold outside of Europe usually have an YPbPr output. An YPbPr signal is an
YUV signal with scaled amplitudes. The YPbPr signals amplitudes for a 100% colour bar are:
Y = 1 Vpp ( 0.7 Vblack-white)
Pr = 0.7 Vpp
Pb = 0.7 Vpp

The synchronisation signal is on the Y signal. To connect an YPbPr signal to the Y, -(B-Y), -(R-Y)
input of the TDA935X/6X/8X, the signals must be amplified and Pb and Pr must also be inverted.
For synchronisation the Y signal must also be connected to the external CVBS input which must be
selected with the INA..B bits (0 1) to enable sync processing.

The following level adaptation is required to obtain simular saturation between 100% CVBS colour
bar and 100% DVD colour bar:
Y_in = 1,40/1 = 1.40 * Y
-(B-Y)_in = -1.77/0.7 = -2.53 * Pb
-(R-Y)_in = -1.40/0.7 = -2.00 * Pr

Please note that we refer to 100% colour bar levels while usually a 75 % colour bar is used.

The advised application given on the following page realises this:

33
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

TDA935X/6X/8X

42
8V
100nF CVBS/Y input

47k 1k8
BC558B
- +
Y = 1Vpp BC548B 47

4µ7
22nF Y = 1.4Vpp

1k
22k 2k2

8V

3k9
BC548B
- + 5k1
Pb = 0.7 Vpp BC548B 48

4µ7
22nF - (B-Y) = 1.78Vpp
4k7

1k8 1k2

8V

3k9
BC548B
- + 5k1
Pr = 0.7 Vpp BC548B 46

4µ7
22nF - (R-Y) = 1.4Vpp
4k7

1k2 1k2

> 0.9V 45
insertion input 2

2
The YUV I C bit address has moved when going from TDA935X/6X/8X N1 to TDA935X/6X/8X PS/N2.
For N1, YUV busbit is at address 2BD1
For N2, YUV busbit is at address 2BD2

For Y, Pr, Pb selection: YUV=1, 1E2=1 in software

Pin45 (insertion pin) > 0.9V in hardware

Figure 4: Interface Y/Pr/Pb to the YUV input

34
Philips Semiconductors Version 1.6 March 2001
TDA935X/6X/8X: Changeover N1 -> N2
TV-processor + µP with Teletext AN20xxx

35
 Business Line Video January 2001
Philips Semiconductors

BROCHURE
Systems
Applications
Support

TDA935x/6x/8x PS/N2
Device Emulation
TDA935x/6x/8x PS/N2 (SDIL64) EMULATION

The following information is only intended as a guide for device

emulation, i.e. TDA935xPS/N2, TDA936xPS/N2 and
TDA938xPS/N2. Please refer to the device datasheet for specific
device information .

For emulation in the following systems:

Hitex Ax/Mx + PxSAA55xx Probe

Ashling Ultra 51 + PRU-SAA56xx Probe

A UOC Interface Board will be required, Ref: 7313 903 03171,

plus the correct emulation (bondout) Microprocessor and
Videoprocessor, as detailed over.
UOC Interface Board, Ref: 7313 903 03171

TDA935x/6x/8x PS/N2 DEVICE PROGRAMMING

For the SDIL64 device the Bench Programmer comes as standard

with an SDIL64 socket for device programming.

However, for the Emulation Microprocessor, SAA5573/83/95

QFP120, a QFP120 Daughter PCB, Ref: 7313 903 02641 will be
required.

Note:This Daughter PCB will also be required for the Hitex probe.
QFP120 Daughter PCB, Ref: 7313 903 02641

For more information on emulation please contact: BL-Video - Systems Applications Support

TEL: +44 (0)2380 316476 or Email: [email protected]

lmtb S PHI
 Business Line Video January 2001
Philips Semiconductors

BROCHURE
Systems
Applications
Support

TDA935x/6x/8x PS/N2
Device Emulation

Target Device Emulation Microprocessor Emulation Videoprocessor

TDA9350PS/N2/x
TDA9351PS/N2/x SAA5583H/Mx KN10161 - FM (SDIL64)*
TDA9353PS/N2/x

TDA9352PS/N2/x SAA5583H/Mx KN10161 - QSS (SDIL64)*

TDA9360PS/N2/x
TDA9361PS/N2/x
TDA9362PS/N2/x SAA5595H/Mx KN10161 - FM (SDIL64)*
TDA9363PS/N2/x

TDA9364PS/N2/x
TDA9365PS/N2/x
SAA5595H/Mx KN10161 - QSS (SDIL64)*
TDA9366PS/N2/x
TDA9367PS/N2/x

TDA9380PS/N2/x
TDA9381PS/N2/x
TDA9383PS/N2/x
TDA9384PS/N2/x SAA5573H/Mx KN10161 - FM (SDIL64)*
TDA9387PS/N2/x
TDA9388PS/N2/x

TDA9382PS/N2/x
TDA9385PS/N2/x
TDA9386PS/N2/x SAA5573H/Mx KN10161 - QSS (SDIL64)*
TDA9389PS/N2/x

* Special version of bondout for emulation purpose only, with full features, to cover the overall family.

lmtb S PHI
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The Netherlands, Fax. +31 40 27 24825

© Philips Electronics N.V. 2001 SCB 71

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