Z180 ™ FAMILY

Zilog QUESTIONS AND ANSWERS

APPLICATION NOTE

Z180 Family
MARCH 1994 QUESTIONS AND ANSWERS
This application note contains the most commonly asked questions about the Z180. Obviously, not
every possible question on the Z180 is answered. However, this application note should give you a
good feel for how the Z180 works. Along with the technical manual and product specification, it should
facilitate your Z180 design.

FEATURES

Q: What are the differences between the Z180, Hitachi’s A: PHI output changes its status on the falling edge of
HD64180R0/R1 and Z versions? EXTAL input. And the delay from the falling edge of
A: Our Z180 is identical to Hitachi’s HD64180Z version EXTAL to PHI is about 30 ns (Reference only; not
except some of the signal names are different in order guaranteed value)
to match Z80 signal names (Z180 was jointly devel-
oped with Hitachi). Q: In our system, sometimes the PHI frequency is the
same as XTAL frequency, not XTAL divided by two.
The HD64180R0 version is the original version, and Why?
has some bugs in it. The R1 version is the version which A: Please check the following points:
corrected the bugs in the R0 version. The 68-pin PLCC ■ Reset is held low at least 6 clock cycles.
and 80-pin QFP versions have 1M bytes of physical ■ The status of ST line during reset. ST should
memory address space. Also, There is a “test” pin not be tied low (ST line is the OUTPUT signal!)
(output; not open to user) assigned to the pin which is
not used on the R0 version.
INSTRUCTIONS
The Z version corrected the R0 and R1 problems (the
problems involve the Z80 peripheral interface.) Q: Which instruction, RET or RETI, is used at the end of
an interrupt service routine?
Q: In Z mode of operation (M1E of OMCR cleared to 0), A: If you don’t have any Z80 peripherals (do not use
there is no interrupt from the Z80 PIO after enabling “interrupt daisy chain”), then you can use either of
the Z80’s PIO interrupt. Why? these instructions at the end of interrupt service routine
A: Write zero to the /M1TE bit of OMCR after enabling the (for interrupt from on-chip peripherals). If you have Z80
Z80’s PIO interrupt. Because the Z80’s PIO interrupt peripherals on board, then you should use RETI for the
control logic requires /M1 to activate its interrupt logic interrupts of Z80 peripherals, and RET for the interrupts
while /M1 only occurs during Interrupt Acknowledge of on-chip peripherals.
and RETI cycles with /M1E cleared.
The reason, from CPU stand point, is both instructions
are the same (POP PC value from stack and return). But
CPU CLOCK Z80 peripherals are looking for RETI sequence on the
bus to correct its interrupt daisy chain status upon
Q: Can I stop the clock in order to minimize the power receiving that sequence. If you have Z80 peripherals
consumption? and are using RETI for the interrupt for on-chip periph-
A: No. However, one possible way is save the registers erals, Z80 peripherals are confused and thus set the
into battery backed up RAM , and then remove power wrong daisy chain status.
from the CPU.
Q: Is the instruction set of the Z180 fully identical to the
Q: What is the relationship between EXTAL and PHI Z80 CPU’s except for new instructions?
clock output when an external clock is input A: There are three instructions which are not the same.
through EXTAL? They are: DAA and RRD/RLD.

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INSTRUCTIONS (Continued)
For DAA (Decimal adjust), if you execute this instruction B) C register indirect
after DEC instruction (especially DEC instruction on IN A,(C) OUT (C),A
00h, then execute DAA), Z180 results in F9H while Z80 A15-A8 ←B register
results in 99H. It is because the Z80 CPU refers “Inter-
nal Carry flag” while the Z180 doesn’t. C) C register indirect with auto increment/decrement
IND INDR INI INIR OUTD OTDR OUTI OTIR
For RLD/RRD (Rotate Left/Right Digit), Z180’s flag will A15-A8 ←B register (B register is loop counter)
reflect the contents of the memory location pointed by
HL register, while Z80 reflects the contents of the D) Z180 original instructions which force A15-A8 to 0
Accumulator. IN0 OUT0 OTIM OTIMR OTDM OTDMR TSTIO
A15-A8 ←0
But, there are very few applications which use DAA
instructions after DEC and use flag after RLD/RRD To utilize “64K Bytes” of I/O address, you can use group
instructions. A) or B) instructions with care, or use group D) instruc-
tions to access the “Page zero” I/O address space.

REFRESH Q: To access on-chip peripherals (and system control

registers), Should A15-A8 be zero?
Q: Is the functionality of R register the same as Z80 A: Yes. It is a good idea to use Z180’s new I/O instructions
CPU’s? for that purpose (These instructions force A15-A8 to 0).
A: No. Z180’s R register is counting M1 cycles, and there
is no relationship with current refresh address. Q: What happens if off-chip peripheral’s address is
assigned to the internal I/O devices (overlapped)?
Q: Is the refresh mechanism of the Z180 different from A: I/O read: data from addressed internal peripheral is
the Z80 CPU’s? read, and the data on the bus at that time is just ignored.
A: Yes. Z180’s refresh mechanism is “periodic refresh” I/O write: output the data to the data bus as well as to
and the refresh period can be programmed and dis- on-chip peripherals. Also, this transaction could write
abled. Refresh address is 8-bit. On the Z80 CPU, the data to off-chip peripherals.
refresh cycle is inserted after every M1 cycle and can
not be disabled.
BUS TIMING
Q: Can the refresh cycle occur during an on-chip DMA
cycle? Q: For the Interrupt Acknowledge cycle timing chart,
A: Yes. Because Z180’s refresh mechanism can not distin- there are no timing specifications for PHI to M1 and
guish whether current activity is by CPU or on-chip PHI to IORQ. Do you have these numbers?
DMA. Refresh cycle will be inserted after the end of A: Yes. These parameters are as follows:
DMA or CPU machine cycle.
PHI rising edge to /M1 falling edge (Interrupt Acknowl-
edge cycle): Same as parameter #10 (tM1D1)
I/O ADDRESSING SPACE
PHI falling edge (of first TWA state) to /IORQ falling edge
Q: Z180’s technical manual states that I/O addressing (Interrupt Acknowledge cycle): Same as parameter
space is 64K Bytes while Z80 CPU’s I/O address #28 (tIOD1, Case IOC=1).
space is only 256 Bytes. How do you access “ex-
panded I/O address space”? PHI rising edge to /M1 rising edge (Interrupt Acknowl-
A: In fact, Z180’s I/O addressing space is the same as Z80 edge cycle): Same as parameter #14 (tM1D2).
CPU’s. You can specify lower half (A7-A0) of I/O ad-
dress directly, as on Z80 CPU, but the upper half PHI falling edge to /IORQ rising edge (Interrupt Ac-
depends on the instruction which you are using for knowledge cycle): Same as parameter #29 (tIOD2).
access. There are four groups of I/O instructions on
Z180 (On Z80 CPU, group D does not exist)

A) 8080 type instruction

IN A,(n) OUT (n),A
A15-A8 ←Acc

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Q: What about the bus status during the access to the WAIT STATES
on-chip peripherals?
A: During I/O access to the on-chip peripherals, Q: When using automatic wait state generator, does
the Z180 sample external /WAIT state before auto-
I/O read: Data bus - Hi-Z matic wait state insertion, or after?
Address bus: holds the I/O address A: External /WAIT status will be sampled after the auto-
matic wait state insertion.
I/O write: Data bus - Data to be written
Address bus: Holds the I/O address Q: Is it possible to insert wait state(s) into a refresh
cycle by /WAIT input?
Q: During sleep or bus release mode, is it possible to A: No. WAIT is not sampled during refresh cycle. How-
extend the E signal pulse width by inserting wait ever, Z180 has a capability to insert “software” wait
states? state into refresh cycle by setting REFW (Bit D6) of RCR
A: No. During sleep or bus release mode, the CPU won’t register to 1.
sample the status of /WAIT input (cannot extend the
cycle). Q: Is the automatic wait state during I/O cycle remov-
able?
Q: What is the timing of E output during -DMA, A: No.
-Refresh, -I/O cycle?
A: For refresh cycle, E output will be held low. For DMA and Q: When accessing on-chip peripherals, it seems that
I/O cycle, E timing is identical to the CPU cycle. Thus: required access time varies case by case. Why?
A: When accessing on-chip peripherals (ASCI, CSI/O,
E is active during... PRT data registers), zero to four wait states are auto-
Memory R/W: T2 rising edge to T3 falling edge. matically inserted depending on the status of CPU and
I/O read: 1st Tw rising edge to T3 falling edge. peripherals. In those cases, the value set in DAM/WAIT
I/O write: 1st Tw rising edge to T3 falling edge. control register is ignored.

Q: Does the Z180 sample the data at the different points

during memory read and opcode fetch cycles, as RESET
the Z80 CPU does?
A: Yes. The data is sampled on the rising edge of T3 during Q: How is the power-on reset sequence performed?
opcode fetch cycles, falling edge of T3 for memory A: The power-on reset sequence is as follows.
read cycles.

Restart
Op-Code Fetch
Reset State T T T
1 2 3

more than 6 clock cycles

RESET

High Impedance
Address 00000H

Restart Address
Control
Signals

Note: /RESET pin should be asserted Low for at least 6 clock cycles to perform power-on reset correctly.

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Zilog QUESTIONS AND ANSWERS

POWER SAVE MODES

Q: How to exit from SYSTEM STOP mode, and what is Except for RESET, I/O STOP mode is maintained until
the CPU’s response after exiting this mode? the I/O stop bit is cleared to 0 after exiting from SYSTEM
A: /NMI, /INT (external) or RESET is necessary to exit from STOP MODE.
SYSTEM STOP mode. If receiving RESET, normal RE-
SET sequence takes place. In case of /NMI, /NMI Q: During SLEEP mode, when is the CPU sampling the
sequence takes place. In case of external /INT: status of INT line?
A: The CPU starts to sample the status of INT line on the
If interrupt is globally disabled (IEF1=0): falling edge of the 1.5 clock cycles after entering the
CPU will execute the instruction following the SLEEP SLEEP mode. When CPU samples INT as active, 1.5
instruction. clock cycles later CPU will wake up from SLEEP mode.

If interrupt is globally enabled (IEF1=1):

Appropriate normal interrupt response sequence
will be performed.

Interrupt can be
Sampled
SLP
Instruction Sleep Interrupt Acknowledge
Cycle Mode Cycle

T T T T T T T
3 1 2 S S 1 2
Ø

Interrupt
1Ø 1.5Ø

Q: What is the status of the bus during SLEEP mode? A: If an interrupt is received during a SLP instruction, /HALT
A: A0-A19 are all one, /HALT stays low, and /MREQ, /M1, is asserted low for one clock cycle and the address bus
/RD stay high. is set to all ones, and is then followed by an interrupt
acknowledge cycle, as shown below.
Q: What happens if an interrupt is received during the
execution of the Sleep (SLP) instruction?
Sleep Mode
SLP Fetch Cycle Interrupt Acknowledge Cycle

T1 T2 T3 T1 T2 T1 T2

Interrupt

HALT

Address
2nd Opcode Address $7FFFF Next Address
SLP

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TRAP
Q: What happens if another trap condition (detecting So that you can determine the starting address for the
undefined opcode) occurs before clearing the instruction which caused the TRAP.
TRAP bit of the ITC register?
A: You will have another TRAP. If the trap handling routine
causes a TRAP it will probably get into an infinity loop, NMI AND INT
and crash. For this case, the TRAP bit remains 1 and the
UFO bit shows the status for the previous TRAP, since Q: Are the addresses of interrupt vectors treated as
the status of the UFO bit cannot be changed while physical addresses or logical addresses?
TRAP=1. A: Z180 always treats those addresses as Logical ad-
dresses. So if you enabled the MMU, care must be
Q: What is the purpose of the UFO bit? taken.
A: UFO bit shows weather TRAP occurred during 2nd
opcode fetch cycle or 3rd. If it is zero, TRAP has Here is one suggestion: If you can make the vector
occurred in the 2nd opcode fetch cycle and the PC table in Common Area 0, the physical address is the
value pushed onto the stack is, 1st opcode address +1. same as the Logical address, which helps.
And if it is one, TRAP has occurred in the 3rd opcode
fetch cycle and the PC value pushed onto the stack is, Q: What happens if an interrupt is received during an
1st opcode address +2. All hex numbers for first on-chip DMA operation?
opcode on Z180 are allocated for instructions, so TRAP A: If it is an /NMI, DMA operations will stop and an /NMI
won’t happen on 1st opcode. acknowledge cycle will be initiated. If it is /INT or
interrupt from on-chip peripherals:
Q: How do you determine the opcode address which
caused TRAP using the UFO bit? During Mem-Mem burst mode transfer, the interrupt is
A: Upon TRAP, the PC value pushed onto the stack for the just ignored.
address of the instruction which caused TRAP is:
During Mem-Mem cycle steal mode of operation, inter-
Instruction start address = rupt acknowledge cycle is initiated between DMA
(value on the stack) -1 when UFO=0 cycles (See following figure).
Instruction start address =
(value on the stack) -2 when UFO=1

DMA CPU DMA

DMA Read DMA Write Interrupt DMA Read DMA Write

Acknowledge

Q: For interrupt mode 2, shall I set bit D0 of interrupt A: No. /NMI and /INT are disabled for three clock cycles
vector to 0, as Z80 requires? immediately after RESET (power on reset). After those
A: Yes. However, the Z180 works correctly even if bit D0 three cycles, the instruction is executed (from 0000h)
of the interrupt vector is 1. and then interrupt is enabled. Note that /NMI status is
latched internally right after the power on reset cycle.
Q: Is /NMI acknowledged during an interrupt acknowl-
edge cycle? Q: Is an interrupt (/NMI or /INT) acknowledged during a
A: Yes. One instruction (except EI and DI instruction) is refresh cycle?
executed after /INT acknowledge cycle, then the /NMI A: /NMI status will be latched internally if /NMI occurs
acknowledge cycle starts. It is also the same for /NMI during the refresh cycle. When current instruction ex-
received during /NMI acknowledge cycle. ecution is completed, the following cycle will be an
/NMI acknowledge cycle. /INT status is not sampled
Q: Are /NMI or /INT acknowledged immediately after during a refresh cycle, and it will be sampled during the
RESET? following instruction execution cycle.

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Zilog QUESTIONS AND ANSWERS
NMI AND INT (Continued)
Q: I have an /NMI input with a pulse width of a couple of A: The Z180 samples an interrupt status at the falling edge
hundred ns. Can it be accepted? of PHI one cycle prior to the last machine cycle of each
A: The /NMI input will be accepted as long as you can instruction (excluding EI instruction). Also, the status of
satisfy the /NMI pulse width specification (120 ns min.), the internal /NMI latch is sampled at the same time.
since /NMI is edge triggered input and its status is
latched internally. Q: During execution of block transfer instructions,
doesn’t the Z180 sample an interrupt status until the
Q: During the execution of EI instruction, can an inter- end of block transfer?
rupt be acknowledged? A: No. The Z180 checks the status of interrupt at the end
A: No. During execution of an EI instruction, interrupt is not of every sequence, as shown below. Note that if you
sampled. So if interrupt (Maskable interrupt) goes accept interrupt during block transfer, your interrupt
active during the instruction just before an EI instruc- service routine will not destroy the contents of registers
tion, or during EI instruction, it will be acknowledged in order to resume from the interrupt correctly (save the
during the following instruction. registers using EX/EXX instructions at the beginning of
interrupt service routine).
Q: When does the Z180 sample an interrupt status?

(n-1)th Byte Transfer Interrupt

Cycle n th Byte Transfer Cycle Acknowledge Cycle

MC1 MC2 MC3 MC4 MC5 MC6

T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T2 T3 T1 T1

Interrupt

Interrupt Sampling

Q: During interrupt Mode 0, if a call instruction is put Q: Is there any way to connect 8259 (interrupt control-
onto the bus during the interrupt acknowledge ler) under mode 0 interrupt?
cycle, software won’t return the correct address. A: When using Mode 0 interrupt, which is “8080 compat-
Why? ible interrupt mode”, there is one important point, which
A: The PC value pushed onto the stack during the interrupt is “concern about the INTA pulse”.
acknowledge cycle is the PC value for the next instruc-
tion if the instruction put onto the bus is the RST (restart) Mode 0 is the mode which maintains the “software
instruction (one byte instruction). compatibility” with the 8080. That means in this mode,
during the INTACK cycle, the Z180 fetches the data on
However, call instruction is a three byte instruction and the bus as an “instruction” and executes it, like the
the return address pushed onto the stack by that Call 8080.
instruction will be the PC value plus two (PC value stays
the same during interrupt acknowledge cycle, and However, from the hardware stand point, it is not true.
incremented by two during operand fetch for jump Because the 8080 generates three INTA pulses during
address). So at the end of the interrupt service routine, the interrupt acknowledge cycle, while the Z180 gener-
you need to decrement the return address pushed onto ates only one INTACK signal (which can be decoded
stack by two. from /M1 and /RD).

Q: What happens if there is /NMI going active and at the This system works fine if you are not using the 8259 and
same time (or just before) /DREQn is also going put “RST” (restart) instruction onto the bus during the
active when using DMA with /DREQn input? Interrupt acknowledge cycle which is a one byte in-
A: The input on /DREQn is ignored. To restart DMA, please struction. However, if you want to use the 8259 with the
refer to previous Q&A. Z180, you’ll have a problem, which is:

Q: When interrupts from on-chip peripherals are The 8259 requires three INTA pulses but the Z180
sampled, is it the same as the external interrupts? generates only one INTACK cycle.
A: Yes. Interrupt status is sampled on the falling edge of T2
or T1 cycle of the last machine cycle of the instruction.

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Zilog QUESTIONS AND ANSWERS
The best way to solve the problem is to “simulate an On the following memory read cycle of the jump ad-
8080 interrupt acknowledge cycle” - generating a total dress for the call instruction, this circuit generates two
of three “INTA” pulses for 8259 upon the Z180’s inter- additional INTA pulses for the 8259 and also masks off
rupt acknowledge cycle by external logic. the read signal for the memory to avoid bus contention
problems.
The following figure is one example of the implementa-
tion. This circuit works as follows (Assume that the On the following write cycle, /WR signal resets the LS74
instruction sent by the 8259 was a “CALL” instruction). to indicate that the interrupt acknowledge cycle is
On interrupt acknowledge cycle, a decoded INTA completed.
signal is sent out as an INTA pulse for the 8259 and at
the same time, sets the LS74 to indicate that the By using this circuit, you can use the 8259 with the
interrupt acknowledge cycle is started. Z180.

'LS32
'LS08
M1 'LS32
INTA
(8259)

PR

Z180 D Q 2C 2Y2 MEMR

'LS74 2Y1 MEMW

Q 1C 1Y1 IOR
CL
1Y2 IOW

MREQ 2G
IORQ 1G
RD B
WR A

'LS155
RESET

'LS08

MMU

Q: When does the effect take place after changing the 68-pin PLCC/80-pin QFP version -
contents of MMU related registers? When “calculated address” is above FFFFFH, carry
A: From the instruction following the I/O write instruction to bit is just ignored (carry from A19). That means the
the register. address wraps around to 00000H.

Q: What happens if the MMU base register is pro- Q: Can I have a Common Area 1 and Bank Area (or,
grammed to exceed 512K (64-pin DIP) or 1M Bytes Common Area 0 and Bank Area) overlapped by
(68-pin PLCC/80-pin QFP) of physical addressing programming associated MMU registers?
space? A: Yes. You can have overlapped areas by programming
A: 64-pin DIP version - MMU Common Base/Bank Base registers (See figure
When “calculated address” is above 7FFFFH, carry on next page).
bit and MSB are just ignored (A19 and carry from
A19). That means the address wraps around to
00000H.

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MMU (Continued)
Physical Address Space

Logical Address Space

FFFFH 1EFFFH

Common1 Common Base

Area Registar 0FH 1CFFFH Overlapped
1B000H Area
C000H
Bank Bank Base
Area Registar 11H 15000H
4000H
Common0
Area

0000H

DMA CHANNELS

Q: What happens if an NMI occurs during a DMA cycle? control. The DME (DMA enable) bit of that DMA channel
A: When the DMA cycle is completed, the CPU gains is reset to Zero.

T T T T T T T
1 2 3 1 2 3 1

NMI

DME bit is reset to '0' then

DMA operation will stop CPU cycle
(DMA operation
is halted)
DMA Read Cycle DMA Write Cycle

To restart DMA after the /NMI processing, DE (DE0 or to 1. This scheme allows changing the status of the DE0
DE1) bit should be set to 1 along with DME bit to 1. or DE1 bit without affecting the operation of the other
DMA channel.
Here is an example to restart DMA0.
Q: When DMA0 is used for data transfer from/to on-
LD A, 01100011B ;DE0=1 with DME=1, /DWE=0 chip ASCI, does it accept the request from DREQ0
OUT0 (30H),A ;Write out to DSTAT reg. input?
A: When DMA0 is used for data transfer for an internal
Q: What is the purpose of the /DWE bit in the DSTAT peripheral (ASCI Tx or Rx data), external input on
register? /DREQ0 is ignored. When using /DREQ0 input for DMA
A: To set/reset the DE0 or DE1 bit in DSTAT register, you request from an off-chip peripheral, both bits of SAR17/
also have to set the corresponding /DWE0 or /DWE1 bit 16 or DAR17/16 should be cleared to zero.

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Q: When using DMA0 for ASCI data transfer, what value data (RDRF flag=1), DMA won’t start the data transfer.
shall I program into SAR0 (DMA0 Source Address For that case, before enabling DMA channel, read TSR
Register) or DAR0 (DMA0 Destination Address Reg- register to reset the RDRF flag.
ister)?
A: You have to program SAR0 or DAR0 as follows: Remember that you cannot use “Level sense mode” for
ASCI data transfer.
For Receive data transfer:
Q: Can I transfer the memory data using DMA and using
Set SAR0L (I/O address 20H) to: logical address?
08H for ASCI0 receive data A: No, you can’t. You have to know the physical address for
09H for ASCI1 receive data the target memory as well as the Common0/Bank/
Common1 address assignments. You may need to
Set SAR0H (I/O address 21H) to 00H calculate the “physical address” using the value in
MMU related registers - BBR, CBR and CBAR.
Set SAR0B (I/O address 22H) to:
01H for ASCI0 receive data Another solution might be using Z180’s “Block transfer
02H for ASCI1 receive data instructions”. For this case, you don’t have to know the
physical address for the target memory.
For Transmit data transfer:
Q: I want to transfer the data from a memory mapped I/
Set DAR0L (I/O address 23H) to: O device (Fixed address) to one of the peripherals
06H for ASCI0 transmit data assigned to an I/O address. Can I do that?
07H for ASCI1 transmit data A: No. The following source/destination combinations are
NOT allowed.
Set DAR0H (I/O address 24H) to 00H
Memory (Fixed address) to Memory
Set DAR0B (I/O address 25H) to: (Fixed address).
01H for ASCI0 transmit data
02H for ASCI1 transmit data Memory (Fixed address) to I/O (Fixed address).

Q: For the DMA transfer from/to ASCI channels, does it I/O(Fixed address) to I/O(Fixed address).
require A15-A8 of SAR or DAR equal to 00H?
A: Yes. Those bits have to be zero for ASCI data transfer. With the memory mapped I/O device (Fixed address),
If the value is not zero, the access by DMA is not going you can transfer data from/to Memory (variable ad-
to ASCI registers but will try to access off-chip I/O dress).
devices. The result is ASCI will continue to request
DMA service (Request status would not be cleared). Q: When using on-chip DMA for Z80 SIO Tx data trans-
fers with level sense mode, sometimes Tx data is
Q: I’m trying to transfer ASCI receive data using on- missed (It has “extra DMA cycle”). Why, and are
chip DMA. But after enabling the DMA channel, it there any workarounds for this situation?
won’t transfer the data. Why? A: The reason for “extra DMA cycles” is the timing when
A: Please check whether ASCI has already received data DMA samples the DREQ status and the timing when
when enabling the DMA channel. If ASCI already has SIO negates the DREQ signal. (See next page)

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Zilog QUESTIONS AND ANSWERS

DMA Read Cycle DMA Write Cycle

T1 T2 T3 T1 T2 TW T
3
Ø
Additional
DMA cycle

Address

ACK

DREQ

(RDY-Z80SIO Output Signal)

DREQ Signal is Sampled.
(If DREQ signal is not negated at this
point, an additional DMA cycle starts.)

Here are possible workarounds. Q: Which DMA channel has higher priority?
1) Program DMA to edge sense mode. A: DMA Channel 0 has higher priority.
2) Put in one wait state for the I/O write cycle.
3) /DREQ signal masked by the Chip enable signal
of the Z80 SIO.

ASCI CHANNELS

Q: Are there any ways to send BREAK via software a break. One possible way to send a break is to utilize
command? the unused modem control signal of the Z180, or using
A: No. ASCI doesn’t have any software commands to send an output port bit and connect as follows:

T
X
T
X
RTSo

TX ' User
RTS o TX '
System
Port

Q: How to calculate baud rate? Q: I could not send data since TDRE always reads zero.
A: Use the following formula to calculate. Why?
A: Please check the /CTS line status. TDRE is qualified by
Baud rate = System Clock Speed the status of the /CTS line. If /CTS stays high, the TDRE
(Clock factor) X (PS bit) X (Divide ratio) bit is zero. Transmit interrupt is generated by the TDRE
bit, so with /CTS high, you won’t receive transmit
Where : Clock factor - 16 or 64 interrupt if you enabled the interrupt.
PS bit - 10 or 30
SS0-SS2 - 1, 2, 4, 8, 16, 32 or 64

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Q: What happens if /CTS goes inactive at the middle of Q: What is the maximum baud rate for ASCI channels?
the data transmission ? A: When using the internal clock for baud rate generation,
A: The character being sent out will be sent completely. it is:

Q: When reading the status of /DCD0 found in STAT0, BRGmax = PHI/(1x10x16)

the status is still one but the real status of the /DCD Where: 1 is divider value, 10 is prescaler value,
pin has already changed to zero. How and why is and 16 is sampling rate.
this?
A: The /DCD0 bit in the status register is reflecting the When using the external clock, clock frequency on the
status of the /DCD0 pin. The low to high change on this external clock input is limited up to PHI/40, so:
pin updates the status of the /DCD0 bit right away. But
if the change on the /DCD0 pin is high to low then the BRGmax = PHI/(40x16)
bit will remain the same until this bit is read (to change Where: 16 is sampling rate.
its status). The reason for this scheme is to serve the
interrupt for /DCD correctly. If it changes its status at Q: When using the external clock for baud rate genera-
both transitions, and if there is an interrupt from ASCI0 tion, can I use the on-chip clock divider/prescaler?
before the service for /DCD, the status of /DCD would A: No. When using external clock input, the on-chip clock
be lost. divider/prescaler is skipped.

Band rate
Prescalor Sampling rate
Internal clock selector
÷16 / ÷30 ÷16 / ÷64
Ø ÷1 - ÷ 64

External clock
fc ≤ Ø ÷ 40

TIMER

Q: Does timer (PRT) Channel 0 have a timer output ? A: When you modify RLDR (Timer Reload Register), make
A: No. If you need to have timer output, you have to use PRT sure the write transactions (write 2 bytes; RLDRL then
channel 1 and use TOUT. followed by RLDRH) start just after TDR (Timer Data
Register) reaches 0000H, and complete before reach-
Note that TOUT pin is multiplexed with A18, so if you want ing 0000H again. If reload condition occurs in the
to have TOUT, you need to consider physical memory middle of these two writes, the Timer loads “Old”
assignments (For this case, physical memory space is RLDRH and “New” RLDRL values.
half size).
Q: What happens to the Timer after resuming IOSTOP
Q: Can I use PRT channel(s) to count external events mode if IOSTOP mode is entered during operation?
(as counter)? A: The timer will hold current settings and values, and
A: No. PRT’s input is always PHI divided by 20 (Works as resume operation from the point when IOSTOP mode
timer only). was entered.

Q: I’m using timer for generating PWM pulses. Some-

time I cannot get the desired pulse width for a cycle.
Why?

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 Z180™ FAMILY
Zilog QUESTIONS AND ANSWERS

NOTES:

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