TEJAA SHAKTHI INSTITUTE OF TECHNOLOGY FOR WOMEN

DEPARTMENT OF CSE

LESSON PLAN – COMPUTER ARCHITECTURE

Name of the Faculty: Mr. G.swaminathan Semester: IV
Reopening Date: December 06, 2010
Cumula
Hours Assign./I.S./
Week Class Topic -tive Reference Remarks
Planned Test
Hours
Unit 1:
DATA REPRESENTATION,
MICRO-OPERATIONS
ORGANIZATION AND DESIGN:
Data types, complements
 Number Systems
1.  Octal and 1 1 2,3
Hexadecimal numbers
 Decimal
Representation
 Alpha Numeric
Representation

Fixed–point representation
Floating-point
representation
 1’sComplement
 2’sComplement
2. 1 2 2,3
 Arithmetic
Addition
 Arithmetic
Subraction
1.
Unit III
COMPUTER
ARITHMETIC, PIPELINE
AND VECTOR
PROCESSING
Addition and subtraction
 Addition and
subtraction with
3. 1 3 2,3
signed magnitude data
 Addition and
subtraction with
signed 2’s
complement data

Multiplication algorithms
 Booth’s algorithm
4.  Array Multiplier 2 5 2,3

2. 2 Division algorithms 2 7 2,3 M.S. – 1

  Divide Overflow
 Hardware Implementation
Unit 1:
Other binary codes, error
4. detection codes 1 8 2,3
 Gray Code
 Other Decimal Codes
 Other Alphanumeric code
Register transfer language
1.  Register transfer 1 9 2,3 Assign 1

Bus and memory transfers

 Three State bus
buffer
2. 1 10 1,4
 Memory Transfer

3. Arithmetic micro-operations
 Binary adder
3.  Binary adder subtractor 1 11 1,4
 Binary Increamenter
 Arithematic Circuit
Logic micro-operations
 List of logic micro
4. 1 12 1,4
operation
 Hardware implementation
4. Submission
Shift micro-operations of
1. 1 13 1,4
 Hardware implementation Assign. - 1

Arithmetic logic shift unit

 Arithmetic logic shift
2. unit 1 14 1,4
 HDL,VHDL

Instruction codes, computer

registers, computer
instructions
3.  Stored Program 1 15 1,4
organization
 Indirect Addressing
 Common Bus System
4. Timing and control, 1 16 1,4 M.S. – 1
instruction cycle, memory Review
reference instructions
 Fetch and Decode
 Determine the type of
Instruction
 AND to AC
 ADD to AC
 Load to AC
  Store AC
5. UNIT TEST -1
Input-output and
interrupt,Complete computer
description
 Input-output
Configuration.
1. 1 17 1,4
 Input-output
instructions
 Program Interrupt
 Interrupt cycle

Design of basic computer,

design of accumulator logic
2. 1 18 1,4
 Control of AC Register
 Adder and Logic Circuit
6.
Unit II:
CONTROL AND
CENTRAL PROCESSING
UNIT
3. 1 19 1,4
Micro programmed Control:
 Control Memory
 Address Sequencing

Micro-program
example, design of control unit
 Computer Configuration
4. 1 20 1,4
 Microinstruction Format
 Symbolic Microinstruction
 Microprogram sequencer
7. General register organization,
stack organization
 Control word
1.  Register stack 1 21 1,4
 Memory stack
 Reverse polish notation

Instruction formats,
addressing modes
2.  1-address Instruction 1 22 1,4
 2-address instruction
 3-address instruction
Data transfer and
manipulation, program
control
 Data transfer instructions
3. 1 23 1,4
 data manipulation
instructions
 Arithmetic instructions

4. Reduced instruction set 1 24 1,4 Assign 2

computer
  CISC Characteristics
 RISC Characteristics
 overlapped register
windows
Floating-point arithmetic
operations
1.  Basic considerations 1 25 1,4
 Register considerations

Pipeline and vector processing

 Parallel processing,
2. 1 26 1,4
pipelining

Arithmetic pipeline, Submission

8. 3. instruction pipeline 1 27 1,4 of M.S. - 1

RISC pipeline, vector

processing array processors
 Delayed Load
 delayed branch
4. 1 28 1,4
 vector operations
 matrix multiplication
 memory interleaving
 super scalar processors
Unit 4: Input output
organization:
Pheripheral devices
1. 1 29 1,4
 ASCII alphanumeric
characters

Input –Output interfaces

I/O bus interface modules
I/O versus memory bus
2. 1 30 1,4
Isolated versus memory
mapped I/O
9.
Asynchronous data transfer
 strobe control
 handshaking M.S. -2
3. 1 31 1,4
 asynchronous serial transfer
 asynchronous
communication interface
Modes of transfer
 Interrupt initiated I/O
4. 1 32 1,4
 Software considerations

10. 1. Priority Interrupt 1 33 1,4

 Daisy –chaining
priority
 Parallel priority
interrupt
 Priority encoder
  Interrupt cycle

Direct memory access

2.  DMA controller 1 34 1,4
 DMA transfer
Input –Output Processor
 cpu-iop communication
3. 1 35 1,4
 IBM 370 I/O channel
 Intel 8089 IOP
Serial Communication
 Character oriented
protocol
 Transmission example
4. 1 36 1,4
 Data transparency
 Bit oriented protocol

11. UNIT TEST – 2

UNIT V:Memory
12. Organization
1. 1 37 1,4
Memory Hierarchy:
 Memory Hierarchy
Main Memory
 RAM and ROM Chips
2. 1 38 1,4 Assign 3
 Memory address map
 Memory connection to CPU
Auxillary CPU
3.  Magnetic disks 1 39 1,4
13
 Magnetic tape
Associative Memory
 Hardware Organisation
4.  match logic 2 41 1,4
 Read operation
 Write operation
14 Cache Memory
 Associative mapping
 Direct Mapping
2. 2 43 1,4
 Set associative mapping
 writing into cache
 cache initialization
Virtual Memory
 Address space and memory
space Submission
 address mapping using of
4. 2 45 1,4
pages Assign. - 3
 associative memory using
page table
 page replacement
2. Memory Management 2 47 1,4 Submission
Hardware of M.S. - 2
15
 Segment page mapping
  Numerical example
 memory protection

Memory management
4 hardware 1 48 1,4
 Problems
16. Unit Test – 3 and Retest / Improvement Test
17. Revision Classes and Model Practical Examination
Last Instructional Day : 19.03.2011
Last Working Day : 12.04.2011
University Theory Examination : 18.04.2011

Text Books

1 Morris Mano, ‘Computer System Architecture’, 3 Edition, Pearson Education, 2002

/ PHI.
References
2 Vincent P.Heuring and Harry F.Jordan, ‘Computer Systems Design and
Architecture’, Pearson Education Asia Publications, 2002.
3 John P.Hayes, ‘Computer Architecture and Organization’, Tata McGraw Hill, 1988.
th
4 Andrew S.Tanenbaum, ‘Structured Computer Organization’, 4 Edition, Prentice
Hall of India/Pearson Education, 2002.
th
5 William Stallings, ‘Computer Organization and Architecture’, 6 Edition, Prentice
Hall of India/Pearson Education, 2003