Genus Synthesis Solution

Massively parallel RTL synthesis and physical synthesis

In the complex world of chip design, you’re constantly pushing to improve your chip—to get
more performance, lower power, and improved area. Developing the best solution requires high
accuracy and correlation, as well as extremely rapid turnaround time. To remain competitive, you
can’t afford to degrade any of these parameters—power, performance, area, accuracy, or runtime.
With the Cadence® Genus™ Synthesis Solution, no compromises are necessary: you get the best
and most highly correlated results in the shortest time.

Overview • Global analytical micro-architecture • Unified next-generation user

optimization delivers up to 20% interface with the Innovus
The Genus Synthesis Solution is a reduction in datapath area without Implementation System and
next-generation RTL synthesis and any impact on performance Cadence Tempus™ Timing Signoff
physical synthesis tool that delivers Solution
up to a 10X boost in RTL design • Unified GigaPlace™ engine, delay
productivity with up to 5X faster calculation, parasitic extraction, and • Physically aware logic structuring
turnaround times.The solution can timing-driven global routing with the and mapping
scale its capacity to well beyond 10 Cadence Innovus™ Implementation
• Power domain and layer-aware net
million instances flat. It also delivers System; timing and wirelength
buffering
tight timing and wirelength correlation between the tools correlate to
to within 5% of place and route. within 5% • Single-pass multi-Vt optimization

Using the Genus Synthesis Solution,

you can experience a 2X or more
reduction in iterations between
block-level and unit-level synthesis.
In addition, you can achieve up to
a 20% reduction in datapath area
without any impact on performance.

Key Features and Benefits

• Massively parallel architecture works
seamlessly over multiple machines
and multiple CPUs per machine;
delivers up to 5X faster runtimes
with linear scalability beyond 10M
instances flat

• Automatic extraction of full timing

and physical contexts for any subset
of a design; reduces iterations
between unit-level and chip-/
Figure 1: The Genus Synthesis Solution enables timing debug with physical interconnect
block-level synthesis by 2X or more knowledge built-in. Cross-probe to the physical viewer to see associated wirelengths,
floorplan blockages, and estimated routing, and extract the chip-/block-level physical context
for use in unit-level RTL design.​
 Genus Synthesis Solution

• Hierarchical RTL register clock gating Tight Correlation to Place Register Retiming
• Timing-driven physically aware multi-bit
and Route
The Genus Synthesis Solution can retime
flop mapping The Genus Synthesis Solution shares registers along pipelines and around
several common engines with the Innovus sequential loops. Retiming can increase or
• Pipeline and general register retiming
Implementation System, including the decrease the number of flops along the
• ChipWare functional components and GigaPlace engine, delay calculation, retiming cut to achieve the best possible
simulation models parasitic extraction, and timing-driven PPA tradeoff.
global routing. Timing and wirelength
• Full support for multiple power domain
between the tools correlate tightly ChipWare Components
design with automatic low-power cell
to within 5%, and global routing
insertion, both CPF and IEEE 1801 The solution includes a complete portfolio
performance is 4X better. Both tools are
power-intent specifications supported of industry-standard functional building
critical for productivity at advanced nodes
block components such as fixed-point
• Concurrent MMMC timing analysis and such as 7nm and below.
arithmetic, floating-point arithmetic, and
optimization
pipeline units. Simulation models are also
Architecture-Level PPA
• Native integration of all design for test included for all ChipWare components.
Optimization
(DFT) logic insertion
A new, proprietary algorithm identifies DFT
• Verilog 1995 and 2001, System Verilog
critical datapath regions in a design,
1800-2009, and VHDL 1987, 1993, and With the Genus Synthesis Solution, you
regardless of their physical or logical
2008 input formats get natively integrated full support for
module hierarchy. For each of these
design for test (DFT), including timing-
• Verilog netlist and DEF placement regions, the Genus Synthesis Solution
driven physically aware scan chain
output formats, Innovus database considers a number of possible
stitching and insertion of compression
output format also supported microarchitectures with different power,
logic, memory BIST, logic BIST, JTAG,
performance, and area (PPA) tradeoffs. It
• Multi-bit cell insertion to group registers on-product clock generation (OPCG), and
then builds and solves an analytical model
for power and area reduction power test access module (PTAM) logic.
over all datapath regions to achieve the
The Genus Synthesis Solution’s native
globally best PPA for the design. This
Massively Parallel Architecture integration of the Cadence Modus DFT
technology can reduce datapath area
Software Solution gives the only working
The Genus Synthesis Solution is built on by up to 20% without any impact on
solution for the routing congestion from
a new massively parallel architecture that performance. Deep datapath applications,
high scan compression ratios using 2D
performs distributed synthesis across such as machine learning processors,
Elastic Compression.
multiple machines and CPUs. It leverages benefit the most from this technology.
a proprietary, timing-driven partitioning Safety Critical and Automotive
algorithm that slices transparently across CPF and IEEE 1801 Support
design hierarchy and evenly distributes The Genus Synthesis Solution is part of
The Genus Synthesis Solution includes
the optimization effort across different the industry’s first comprehensive “Fit for
extensive capabilities to support complex
machines. All told, this architecture Purpose - Tool Confidence Level 1 (TCL1)”
multi-power domain designs. Power-
enables the solution to deliver up to 5X certification from TÜV SÜD, enabling
intentpecifications can be provided in
faster synthesis turnaround times with automotive semiconductor manufacturers,
either CPF or IEEE 1801 formats, with
linear scalability to well beyond 10 million OEMs, and component suppliers to meet
the solution performing full automatic
instances. stringent ISO 26262 automotive safety
insertion of level shifters, isolation cells,
requirements. To achieve certification,
and retention elements. Always-on
Physically Aware Context Cadence provided its tool and flow
buffering and power domain-aware
Generation documentation to TÜV SÜD for evaluation,
routing are also fully supported.
and TÜV SÜD confirmed the Cadence
A simple Tcl command at the end of a flows are fit for use with ASIL A through
chip- or block-level synthesis can be used Power Optimization
ASIL D automotive design projects.
to “clip” out the full timing and physical To reduce power consumption, the Cadence customers can easily access the
context for any subset of a design. These solution features a comprehensive tool and flow documentation and TÜV
clips can be used to drive unit-level RTL range of techniques, including timing SÜD technical reports via the Cadence
synthesis with full consideration of chip- and physically aware multi-bit flop Automotive Functional Safety Kits at
or block-level timing, floorplan, and mapping, hierarchical RTL clock gating, www.cadence.com/go/iso26262cert.
placement. By using these clips, you can and intelligent one-step use of multiple
experience a 2X or more reduction in threshold cell libraries during mapping and
unit-level iterations required to achieve optimization.
timing closure.

www.cadence.com 2
 Genus Synthesis Solution

Common UI for Ease of Use Cadence Services and Support

The Genus Synthesis Solution has • Cadence application engineers can
a common UI with the Innovus answer your technical questions by
Implementation System and the Tempus telephone, email, or Internet—they can
Timing Signoff Solution. The system also provide technical assistance and
simplifies command naming and align custom training.
common implementation methods across
• Cadence certified instructors teach
these Cadence digital and signoff tools.
more than 70 courses and bring
For example, the processes of design
their real-world experience into the
initialization, database access, command
classroom.
consistency, and metric collection have
all been streamlined and simplified. In • More than 25 Internet Learning
addition, updated and shared methods Series (iLS) online courses allow you
have been added to run, define, and the flexibility of training at your own
deploy reference flows. These updated computer via the Internet.
interfaces and reference flows increase
productivity by delivering a familiar • Cadence Online Support gives you
interface across core implementation and 24x7 online access to a knowledgebase
signoff products. You can take advantage of the latest solutions, technical
of consistently robust RTL-to-signoff documentation, software downloads,
reporting and management, as well as a and more.
customizable environment. • For more information, please visit
www.cadence.com/support for support
and www.cadence.com/training for
training.

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to create the innovative end products that are transforming the way people live, work, and play. The
company’s Intelligent System Design strategy helps customers develop differentiated products—from
chips to boards to intelligent systems. www.cadence.com
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