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Experiment 2

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saksham
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24 views3 pages

Experiment 2

Uploaded by

saksham
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Experiment – 2

Statement of objective: Design and implementation of Half Adder using


CMOS logic.

Tool: MULTISIM 11.0

Theory: Half adder is a combinational arithmetic circuit that adds two numbers
and produces a sum bit. (S) and carry bit (C) as the output. If A and B are the input
bits, then sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND
of A and B. From this it is clear that a half adder circuit can be easily constructed
using one X-OR gate and one AND gate.

Half adder is the simplest of all adder circuit, but it has a major disadvantage. The
half adder can add only two input bits (A and B) and has nothing to do with the
carry if there is any in the input. So, if the input to a half adder has a carry, then it
will be neglected it and adds only the A and B bits. That means the binary addition
process is not complete and that’s why it is called a half adder. The truth table,
schematic representation and XOR//AND realization of a half adder.

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Circuit diagram:
 For sum:

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 For Carry:

Result : Circuits of Half Adder for Sum and Carry are verified through its
Truth table.

Precautions:
 Choose the Right components for the circuit diagram.
 Connect the wire properly otherwise you will get error in result.

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