CHAPTER 1

INTRODUCTION
Reversible logic has applications in Nanotechnology, quantum computing, Low
power CMOS, Optical computing and DNA computing, etc., one of the important
applications of the reversible logic is quantum computation. Reversible circuits are
those circuits that do not lose information and reversible computation in a system can be
performed only when system comprises of reversible gates.
Most of the gates used in digital design are not reversible for example the AND,
OR and EXOR gates does not perform reversible operation. A reversible circuit/gate
can generate unique output vector from each input vector, and vice versa, that is there is
a one to one mapping between the input and output vectors. Therefore, of the commonly
used gates only the NOT gate is reversible.
Energy loss is an important consideration in digital design. Part of the problem
of energy dissipation is related to non ideality of switches and materials. A set of
reversible gates are needed to design reversible circuit. Several such gates are proposed
over the past decades. Reversible gates are the building blocks for reversible circuits,
having the following characteristics.
 A reversible gate has its input and output with a one to one correspondence.
That is the inputs of a reversible gate can be uniquely determined from its
outputs.
 A reversible logic gate must have an equal number of inputs and outputs.
 The fan out of every signal including primary inputs in a reversible gate must
be one.

 Classical logic synthesis methods cannot be directly applied to design

reversible logic circuit.

 One of the most important features of a reversible gate is its garbage output.
Every gate output that is not used as input to other gate or as a primary output
is called garbage output. Simply to say an unutilized output from a gate is
garbage.
 Each reversible gate has a cost associated with it called quantum cost. The
quantum cost of a reversible gate is the number of 2x2 reversible gates or
quantum logic gates required in designing it.
1
 CHAPTER 2
LITERATURE SURVEY
The simplest reversible gate is NOT gate and is a 1x1 gate. Controlled NOT
(CNOT) gate is an example for a 2x2 gate. There are many 3x3 reversible gates such as
Fredkin gate, Toffoli gate, Peres gate and TR gate. Each reversible gate has a cost
associated with it called quantum cost. The quantum cost of 1x1 reversible gates is zero,
and quantum cost of 2x2 reversible gates is one. Any reversible gate is realized by using
1x1 NOT gates and 2x2 reversible gates, such as V and V + (V is square root of NOT
gate and V+ is its hermitian) and Feynman gate which is also known as controlled NOT
gate (CNOT). The V and V+ quantum gates have the following property:
V x V = NOT
V x V+ = V+ x V = I V+ x V+ = NOT.
The quantum cost of a reversible gate can be calculated by counting the number
V, V+ and CNOT gates used in implementing it except in few cases.
2.1 NOT Gate
This is the only reversible gate among the conventional logic gates. This is a 1x1
gate with quantum cost of zero.

Fig.1 NOT gate.

2.2Feynman Gate (CNOT gate)
This is a 2x2 gate having mapping (A, B) to (P=A, Q=A B) where A, B are
inputs and P, Q are outputs respectively. Since it is 2x2 gate it has a quantum cost of
one.

Fig. 2 Feynman or CNOT gate

2.3Toffoli Gate
`This is a 3x3 reversible gate with two of its outputs are same as inputs with the
mapping (A, B, C) to (P=A, Q=B, R= A.B C). Where A, B, C are inputs and P, Q, R
outputs respectively. Toffoli gate is one of the most popular reversible gates and has
quantum cost of 5. It requires 2V gates, 1 V+ gate and 2 CNOT gates.

2
 Fig. 3 Toffoli gate
2.4Peres Gate
Peres gate is a three input and three output (3x3) reversible gate having the
mapping (A, B, C) to (P=A, C), where A, B, C are the
inputs and P, Q, R are the outputs, respectively. Peres gate has the quantum cost
of 4, since it requires 2 V+ gate, 1 V gate and 1 CNOT gate. Among 3x3 reversible
gates, this has the minimum quantum cost.

Fig. 4 Peres gate

2.5Fredkin Gate
Fredkin gate is a 3x3 conservative reversible gate. It maps (A, B, C) to (P=A,
Q= A' B+AC, R=AB+ A'C), where A, B, C are the inputs and P, Q, R are the outputs,
respectively. Fredkin gate can be implemented with a quantum cost of 5 and it requires
2 dotted rectangles, 1 V gate and 2 CNOT gates.

Fig .5 Fredkin gate

2.6TR Gate
TR gate has 3 inputs and 3 outputs having inputs and outputs mapping as (P = A,
Q=A B, R=(A . B') C), where A, B, C are the inputs and P, Q, R are the outputs,
respectively. TR gate may also be realized in a different implementation with quantum
cost of 6 or lesser than 6. Therefore it is considered that the quantum of TR gate as 6 for
the calculation of parallel Subtractor implementing by reversible gate.

3
 Fig. 6 TR gate

CHAPTER 3
SYSTEM DESIGN
Reversible circuit/gate can generate unique output vector from each input vector,
and vice versa, i.e., there is a one to one correspondence between the input and output
vectors. Thus, the number of outputs in a reversible gate or circuit has the same as the
number of inputs, and commonly used traditional NOT gate is the only reversible gate.
Each Reversible gate has a cost associated with it called Quantum cost. The Quantum
cost of a Reversible gate is the number of 2*2 Reversible gates or Quantum logic gates
required in designing. One of the most important features of a Reversible gate is its
garbage output i.e., every input of the gate, which is not used as input to other gate or as
a primary output is called garbage output.
3.1 Reversible Logic Gates
A reasonable computation is one that may be written in terms of some (possibly
large) Boolean expression, and any Boolean expression may be constructed out of a
fixed set of logic gates. Such a set (e.g., AND, OR and NOT) is called universal. In fact
we can get by with only two gates, such as AND and NOT or OR and NOT.
Alternatively, we may replace some of these primitive gates by others, such as the
exclusive-OR (called XOR); then AND and XOR form a universal set. Any machine,
which can build up arbitrary combinations of logic gates from a universal set is then a
universal computer. Which of the above gates is reversible? Since AND, OR, and XOR
are many-to-one operations, they are not logically reversible. Before we discuss how
these logic gates
Several reversible gates have been proposed over the years, e.g., the Toffoli
gate, the Fredkin gate etc. A 3-input and 3-output reversible logic gate was proposed
in. It has inputs a, b, c and outputs x, y and z as shown in Fig 7. The truth table of the
gate is shown in the Table 1. It can be verified from the truth table that the input pattern
corresponding to a particular output pattern can be uniquely determined. The gate can
be used to invert a signal and also to duplicate a signal. The signal duplication function
can be obtained by setting input b to 0. The EX-OR function is available at the output x
of the gate. The AND function is obtained by connecting the input c to 0, the output is
obtained at the terminal z. An OR gate is realized by connecting two new reversible
gates.
4
 Fig. 7 Reversible gate R
Table:3.1 Truth table for Reversible Gate R
a b c x y z
0 0 0 0 0 1
0 0 1 0 0 0
0 1 0 1 0 1
0 1 1 1 0 0
1 0 0 1 1 1
1 0 1 1 1 0
1 1 0 0 1 0
1 1 1 0 1 1

3.2 Reversible Adder/ Subtractor Design

3.2.1 Adder circuits

Several types of adders are used in computing systems. A ripple carry adder has
the simplest structure. In a ripple carry adder, full adders connected in series generate
the sum and the carry outputs based on the addend bits and the carry input. The
disadvantage of a ripple carry adder is that the carry has to propagate through all stages.
3.2.2 Ripple carry adders
The basic building block of a ripple carry adder is a full adder block. A full
adder computes the sum bit Si and the carry output c i+1 based on addend inputs a and
b and carry input c. The output expressions for a ripple carry adder are
(1) Si = a xor b xor c;
(2) Ci+1 = ab + bc + ca; (i = 0,1,2,….)
A Reversible circuit/gate can generate unique output vector from each input
vector, and vice versa, i.e., there is a one to one correspondence between the input and
output vectors. Thus, the number of outputs in a reversible gate or circuit has the same
as the number of inputs, and commonly used traditional NOT gate is the only reversible
gate. Each Reversible gate has a cost associated with it called Quantum cost. The
Quantum cost of a Reversible gate is the number of 2*2 Reversible gates or Quantum
logic gates required in designing.
One of the most important features of a Reversible gate is its garbage output i.e.,
every input of the gate which is not used as input to other gate or as a primary output is
5
called garbage output. Minimization of the number of Reversible gates, Quantum cost
and garbage inputs/outputs are the focus of research in Reversible logic.

CHAPTER 4

6
 EXISTING AND PROPOSED WORK

4.1 Proposed Reversible Adder / Subtractor unit

The design approach followed here mainly focuses on the reversible full adder
and subtractor together in a single unit. Three types of full adder/subtractor
implementations have discussed and the performance of each designs have been
compared in terms of the number of reversible gates used, number of garbage
inputs/outputs and the quantum cost. A four-bit parallel adder/subtractor is built using
the full adder/subtractor and half adder/subtractor units. Four-bit parallel subtractor is
designed using all the three types of adder/subtractor units.
Table:4.1 Truth Table for Full Adder/Subtractor
CTRL A B C Carry/ Sum /
Barrow Difference
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 1 1
0 0 1 1 1 0
0 1 0 0 0 1
0 1 0 1 0 0
0 1 1 0 0 0
0 1 1 1 1 1
1 0 0 0 0 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 1 1

4.2 Half Adder – Subtractor

Reversible half adder/subtractor logic is implemented with the four reversible
gates of which two are Fredkin and two are Feynman gates. The numbers of garbage
outputs are three, garbage inputs are two and quantum cost is twelve. This

7
implementation is as shown in figure15. This half adder/subtractor is used in
implementing four-bit parallel reversible adder/subtractor unit.

Fig:4.1 Logic implementation of reversible Half Adder/Subtractor

Table:4.2 Truth Table for Half Adder/Subtractor

CTRL A B Carry/ Sum /
Barrow Difference
0 0 0 0 0
0 0 1 1 1
0 1 0 0 1
0 1 1 0 0
1 0 0 0 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 0

4.3 Full Adder-Subtractor-Mux

This design is based on the utilization of appropriate reversible gates for each
function namely, Peres gate for adder function, TR gate for substractor function and
Fredkin gate for multiplexing the Carry and Borrow line into single line output. 3
Feynman gates are used for creating the necessary signal multiplication (buffering) of
each input signal. This design uses 8 reversible gates, 3 Feynman gates, 2 Peres gates, 2
TR gates and one Fredkin gate. As shown in the table 1 there are 7 garbage outputs5
garbage (constant) inputs and the total quantum cost is 28.
This implementation is as shown in fig. 5.2.

8
 Fig:4.2 Logic implementation of reversible Full Adder/ Subtractor- Mux

This logic is implemented using VHDL code and simulated using Modelsim
simulator. The individual gates functionality is implemented using Behavioral style of
modeling and the overall logic is implemented using structural style of modeling.
4.4 Full Adder-Subtractor-TR gate
In this design the main functionality of addition and substraction is realized by
using only TR gates. Feynman gates are used for input signal buffering. The design
utilizes 3 TR gates and 6 Feynman gates, in total 9 gates. The garbage output in this
design is 7 and the garbage inputs are 5. The quantum cost for the design is 24. Even
though one additional Feynman gate (C-NOT Gate) is used in this design, a quantum
cost advantage of 4 is obtained when compared to the Adder-Substractor-Mux design.
This quantum cost advantage is mainly due to the realization of arithmetic blocks of
adder and substractor is realized with 3 TR gates as against the 5 numbers of 3x3
reversible gates for Adder-Sustractor-Mux design. (Two Pearson gates, two TR gates
and one Fredkin gate). This implementation is as shown in fig.4.3.

Fig:4.3 Logic implementation of reversible Full Adder-Subtractor-TR gate

This logic is implemented using VHDL code and simulated using Modelsim
simulator. The individual gates functionality is implemented using Behavioral style of
modeling and the overall logic is implemented using structural style of modeling.

4.5 Full Adder-Subtractor- Hybrid

This is an optimized implementation of adder-substractor function. The
sum/difference output is realized in this case with two Feynman gates. To realize the
carry borrow line we utilized two Fredkin gates and a TR gate. This design, in total
utilizes 8 gates including the C-NOT gates for input signal multiplication. The garbage
output is 5 and garbage input in this design is 3. The quantum cost is 21. The

9
optimization in terms of the garbage input, garbage output and quantum cost in this case
is obtained due to optimal utilization of gates. The sum/difference function in this case
is realized with just two CNOT gates. Therefore it is essential to have a design approach
where, the required functionality may be realized with simplest gates as much as
possible. We could not realize the carry/borrow function with simple 2x2 gates
effectively. So, we utilized 3x3 gates for the realization. Many algorithms are available
in literature. To synthesize the reversible logics, one of the basic goals of these
algorithms is to realize the required function with simplest possible gates. This
implementation is as shown in fig.4.4.

Fig:4.4 Logic implementation of reversible Full Adder-Subtractor-Hybrid

This logic is implemented using VHDL code and simulated using Modelsim
simulator. The individual gates functionality is implemented using Behavioral style of
modeling and the overall logic is implemented using structural style of modeling.
4.6 Four-Bit reversible Parallel Adder/Subtractor unit
A four-bit reversible parallel adder/subtractor is built using the full
adder/subtractor and half adder/subtractor units. Four-bit parallel adder/subtractor is
designed using all the three types of adder/subtractor units. This implementation
requires three full adder/subtractor blocks and one half adder/subtractor blocks. These
implementation is been done using VHDL code and verified for its functionality.

10
Fig:4.5 Logic implementation of four-bit reversible Full Adder/Subtractor

11
 CHAPTER 5
XILINX SOFTWARE
Xilinx Tools is a suite of software tools used for the design of digital circuits
implemented using Xilinx Field Programmable Gate Array (FPGA) or Complex
Programmable Logic Device (CPLD). The design procedure consists of (a) design
entry, (b) synthesis and implementation of the design, (c) functional simulation and (d)
testing and verification. Digital designs can be entered in various ways using the above
CAD tools: using a schematic entry tool, using a hardware description language (HDL)
– Verilog or VHDL or a combination of both. In this lab we will only use the design
flow that involves the use of VerilogHDL.
The CAD tools enable you to design combinational and sequential circuits
starting with Verilog HDL design specifications. The steps of this design procedure are
listed below:
 Create Verilog design input file(s) using template driveneditor.
 Compile and implement the Verilog designfile(s).
 Create the test-vectors and simulate the design (functional simulation) without
using a PLD (FPGA orCPLD).
 Assign input/output pins to implement the design on a targetdevice.
 Download bitstream to an FPGA or CPLDdevice.
 Test design on FPGA/CPLDdevice
A Verilog input file in the Xilinx software environment consists of the following
segments:
 Header: module name, list of input and output ports.
 Declarations: input and output ports, registers and wires.
 Logic Descriptions: equations, state machines and logic functions.
 End: endmodule
All your designs for this lab must be specified in the above Verilog input format.
Note that the state diagram segment does not exist for combinational logic designs.

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1. Programmable Logic Device:FPGA
In this lab digital designs will be implemented in the Basys2 board which has a
Xilinx Spartan3E–XC3S250E FPGA with CP132 package. This FPGA part belongs to
the Spartan family of FPGAs. These devices come in a variety of packages. We will be
using devices that are packaged in 132 pin package with the following part number:
XC3S250E-CP132. This FPGA is a device with about 50K gates. Detailed information
on this device is available at the Xilinx website.
2. Creating a NewProject
Xilinx Tools can be started by clicking on the Project Navigator Icon on the
Windows desktop. This should open up the Project Navigator window on your screen.
This window shows (see Figure 1) the last accessed project.

13
 Figure::5.1 Xilinx Project Navigator window (snapshot from Xilinx ISE software)

3. Opening aproject
Select File->New Project to create a new project. This will bring up a new
project window (Figure 2) on the desktop. Fill up the necessary entries as follows:

14
 Figure:5.2 New Project Initiation window (snapshot from Xilinx ISE software)

ProjectName: Write the name of your newproject

Project Location: The directory where you want to store the new project (Note: DO
NOT specify the project location as a folder on Desktop or a folder in the Xilinx\bin
directory. Your H: drive is the best place to put it. The project location path is NOT to
have any spaces in it eg: C:\Nivash\TA\new lab\sample exercises\o_gate is NOT to be
used)
Leave the top level module type as HDL.
Example: If the project name were “o_gate”, enter “o_gate” as the project name and
then click “Next”.

Clicking on NEXT should bring up the following window:

15
Figure:5.3 Device and Design Flow of Project (snapshot from Xilinx ISE software)
For each of the properties given below, click on the ‘value’ area and select from the list
of values that appear.
 Device Family: Family of the FPGA/CPLD used. In this laboratory we will be
using the Spartan3EFPGA’s.
 Device: The number of the actual device. For this lab you may
enterXC3S250E (this can be found on the attached prototyping board)
 Package:Thetypeofpackagewiththenumberofpins.TheSpartanFPGAusedin this
lab is packaged in CP132package.
 Speed Grade: The Speed grade is“-4”.
 Synthesis Tool: XST[VHDL/Verilog]
 Simulator: The tool used to simulate and verify the functionality of the design.
Modelsim simulator is integrated in the Xilinx ISE. Hence choose “Modelsim-
XE Verilog” as the simulator or even Xilinx ISE Simulator can beused.
 Then click on NEXT to save theentries.
All project files such as schematics, netlists, Verilog files, VHDL files, etc., will
be stored in a subdirectory with the project name. A project can only have one top level

16
HDL source file (or schematic). Modules can be added to the project to create a
modular, hierarchical design (see Section 9).
In order to open an existing project in Xilinx Tools, select File->Open Project
to show the list of projects on the machine. Choose the project you want and click OK.
Clicking on NEXT on the above window brings up the following window:

Figure:5.4 Create New source window (snapshot from Xilinx ISE software)
If creating a new source file, Click on the NEW SOURCE.
4. Creating a Verilog HDL input file for a combinational logicdesign
In this lab we will enter a design using a structural or RTL description using the
Verilog HDL. You can create a Verilog HDL input file (.v file) using the HDL Editor
available in the Xilinx ISE Tools (or any text editor).
In the previous window, click on the NEW SOURCE
A window pops up as shown in Figure 4. (Note: “Add to project” option is
selected by default. If you do not select it then you will have to add the new source file
to the project manually.)

17
 Figure:5.5 Creating Verilog-HDL source file (snapshot from Xilinx ISE software)

Select Verilog Module and in the “File Name:” area, enter the name of the Verilog
source file you are going to create. Also make sure that the option Add to project is
selected so that the source need not be added to the project again. Then click on Next to
accept the entries. This pops up the following window (Figure 5).

Figure:5.6 Define Verilog Source window (snapshot from Xilinx ISE software)

In the Port Name column, enter the names of all input and output pins and

18
specify the Direction accordingly. A Vector/Bus can be defined by entering appropriate
bit numbers in the MSB/LSB columns. Then click on Next> to get a window showing
all the new source information (Figure 6). If any changes are to be made, just click on
<Back to go back and make changes. If everything is acceptable, click on Finish > Next
> Next > Finish tocontinue.

Figure:5.7 New Project Information window(snapshot from Xilinx ISE software)

Once you click on Finish, the source file will be displayed in the sources
window in the Project Navigator (Figure 1).
If a source has to be removed, just right click on the source file in the Sources in
Project window in the Project Navigator and select Removein that. Then select
Project -> Delete Implementation Data from the Project Navigator menu bar to
remove any relatedfiles.
5.Editing the Verilog sourcefile
The source file will now be displayed in the Project Navigator window (Figure
8). The source file window can be used as a text editor to make any necessary changes
to the source file. All

19
 The input/output pins will be displayed. Save your Verilog program periodically
by selecting the File->Save from the menu. You can also edit Verilog programs in any
text editor and add them to the project directory using “Add Copy Source”.

Figure:5.8 Verilog Source code editor window in the Project Navigator (from Xilinx
ISE software)
6.Adding Logic in the generated Verilog Source codetemplate:
A brief Verilog Tutorial is available in Appendix-A. Hence, the language syntax
and construction of logic equations can be referred to Appendix-A.
The Verilog source code template generated shows the module name, the list of
ports and also the declarations (input/output) for each port. Combinational logic code
can be added to the verilog code after the declarations and before the endmodule line.
For example, an output z in an OR gate with inputs a and b can be described as,
assign z = a | b;
Remember that the names are case sensitive.

20
7. Other constructs for modeling the logicfunction:
A given logic function can be modeled in many ways in verilog. Here is
another example in which the logic function, is implemented as a truth table using a
case statement:
moduleor_gate(a,b,z); input a;
input b; output z;
reg z;

always @(a or b) begin

case ({a,b}) 00: z =1'b0;
01: z =1'b1;
10: z =1'b1;
11: z =1'b1;
endcase
end
endmodule
Suppose we want to describe an OR gate. It can be done using the logic equation
as shown in Figure 9a or using the case statement (describing the truth table) as shown
in Figure 9b. These are just two example constructs to design a logic function. Verilog
offers numerous such constructs to efficiently model designs. A brief tutorial of Verilog
is available in Appendix-A.

Figure:5.9 OR gate description using assign statement (snapshot from Xilinx ISE

21
software)

22
Figure:5.10 OR gate description using case statement (from Xilinx ISE software)
8. Synthesis and Implementation of theDesign
The design has to be synthesized and implemented before it can be checked for
correctness, by running functional simulation or downloaded onto the prototyping
board. With the top-level Verilog file opened (can be done by double-clicking that file)
in the HDL editor window in the right half of the Project Navigator, and the view of the
project being in the Module view , the implement design option can be seen in the
process view. Design entry utilities and Generate Programming File options can also be
seen in the process view. The former can be used to include user constraints, if any and
the latter will be discussed later.
To synthesize the design, double click on the Synthesize Design option in the
Processes window.

23
 To implement the design, double click the Implement design option in the
Processes window. It will go through steps like Translate, Map and Place & Route. If
any of these steps could not be done or done with errors, it will place a X mark in front
of that, otherwise a tick mark will be placed after each of them to indicate the successful
completion. If everything is done successfully, a tick mark will be placed before the
Implement Design option. If thereare warnings, one can see mark in front of the
option indicating that there are some warnings. One can look at the warnings or errors
in the Console window present at the bottom of the Navigator window. Every time the
design file is saved; all these marks disappear asking for a freshcompilation.

Figure:5.11 Implementing the Design (snapshot from Xilinx ISE software)

The schematic diagram of the synthesized verilog code can be viewed by double
clicking View RTL Schematic under Synthesize-XST menu in the Process Window.
This would be a handy way to debug the code if the output is not meeting our
specifications in the proto type board.

By double clicking it opens the top level module showing only input(s) and
24
output(s) as shown below.

Figure5.12 Top Level Hierarchy of the design

By double clicking the rectangle, it opens the realized internal logic as shown below.

Figure:5.13 Realized logic by the XilinxISE for the verilog code

9.Functional Simulation of Combinational Designs

25
Adding the testvectors
To check the functionality of a design, we have to apply test vectors and
simulate the circuit. In order to apply test vectors, a test bench file is written. Essentially
it will supply all the inputs to the module designed and will check the outputs of the
module. Example: For the 2 input OR Gate, the steps to generate the test bench is as
follows:
In the Sources window (top left corner) right click on the file that you want to
generate the test bench for and select ‘New Source’
Provide a name for the test bench in the file name text box and select ‘Verilog
test fixture’ among the file types in the list on the right side as shown in figure 11.

Figure :5.14 Adding test vectors to the design (snapshot from Xilinx ISE software)

Click on ‘Next’ to proceed. In the next window select the source file with which
you want to associate the test bench.
26
 Figure:5.15 Associating a module to a testbench (snapshot from Xilinx ISE software)

Click on Next to proceed. In the next window click on Finish. You will now be
provided with a template for your test bench. If it does not open automatically click the
radio button next to Simulation .

You should now be able to view your test bench template. The code generated
would be something like this:
moduleo_gate_tb_v;
// Inputs reg a;
reg b;
// Outputs wire z;
// Instantiate the Unit Under Test (UUT) o_gateuut (
.a(a),
27
 .b(b),
.z(z)
);
initialbegin
// Initialize Inputs a = 0;
b =0;
// Wait 100 ns for global reset tofinish #100;
// Add stimulus here
end
endmodule
The Xilinx tool detects the inputs and outputs of the module that you are going
to test an assigns them initial values. In order to test the gate completely we shall
provide all the different input combinations. ‘#100’ is the time delay for which the input
has to maintain the current value. After 100 units of time have elapsed the next set of
values can be assign to the inputs.
Complete the test bench as shown below:
moduleo_gate_tb_v;
// Inputs reg a; regb;
// Outputs wire z;
// Instantiate the Unit Under Test (UUT) o_gateuut (
.a(a),
.b(b),
.z(z)
);
initialbegin
// Initialize Inputs a = 0;
b =0;
// Wait 100 ns for global reset to finish #100;
a = 0;
b =1;
// Wait 100 ns for global reset tofinish #100;
a = 1;
b =0;

28
 // Wait 100 ns for global reset tofinish #100;
a = 1;
b =1;
// Wait 100 ns for global reset tofinish #100;
end
endmodule
Save your test bench file using the File menu.

5.1 Sample Code

29
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE'
VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3
WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>PATHEXT</td>
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<
br>.WSF;<br>.WSH;<br>.MSC</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>Path</td>
<td>C:\Xilinx\14.5\ISE_DS\ISE\\lib\nt64;<br>C:\Xilinx\14.5\ISE_DS\ISE\\bin\nt64;<b
r>C:\Xilinx\14.5\ISE_DS\ISE\bin\nt64;<br>C:\Xilinx\14.5\ISE_DS\ISE\lib\nt64;<br>C
:\Xilinx\14.5\ISE_DS\ISE\..\..\..\DocNav;<br>C:\Xilinx\14.5\ISE_DS\PlanAhead\bin;<
br>C:\Xilinx\14.5\ISE_DS\EDK\bin\nt64;<br>C:\Xilinx\14.5\ISE_DS\EDK\lib\nt64;<b
r>C:\Xilinx\14.5\ISE_DS\EDK\gnu\microblaze\nt64\bin;<br>C:\Xilinx\14.5\ISE_DS\E
DK\gnu\powerpc- Apps</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
30
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX</td>
<td>C:\Xilinx\14.5\ISE_DS\ISE\</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>C:\Xilinx\14.5\ISE_DS\ISE</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>C:\Xilinx\14.5\ISE_DS\EDK</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>C:\Xilinx\14.5\ISE_DS\PlanAhead</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3
31
WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>Full_Adder_Full_sub.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ifmt</td>
<td>&nbsp;</td>
<td>mixed</td>
<td>MIXED</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>Full_Adder_Full_sub</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
32
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s500e-4-fg320</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>Full_Adder_Full_sub</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>SPEED</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
33
<td>NO</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>as_optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>NO</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100%</td>
</tr>
<tr>
<td>-verilog2001</td>
<td>Verilog 2001</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_encoding</td>
34
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
35
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>100000</td>
<td>500</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>24</td>
<td>24</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
36
<td>NO</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0%</td>
</tr>
</TABLE>
<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3
WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information
</B></TD>
<td>OS Name</td>
<td>Microsoft , 64-bit</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>OS Release</td>
<td>major release (build 9200)</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
</TABLE>
</BODY> </HTML>

CHAPTER 6
37
 RESULT AND DISCUSSION

Implementations of three types of reversible full adder/subtractor are coded in

VHDL and simulated using ModelSim simulator. The functionality is verified. A
comparison of the implementations based on the number of gates used, number of
garbage inputs/outputs and quantum cost of the logics is as shown in the Table IV.
Reversible four-bit parallel adder/subtractor implementations in all the three
types are verified. A structural model coding is used to build four-bit parallel
adder/subtractor with three full adder/subtractor and one half adder/subtractor blocks.
The functionality is verified. A comparison of the implementations based on the number
of gates used, number of garbage inputs/outputs and quantum cost of the logics.

Fig:6.1 Full adder using TR GATE

38
 Fig:6.2 Full adder delay using TR gate

Fig:6.3 Full adder and substractor using TR,fredkin,pg gate

39
Fig:6.4 Delay of full adder and substractor using TR,PG,Fredkin gate

Fig;6.5 Reversible adder and substractor

40
 Fig: 6.6 Full adder with any reversible gate output wave form

Table :6.1 Truth Table For Half Adder/Subtractor

No. of Garba ge No. of

No. of reversibl output Garbag e Quantu m cost
e gates s inputs
ADD_SUB_M 8 6 5 28
UX
ADD_SUB_TR 9 7 5 24
ADD_SUB_HY 8 5 3 21
B

Table:6.2 Truth Table For Half Adder/Subtractor

No. of Garba No. of Garbag e

No. of ge output inputs Quantu
reversibl e s m cost
gates
ADD_SUB_MUX 28 21 17 96
_4
41
 ADD_SUB_TR_4 31 24 17 84
ADD_SUB_HYB_ 28 18 11 75
4

Comparison of Optimization Results of reversible Full Adder/Subtractor design

with Conventional Ripple carry adder, carry look ahead adder, carry skip adder
manchhester carry adder with respect to area, timing and power is shown in Table VI.

42
Table:6.3 Truth Table for Adder/Subtractor Circuits

IOs Timing Power

Used Details Summary
RIPPLE CARRY 14 12.791ns 25mW
CONVENTION ADDER
CARRY LOOK 50 24.376ns 25mW
A L ADDER
AHEAD
ADDER
CARRY SKIP 37 20.956ns 25mW
ADDER
MANCHESTER CARRY ADDER 14 12.791ns 7mW
REVERSIBLE FULL ADD/SUB 6 7.937ns 7mW

CONCLUSION

43
 Successfully designed three types of reversible full adder/subtractor unit and
compared their performance in terms of number of gates used, garbage inputs/outputs
and quantum cost. Many algorithms are available in literature to realize the reversible
logic; one of the basic goals of these algorithms is to realize the required function with
the simplest possible reversible gates. Out my three designs full adder-subtractor-hybrid
implementation is optimized as it utilizes appropriate gates to realize the required
functions of the unit. Also four-bit reversible parallel adder/subtractor is implemented
and performance in terms of number of gates used, garbage inputs/outputs and quantum
cost are compared

REFERENCES
44
[1].V.Kamalakannan, Dr P.V.Rao, Veeresh Patil ,“Analysis of Reversible Binary
Adder/Subtractor Circuit”, International Journal of Advanced and Innovative
Research, ISSN: 2278-7844,Volume 1, Issue 4, pp 129-134.
[2].R.landauer,”Irreversibility and heat generation in the computational Process",
IBM Research and Development, pp. 183-191, 1961.
[3].C.H Bennett “Logical Reversibility of computations” IBM J. Research and
development, pp 525-532, November-1973.
[4].Pallav Gupta, Abhinav Agarwal, and Niraj K.Jha “An Algorithm for Synthesis
of Reversible Logic Circuits”, IEEE transactions on computer Aided Design of
Integrated circuits and Systems, vol.25, 2006.
[5].J.W. Bruce, M.A.Thornton, L. Shivakumaraiah, P.S. Karate and
X.Li,”Efficient Adder Circuits Based on a Conservative Logic Gate”,
[6].Procu.of the IEEE computer Society Annual Symposium on VLSI, pp.83-88,
2002.
[7].D.Maslov and G. W. Dueck, “Reversible Cascades with Minimal Garbage”,
IEEE Trans on CAD, pp.1497-1509, 2004.
[8].M.S Islam, M.M.Rehman, Z.Begam, M.Z.Hafiz “Low Cost Quantum
Realization of Reversible Multiplier Circuit” Information Technology Journal
8(2), pp-208-213, 2009.
[9].V.Verdal A. Bareno and A Ekert, “Quantum Network for Elementary Arithmetic
Operations”arXiv: quant-ph/9511018v1, nov-1995.

45