A Mini-Project Report

On

IMPLEMENTATION OF FULL ADDER/SUBTRACTOR

USING FREDKIN AND FEYNMAN GATE

Submitted for partial fulfillment of the requirements for the award of the degree

of

MASTER OF TECHNOLOGY
IN

VLSI SYSTEM DESIGN

BY

Ms.R.SRAVANTHI (20641D5715)

Under the Guidance of

Mrs. V. SABITHA

Associate Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

VAAGDEVI COLLEGE OF ENGINEERING

(Autonomous, Affiliated to JNTUH, NAAC ‘A’ Grade and NBA Accredited)

BOLLIKUNTA, WARANGAL - 506 005

2020-2021
 VAAGDEVI COLLEGE OF ENGINEERING
(Autonomous, Affiliated to JNTUH, NAAC ‘A’ Grade and NBA Accredited)

BOLLIKUNTA, WARANGAL - 506 005

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

CERTIFICATE
This is to certify that the mini-project work entitled “IMPLEMENTATION OF
FULL ADDER/SUBTRACTOR USING FREDKIN AND FEYNMAN GATE” is a
bonafide work carried out by Ms.R.SRAVANTHI (20641D5715) in partial fulfillment
of the requirements for the award of degree of Master of Technology in VLSI System
Design from Vaagdevi College of Engineering, (Autonomous) during the academic year
2020-2021.

Y.SOUJANYA Dr. M. SHASHIDHAR

VLSI System Design Head of the Department

Project Guide

Mrs.V.SABITHA

Associate Professor
 DECLARATION

I declare that the work reported in the mini-project entitled

“IMPLEMENTATION OF FULL ADDER/SUBTRACTOR USING FREDKIN
AND FEYNMAN GATE” is a record of work done by us in the partial fulfillment for
the award of the degree of Master of Technology in VLSI System Design VAAGDEVI
COLLEGE OF ENGINEERING (Autonomous), Affiliated to JNTUH, Accredited
By NAAC, under the guidance of Mrs.V.Sabitha,Associate professor, ECE Department,
I/We hereby declare that this mini-project work bears no resemblance to any other
project submitted at Vaagdevi College of Engineering or any other university/college
for the award of the degree.

Ms.R.SRAVANTHI (20641D5715)
 ACKNOWLEDGEMENT

The development of the project though it was an arduous task, it has been made
by the help of many people. We are pleased to express our thanks to the people whose
suggestions, comments, criticisms greatly encouraged us in betterment of the project.

I would like to express my sincere gratitude and indebtedness to my project

Guide Mrs. V.SABITHA, Associate Professor, for her valuable suggestions and
interest throughout the course of this project.

We would like to express my sincere thanks and profound gratitude to

Dr. K. PRAKASH, Principal of Vaagdevi College of Engineering, for his support,
guidance and encouragement in the course of our project.

We are also thankful to the Head of the Department Dr. M. SHASHIDHAR,

Associate Professor for providing excellent infrastructure and a nice atmosphere for
completing this project successfully.

We are highly thankful to the Project Coordinators fortheir valuable

suggestions, encouragement and motivations for completing this project successfully.

I am thankful to all other faculty members for their encouragement

I convey my heartfelt thanks to the lab staff for allowing me to use the required
equipment whenever needed.

Finally, I would like to take this opportunity to thank my family for their
support through the work. I sincerely acknowledge and thank all those who gave
directly or indirectly their support in completion of this work.

Ms.R.SRAVANTHI (20641D5715)
 TABLE OF CONTENTS
PAGE NOS.
ABSTRACT i
LIST OF FIGURES ii
LIST OF TABLES iii
LIST OF ACRONYMS iv
CHAPTER 1
INTRODUCTION 1
CHAPTER 2
LITERATURE SURVEY 2
2.1 NOT Gate 2
2.2 Feynman Gate (CNOT gate) 2
2.3 Toffoli Gate 2
2.4 Peres Gate 3
2.5 Fredkin Gate 3
2.6 TR Gate 3
CHAPTER 3
SYSTEM DESIGN 4
3.1 Reversible Logic Gates 4
3.2 Reversible Adder/ Subtractor Design 5
3.2.1 Adder circuits 5
3.2.2 Ripple carry adders 5
CHAPTER 4
EXISTING AND PROPOSED WORK 7
4.1 Proposed Reversible Adder / Subtractor unit 7
4.2 Half Adder – Subtractor 8
4.3 Full Adder-Subtractor-Mux 8
4.4 Full Adder-Subtractor-TR gate 9
4.5 Full Adder-Subtractor- Hybrid 10
4.6 Four-Bit reversible Parallel Adder/Subtractor unit 10
CHAPTER 5
XILINX SOFTWARE 12
5.1 Sample Code 28
CHAPTER 6
RESULT AND DISCUSSION 36
CONCLUSION 41
REFERENCES 42
 ABSTRACT

The widely using CMOS technology implementing with irreversible logic will hit a
scaling limit beyond 2020 and the major limiting factor is increased power dissipation. Their
reversible logic is replaced by reversible logic to decrease the power dissipation. The main
motivation behind the study of this technology is aimed at implementing reversible
computing to improve the energy efficiency of computers. The devices implemented with
reversible logic gates will have demand for the upcoming future computing technologies as
they consumes less power. Reversible logic has applications in Low Power VLSI, Quantum
Computing, Nanotechnology and Optical computing. This project proposes the design of a
optimal fault tolerant Full adder/ Full Subtractor. The method require less complexity, less
hardware, minimum number of gates, minimum number of garbage inputs and minimum
number of constant inputs.

i
 LIST OF FIGURES
Fig.No. Figure Name Page No.

Fig:4.1 Logic implementation of reversible Half Adder/Subtractor 8

Fig:4.2 Logic implementation of reversible Full Adder/ Subtractor- Mux 9
Fig:4.3 Logic implementation of reversible Full Adder-Subtractor-TR gate 9
Fig:4.4 Logic implementation of reversible Full Adder-Subtractor-Hybrid 10
Fig:4.5 Logic implementation of four-bit reversible Full Adder/Subtractor 11
Fig:5.1 Xilinx Project Navigator window 13
Fig:5.2 New Project Initiation window 14
Fig:5.3 Device and Design Flow of Project 15
Fig:5.4 Create New source window 16
Fig:5.5 Creating Verilog-HDL source file 17
Fig:5.6 Define Verilog Source window 17
Fig:5.7 New Project Information window 18
Fig:5.8 Verilog Source code editor window in the Project Navigator 19
Fig:5.9 OR gate description using assign statement 20
Fig:5.10 OR gate description using case statement 21
Fig:5.11 Implementing the Design 22
Fig:5.12 Top Level Hierarchy of the design 23
Fig:5.13 Realized logic by the XilinxISE for the verilog code 23
Fig:5.14 Adding test vectors to the design 24
Fig:5.15 Associating a module to a testbench 25
Fig:6.1 Full adder using TR GATE 36
Fig:6.2 Full adder delay using TR gate 36
Fig:6.3 Full adder and substractor using TR,fredkin,pg gate 37
Fig;6.5 Reversible adder and substractor 38
Fig: 6.6 Full adder with any reversible gate output wave form 38

ii
 LIST OF TABLES

Table No. Table Name Page No.

Table:3.1 Truth table for Reversible Gate R 5
Table:4.1 Truth Table for Full Adder/Subtractor 7
Table:4.2 Truth Table for Half Adder/Subtractor 8
Table :6.1 Truth Table For Half Adder/Subtractor 39
Table:6.2 Truth Table For Half Adder/Subtractor 39
Table:6.3 Truth Table for Adder/Subtractor Circuits 40

iii
 LIST OF ACRONYMS

S.NO ACRONYM FULL FORM

1 MOSFET Metal-Oxide Semiconductor Field Effect Transistor

2 VLSI Very Large Scale Integration
3 ALU Arithmetic Logic Unit
4 CNOT Controlled NOT gate
5. CMOS Complementary Metal-Oxide Semiconductor
6. QMUX Quantum Multiplexers
7 QDe-MUX Quantum Demultiplexers
8 ASICs Application Specific Integrated Circuits
9. QC Quantum Cost
10 DSP Digital Signal Processing
11 FPGA Field Programmable Gate Arrays
12. CPLD Complex Programmable Logic Device
13. VHDL Verilog Hardware Description Language
14 Xilinx ISE Xilinx Integrated Synthesis Environment
15 RTL Register Transfer Level

iv