m
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The mA733M is obsolete



 
 

 

and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

D 200-MHz Bandwidth D Selectable Nominal Amplification of 10,

D 250-kΩ Input Resistance 100, or 400
D No Frequency Compensation Required

mA733C . . . D, N, OR NS PACKAGE mA733M . . . U PACKAGE

mA733M . . . J PACKAGE (TOP VIEW)
(TOP VIEW)

IN+ 1 10 IN −
IN+ 1 14 IN−
GAIN ADJ 2A 2 9 GAIN ADJ 2B
NC 2 13 NC
GAIN ADJ 1A 3 8 GAIN ADJ 1B
GAIN ADJ 2A 3 12 GAIN ADJ 2B
VCC − 4 7 VCC+
GAIN ADJ 1A 4 11 GAIN ADJ 1B
OUT+ 5 6 OUT−
VCC− 5 10 VCC+
NC 6 9 NC
OUT+ 7 8 OUT−

NC  No internal connection

description/ordering information
The µA733 is a monolithic two-stage video amplifier with differential inputs and differential outputs. Internal
series-shunt feedback provides wide bandwidth, low phase distortion, and excellent gain stability.
Emitter-follower outputs enable the device to drive capacitive loads, and all stages are current-source biased
to obtain high common-mode and supply-voltage rejection ratios.
Fixed differential amplification of 10 V/ V, 100 V/ V, or 400 V/ V may be selected without external components,
or amplification may be adjusted from 10 V/ V to 400 V/ V by the use of a single external resistor connected
between 1A and 1B. No external frequency-compensating components are required for any gain option.
The device is particularly useful in magnetic-tape or disc-file systems using phase or NRZ encoding and in
high-speed thin-film or plated-wire memories. Other applications include general-purpose video and pulse
amplifiers where wide bandwidth, low phase shift, and excellent gain stability are required.
The µA733C is characterized for operation from 0°C to 70°C; the µA733M is characterized for operation over
the full military temperature range of −55°C to 125°C.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
P-DIP (N) Tube of 25 UA733CN UA733CN
Tube of 50 UA733CD
0°C to 70°C SOIC (D) UA733C
Reel of 2500 UA733CDR
SOP (NS) Reel of 2000 UA733CNSR UA733
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

  

     !"# $% Copyright  2004, Texas Instruments Incorporated
$   ! ! &   ' 
$$ ()% $ !* $  #) #$
*  ## !%

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1

m
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 The mA733M is obsolete
and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

symbol
GAIN ADJ 1A
GAIN ADJ 2A

IN + + OUT+

_
IN − OUT−

GAIN ADJ 1B
GAIN ADJ 2B

schematic
VCC+

2.4 kΩ 2.4 kΩ 10 kΩ 1.1 kΩ 1.1 kΩ

OUT+
IN + IN − 7 kΩ

1A 1B 7 kΩ
GAIN 50 Ω GAIN OUT −
ADJ 50 Ω ADJ
2A 2B

590 Ω 590 Ω

300 Ω 1.4 kΩ 300 Ω 400 Ω 400 Ω

VCC −

Component values shown are nominal.

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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The mA733M is obsolete


 
 

 

and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
mA733C mA733M UNIT
Supply voltage VCC+ (see Note 1) 8 8 V
Supply voltage VCC− (see Note 1) −8 −8 V
Differential input voltage ±5 ±5 V
Common-mode input voltage ±6 ±6 V
Output current 10 10 mA
Continuous total power dissipation See Dissipation Rating Table
D package 86
Package thermal impedance, qJA (see Notes 2 and 3) N package 80 °C/W
C/W
NS package 76
Maximum junction temperature, TJ 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 60 seconds J or U package 300 °C
Storage temperature range, Tstg − 65 to 150 − 65 to 150 °C
† Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the recommended operating conditions section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential input voltages, are with respect to the midpoint between VCC+ and VCC–.
2. Maximum power dissipation is a function of TJ(max), qJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) – TA)/qJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

DISSIPATION RATING TABLE

TA ≤ 25°C DERATING DERATE TA = 70°C TA = 125°C
PACKAGE
POWER RATING FACTOR ABOVE TA POWER RATING POWER RATING
J (µA733M) 500 mW 11.0 mW/°C 104°C 500 mW 269 mW

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3

m
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 The mA733M is obsolete
and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

electrical characteristics, VCC± = ±6 V, TA = 25°C

GAIN mA733C mA733M
PARAMETER FIGURE TEST CONDITIONS UNIT
OPTION† MIN TYP MAX MIN TYP MAX
Large-signal 1 250 400 600 300 400 500
differential
AVD 1 VOD = 1 V 2 80 100 120 90 100 110 V/ V
voltage
amplification 3 8 10 12 9 10 11
1 50 50
BW Bandwidth 2 RS = 50 Ω 2 90 90 MHz
3 200 200
Input offset
IIO Any 0.4 5 0.4 3 µA
current
IIB Input bias current Any 9 30 9 20 µA
Common-mode
VICR input voltage 1 Any ±1 ±1 V
range
Common-mode
VOC 1 Any 2.4 2.9 3.4 2.4 2.9 3.4 V
output voltage
Output offset 1 0.6 1.5 0.6 1.5
VOO 1 V
voltage 2&3 0.35 1.5 0.35 1
Maximum peak-
VOPP to-peak output 1 Any 3 4.7 3 4.7 V
voltage swing
1 4 4
ri Input resistance 3 VOD ≤ 1 V 2 10 24 20 24 kΩ
3 250 250
ro Output resistance 20 20 Ω
Ci Input capacitance 3 VOD ≤ 1 V 2 2 2 pF
VIC = ±1 V,
2 60 86 60 86
Common-mode f ≤ 100 kHz
CMRR 4 dB
rejection ration VIC = ±1 V,
2 70 70
f = 5 MHz
Supply voltage
kSVR rejection ratio 1 ∆VCC± = ±0.5 V 2 50 70 50 70 dB
(∆VCC/(∆VIO)
Broadband
Vn equivalent input 5 BW = 1 kHz to 10 MHz Any 12 12 µV
noise voltage

RS = 50 Ω, 1 7.5 7.5
Propagation
tpd 2 Output voltage 2 6.0 10 6.0 10 ns
delay time
step = 1 V 3 3.6 3.6

RS = 50 Ω, 1 10.5 10.5
tr Rise time 2 Output voltage 2 4.5 12 4.5 10 ns
step = 1 V 3 2.5 2.5
Maximum output
Isink(max) Any 2.5 3.6 2.5 3.6 mA
sink current
No load,
ICC Supply current Any 16 24 16 24 mA
No signal
† The gain option is selected as follows:
Gain Option 1: Gain-adjust pin 1A is connected to pin 1B, and pins 2A and 2B are open.
Gain Option 2: Gain-adjust pin 1A and pin 1B are open, pin 2A is connected to pin 2B.
Gain Option 3: All four gain-adjust pins are open.

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 m
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The mA733M is obsolete


 
 

 

and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

electrical characteristics, VCC± = ±6 V, TA = 0°C to 70°C for mA733C, − 55°C to 125°C for mA733M
GAIN mA733C mA733M
PARAMETER FIGURE TEST CONDITIONS UNIT
OPTION† MIN MAX MIN MAX
1 250 600 200 600
Large-signal differential
AVD 1 VOD = 1 V 2 80 120 80 120 V/ V
voltage amplification
3 8 12 8 12
IIO Input offset current Any 6 5 µA
IIB Input bias current Any 40 40 µA
Common-mode input
VICR 1 Any ±1 ±1 V
voltage range
1 1.5 1.5
VOO Output offset voltage 1 V
2&3 1.5 1.2
Maximum peak-to-peak
VOPP 1 Any 2.8 2.5 V
output voltage swing
ri Input resistance 3 VOD ≤ 1 V 2 8 8 kΩ
Common-mode rejection VIC = +1 V,
CMRR 4 2 50 50 dB
ratio f ≤ 100 kHz
Supply voltage rejection
kSVR 1 ∆VCC± = ± 0.5 V 2 50 50 dB
ratio (∆VCC /(∆VIO)
Maximum output sink
Isink(max) Any 2.5 2.2 mA
current
No load,
ICC Supply current Any 27 27 mA
No signal
† The gain option is selected as follows:
Gain Option 1: Gain-adjust pin 1A is connected to pin 1B, and pins 2A and 2B are open.
Gain Option 2: Gain-adjust pin 1A and pin 1B are open, pin 2A is connected to pin 2B.
Gain Option 3: All four gain-adjust pins are open.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5

m
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 The mA733M is obsolete
and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION

test circuits

0.2 µF
+ +
VID VOD 2 kΩ VID 0.2 µF
− −

50 Ω 50 Ω 50 Ω 50 Ω 1 kΩ 1 kΩ

Figure 1 Figure 2

0.2 µF
50 Ω
+
+
VOD 2 kΩ 50 Ω 0.2 µF
−
−
VIC
1 kΩ 1 kΩ

Figure 3 Figure 4

2B 1B

0.2 µF

+
0.2 µF
+ −
VOD 2 kΩ
−
50 Ω 50 Ω 1 kΩ 1 kΩ
Radj

2A 1A

VOLTAGE AMPLIFICATION ADJUSTMENT

Figure 5 Figure 6

6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 m
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and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

TYPICAL CHARACTERISTICS

PHASE SHIFT
PHASE SHIFT
vs
vs
FREQUENCY
FREQUENCY
5
50
VCC ± = ± 6 V
VCC ± = ± 6 V
TA = 25°C 0 TA = 25°C
0
− 50
GAIN 2
Phase Shift − Degrees

Phase Shift − Degrees

−100
−5
−150
GAIN 2
−200
−10
−250

−300
−15
−350

−400
−20
0 1 2 3 4 5 6 7 8 9 10 −450
1 4 10 40 100 400
f − Frequency − MHz
f − Frequency − MHz

Figure 7 Figure 8

VOLTAGE AMPLIFICATION
VOLTAGE AMPLIFICATION
(SINGLE-ENDED OR DIFFERENTIAL)
(SINGLE-ENDED OR DIFFERENTIAL)
vs
vs
TEMPERATURE
SUPPLY VOLTAGE
Voltage Amplification Relative to Value at VCC +_ = +_ 6 V
Voltage Amplification Relative to Value at TA = 25o C

1.2
1.4
VCC ± = ± 6 V TA = 25°C
GAIN 1
1.2
1.1
mA733C

1.0 GAIN 3
GAIN 2 GAIN 3
1.0

GAIN 2 0.8
GAIN 3 GAIN 2

0.9
0.6
GAIN 1
GAIN 1
0.8
−75 − 50 − 25 0 25 50 75 100 125 0.4
3 4 5 6 7 8
TA − Free-Air Temperature − °C
|VCC±| − Supply Voltage − V

Figure 9 Figure 10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7

m
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 The mA733M is obsolete
and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

TYPICAL CHARACTERISTICS

DIFFERENTIAL VOLTAGE AMPLIFICATION SINGLE-ENDED VOLTAGE AMPLIFICATION

vs vs
RESISTANCE BETWEEN G1A AND G1B FREQUENCY
1000 50

AVS − Single-ended Voltage Amplification − dB

700 VCC ± = ± 6 V GAIN 1
VOD = 1 V
AVD − Differential Voltage Amplification

400 TA = 25°C 40
See Figure 6
GAIN 2
200
30

100
70
20
GAIN 3
40

10
20 VCC ± = ± 6 V
TA = 25°C

10 0
10 40 100 400 1k 4k 10 k 1 4 10 40 100 400
Radj − Resistance Between G1A and G1B − Ω f − Frequency − MHz

Figure 11 Figure 12

SUPPLY CURRENT
SUPPLY CURRENT
vs
vs
FREE-AIR TEMPERATURE
SUPPLY VOLTAGE
20
24
No Load
18
No Signal
16 20 TA = 25°C
I CC − Supply Current − mA

I CC − Supply Current − mA

14
mA733C 16
12

10
12
8

6 8

4 VCC ± = ± 6 V
No Load 4
2 No Signal

0
−75 − 50 − 25 0 25 50 75 100 125 0
3 4 5 6 7 8
TA − Free-Air Temperature − °C
|VCC±| − Supply Voltage − V

Figure 13 Figure 14

8 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 m
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The mA733M is obsolete


 
 

 

and no longer supplied.
SLFS027B − NOVEMBER 1970 − REVISED MAY 2004

TYPICAL CHARACTERISTICS

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE

vs vs
LOAD RESISTANCE SUPPLY VOLTAGE
VOPP − Maximum Peak-to-Peak Output Voltage − V

VOPP − Maximum Peak-to-Peak Output Voltage − V

5
VCC ± = ± 6 V TA = 25°C
TA = 25°C 7
4
6

5
3

2
3

2
1
1

0 0
10 40 100 400 1k 4k 10 k 3 4 5 6 7 8
RL − Load Resistance − Ω |VCC±| − Supply Voltage − V

Figure 15 Figure 16

MAXIMUM PEAK-TO-PEAK OUTPUT VOLTAGE INPUT RESISTANCE

vs vs
FREQUENCY FREE-AIR TEMPERATURE
6
VOPP − Maximum Peak-to-Peak Output Voltage − V

40
VCC ± = ± 6 V
TA = 25°C VCC ± = ± 6 V
35
5

30
r i − Input Resistance − kΩ

4
25
GAIN 2
3
20
mA733C
2 15

10
1
5

0
1 2 4 7 10 20 40 70 100 200 400 0
− 60 − 40 −20 0 20 40 60 80 100 120 140
f − Frequency − MHz
TA − Free-Air Temperature − °C

Figure 17 Figure 18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9

 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

UA733CD ACTIVE SOIC D 14 50 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UA733C

& no Sb/Br)
UA733CDR ACTIVE SOIC D 14 2500 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UA733C
& no Sb/Br)
UA733CN ACTIVE PDIP N 14 25 Green (RoHS NIPDAU N / A for Pkg Type 0 to 70 UA733CN
& no Sb/Br)
UA733CNSR ACTIVE SO NS 14 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM 0 to 70 UA733
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UA733CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UA733CNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UA733CDR SOIC D 14 2500 367.0 367.0 38.0
UA733CNSR SO NS 14 2000 367.0 367.0 38.0

Pack Materials-Page 2
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