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Digital instantaneous frequency measurement technique utilising high-speed
ADC’s and FPGA’s
Article · January 2006
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A Digital Instantaneous Frequency
Measurement Technique Utilising
High-Speed ADC’s and FPGA’s
2006 CSIR Research and Innovation Conference
CSIR Defence, Peace, Safety and Security
Dr PL Herselman
Visiting Researcher at the University College London
27 February 2006
 Electronic Warfare

Image courtesy of Altera, www.altera.com

Slide 2 © CSIR 2006 www.csir.co.za

 Signal Intelligence (SIGINT)
• Complex battlefield
multiple RF emitters
• Receiver analyses intercepted waveforms
• Situational awareness
• Queuing of defensive/evasive action(s)
• Compact packaging for operational systems
• Employed on a range of systems
• Airborne Warning and Control System (AWACS)

Image courtesy of Rockwell Collins

Image courtesy of NATO, www.nato.int

Image courtesy of
Northrop Grumman
Movie courtesy of Macom

Slide 3 © CSIR 2006 www.csir.co.za

 Agenda

• Background • Example Implementation

DIFM research as part of CSIR Shared aperture DIFM on
Defence, Peace, Safety and SWIFT500 DRFM system
Security R&D strategy
• Simulation Results
• IFM Theory Bit-true functional simulations for
Overview of basic theory a range of input signals

• Optimal Time Delay • Experimental Verification

Led to DIFM invention Results of a prototype system

• DIFM Basics • Conclusions

Digital implementation of IFM
using innovative parallel DSP
techniques

Slide 4 © CSIR 2006 www.csir.co.za

Background
 Digital Radio Frequency Memory (DRFM)
Research and Development at the CSIR
• Active R&D field since 1999

• Advanced and highly configurable repeater

• Analog to digital converter
memory
digital to analog converter
• Information bandwidth limited to half the sampling rate

• Utilised in a range of applications

• Field (electronic countermeasures)
• Obscure the platform (e.g aircraft)
• Deceive the hostile radar
• Laboratory (test equipment)
• Coherently simulate the signals emitted by electronic
countermeasures and the signals reflected from targets

Slide 6 © CSIR 2006 www.csir.co.za

 Digital Radio Frequency Memory (DRFM)
Research and Development at the CSIR
• Levels of development
Digital DRFM Module
DRFM Kernel
DRFM-based simulator system

Slide 7 © CSIR 2006 www.csir.co.za

 Need for Frequency Measurement
in DRFM-Based Systems
• Pulse qualification
Deceive and obscure only hostile systems

• Frequency dependant techniques Estimate

Accurate Doppler response required in
RF bandwidth is a scarce resource less than a
Maximise ECM effectiveness microsecond
• Compensate DRFM-induced phase
perturbations
Poster presentation

Slide 8 © CSIR 2006 www.csir.co.za

 Frequency Measurement Solutions

• Instantaneous Frequency
Measurement (IFM)
• Analog technique
• Combined with analog-to-digital Preferred frequency
converter
DFD
• Multiple parallel IFM’s estimation technique
• Single output
• Dual aperture
• Discrete Fourier Transform
(DFT)
• Measures spectral response
• Aliased to [0,fs/2) frequency
range
• Multiple input signals Table taken
Graph
fromcourtesy
Schleherof(1986)
Altera
• Multiple outputs

Slide 9 © CSIR 2006 www.csir.co.za

Instantaneous Frequency
Measurement Theory
 Instantaneous Frequency Measurement
Digital Frequency Discriminator
Analog Mixer Digital
c0*arccos[c1*yfilt(tn)]
Input Output
R I yfilt(tn) f0(tn)
L
Low-pass
3 dB Filter ADC
Coupler Analog Lookup Table
Delay line

A02
• Multiply signal with delayed replica ymix (t ) = [cos(2πf 0τ ) + cos(4πf 0t − 2πf 0τ )]
8
A02
• Low-pass filter y filt (t ) ≈ H (0 ) cos(2πf 0τ ) , H (2 f 0 ) << H (0 )
8

• Inverse cosine operation 1  8 y filt (t ) 

• f0 ≈ arccos 2 
 A0 H (0) 
Typically preceded with ADC
• Lookup table 2πτ
• Digital Frequency Discriminator (DFD)

Slide 11 © CSIR 2006 www.csir.co.za

Optimal Time Delay
 Delay Line Calculation

• One-to-one mapping: Input frequency
output value

• Maximum one-to-one input frequency calculated as

arccos(− 1) = (1 + 2n )π =
1 1 1
τ= , n=0
2πf 0(max ) 2πf 0(max ) 2 f 0(max )
• Inverse of twice the maximum input frequency

• IFM with frequency range equal to ADC IBW

• Unambiguous input frequency range [0,fs/2) chosen
1 1 1
τ= = = = ts
2 f 0(max )  f  fs
2 s 
2
• Optimal time delay = one ADC sampling period
Slide 13 © CSIR 2006 www.csir.co.za
Digital Instantaneous Frequency
Measurement Basics
 Steps 1&2: Sampling, Quantisation and
Multiplication
• Sampling and quantisation
  f 
yq (n ) = Q[ y (nt s )] = Q  A0 cos 2π 0 n  = Q[A0 cos(2πF0 n )] , F0 = 0
f
  f s  fs
2A  A
= round  0 2 N −1 cos(2πF0 n ) = 0 2 N cos(2πF0 n ) + ε q (n )
 D  D

• Multiplication with time-delayed replica

ymix (n ) = yq (n )yq (n − 1)
A02 2 N −1
= 22 [cos(2πF0 ) + cos(4πF0 n − 2πF0 )]
D
+ 0 2 N {cos(2πF0 n )ε q (n − 1) + cos[2πF0 (n − 1)]ε q (n )}+ ε q (n )ε q (n − 1)
A
D

Slide 15 © CSIR 2006 www.csir.co.za

 Step 3: Low-Pass Filtering

• Finite Impulse Response (FIR) digital filter

N
y filt (n ) = ∑ ck ymix (n − k )
k =0

A02 2 N −1
= 22 [ H LPF (0) cos(2πF0 ) + H LPF (F0′) cos(2πF0′n − 2πF0 + ∠H LPF (F0′))]+ ε q′ (n)
D

where

fs
F0′ = 2 F0 , f0 ≤
4
fs
F0′ = 1 − 2 F0 , f 0 >
4

Slide 16 © CSIR 2006 www.csir.co.za

 Step 3: Low-Pass Filtering

• Interactive filter design tools (e.g. MATLAB FDATool)

Slide 17 © CSIR 2006 www.csir.co.za

 Step 4: Inverse Cosine Operation

• Digital inverse cosine estimation

• Cordic algorithm
• Lookup table
• Output of low-pass filter is used as the input to a lookup table
• Lookup table output estimates frequency of the input signal

2 N out − 1  y filt (n )D 2 
yout (n ) = 
arccos 2 2 N −1 
2π 
 A0 2 H LPF (0 ) 

Slide 18 © CSIR 2006 www.csir.co.za

 Digital Instantaneous Frequency
Measurement
• Advantages • Issues
Mixing product relatively linear FPGA clock speeds > 100 MHz
yielding lower spurious response
DIFM up to 50 MHz bandwidth
Filter response can be optimised with serial processing
for the specific requirements, i.e.
fast response versus Exhibit the same amplitude
measurement accuracy sensitivity as an analog IFM

Slide 19 © CSIR 2006 www.csir.co.za

 Parallel Processing DIFM

• High-speed flash converter ADC’s

• > 10 bits
• > 2 GSPS

• Techniques often employed include time-domain

demultiplexing, i.e. wider bus, lower data rate
• ASIC or commercial demultiplexers
• For 1.2 GSPS 10-bit ADC
• 16x demulitplex
• 75 MSPS 160-bit

• Calculate in a single FPGA clock cycle

• 15 multiplications
• 14th order FIR filter

• Possible to artificially extend the bus width

Slide 20 © CSIR 2006 www.csir.co.za

 Amplitude Insensitive DIFM
• Suppose an estimate of the input amplitude was available
y filt (n ) y filt (n ) y filt (n )
ydiv (n ) = = ≈ , A0 >> ε a (n )
A2 (n ) [A0 + ε a (n )]2 A02
ε q′ (n )
4 2 N −1
≈ 22 [ H LPF (0) cos(2πF0 ) + H LPF (F0 ) cos(2πF0 n − 2πF0 + ∠H LPF (F0 ))]+ 2
′ ′ ′
D A0

• Technique analogous to DIFM with time delay equal to 0

• Multiply y′mix (n ) = yq (n )yq (n − 0) = yq (n )yq (n ) = y q2 (n )

• Low-pass
A02 2 N −1
y′filt (n ) = 2 2 [ H LPF (0) + H LPF (F0′) cos(2πF0′n + ∠H LPF (F0′))]+ ε q′′(n)
D

Slide 21 © CSIR 2006 www.csir.co.za

 Amplitude Insensitive DIFM
• Divide basic DIFM filter output with amplitude estimation
H LPF (F0′)
ydiv (n ) ≈ cos(2πF0 ) + cos(2πF0′n − 2πF0 + ∠H LPF (F0′)) + ε q′′′(n )
H LPF (0)
≈ cos(2πF0 )

• Inverse cosine lookup table yield frequency estimation

ylt (n ) ≈ 2πF0 = 2π
f0
fs

• Advantages
• Amplitude estimation exactly aligned with frequency estimation
• No external calibration or alignment required
• Time-domain multiplex hardware

Slide 22 © CSIR 2006 www.csir.co.za

Example Implementation
 SWIFT500 Digital DRFM Module with
Built-In Amplitude Insensitive DIFM
• 1.2 GSPS , 500 MHz IBW
• 16x demultiplexing
• Stratix 1S30 with 96 9x9 multipliers

Slide 24 © CSIR 2006 www.csir.co.za

 SWIFT500 Digital DRFM Module with
Built-In Amplitude Insensitive DIFM
y'q(n-40) y24mm ya
UnitDelay24
MuxMult24 UnitDelay25
UnitDelay18 Adder
y'q(n-33)
UnitDelay17 0 1 0 1
y'q(n-32)
UnitDelay16 DeMux1 DeMux2
y'q(n-31)

y'q(n-25)
Select Select
UnitDelay15 ydm1 ydm2
UnitDelay25 Inverse

Delay8
Unit
Lookup

y'q(n-24)
UnitDelay26 Table
y'q(n-18)
UnitDelay2
y'q(n-17)
UnitDelay1
y'q(n-16)
UnitDelay0 Multiply
y'q(n-15)
yq(n-15) InputCast15
ym
y2mm
Arccos
MuxMult1 Lookup
y'q(n-2) Table
yq(n-2) InputCast2 y1mm
y'q(n-1)
yq(n-1) InputCast1 MuxMult0 yout
y'q(n)
yq(n) InputCast0

14 22 38 57 81 109 138 168 196 221 240 252 255 252 240 221 196 168 138 109 81 57 38 22 14
c0 c1 c2 c3 c4 c5 c6 c7 c8 c9 c10 c11 c12 c13 c14 c15 c16 c17 c18 c19 c20 c21 c22 c23 c24
Flip-Flop

y'q(n-#-16)

y'q(n-#-1) 0
Mux#B
1
Select
Multiply
#A Multiply
Y#mm(m+d1)
0
#B
Mux#A
y'q(n-#) 1
Select

Coeff In #

Select In

Slide 25 © CSIR 2006 www.csir.co.za

 SWIFT500 Digital DRFM Module with
Built-In Amplitude Insensitive DIFM
• Key specifications
• 9-bit multiplication
• 24th order low-pass FIR filter with Chebyshev windowing
• Cut-off frequency of 100 MHz and 48 dB side-lobe suppression
• Frequency response 50 MHz to 550 MHz
• Time-multiplexed resources to estimate amplitude and frequency
• Division implemented in a two-step process
• Inversion of denominator using lookup table (12-bit x 12-bit)
• Multiplication of numerator with inversed denominator
• 12-bit by 10-bit inverse cosine lookup table

Slide 26 © CSIR 2006 www.csir.co.za

Simulation Results
 Monochromatic Input Signal With Additive
Coloured Noise

Slide 28 © CSIR 2006 www.csir.co.za

 Analysis of DIFM Accuracy

Slide 29 © CSIR 2006 www.csir.co.za

 Key Performance Specifications
• High signal-to-noise ratios
• Mean deviation less than ± 2 MHz
• Absolute error less than 6 MHz across bandwidth
• Absolute error less than 2 MHz in > 300 MHz bandwidth
• RMS error less than 3 MHz across bandwidth
• RMS error less than 1 MHz in > 300 MHz bandwidth

• Low signal-to-noise ratios

• Bias in frequency estimation
• Due to bias in amplitude estimation
• Reduced by implementing higher order FIR filter (longer latency)

• Latency (processing time)

• 13 FGPA clock cycles (173.33 ns)

• Throughput rate
• 2 FGPA clock cycles (37.5 MHz)

Slide 30 © CSIR 2006 www.csir.co.za

Experimental Verification
 Quantitative Laboratory Experiments

Slide 32 © CSIR 2006 www.csir.co.za

Conclusions
View publication stats

Conclusions

• Viable, shared aperture, frequency estimation technique

• Implemented efficiently in current commercial hardware
• Results comparable to existing analog techniques
• Flexibility and ability to be optimised for the specific
requirements
• Real-time changing the filter coefficients
• Insensitive to temperature
• Does not require periodic calibration to maintain accuracy
• Operationally superior to its analog counterparts

• South African provisional patent application 2006/00946,

2006-02-01

Slide 34 © CSIR 2006 www.csir.co.za