MTD20P06HDL

Preferred Device

Power MOSFET
20 Amps, 60 Volts, Logic
Level
P−Channel DPAK
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This Power MOSFET is designed to withstand high energy in the
avalanche and commutation modes. The energy efficient design also
offers a drain−to−source diode with a fast recovery time. Designed for 20 AMPERES, 60 VOLTS
low−voltage, high−speed switching applications in power supplies,
RDS(on) = 175 mW
converters and PWM motor controls, and other inductive loads. The
avalanche energy capability is specified to eliminate the guesswork in
designs where inductive loads are switched, and to offer additional P−Channel
safety margin against unexpected voltage transients.
D
Features
• Ultra Low RDS(on), High−Cell Density, HDTMOS
• Diode is Characterized for Use in Bridge Circuits
G
• IDSS and VDS(on) Specified at Elevated Temperature
• Avalanche Energy Specified
S
• Pb−Free Package is Available
MAXIMUM RATINGS (TC = 25°C unless otherwise noted) MARKING DIAGRAM & PIN ASSIGNMENTS
Rating Symbol Value Unit
Gate 1
Drain−Source Voltage VDSS 60 Vdc 4
YWW
Drain−Gate Voltage (RGS = 1.0 MW) VDGR 60 Vdc 4
Drain 2 20P
1 2 Drain
Gate−Source Voltage 06HLG
3
− Continuous VGS "15 Vdc DPAK Source 3
− Non−Repetitive (tpv10 ms) VGSM "20 Vpk CASE 369C
(Surface Mount)
Drain Current
− Continuous ID 15 Adc STYLE 2
− Continuous @ 100°C ID 9.0
− Single Pulse (tpv10 ms) IDM 45 Apk
20P06HL = Device Code
Total Power Dissipation PD 72 W Y = Year
Derate above 25°C 0.58 W/°C WW = Work Week
Total Power Dissipation @ TC = 25°C (Note 2) 1.75 W G = Pb−Free Package
Operating and Storage Temperature Range TJ, Tstg −55 to °C
150 ORDERING INFORMATION
Single Pulse Drain−to−Source Avalanche EAS 300 mJ
Energy − Starting TJ = 25°C Device Package Shipping †
(VDD = 25 Vdc, VGS = 5.0 Vdc,
IL = 15 Apk, L = 2.7 mH, RG = 25 W) MTD20P06HDL DPAK 75 Units/Rail

Thermal Resistance °C/W MTD20P06HDLT4 DPAK 2500 Tape & Reel

− Junction−to−Case RqJC 1.73
− Junction−to−Ambient (Note 1) RqJA 100 MTD20P06HDLT4G DPAK 2500 Tape & Reel
− Junction−to−Ambient (Note 2) RqJA 71.4 (Pb−Free)
Maximum Lead Temperature for Soldering TL 260 °C †For information on tape and reel specifications,
Purposes, 1/8″ from case for 10 seconds including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Stresses exceeding Maximum Ratings may damage the device. Maximum Brochure, BRD8011/D.
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the Preferred devices are recommended choices for future use
Recommended Operating Conditions may affect device reliability. and best overall value.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
2. When surface mounted to an FR4 board using 0.5 sq. inch pad size.

© Semiconductor Components Industries, LLC, 2006 1 Publication Order Number:

June, 2006 − Rev. 6 MTD20P06HDL/D
 MTD20P06HDL

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 mAdc) 60 − −
Temperature Coefficient (Positive) − 81.3 − mV/°C

Zero Gate Voltage Drain Current IDSS mAdc

(VDS = 60 Vdc, VGS = 0 Vdc) − − 1.0
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C) − − 10
Gate−Body Leakage Current (VGS = ±15 Vdc, VDS = 0) IGSS − − 100 nAdc
ON CHARACTERISTICS (Note 3)
Gate Threshold Voltage VGS(th) Vdc
(VDS = VGS, ID = 250 mAdc) 1.0 1.7 2.0
Temperature Coefficient (Negative) − 3.9 − mV/°C

Static Drain−Source On−Resistance RDS(on) − 143 175 mW

(VGS = 5.0 Vdc, ID = 7.5 Adc)

Drain−Source On−Voltage (VGS = 5.0 Vdc) VDS(on) Vdc

(ID = 15 Adc) − 2.3 3.0
(ID = 7.5 Adc, TJ = 125°C) − 1.6 2.0
Forward Transconductance (VDS = 10 Vdc, ID = 7.5 Adc) gFS 9.0 11 − mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss − 850 1190 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Coss − 210 290
Reverse Transfer Capacitance Crss − 66 130
SWITCHING CHARACTERISTICS (Note 4)
Turn−On Delay Time td(on) − 19 38 ns
Rise Time (VDS = 30 Vdc, ID = 15 Adc, tr − 175 350
Turn−Off Delay Time VGS = 5.0 Vdc,RG = 9.1 W) td(off) − 41 82
Fall Time tf − 68 136
Gate Charge QT − 20.6 29 nC

(VDS = 48 Vdc, ID = 15 Adc, Q1 − 3.7 −

VGS = 5.0 Vdc) Q2 − 7.6 −
Q3 − 8.4 −
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage VSD Vdc
(IS = 15 Adc, VGS = 0 Vdc)
− 2.5 3.0
(IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C)
− 1.9 −
Reverse Recovery Time trr − 64 − ns

(IS = 15 Adc, VGS = 0 Vdc, ta − 50 −

dIS/dt = 100 A/ms) tb − 14 −
Reverse Recovery Stored Charge QRR − 0.177 − mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance LD − 4.5 − nH
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance LS − 7.5 − nH
(Measured from the source lead 0.25″ from package to source bond pad)
3. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
4. Switching characteristics are independent of operating junction temperature.

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 MTD20P06HDL

TYPICAL ELECTRICAL CHARACTERISTICS

30 30
TJ = 25°C VGS = 10 V 9V VDS ≥ 5 V
8V
25 25

I D , DRAIN CURRENT (AMPS)

TJ = −55°C 25°C
I D , DRAIN CURRENT (AMPS)

20 7V 20
100°C
15 15
6V

10 10
5V
5 5
4V

0 0
0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

RDS(on) , DRAIN−TO−SOURCE RESISTANCE (OHMS)

0.40 0.275
VGS = 5 V TJ = 25°C
0.250
0.32
0.225

0.24 0.200
TJ = 100°C
25°C 0.175
0.16
VGS = 5 V
−55°C 0.150
0.08
0.125 10 V

0 0.100
0 5 10 15 20 25 30 0 5 10 15 20 25 30
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Drain Current Figure 4. On−Resistance versus Drain Current
and Temperature and Gate Voltage
R DS(on) , DRAIN−TO−SOURCE RESISTANCE

1.8 100
VGS = 5 V VGS = 0 V
1.6 ID = 7.5 A
1.4
I DSS, LEAKAGE (nA)
(NORMALIZED)

1.2
TJ = 125°C
1
10 100°C
0.8

0.6

0.4
0.2
0 1
−50 −25 0 25 50 75 100 125 150 0 10 20 30 40 50 60
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−To−Source Leakage

Temperature Current versus Voltage

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 MTD20P06HDL

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when
controlled. The lengths of various switching intervals (Dt) calculating td(on) and is read at a voltage corresponding to the
are determined by how fast the FET input capacitance can on−state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
t = Q/IG(AV) complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching
tf = Q2 x RG/VGSP performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
where maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize
RG = the gate drive resistance common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the
During the turn−on and turn−off delay times, gate current is data in the figure is taken with a resistive load, which
not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power
values from the capacitance curves in a standard equation for MOSFETs may be safely operated into an inductive load;
voltage change in an RC network. The equations are: however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

2500
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
2000
C, CAPACITANCE (pF)

1500

Crss
1000 Ciss

500
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (Volts)

Figure 7. Capacitance Variation

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 MTD20P06HDL

6 1000
VGS, GATE−TO−SOURCE VOLTAGE (VOLTS) 50

VDS , DRAIN−TO−SOURCE VOLTAGE (VOLTS)

QT VDD = 30 V
45 ID = 15 A
5
40 VGS = 5.0 V
TJ = 25°C tr
4 35 100
tf
VDS VGS 30

t, TIME (ns)
3 25 td(off)
Q1 Q2 20 td(on)
ID = 15 A
2 TJ = 25°C 10
15
10
1 Q3
5
0 0 1
0 4 8 12 16 20 24 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode high di/dts. The diode’s negative di/dt during ta is directly
are very important in systems using it as a freewheeling or controlled by the device clearing the stored charge.
commutating diode. Of particular interest are the reverse However, the positive di/dt during tb is an uncontrollable
recovery characteristics which play a major role in diode characteristic and is usually the culprit that induces
determining switching losses, radiated noise, EMI and RFI. current ringing. Therefore, when comparing diodes, the
System switching losses are largely due to the nature of ratio of tb/ta serves as a good indicator of recovery
the body diode itself. The body diode is a minority carrier abruptness and thus gives a comparative estimate of
device, therefore it has a finite reverse recovery time, trr, due probable noise generated. A ratio of 1 is considered ideal and
to the storage of minority carrier charge, QRR, as shown in values less than 0.5 are considered snappy.
the typical reverse recovery wave form of Figure 12. It is this Compared to ON Semiconductor standard cell density
stored charge that, when cleared from the diode, passes low voltage MOSFETs, high cell density MOSFET diodes
through a potential and defines an energy loss. Obviously, are faster (shorter trr), have less stored charge and a softer
repeatedly forcing the diode through reverse recovery reverse recovery characteristic. The softness advantage of
further increases switching losses. Therefore, one would the high cell density diode means they can be forced through
like a diode with short trr and low QRR specifications to reverse recovery at a higher di/dt than a standard cell
minimize these losses. MOSFET diode without increasing the current ringing or the
The abruptness of diode reverse recovery effects the noise generated. In addition, power dissipation incurred
amount of radiated noise, voltage spikes, and current from switching the diode will be less due to the shorter
ringing. The mechanisms at work are finite irremovable recovery time and lower switching losses.
circuit parasitic inductances and capacitances acted upon by

15
VGS = 0 V
TJ = 25°C
IS , SOURCE CURRENT (AMPS)

12

0
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
VSD, SOURCE−TO−DRAIN VOLTAGE (Volts)
Figure 10. Diode Forward Voltage versus Current

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 MTD20P06HDL

di/dt = 300 A/ms Standard Cell Density

trr
High Cell Density
trr

I S , SOURCE CURRENT
tb
ta

t, TIME

Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain−to−source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and must be adjusted for operating
forward biased. Curves are based upon maximum peak conditions differing from those specified. Although industry
junction temperature and a case temperature (TC) of 25°C. practice is to rate in terms of energy, avalanche energy
Peak repetitive pulsed power limits are determined by using capability is not a constant. The energy rating decreases
the thermal response data in conjunction with the procedures non−linearly with an increase of peak current in avalanche
discussed in AN569, “Transient Thermal Resistance − and peak junction temperature.
General Data and Its Use.” Although many E−FETs can withstand the stress of
Switching between the off−state and the on−state may drain−to−source avalanche at currents up to rated pulsed
traverse any load line provided neither rated peak current current (IDM), the energy rating is specified at rated
(IDM) nor rated voltage (VDSS) is exceeded, and that the continuous current (ID), in accordance with industry
transition time (tr, tf) does not exceed 10 ms. In addition the custom. The energy rating must be derated for temperature
total power averaged over a complete switching cycle must as shown in the accompanying graph (Figure 13). Maximum
not exceed (TJ(MAX) − TC)/(RqJC). energy at currents below rated continuous ID can safely be
A power MOSFET designated E−FET can be safely used assumed to equal the values indicated.
in switching circuits with unclamped inductive loads. For

100 300
EAS, SINGLE PULSE DRAIN−TO−SOURCE

VGS = 20 V
ID = 15 A
SINGLE PULSE
TC = 25°C
AVALANCHE ENERGY (mJ)

240
I D , DRAIN CURRENT (AMPS)

10 100 ms
180
1 ms
10 ms
120
1.0 dc

RDS(on) LIMIT 60
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 12. Maximum Rated Forward Biased Figure 13. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

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 MTD20P06HDL

TYPICAL ELECTRICAL CHARACTERISTICS

r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5

0.2
(NORMALIZED)

0.1
P(pk)
0.1 0.05 RqJC(t) = r(t) RqJC
0.02 D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01 t1 READ TIME AT t1
t2 TJ(pk) − TC = P(pk) RqJC(t)
SINGLE PULSE DUTY CYCLE, D = t1/t2

0.01
1.0E−05 1.0E−04 1.0E−03 1.0E−02 1.0E−01 1.0E+00 1.0E+01
t, TIME (s)

Figure 14. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 15. Diode Reverse Recovery Waveform

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 MTD20P06HDL

PACKAGE DIMENSIONS

DPAK
CASE 369C−01
ISSUE O
NOTES:
−T− SEATING
PLANE 1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
B C 2. CONTROLLING DIMENSION: INCH.

INCHES MILLIMETERS
V R E
DIM MIN MAX MIN MAX
A 0.235 0.245 5.97 6.22
B 0.250 0.265 6.35 6.73
4 C 0.086 0.094 2.19 2.38
Z D 0.027 0.035 0.69 0.88
A E 0.018 0.023 0.46 0.58
S F 0.037 0.045 0.94 1.14
1 2 3
G 0.180 BSC 4.58 BSC
U H 0.034 0.040 0.87 1.01
K J 0.018 0.023 0.46 0.58
K 0.102 0.114 2.60 2.89
L 0.090 BSC 2.29 BSC
F J R 0.180 0.215 4.57 5.45
L H
S 0.025 0.040 0.63 1.01
U 0.020 −−− 0.51 −−−
V 0.035 0.050 0.89 1.27
D 2 PL Z 0.155 −−− 3.93 −−−
G 0.13 (0.005) M T STYLE 2:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN

SOLDERING FOOTPRINT*

6.20 3.0
0.244 0.118
2.58
0.101

5.80 1.6 6.172

0.228 0.063 0.243

SCALE 3:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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