http://dx.doi.org/10.5755/j01.eee.22.1.14110 ELEKTRONIKA IR ELEKTROTECHNIKA, ISSN 1392-1215, VOL. 22, NO.

1, 2016

Serial-Parallel IGBT Connection Method Based

on Overvoltage Measurement
Lubos Streit1,2, Dusan Janik1,2, Jakub Talla1
1
Regional Innovation Centre for Electrical Engineering, University of West Bohemia,
Univerzitni 8, Pilsen 306 14, Czech Republic
2
Department of Electromechanics and Power Electronics, University of West Bohemia,
Univerzitni 8, Pilsen 306 14, Czech Republic
[email protected]

1Abstract—This paper deals with a novel method which The derating (oversizing) is the most commonly used
allows the serial connection of Insulated Gate Bipolar method for parallel connecting of IGBTs. This method is
Transistors (IGBTs). The different dynamic characteristics of supplemented by symmetric output wires and selecting
serially connected IGBTs during turn ON and OFF cause a
IGBTs with characteristics as similar to each other as
short-term overvoltage stress in the transistors. In contrary to
the commonly used techniques, the presented method reduces possible. Symmetric output wires of IGBTs mean a special
additional commutation losses by actively correcting turn ON mechanical arrangement, which ensures uniform current
and OFF delays. The presented method uses overvoltages as distribution in parallel conductors (conductors of the same
measured by a peak detector. The correction circuit doesn’t length and shape). A positive temperature coefficient of
require a high speed Analog-Digital converter (ADC) or high IGBTs also contributes to correct current distribution. A
speed computation.
more detailed description of the parallel connection is
The target power switch unit consists of two serial connected
transistors with two identical parallel branches. The well-
described in [2]. Examples of IGBT behaviours during turn
known 2-level inverter topology equipped with the power ON and OFF are described in [3].
switch unit can be connected directly to the high-voltage grid. Connecting IGBTs serially is more difficult than
This converter topology was demanded by our industry connecting them parallely. A fast turn ON of the first
partner for 11 MW mining machines. The paper contains a transistor leads to the second one suffering an overvoltage
laboratory experiment conducted on a serial-parallel IGBT stress. This could cause a rapid destruction of stressed
power switch unit with a tested output power of 1 kW.
transistors. To ensure correct switching, there are several
Index Terms—Power semiconductor switches, insulated methods that compensate for the different dynamic
gate bipolar transistors, driver circuits, digital signal behaviour of IGBTs. The presented principle is based on the
processors, field programmable gate arrays. active compensation of different turn ON and turn OFF
times of serially connected IGBTs.
I. INTRODUCTION A combination of different methods is usually used in
Actual voltage, along with the physical limits of the serially connected IGBTs. The presented method is
current of semiconductor power switches, lead to serial and complementary to other IGBT voltage balancing methods:
parallel connection of power components or whole power RC or RCD (Resistor, Capacitor, Diode) snubber [4]–[6],
converters in high power applications (e.g. STATCOM [1], active clamping [7], [8] and is analogous to the presented
HVAC and HVDC). This paper describes a possible variant one in [9]. These methods allow the function of the serially
of the implementation of the serial-parallel IGBT switch. It connected IGBTs but with an increase in commutation
is a power unit with two parallel transistors connected in losses. The presented method compensates for different
series to the other two parallel transistors (see Fig. 1). delays of serially connected IGBTs and thus enables a
reduction of losses in other balance circuits. The power
converter efficiency can also be additionally increased by
using the soft-switching methods described in [10].

II. PRINCIPLE OF OVERVOLTAGE DETECTION AND IGBT

DELAY COMPENSATION
The principle of the presented balancing method involves
Fig. 1. Serial-Parallel IGBT switch. measuring the overvoltage caused by different turn ON and
turn OFF times of serially connected IGBTs. A block
Manuscript received 9 January, 2015; accepted 13 April, 2015. diagram of the prototype is shown in Fig. 2. The overvoltage
This research has been supported by the European Regional can’t be measured directly by an ADC because the duration
Development Fund and Ministry of Education, Youth and Sports of the of the overvoltage is very short (10× ns). Therefore a peak
Czech Republic under project No. CZ.1.05/2.1.00/03.0094: Regional
Innovation Centre for Electrical Engineering (RICE) and project detector is used to capture these short pulses. It holds the
No. SGS-2015-038. captured peak voltage value until it is read by the ADC.

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Fig. 2. Functional block diagram of Serial-Parallel IGBT unit of power 1 kW.

A peak detector is used to capture overvoltages during detector for detecting peaks (Collector Emitter overvoltage
both turn ON and turn OFF. The implemented software in UCE PEAK). A rising edge of this signal also resets the peak
Digital Signal Processor (DSP) then decides which detector (erasing previously captured overvoltage).
overvoltage was measured (turn ON or turn OFF). A falling edge of the ENABLE signal starts the ADC’s
Furthermore, the DSP calculates the control deviation from conversion (SOC Start Of Conversion). The ADC has
overvoltages on both transistors (as at turn ON UB (ON) - enough time to convert until the next rising edge appears for
UA(ON) as at turn OFF UA(OFF) - UB(OFF)). The resulted error the signal ENABLE. The ADC therefore reads the
signal is the input of PI (Proportional-Integral) controllers, overvoltage during turn ON and the subsequent pulse of the
whose outputs are the relative delay between transistor A ENABLE signal triggers another detection but with the
and transistor B (one for turn ON and one for turn OFF). result of the turn OFF. The detection of both overvoltages is
These delays are entered to the modulator implemented in therefore carried out during two periods.
Field-Programmable Gate Array (FPGA). The FPGA This procedure was chosen because of the relatively long
modulator allows delaying the turn ON and turn OFF edges conversion time of the ADC compared with a minimum
of the control signal with step 5 ns. The minimal step is Pulse Width Modulation (PWM). In the PWM’s case, close
determined by the maximal allowable frequency due to the to 0 %, or 100 %, the time between overvoltage during turn
longest critical signal path of the FPGA. Delayed control ON and turn OFF is very short.
signals control IGBT transistors via IGBT drivers. Parallel From the described principle it is evident that this is not a
transistors are controlled by the same output signal of the method that would balance transistor voltages in the current
driver; each transistor has only its own Gate resistor RG = switching period. As was mentioned in Section I, this
10 Ω. The value of the gate resistor was chosen as relatively method is complementary to loss-making methods of
high in order to obtain more visible differences between balancing (active clamping, RCD snubber). Therefore, it is
transistors. The other outputs of the FPGA are control imperative to effectively balance the voltage of the
signals for the peak detector: ENABLE and transistors immediately for the first switch. The transistors
SAMPLE_STATE, because the FPGA modulator generates are protected by the supplementary methods. After several
the PWM signal. periods the delay differences in IGBTs are already
ENABLE and SAMPLE_STATE signal generation is compensated for, and thereby the losses caused by the
explained in Fig. 3. The ENABLE signal activates a peak complementary balancing methods are reduced.

Fig. 3. Diagram showing the timing of peak detector overvoltage measurement and AD conversion.

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III. TESTING CIRCUIT DESIGN for both channels A and B).

The testing prototype of output power 1 kW (at switching
frequency 10 kHz and PWM 40 %) was constructed to IV. MEASUREMENT
verify the method. A half bridge module package was used After the first functionality test of the serial-parallel unit,
as a serial arrangement of transistors. Transistors are already several measurements were executed. These measurements
connected in series in the package. Their common showed the expected function of delay compensation. The
connection was used only for parallel connection with waveforms listed first during incorrect compensation of
another module and voltage measurement UCE. The IGBT delays are listed in the following subsections IV.A and IV.B.
Module of serial-connected transistors is Semikron As was mentioned above, the supply voltage for the test did
SKM50GB12T4 (two modules were used for parallel not reach the maximum capability of the IGBTs. Therefore
connecting). the consequences of an unbalanced transistor’s voltage
A freewheeling diode module was formed by Semikron could be demonstrated without its destruction.
SKM75GB12V, whose control gates were short-circuited The subsection IV.C already demonstrates the presented
(UGE = 0). Balancing during the steady state in off method of the IGBT delay compensation. The following
transistors was ensured by resistors RA and RB of the value settings were applied for all measurements:
27 kΩ. The switching power supply Chroma 61504 ensures  CH1 voltage of the transistor A (TA) UCE A 20 V/div;
the DC voltage of the value 120 V. The control algorithm  CH2 voltage of the transistor B (TB) UCE B 20 V/div;
was implemented in DSP TMS320F28335. A master control  CH4 current of the load ILOAD 20 A/div;
unit is shown in Fig. 4. Fig. 5 is a photo of the assembled  Time base400 ns/div (IV.A, IV.C) 10 µs/div (IV.B).
serial-parallel IGBT unit. Conclusions of measurements are valid for all expectable
switching frequencies (approximately up to 20 kHz) and for
the full range of the PWM. The duty cycle of PWM, close to
0 % or 100 %, causes difficulties due to insufficient time for
capturing the overvoltage (see Fig. 3). If these conditions
persist only in a few PWM periods, PI controllers will not
change the output delays significantly. In case of long
duration of duty cycle close to 0 % or 100 % other balancing
method (RCD snubber, active clamp) will balance the
voltage with losses. Using this method for voltage higher
than 120 V requires changing the sense voltage divider of
peak detectors and balancing resistors (RA, RB). It will also
be necessary to ensure greater resistance to interference
whose levels will increase with increasing voltage (power).
A. Forced Imbalance during Turn ON
Fig. 4. Master control unit implemented in Code Composer Studio 5.5. This subsection demonstrates the impact of incorrect
voltage distribution on different delays during turn ON. One
of the transistors was delayed intentionally by 100 ns.
Figure 6(a) shows transistor A’s delay. Figure 6(b) shows
transistor B’s delay. The DC voltage is equally divided into
both transistors’ voltages before turn ON. After 100 ns both
transistors were opened and their voltages were equal to the
saturation voltage. The overvoltage of the transistors during
imbalanced voltages reaches 116 % of the DC voltage. This
can lead to the transistors’ destruction.

Fig. 5. Testing prototype of Serial-Parallel IGBT unit of power 1 kW.

The testing prototype isn’t equipped by the balancing

complementary circuits (active clamping, RCD snubber);
this makes for a more noticeable effect of the presented
method, including a demonstration of the voltage
distribution in uncompensated delays of IGBT transistors.
For this reason a lower voltage (120 V) than the blocking
voltage of the transistors (1200 V) was chosen. The
overvoltage detection circuit consists of two peak detectors
(for transistor A and B), the galvanic isolation of the control (a) (b)
signals ENABLE and SAMPLE_STATE and galvanic Fig. 6. Turn ON overvoltage (Timebase 400 ns/div): a) transistor A
isolation between the analog values of detected peaks (again delayed 100 ns; b) transistor B delayed 100 ns.

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B. Forced Imbalance during Turn OFF V. CONCLUSIONS

This subsection demonstrates the impact of incorrect This paper presents a novel method for the serial
voltage distribution on different delays during the turn OFF. connection of IGBTs. The different dynamic characteristics
Again, one of the transistors was intentionally delayed by of serially connected IGBTs during turn ON and OFF cause
100 ns during turn OFF. Figure 7 shows the delay of both short-term overvoltage stress of transistors. The presented
transistor A and B. Both transistors were opened before turn method uses a peak detector to capture overvoltages for
OFF, therefore their voltages UCE was equal to saturation enough time to enable conversion by a common ADC.
voltage. The transistors’ voltages were going to be equally The DSP measures overvoltages and defines required
divided due to balancing resistor RA and RB after turn OFF. delays using PI controller computation. Output delays are
The overvoltage on transistors during imbalanced voltages generated by FPGA with a minimal delay step of 5 ns. In
reaches 133 % of the DC voltage. This too can destroy the order to apply this method at nominal power (for a voltage
transistors. supply higher than the blocking voltage of one transistor), it
is necessary to supplement the serial-parallel unit with
auxiliary balancing methods that protect semiconductor
devices until the PI controllers finish balancing the voltage
in the transistors.
Another improvement of the balancing control process is
the reduction of step delay (less than 5 ns). It can be
expected that a high current will unbalance the voltage in
transistors more significantly during the same delays.
The proper function of the presented method was
demonstrated on a 1 kW testing prototype. The final
application of the presented method will be the 11 MW
mining machine.

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