The 80x86 Microprocessors The 80x86 Microprocessors

Chapter 1
The 80x86 Microprocessors
Processor Architecture Impacting Factors
Markets
Processor
Architecture
Technology Applications
The 80x86 Microprocessors 1.2 Assembly Language
1
Evolution of Intel’s Processors
Moore’s law: The number of transistors per integrated

circuit would double every 18 months
Pentium 4, 2001
55 Million Transistors
1.5 GHz
~ 30 years
4004, 1971
2300 Transistors
108 kHz
http://www.intel.com/research/silicon/mooreslaw.htm
By End of the Decade…

10,,000
10
~2B Transistors 100,,000
100
~30 GHz 30GHz
30GHz
1.8B
1,000 10,,000
10 14GHz
14GHz
6.5GHz
100 Itanium® 3 GHz
Transistors
1,000
Itanium® proc
(MT)
10
Pentium® Pro
100 Pentium® Pro
1 Pentium proc
486Pentium
486 Pentium® proc
486
386 10 8085
0.1 286 Frequency 286 386
8085 8086
8086
(MHz) 1 8080
0.01 8080
8008 8008
4004
0.001 0.1 4004
’70 ’80 ’90 ’00 ’10
’70 ’80 ’90 ’00 ’10
30 gigahertz devices, 10 nanometer or less

“…30
“…
delivering a tera instruction of performance by 2010”(”(11)
1) Pat Gelsinger, Intel CTO, Spring 2002 IDF
2
Evolution of Intel’s Processors
Product 4004 8008 8080 8085 8086 8088 80286 80386 80486 Pentium P. Pro
Year 1971 1972 1974 1976 1978 1979 1982 1985 1989 1992 1995
MHz .108 .5-.8 2 -3 3-8 5-10 5 -8 6-16 16--33

16 25--50
25 60,, 66
60 150
# Pins 18 18 40 40 40 40 68 132 168 273 387
# Tran K 2 .3 3 4 .5 6 .5 29 29 130 275 1,200 3,100 5,500
Memory 4K 16K 64K 64K 1M 1M 16M 4G 4G 4G 64G

Data bus
Int. 4 8 8 8 16 16 16 32 32 32 32
Ext. 4 8 8 8 16 8 16 32 32 64 64
Add bus 4 8 16 16 20 20 24 32 32 32 36
Data type 4 8 8 8 8, 16 8, 16 8, 16 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32
Evolution from 8080

8080//8085 to 8086
 In 1978, Intel Corp. introduced a 16--bit microprocessor called the 8086.
16
 8086 was a major improvement over 8080/8085 in several ways:
1. The 8086's capacity of 1 megabyte of memory exceeded the
8080/8085's capability of handling a maximum of 64K bytes.
2. The 8080/8085 was an 8-bit system (work on only 8 bits of data at a
time). Data larger than 8 bits had to be broken into 8-bit pieces to be
processed by the CPU.
3. The 8086 was a pipelined processor, as opposed to the non
pipelined 8080/8085.
 In a system with pipelining, the data and address buses are busy
transferring data while the CPU is processing information, thereby
increasing the effective processing power of the microprocessor.
3
Evolution from 8086 to 8088
 The 8086 is a microprocessor with a 16-bit data bus internally and
externally
 All registers are 16 bits wide and there is a 16-bit data bus to transfer
data in and out of the CPU.
 At that time all peripherals were designed around an 8-bit microprocessor
instead of 16-bit external data bus .
 A printed circuit board with a 16-bit data bus was much more expensive.
 Therefore, Intel came out with the 8088 version.
 8088 is identical to the 8086 as far as programming is concerned, but
externally it has an 8-bit data bus instead of a 16-bit bus.
 8088 has the same memory capacity, 1 megabyte.
 In 1981, Intel's fortunes changed forever when IBM picked up the 8088
as their microprocessor of choice in designing the IBM PC.
Other Microprocessors: 80286

80286,, 80386
80386,, 80486
 Intel introduced the 80286 in 1982.
 Its features included
 16--bit internal and external data buses
16
 24 address lines, which give 16 megabytes of memory (224 = 16
megabytes); and most significantly,
 Virtual memory
 The 80286 can operate in one of two modes: real mode or protected
mode.
 Real mode is simply a faster 8088/8086 with the same maximum of
1 megabyte of memory. Protected mode allows for 16M of memory
but is also capable of protecting the operating system and programs
from accidental or deliberate destruction by a user
 Virtual memory is a way of fooling the microprocessor into thinking
that it has access to an almost unlimited amount of memory by
swapping data between disk storage and RAM.
4
32--bit Microprocessor
32
 In 1985 Intel introduced the 80386 (sometimes called 80386DX), internally
and externally a 32
32--bit microprocessor with a 32-bit address bus.
 It is capable of handling physical memory of up to 4 gigabytes (232).
 Virtual memory was increased to 64 terabytes (246).
 Intel introduced numeric data processing chips, called math coprocessors,
such as the 8087, 80287, and 80387.
 Later Intel introduced the 386SX, which is internally identical to the 80386
but has a 16-bit external data bus and a 24-bit address bus which gives a
capacity of 16 megabytes (224) of memory.
 This makes the 386SX system much cheaper.
 With the introduction of the 486 in 1989, Intel put a greatly enhanced
version of the 386 and the math coprocessor on a single chip plus
additional features such as cache memory.
 Cache memory is static RAM with a very fast access time.
Pentium
 In 1992 Intel introduced the Pentium.
 The Pentium had speeds of 60 and 66 MHz, but new design features
made its processing speed twice that of the 66-MHz 80486.
 Although the Pentium has a 64--bit data bus, its registers are 32-bit and
64
it has a 32
32--bit address bus capable of addressing 4 gigabyes of
memory.
 In 1995 Intel introduced the Pentium Pro, the sixth generation of the x86
family.
 Pentium Pro is an enhanced version of the Pentium.
5
Internal Block Diagram of the 8088
8088//86 CPU
EXECUTION UNIT (EU) BUS INTERFACE UNIT (BIU)
address
generation and
bus control
Pipelining
 There are two ways to make the CPU process information faster:
1. Increase the working frequency or
2. Change the internal architecture of the CPU
 The first option is technology dependent, meaning that the designer must
use whatever technology is available at the time, with consideration for
cost.
 The technology determines the working frequency, power consumption,
and the number of transistors packed into a single-chip microprocessor.
 The second option for improving the processing power of the CPU has to
do with the internal working of the CPU.
 In the 8085 microprocessor, the CPU could either fetch or execute at a
given time.
Fetch Execute Fetch Execute
6
Pipelining (Cont.)
 The idea of pipelining in its simplest form is to allow the CPU to fetch and
execute at the same time.
Fetch Execute Fetch Execute Non pipelined
Fetch Execute
Fetch Execute
2-stage pipeline
Fetch Execute
Fetch Decode Execute

3-stage pipeline
Pipelining in the 8088

8088//86
 Intel implemented the concept of pipelining in the 8088/86 by splitting the
internal structure of the microprocessor into two sections:
 the execution unit (EU) and
 the bus interface unit (BIU).
 These two sections work simultaneously. The BIU accesses memory and
peripherals while the EU executes instructions previously fetched.
 This works only if the BIU keeps ahead of the EU; thus the BIU of the
8088/86 has a buffer, or queue.
 The buffer is 4 bytes long in the 8088 and 6 bytes in the 8086.
 If any instruction takes too long to execute, the queue is filled to its
maximum capacity and the buses will sit idle.
 The BIU fetches a new instruction whenever the queue has room for 2
bytes in the 6-byte 8086 queue, and for 1 byte in the 4-byte 8088 queue.
 In some circumstances, the microprocessor must flush out the queue.
7
8088//86 Registers
8088
 Registers: used to store information temporarily.
 Information: data (8/16-bit) to be processed or the address of data.
Category Bits Register Names

AX (accumulator), BX (base addressing),
General 16
CX (counter), DX (point to data in I/O operations)
registers, 16-bit each
8 AH, AL, BH, BL, CH, CL, DH, DL

categories
Pointer 16 SP (stack pointer), BP (base pointer)

Index 16 SI (source index), DI (destination index)
Six
CS (code segment), DS (data segment),

Segment 16
SS (stack segment), ES (extra segment)
14
Instruction 16 IP (instruction pointer)

Flag 16 FR (flag register)
8-bit/
bit/16
16--bit Registers
8-bit registers
16-bit registers
8
Introduction to Assembly Programming
 A program that consists of 0s and 1s is called machine language.

 In the early days of the computer, programmers actually coded programs
in machine language.
 Assembly languages were developed, which provided mnemonics for
the machine code instructions, plus other features that made
programming faster and less prone to error.
 Mnemonic  codes and abbreviations that are relatively easy to
remember.
 Assembler  Translator program from assembly code to machine code
 Assembly language is referred to as a low-level language because it
deals directly with the internal structure of the CPU.
 To program in Assembly language, the programmer must know the
number of registers and their size, as well as other details of the CPU.
 Pascal, BASIC, C, ... are called high
high--level languages because the
programmer does not have to be concerned with the internal details of the
CPU.
Assembly Language Programming

 Assembly language program consists of a series of lines of Assembly
language instructions.
 Each instruction consists of a mnemonic, optionally followed by one or two
operands.
 The operands are the data items being manipulated, and the mnemonics
are the commands to the CPU, telling it what to do with those items.

9
MOV Instruction
 The MOV instruction copies data from one location to another.
 MOV destination, source ;copy source operand to destination
Destination  Source
 The MOV instruction does not affect the source operand.
 MOV AX, 35A0H
AH AL High byte Low byte
35 A0
AX 00110101 10100000
00110101 10100000
 MOV DX, AX ; copies the contents of register AX to register DX

DH DL AH AL
DX 00110101 10100000 AX 00110101 10100000
Data can be moved among all registers

including the segment registers
 MOV AL, DX ; cause an error
 The source and destination registers must be matched in size
 MOV FR, AX ; cause an error
 Loading the flag register is done through other means
 MOV CX, 468FH ;move 468FH into CX (now CH=46,CL=8F)
 MOV AX, CX ;copy contents of CX to AX (now AX=CX=468FH)
 MOV DX,AX ;copy contents of AX to DX (now DX=AX=468FH)
 MOV BX,DX
 MOV DI,BX
 MOV SI,DI
 MOV DS,SI
 MOV BP,DI
 MOV CS, AX
 MOV DS, BX
10
Immediate MOV
 Data can be moved directly into nonsegment registers only, using the
MOV instruction
 MOV AX,58FCH ;move 58FCH into AX (LEGAL)
 MOV DX,6678H ;move 6678H into DX (LEGAL)
 MOV SI,924BH ;move 924B into Sl (LEGAL)
 MOV BP,2459H ;move 2459H into BP (LEGAL)
 MOV DS,2341H ;move2341H into DS (ILLEGAL)
 MOV CX,8876H ;move 8876H into CX (LEGAL)
 MOV CS,3F47H ;move 3F47H into CS (ILLEGAL)
 MOV BH,99H ;move 99H into BH (LEGAL)
Loading Segment Registers

 Values cannot be loaded directly into any segment register
(CS, DS, ES, or SS).
 To load a value into a segment register, first load it to a nonsegment register
and then move it to the segment register
 MOV AX,2345H ;load 2345H into AX
 MOV DS,AX ;then load the value of AX into DS
 MOV DI,1400H ;load 1400H into Dl
 MOV ES,DI ;then move it into ES, now ES=DI=1400
 If a value less than FFH is moved into a 16-bit register, the rest of the bits
are assumed to be all zeros.
 MOV BX,5 ;BX = 0005 (BH = 00 and BL = 05)
 Moving a value that is too large into a register will cause an error.
 MOV BL,7F2H ;ILLEGAL: BL is 8-bit register and 7F2H > 8 bits
 MOV AX,2FE456H ;ILLEGAL: the value is larger than AX
11
ADD instruction
ADD destination, source ;ADD the source operand to the destination
Destination  Destination + Source

 The ADD instruction tells the CPU to add the source and the destination
operands and put the result in the destination.
 To add two numbers such as 25H and 34H:
 MOV AL,25H ;move (25)16 = (00100101)2 into AL
 MOV BL,34H ;move (34)16 = (00110100)2 into BL
 ADD AL,BL ;AL = AL + BL, AL = (01011001)2 , BL = 34)16
 Another way:
 MOV DH,25H ;move 25 into DH
 MOV CL,34H ;move 34 into CL
 ADD DH,CL ;add CL to DH: DH = DH + CL
 Using immediate operand:
 MOV DH,25H ;load one operand into DH
 ADD DH,34H ;add the second operand to DH
16--bit Addition
16
 To add two numbers such as 34EH and 6A5H:
 MOV AX,34EH ; AX  001101001110
 MOV DX,6A5H ; DX  011010100101
 ADD DX,AX ; DX = DX + AX, DX = 100111110011
12
Introduction to Program Segments
 A typical Assembly language program consists of at least three segments:
 Code segment (CS contains the program instructions ),
 Data segment (DS store data that needs to be processed by the

instructions in CS), and
 Stack segment (The stack is used to store information temporarily).
8085//8086 Segments
8085
 A segment is an area of memory
 includes up to 64K bytes and
 begins on an address evenly divisible by 16 (address ends in 0H).
 8085 microprocessor had only 16 pins for the address lines (216 = 64K).
 8085 microprocessor could address a maximum of 64K bytes of physical
memory for code, data, and stack.
 For compatibility
compatibility, 64K bytes segment was carried into the design of the
8088/86.
 Three segments can be used: code, data, and stack segments.
 8088/86 can only handle a maximum of 64K bytes of code and 64K bytes
of data and 64K bytes of stack at any given time, although it has a range
of 1 megabyte of memory (20 address pins  220  1 megabyte).
13
Logical address and physical address
 In Intel literature, there are three types of addresses mentioned frequently:
 Physical address
 20-bit address that is actually put on the address pins of the 8086
microprocessor and decoded by the memory interfacing circuitry.
 This address can have a range of 00000H to FFFFFH.
 Offset address
 a location within a 64K-byte segment range.
 An offset address can range from 0000H to FFFFH.
 Logical address
 The logical address consists of a segment value and an offset
address
 Segment value : Offset address
Code segment
 To execute a program, the 8086 fetches the instructions (opcodes and operands)
from the code segment.
 The logical address of an instruction, CS:IP
 The physical address for the location of the instruction is
 CS10H + IP Shifting the CS left one hex digit and then adding it to the IP
 CS or IP is 16-bit register, the physical address (CS10H + IP) is 20-bit.
 Example: assume CS = 2500H and IP = 95F3H.
 The offset address: 95F3H (the content of IP)
 The logical address: 2500:95F3H (CS:IP)
 The physical address: 250010 + 95F3 = 2E5F3H
 The logical address range: 2500:0000 to 2500:FFFF
 The lowest memory location of the code segment: 25000H (25000+0000)
 The highest memory location of the code segment: 34FFFH (25000+FFFF)
 8086 will read the instruction from memory locations starting at 2E5F3H
14
Example
 If CS = 24F6H and IP = 634AH
Show: (a) The logical address (b) The offset address
Calculate: (c) The physical address (d) The lower range of the code segment
(e) The upper range of the code segment
 Solution:
(a) The logical address  24F6:634A
(b) The offset address  634A
(c) The physical address  2B2AA (24F610 + 634A)
(d) The lower range of the code segment  24F60 (24F610 + 0000)
(e) The upper range of the code segment  34F5F (24F610 + FFFF)
80x
80 x86 ADDRESSING MODES
 The CPU can access operands (data) in various ways, called addressing
modes.
 The 80x86 provides a total of seven distinct addressing modes:

1. Register
2. Immediate
3. Direct
4. register indirect
5. Based relative
6. Indexed relative
7. Based indexed relative
15
Register addressing mode
 The operands are inside the microprocessor.
 The register addressing mode involves the use of registers to hold the
data to be manipulated.
 Memory is not accessed when this addressing mode is executed;
 It is relatively fast
 Examples:
MOV BX,DX ; copy the contents of DX into BX
MOV ES,AX ; copy the contents of AX into ES
ADD AL,BH ; add the contents of BH to contents of AL
 The source and destination registers must match in size.

MOV CL,AX ; this instruction will give an error
Immediate addressing mode

 In the immediate addressing mode, the source operand is a constant.
 In immediate addressing mode, as the name implies, when the instruction
is assembled, the operand comes immediately after the opcode.
 For this reason, this addressing mode executes quickly.
 However, in programming it has limited use.
 Immediate addressing mode can be used to load information into any of
the registers except the segment registers and flag registers.
 Examples:
MOV AX,2550H ; move 2550H into AX
MOV CX,625 ; load the decimal value 625 into CX
MOV BL,40H ; load 40H into BL
MOV DS,0123H ; illegal
16
Direct addressing mode
 In the direct addressing mode the data is in some memory location(s) and
the address of the data in memory comes immediately after the
instruction.
 Note that in immediate addressing, the operand itself is provided with the
instruction, whereas in direct addressing mode, the address of the
operand is provided with the instruction.
 This address is the offset address and one can calculate the physical
address by shifting left the DS register and adding it to the offset as
follows:
MOV DL,[2400] ;move contents of DS:2400H into DL
 Notice the bracket [ ] around the address.
 In the absence of this bracket it will give an error since it is interpreted to
move the value 2400 (16-bit data) into register DL, an 8-bit register.
MOV DL,2400 ; move 2400 into DL illegal
Example
 Find the physical address of the memory location and its contents after
the execution of the following instructions
assuming that DS = 1512H.
MOV AL,99H ; AL is initialized to 99H
MOV [3518],AL
 Solution:
 The contents of AL are moved to logical address DS:3518 which is
1512:3518.
 The physical address: 18638H (151210H + 3518H = 18638H).
 That means after the execution of the second instruction, the memory
location with address 18638H will contain the value 99H.
17
Register indirect addressing mode
 In the register indirect addressing mode, the address of the memory location
where the operand resides is held by a register.
 The registers used for this purpose are SI, DI, and BX.
 If these three registers are used as pointers, they must be combined with DS
in order to generate the 20-bit physical address.
Example:
MOV AL,[BX] ; AL contents of the memory location pointed to by DS:BX
 Notice that BX is in brackets.
 In the absence of brackets: MOV AL,BX  illegal
 Physical address: DS10H+ BX
 The same rules apply when using register SI or DI.
MOV CL,[SI] ; move contents of DS:SI into CL (move a byte)
MOV [DI],AH ; move contents of AH into DS:DI (move a byte)
Example
 Assume that DS = 1120, SI = 2498, and AX = 17FE. Show the contents of
memory locations after the execution of
MOV [SI],AX
 Solution:
 The contents of AX are moved into memory locations with logical
address DS:SI and DS:SI + 1
 The physical address: DS10H + SI = 13698.
 According to the little endian convention
 low address 13698H contains FE, the low byte, and
 high address 13699H will contain 17, the high byte.
18
Based relative addressing mode
 In the based relative addressing mode, base registers BX and BP, as well
as a displacement value, are used to calculate what is called the physical
address.
Physical address = segment register
register10
10H
H + offset register + displacement
 The default segments are DS for BX and SS for BP.
 For example:
MOV CX,[BX]+10 ; move DS:BX+10 and DS:BX+10+1 into CX
MOV CX,[BX+10] ; BX+10 is called the effective address
MOV CX,10[BX] ; BX is called the offset address
 Physical address: DS10H + BX + 10
 The low address contents will go into CL and the high address contents into
CH. In the case of the BP register,
MOV AL,[BP]+5 ; PA = SS 10H + BP + 5
MOV AL,[BP+5] ; BP+5 is called the effective address
MOV AL,5[BP] ; BP is called the offset address
Indexed relative addressing mode

 The indexed relative addressing mode works the same as the based
relative addressing mode, except that registers DI and SI hold the offset
address.
MOV DX,[SI]+5 ; PA=DS10H + SI + 5
MOV CL,[DI]+20 ; PA=DS10H + DI + 20
Example
 Assume that DS = 4500, SS = 2000, BX = 2100, SI = 1486, DI = 8500, BP
= 7814, and AX = 2512. Show the exact physical memory location where
AX is stored in each of the following. All values are in hex.
MOV [BX]+20,AX MOV [SI]+10,AX MOV [DI]+4,AX MOV [BP]+12,AX
 Solution:
DS:BX+20 location 47120 = (12) and 47121 = (25)
DS:SI+10 location 46496 = (12) and 46497 = (25)
DS:DI+4 location 4D504 = (12) and 4D505 = (25)
SS:BP+12 location 27826 = (12) and 27827 = (25)
19
Based indexed addressing mode
 By combining based and indexed addressing modes, a new addressing
mode is derived called the based indexed addressing mode.
 In this mode, one base register and one index register are used.
Examples:
 MOV CL,[BX][DI]+8 ; PA = DS10H + BX + Dl + 8
 MOV CH,[BX][SI]+20 ; PA = DS 10H + BX + SI + 20
 MOV AH,[BP][DI]+12 ; PA = SS 10H + BP + DI + 12

 MOV AH,[BP][SI]+29 ;PA = SS 10H + BP + SI + 29
 MOV AH,[BP+SI+29]
 MOV AH,[SI+BP+29] ;the register order does not matter.
 MOV AX,[SI][DI]+10 ;illegal.
Summary of 80
80xx86 Addressing Modes
Addressing Mode Operand Default Segment
Register register none
Immediate data none
Direct [offset] DS
Register indirect [BX] DS
[SI] DS
[DI] DS
Based relative [BX]+disp DS
[BP]+disp SS
Indexed relative [DI]+disp DS
[SI]+disp DS
Based indexed relative [BX][SI]+disp DS
[BX][DI]+disp DS
[BP][SI]+ disp SS
[BP] [DI]+ disp SS
20
Offset Registers for Various Segments
Segment register: Offset register (s):
CS IP
DS SI, DI, BX
ES SI, DI, BX
SS SP, BP
 The 80x86 CPU allows the program to override the default segment and
use any segment register.
 MOV AL,[BX]
; the physical address of the operand to be moved into AL is DS:BX
 MOV AL,ES:[BX]
; the address of the operand being moved to AL is ES:BX instead of
DS:BX.
Segment overrides
Default Segment
Instruction Instruction
Segment Used
MOV AX,[BP] SS:BP MOV AX,CS:[BP] CS:BP
MOV DX,[SI] DS:SI MOV DX,SS:[SI] SS:SI
MOV AX,[BP] SS:BP MOV AX,DS:[BP] DS:BP
MOV CX,[BX]+12 DS:BX+12 MOV CX,ES:[BX]+12 ES:BX+12
MOV [BX][DI]+32,AX DS:BX+DI+32 MOV SS:[BX][DI]+32,AX SS:BX+DI+32
21
Translating to Machine Code
Translate the following Assembly language instructions into machine code
MOV AL,57H
MOV DH,86H
MOV DL,72H
MOV CX,DX
MOV BH,AL
MOV BL,9FH
MOV AH,20H
ADD AX,DX
ADD CX,BX
ADD AX,1F35H
Assembly Language / Machine Code

Assembly Machine Logical address Physical
language language (CS:IP) address
MOV AL,57H B057 1132:0100 11420
MOV DH,86H B686 1132:0102 11422
MOV DL,72H B272 1132:0104 11424
MOV CX,DX 89D1 1132:0106 11426
MOV BH,AL 88C7 1132:0108 11428
MOV BL,9FH B39F 1132:010A 1142A
MOV AH,20H B420 1132:010C 1142C
ADD AX,DX 01D0 1132:010E 1142E
ADD CX,BX 01D9 1132:0110 11430
ADD AX,1F35H 05351F 1132:0112 11432
22
MOV Immediate Value to 8-bit Registers
10110 Reg 8-bit data
 MOV AL,57H
Reg
 10110 000 01010111 AL  000
CL  001
 1011000001010111  B057
DL  010
 MOV DH,86H BL  011
AH  100
 10110 110 10000110 CH  101
DH  110
 1011011010000110  B686 BH  111
 MOV DL,72H
 10110 010 01110010
 1011001001110010  B272
MOV Immediate to 16
16--bit Registers
10111 Reg 16-bit data
 MOV AX,1F35H
 10111 000 0001111100110101 Reg
AX  000
 101110000001111100110101  B81F35 CX  001
DX  010
 MOV DX,86H BX  011
SP  100
 10111 010 0000000010000110 BP  101
SI  110
 101110100000000010000110  BA0086 DI  111
23
MOV from 8-bit Registers to 8-bit Registers
1000100011 Regsource Regdestination
• MOV BH,AL
• 1000100011000111 Reg
• 1000100011000111  88C7 AL  000
CL  001
DL  010
BL  011
AH  100
CH  101
DH  110
BH  111
MOV from 16
16--bit Registers to 16
16--bit Registers
1000100111 Regsource Regdestination
 MOV CX,DX
 1000100111010001 Reg
AX  000
 1000100111010001  89D1 CX  001
DX  010
BX  011
SP  100
BP  101
SI  110
DI  111
24
Machine Code
Logical address Physical address Machine code contents
1132:0100 11420 B0
1132:0101 11421 57
1132:0102 11422 B6
1132:0103 11423 86
1132:0104 11424 B2
1132:0105 11425 72
1132:0106 11426 89
1132:0107 11427 D1
1132:0108 11428 88
1132:0109 11429 C7
1132:010A 1142A B3
1132:010B 1142B 9F
1132:010C 1142C B4
1132:010D 1142D 20
1132:010E 1142E 01
1132:010F 1142F D0
1132:0110 11430 01
1132:0111 11431 D9
1132:0112 11432 05
1132:0113 11433 35
1132:0114 11434 1F
Data Segment
Write a program that adds 5 bytes of data, such as 25H, 12H, 15H, 1FH,
and 2BH, where each byte represents a person's daily overtime pay.
 Answer
MOV AL,0 ; initialize AL
ADD AL,25H ; add 25H to AL
ADD AL,1FH ; add 1FH to AL
ADD AL,2BH ; add2BHtoAL
 -ve
The data and code are mixed together in the instructions.

Changing in data  the code must be searched for every place the

data is included, and the data retyped.
 In 80x86 microprocessors, the area of memory set aside for data is called
the data segment.
 the data segment uses register DS and an offset value.
25
Data Segment (Cont.)
 Assume that the offset for the data segment begins at 200H.
The data is placed in memory locations:
DS:0200 = 25
DS:0201 = 12
DS:0202 = 15
DS:0203 = 1F
DS:0204 = 2B
 The program can be rewritten as follows:
MOV AL, 0 ; clear AL
ADD AL,[0200] ; add the contents of DS:200 to AL
 The brackets [ ] indicate that the operand represents the address of the
data and not the data itself.
Data Segment (Cont.)

 CS uses only the IP register as an offset
 The 8086/88 allows only the use of registers BX, SI, and DI as
offset registers for the data segment.
 DS uses only BX, DI, and SI to hold the offset address of the data.
 DS:0200 = 25 DS:0201 = 12 DS:0202 = 15

DS:0203 = 1F DS:0204 = 2B
MOV AL,0 ; initialize AL
MOV BX,0200H ; BX points to the offset address of first byte
ADD AL,[BX] ; add the first byte to AL
INC BX ; increment BX to point to the next byte
ADD AL,[BX] ; add the next byte to AL
INC BX ; increment the pointer
ADD AL,[BX] ; add the next byte to AL
INC BX ; increment the pointer
ADD AL,[BX] ; add the last byte to AL
26
Logical and Physical address in Data Segment
Example: If DS = 7FA2H and the offset is 438EH,

(a) Calculate the physical address.
(b) Calculate the lower range of the data segment.
(c) Calculate the upper range of the data segment.
(d) Show the logical address.
Solution:
(a) The physical address  83DAE (7FA20 + 438E)
(b) The lower range of the data segment  7FA20 (7FA20 + 0000)
(c) The upper range of the data segment  8FAlF (7FA20 + FFFF)
(d) The logical address  7FA2:438E
Example
Assume that the DS register is 578C. To access a given byte of data at
physical memory location 67F66, does the data segment cover the range
where the data is located? If not, what changes need to be made?
 Solution:
No, since the range is 578C0 to 678BF

Location 67F66 is not included in this range.
To access that byte, DS must be changed so that its range will include that
byte.
27
What is a stack, and why is it needed?
 The stack is a section of read/write memory (RAM) used by the CPU to
store information temporarily.
 The CPU needs this storage area since there are only a limited number of
registers.
 The main disadvantage of the stack is its access time.
 The two main registers used to access the stack are the SS (stack
segment) register and the SP (stack pointer) register.
 These registers must be loaded before any instructions accessing the
stack are used.
 Every register inside the 80x86 (except segment registers and SP) can be
stored in the stack and brought back into the CPU from the stack memory.
 The storing of a CPU register in the stack is called PUSH, and loading the
contents of the stack into the CPU register is called POP.
 In the 80x86, the stack pointer register (SP) points at the current memory
location used for the top of the stack and as data is pushed onto the stack
it is decremented.
 SP is incremented as data is popped off the stack into the CPU.
Example
 Assuming that SP = 1236, AX = 24B6, DI = 85C2, and DX = 5F93,
show the contents of the stack as each of the following instructions is
executed:
PUSH AX
PUSH DI
PUSH DX BX = 5F93
POP BX
POP AX AX = 85C2
POP CX CX = 24B6
SS:1230 93
SS:1231 5F
SS:1232 C2 C2 C2
SS:1233 85 85 85
SS:1234 B6 B6 B6 B6 B6
SS:1235 24 24 24 24 24
SS:1236
PUSH AX PUSH DI PUSH DX POP BX POP AX POP CX
28
Example
 Assuming that SP = 1236, AX = 24B6, DI = 85C2, and DX = 5F93,
show the contents of the stack as each of the following instructions is
executed:
PUSH AX
PUSH DI
POP BX AX = 5F93
PUSH DX
POP AX BX = 85C2
POP CX CX = 24B6
SS:1230
SS:1231
SS:1232 C2 93
SS:1233 85 5F
SS:1234 B6 B6 B6 B6 B6
SS:1235 24 24 24 24 24
SS:1236
PUSH AX PUSH DI POP BX PUSH DX POP AX POP CX
Can a single physical address-

address-belong to many
different logical addresses?
Yes
Logical address (hex) Physical address (hex)
1000:5020 15020
1500:0020 15020
1502:0000 15020
1400:1020 15020
1302:2000 15020
29
Flag register (status register)
 The flag register is a 16-bit register.
 Only 9 of the bits are used and the rest are either undefined or reserved by
Intel.
 6 of the flags are called conditional flags: CF, PF, AF, ZF, SF, and OF
 They indicate some condition that resulted after an instruction was
executed
 3 flags are sometimes called control flags: DF, IF, and TF
 They are used to control the operation of instructions before they are
executed.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R R R OF DF IF TF SF ZF U AF U PF U CF
R = reserved U = undefined
CF = carry flag PF = parity flag AF = auxiliary carry flag
ZF = zero flag SF = sign flag OF = overflow flag
DF = direction flag IF = interrupt flag TF = trap flag
Bits of the flag register

 CF: Carry Flag
 This flag is set whenever there is a carry out, either from r7 after an 8-
bit operation, or from r15 after a 16-bit data operation.
a7 a6 a5 a4 a3 a2 a1 a0
OP
b7 b6 b5 b4 b3 b2 b1 b0
C r7 r6 r5 r4 r3 r2 r1 r0
 PF: Parity Flag

 After certain operations, the parity of the result's low-order byte is
checked
Low byte has an even number of 1s  PF=1; otherwise, PF=0
 AF: Auxiliary Carry Flag
 If there is a carry from d3 to d4 of an operation, this bit is set (AF=1;);
otherwise, AF=0. This flag is used by the instructions that perform BCD
(binary coded decimal) arithmetic.
 ZF: Zero Flag
 ZF=1, if the result of an arithmetic or logical operation is zero;
otherwise, ZF=0.
30
Bits of the flag register (Cont.)
 SF: Sign Flag
 Signed numbers uses the most significant bit as the sign bit. After
arithmetic or logic operations, the status of this sign bit is copied into
the SF, thereby indicating the sign of the result.
 TF: Trap Flag
 When this flag is set it allows the program to single-step, meaning to
execute one instruction at a time.
 Single-stepping is used for debugging purposes.
 IF: Interrupt Enable Flag
 This bit is set or cleared to enable or disable only the external
maskable interrupt requests.
 DF: Direction Flag
 This bit is used to control the direction of string operations.
 OF: Overflow Flag
 This flag is set whenever the result of a signed number operation is
too large, causing the high-order bit to overflow into the sign bit.
 In general, the carry flag is used to detect errors in unsigned
arithmetic operations.
 The overflow flag is only used to detect errors in signed arithmetic
operations.
Flag register and ADD instruction

 The flag bits affected by the ADD instruction are
 CF (carry flag),
 PF (parity flag),
 AF (auxiliary carry flag),
 ZF (zero flag),
 SF (sign flag), and
 OF (overflow flag): it relates only to signed number arithmetic
 The flag bits affected by the INC/DEC instructions are

 PF (parity flag),
 AF (auxiliary carry flag),
 ZF (zero flag),
 SF (sign flag), and
 OF (overflow flag)
31
Example
Show how the flag register is affected by the addition of 38H and 2FH
MOV BH,38H ; BH= 38H
ADD BH,2FH ; add 2F to BH, now BH = 67H
 Solution:
38 0011 1000
2F 0010 1111
67 0110 0111
 CF = 0 since there is no carry beyond d7

 PF = 0 since there is an odd number of Is in the result
 AF = 1 since there is a carry from d3 to d4
 ZF = 0 since the result is not zero
 SF = 0 since d7 of the result is zero
Example
Show how the flag register is affected by
MOV AL,9CH ; AL = 9CH
MOV DH,64H ; DH = 64H
ADD AL,DH ; now AL=0
 Solution:
9C 1001 1100
64 0110 0100
00 0000 0000
CF= 1 since there is a carry beyond d7

PF= 1 since there is an even number of 1s in the result
AF= 1 since there is a carry from d3 to d4
ZF= 1 since the result is zero
SF= 0 since d7 of the result is zero
32
Use of the zero flag for looping
 One of the most widely used applications of the flag register is the use of
the zero flag to implement program loops.
 The term loop refers to a set of instructions that is repeated a number of
times.
MOV CX,05 ;CX holds the loop count
MOV BX,0200H ;BX holds the offset data address
MOV AL,00 ;initialize AL
ADD_LP: ADD AL,[BX] ;add the next byte to AL
INC BX ;increment the data pointer
DEC CX ;decrement the loop counter
JNZ ADD_LP ;jump to next iteration if counter not zero
Using LOOP instruction

 LOOP target ; loop until CX equals zero
 DEC CX
 JNZ target
MOV CX,05 ;CX holds the loop count

MOV BX,0200H ;BX holds the offset data address
MOV AL,00 ;initialize AL
ADD_LP: ADD AL,[BX] ;add the next byte to AL
INC BX ;increment the data pointer
LOOP ADD_LP ;jump to next iteration if counter not zero
33
Operations on Flags
 CLC
CLC: Clear Carry Flag  CF = 0
 STC
STC: Set Carry Flag  CF = 1
 CMC
CMC: Complement Carry Flag  if CF = 0  CF = 1, otherwise CF = 0
 CLD
CLD: Clear Direction Flag  DF = 0
 STD
STD: Set Direction Flag  DF = 1
 CLI
CLI: Clear Interrupt Flag  IF = 0
 STI
STI: Set Interrupt Flag  IF = 1
Wrap--around and Overlapping

Wrap
 When adding the offset to the shifted segment register results in an
address beyond the maximum allowed range of FFFFFH
 In that situation, wrap-around will occur.
Example: What is the range of physical addresses if CS = FF59?

 The low range is FF590 (FF590 + 0000).
 The range goes to FFFFF and wraps around, from 00000 to 0F58F
(FF590 + FFFF = 0F58F), which is illustrated below.
 In calculating the physical address, it is possible that two segments can
overlap, which is desirable in some circumstances.
34
Jump
 Unconditional Jump
xxx: ………
………
………
JMP xxx
 Conditional Jump
xxx: ………
………
………
JC xxx JNC xxx
JZ xxx JNZ xxx
JP xxx JNP xxx
JO xxx JNO xxx
JS xxx JNS xxx
Unsigned Numbers
 Unsigned numbers: Data in which all the bits are used to represent data
and no bits are set aside for the positive or negative sign.
 An 8-bit operand ranges from 00 to FFH (0 to 255 decimal)
 A 16-bit operand ranges from 0000 to FFFFH (0 to 65535 decimal)
 for and between 0000 and FFFFH (O to 65535 decimal)
 Example: A byte of memory contains (A3)16.
What decimal number does this represent if the byte is interpreted as
containing: - an eight-bit unsigned integer.
- an eight-bit signed integer.
Answer:
Unsigned integer (A3)16 =
(10100011)2 = 271 + 260 + 251 + 240 + 230 + 220 + 211 + 201 = 163
Signed integer (A3)16 =
(A3)16 = (10100011)2 = - (01011101)2
- (270 + 261 + 250 + 241 + 231 + 221 + 210 + 201) = -93
35
Addition of unsigned numbers
 ADD destination, source ; destination = destination + source
 ADC destination, source ; destination = destination + source + CF
 The destination operand can be a register or in memory.
 The source operand can be a register, in memory, or immediate.
 Remember that memory-to-memory operations are never allowed in
80x86 Assembly language.
 The instruction could change any of the ZF, SF, AF, CF, or PF bits of the
flag register, depending on the operands involved.
 Example: Show how the flag register is affected by
MOV AL,0F5H F5 11110101
+
ADD AL,0BH 0B 00001011
 After the addition, the AL register (destination) contains 00 100 100000000
 CF = 1 since there is a carry out from D7
 SF = 0 the status of D7 of the result
 PF = 1 the number of 1s is zero (zero is an even number)
 AF = 1 there is a carry from D3 to D41.71
The 80x86 Microprocessors Assembly Language
Example
Show how the flag register is affected by
MOV AL,0F5H
ADD AL,0BH
F5 11110101
+
0B 00001011
100 100000000
 After the addition, the AL register (destination) contains 00

 CF = 1 since there is a carry out from D7
 SF = 0 the status of D7 of the result
 PF = 1 the number of 1s is zero (zero is an even number)
 AF = 1 there is a carry from D3 to D4
 ZF = 1 the result of the action is zero (for the 8 bits)
36
Addition of individual byte and word data
Write a program to calculate the total sum of 5 bytes of data. Each byte
represents the daily wages of a worker. This person does not make more than
$255 (FFH) a day. The decimal data is as follows: 125, 235, 197, 91, and 48
COUNT EQU 05
DATA DB 125, 235, 197, 91, 48
SUM DW ?
MOV AX,DTSEG
MOV DS, AX
MOV CX,COUNT
MOV SI, OFFSET DATA
MOV AX,00
BACK ADD AL,[SI]
JNC OVER
INC AH
OVER INC SI
DEC CX
JNZ BACK
MOV SUM,AX
MOV AH, 4CH
INT 21H
37

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Chapter 1

The 80x86 Microprocessors

Processor Architecture Impacting Factors

The 80x86 Microprocessors 1.2 Assembly Language

Moore’s law: The number of transistors per integrated

By End of the Decade…

30 gigahertz devices, 10 nanometer or less

The 80x86 Microprocessors 1.4 Assembly Language

MHz .108 .5-.8 2 -3 3-8 5-10 5 -8 6-16 16--33

# Pins 18 18 40 40 40 40 68 132 168 273 387

# Tran K 2 .3 3 4 .5 6 .5 29 29 130 275 1,200 3,100 5,500

Memory 4K 16K 64K 64K 1M 1M 16M 4G 4G 4G 64G

Data type 4 8 8 8 8, 16 8, 16 8, 16 8, 16, 32 8, 16, 32 8, 16, 32 8, 16, 32

The 80x86 Microprocessors 1.5 Assembly Language

Evolution from 8080

The 80x86 Microprocessors 1.6 Assembly Language

The 80x86 Microprocessors 1.7 Assembly Language

Other Microprocessors: 80286

The 80x86 Microprocessors 1.8 Assembly Language

The 80x86 Microprocessors 1.9 Assembly Language

The 80x86 Microprocessors 1.10 Assembly Language

The 80x86 Microprocessors 1.11 Assembly Language

Fetch Execute Fetch Execute

The 80x86 Microprocessors 1.12 Assembly Language

Fetch Execute Fetch Execute Non pipelined

Fetch Decode Execute

The 80x86 Microprocessors 1.13 Assembly Language

Pipelining in the 8088

The 80x86 Microprocessors 1.14 Assembly Language

Category Bits Register Names

8 AH, AL, BH, BL, CH, CL, DH, DL

Pointer 16 SP (stack pointer), BP (base pointer)

CS (code segment), DS (data segment),

Instruction 16 IP (instruction pointer)

The 80x86 Microprocessors 1.15 Assembly Language

The 80x86 Microprocessors 1.16 Assembly Language

 A program that consists of 0s and 1s is called machine language.

Assembly Language Programming

The 80x86 Microprocessors 1.18 Assembly Language

 MOV DX, AX ; copies the contents of register AX to register DX

The 80x86 Microprocessors 1.19 Assembly Language

Data can be moved among all registers

The 80x86 Microprocessors 1.20 Assembly Language

 MOV AX,58FCH ;move 58FCH into AX (LEGAL)

 MOV DX,6678H ;move 6678H into DX (LEGAL)

 MOV SI,924BH ;move 924B into Sl (LEGAL)

 MOV BP,2459H ;move 2459H into BP (LEGAL)

 MOV DS,2341H ;move2341H into DS (ILLEGAL)

 MOV CX,8876H ;move 8876H into CX (LEGAL)

 MOV CS,3F47H ;move 3F47H into CS (ILLEGAL)

 MOV BH,99H ;move 99H into BH (LEGAL)

The 80x86 Microprocessors 1.21 Assembly Language

Loading Segment Registers

The 80x86 Microprocessors 1.22 Assembly Language

Destination  Destination + Source

The 80x86 Microprocessors 1.23 Assembly Language

 MOV AX,34EH ; AX  001101001110

 MOV DX,6A5H ; DX  011010100101

 ADD DX,AX ; DX = DX + AX, DX = 100111110011