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Assignment Solution Week10

This document provides solutions to 10 assignment questions about computer architecture topics like DMA, programmed I/O, bit stuffing, USB standards, and estimating CPU slowdown due to DMA transfers. Each question is followed by an explanation of the correct answer. Key topics covered include advantages of DMA over programmed I/O for high-speed transfers, estimating transfer rates based on disk rotation speed, applying bit stuffing encoding, and calculating CPU slowdown percentage from overlapping DMA and instruction execution.

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Shifa Sheikh
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Download as PDF, TXT or read online on Scribd
126 views

Assignment Solution Week10

This document provides solutions to 10 assignment questions about computer architecture topics like DMA, programmed I/O, bit stuffing, USB standards, and estimating CPU slowdown due to DMA transfers. Each question is followed by an explanation of the correct answer. Key topics covered include advantages of DMA over programmed I/O for high-speed transfers, estimating transfer rates based on disk rotation speed, applying bit stuffing encoding, and calculating CPU slowdown percentage from overlapping DMA and instruction execution.

Uploaded by

Shifa Sheikh
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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Week 10: Assignment Solutions

1. Which of the following are not true for DMA data transfer?
a. Data are transferred directly between the memory and the
peripheral without CPU intervention.
b. CPU puts all its memory bus lines in high impedance state before
data transfer can begin.
c. It is more suitable for devices where the data transfer rates can
vary widely.
d. None of the above.
Correct answer is (c).
In DMA transfer, the DMA controller sends a DMA request to the CPU, in
response to which CPU puts all its address, data and control bus lines in
the high impedance states. The DMA controller can then transfer data
directly between device and memory without CPU intervention. Clearly, it
is more suitable for devices with high data transfer rates like disk.
2. Programmed I/O is not suitable for high-speed data transfer because:
a. For transfer of every word between I/O device and memory, a set
of machine instructions has to be executed.
b. It does not support synchronous mode of data transmission that is
a requirement for many high-speed peripherals like disk.
c. Lot of CPU time is wasted.
d. None of the above.
Correct answers are (a) and (b).
In programmed I/O, CPU executes a program that is responsible for the
data transfer. The CPU cannot do anything else during the period of data
transfer. Since program execution takes time, this mode is more suitable
for devices with low to moderate data rates. In particular, it is not suitable
for high speed devices like disk which transfers data continuously
(synchronously) when the read/write head is on the correct track.
3. Suppose that a disk is rotating at a speed of 10,000 rpm, and there are
120 Kbytes of data recorded in every track. Once the disk head reaches
the desired track, the sustained data transfer rate will be ………………
Mbytes/sec.
Correct answer is 20.
In a 10,000 rpm disk, one complete revolution takes 6 milliseconds.
So, 6 msec time is required to transfer 120 Kbytes
Thus, 1 sec time is required to transfer 120/6 Mbytes = 20 Mbytes.
4. On a non-pipelined sequential processor, the following program segment,
that is part of the Interrupt Service Routine (ISR), is given to transfer 500
bytes from an I/O device to memory.
Initialize the memory address register
Initialize word count register to 500
Loop: Load a byte from device
Store in memory at address given by address register
Increment the memory address register
Decrement the word count register
If count != 0 goto Loop
Assume that each statement in the program is equivalent to a machine
instruction that takes 1 clock cycle to execute if it is a non-LOAD/STORE
instruction. The LOAD/STORE instructions take 2 clock cycles to execute.
The designer of the system also has an alternate approach of using the
DMA controller to implement the same transfer. The DMA controller
requires 20 clock cycles for initialization and other overheads. Eack DMA
transfer cycle takes 2 clock cycles to transfer one byte of data from the
device to the memory.
The approximate speedup when the DMA controller based design is used
in place of the interrupt driven approach is ………………….
Correct answer is 3.43.
In alternative 1, total number of clock cycles required
= 1 + 1 + 500 (2 + 2 + 1 + 1 + 1) = 3502
In alternative 2, total number of clock cycles required
= 20 + 500 x 2 = 1020
Speedup = 3502 / 1020 = 3.43

5. The size of the word count register of a DMA controller is 16 bits. The
processor needs to transfer a file of 29,154 Kbytes from disk to main
memory. The memory is byte addressable. The minimum number of times
the DMA controller needs to get control of the system bus from the
processor to transfer the file from disk to main memory is ………………
Assume 1K = 1024.
Correct answer is 455.5.
Maximum number that can be stored in 16 bits is 216 – 1 = 65535 = 64K
(approx.)
So, up to 64K bytes of data can be transferred by the DMA controller at a
time.
Number of times DMA controller needs to be invoked
= 29154 / 64 = 455.5

6. Which of the following statements are true?


a. In cycle stealing mode of DMA transfer, it is possible to overlap
CPU and DMA cycles.
b. In DMA block transfer mode, it is possible to overlap CPU and DMA
cycles.
c. Cycle stealing mode of transfer is preferable when the size of block
to be transferred is large.
d. None of the above.
Correct answer is (a).
In cycle stealing DMA transfer, the DMA controller requests only one or
two memory cycles from the CPU at a time. If the CPU is trying to access
memory during that time, it will wait. Otherwise, CPU can continue with
its internal operation that does not require access to the memory bus. So
CPU and DMA cycles can be overlapped. Cycle stealing mode is not
suitable for large block transfers since the overhead will be high.
7. For interfacing a matrix keyboard with 128 keys, the minimum number of
port lines required for interfacing is ………………. Assume that each of the
row/column junctions has a key connected.
Correct answer is 24.
The possible configurations are 128 x 1, 64 x 2, 32 x 4, and 16 x 8. The
number of port lines required in each case will be 128+1=129, 64+2=66,
32+4=36, and 16+8=24 respectively. 24 is the minimum.
8. If we apply bit stuffing on the bit stream 100011111110011111101, the
output bit stream will be:
a. 10001111110100111111001
b. 1000111111010011111101
c. 10001111111000111111001
d. None of the above
Correct answer is (a).
In bit stuffing a 0 is inserted whenever 6 consecutive 1’s are encountered.
100011111110011111101
0 inserted: 0 0
It may be noted that in some other bit stuffing systems, a 0 is inserted
after five consecutive 1’s are encountered.
9. The maximum data transfer rates supported by USB 3.0 and USB 3.1
standards are respectively:
a. 5 Mbits/sec and 10 Mbits/sec
b. 5 Gbits/sec and 10 Gbits/sec
c. 5 Gbytes/sec and 10 Gbytes/sec
d. None of the above
Correct answer is (b).
Follows from the specification of the standards.
10. A DMA controller transfers 32-bit words from an input device to memory
in one clock cycle using cycle stealing. The input device transmits data at
a rate of 9600 bytes per second. The CPU is fetching and executing
instructions at an average rate of 2,000,000 instructions per second
(assume 32-bit instructions). The CPU will be slowed down because of the
DMA transfer by …………….. percent.
Correct answer is 0.24
In 1 second, the input device transfers 9600 bytes of data.
This is equivalent to 9600 / 4 = 2400 DMA cycles, as 4 bytes are
transferred every cycle.
Earlier, in 1 second, 1,000,000 instructions were executed.
But now, in 1 second, (1,000,000 – 2400) = 997600 instructions are
executed.
So, slowdown = 2400/1000000 = 0.24 %

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