The Processor Design – A Multicycle Approach

• The Processor and Main Memory System are still the same

Address
Data
Control

CPU Memory
• However, CPU will be designed differently
• Will use the same blocks but somewhat differently
• We will focus on reuse of blocks and adjust timing

These slides are based on the course taught by Dr. Somani at Iowa State University using
the textbook by Patterson and Hennessey titled “Computer Organization and Design.” It uses
a combination of slides provide with the teaching aids with the book and their variation
created by Dr. Somani over multiple years, before and after the adoption of the book.

Simple Implementation

• Include the functional units we need for each instruction

MemWrite
Instruction
address

PC Address Read
Instruction Add Sum data 16 32
Sign
Instruction extend
Write Data
memory data memory

a. Instruction memory b. Program counter c. Adder MemRead

a. Data memory unit b. Sign-extension unit

ALU control
5 Read 3
register 1
Read
Register 5 data 1
Read
numbers register 2 Zero
Registers Data ALU ALU
5 Write result
register
Read
Write data 2
Data data

RegWrite

a. Registers b. ALU

2
 A Single-Cycle Datapath for Basic Instructions

• Lw, Sw, Add, Sub, And, Or, Slt can be performed

• For j (jump) we need an additional multiplexor
PCSrc

1
Add M
u
x
4 ALU 0
Add result
RegWrite Shift
left 2

Instruction [25–21] Read

Read register 1 Read MemWrite
PC data 1
address Instruction [20–16] Read MemtoReg
ALUSrc
Instruction register 2 Zero
1 Read ALU ALU
[31–0] Write data 2 1 Read
M result Address 1
u register M data
Instruction Instruction [15–11] x u M
memory Write x u
0 data Registers 0
x
Write Data 0
RegDst data memory
Instruction [15–0] 16 Sign 32
extend ALU MemRead
control
Instruction [5–0]

ALUOp

Where we are headed

• Single Cycle Problems:

– what if we had a more complicated instruction like floating point?
– wasteful of area
• One Solution:
– use a “smaller” cycle time and use different numbers of cycles
for each instruction using a “multicycle” datapath:

Instruction
register
Data
PC Address
A
Register #
Instruction
Memory or data Registers ALU ALUOut
Memory Register #
data B
Data register Register #

4
 MIPS Instruction Format Again

31 26 25 21 20 16 15 11 10 6 5 0

REG 1 REG 2 LOAD ADDRESS OFFSET

LW

31 26 25 21 20 16 15 11 10 6 5 0

REG 1 REG 2 STORE ADDRESS OFFSET

SW

31 26 25 21 20 16 15 11 10 6 5 0

R-TYPE REG 1 REG 2 DST SHIFT AMOUNT ADD/AND/OR/SLT

31 26 25 21 20 16 15 11 10 6 5 0

BEQ/BNE REG 1 REG 2 BRANCH ADDRESS OFFSET

31 26 25 21 20 16 15 11 10 6 5 0

JUMP/JR/JAL JUMP ADDRESS

Operation for Each Instruction

LW: SW: R-Type: BR-Type: JMP-Type:

1. READ INST 1. READ INST 1. READ INST 1. READ INST 1. READ
INST
2. READ REG 1 2. READ REG 1 2. READ REG 1 2. READ REG 1 2. READ
REG 1
READ REG 2 READ REG 2 READ REG 2 READ REG 2
READ REG
3. ADD REG 1 + 3. ADD REG 1 + 3. OPERATE on 3. SUB REG 2
2
OFFSET OFFSET REG 1 / REG 2 from REG 1
WRITE PC
4. READ MEM 4. WRITE MEM 4. WRITE DST Write into PC if
REG successful
3.
5. WRITE REG2

4.

5
6
 Multicycle Approach

• We will be reusing functional units

– Break up the instruction execution in smaller steps
– Each functional unit is used for a specific purpose in one cycle
– Balance the workload
– ALU used to compute address and to increment PC
– Memory used for instruction and data
• At the end of cycle, store results to be used again
– Need additional registers
• Our control signals will not be determined solely by instruction
– e.g., what should the ALU do for a “subtract” instruction?
• We’ll use a finite state machine for control

Multi-Cycle DataPath Operation

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
RD2 M
U WA WD R 4
U
Add X X
15-11 BR
MEM Data COND
Out D Sign Shift
15-00
R Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

8
 Five Execution Steps

• Instruction Fetch

• Instruction Decode and Register Fetch

• Execution, Memory Address Computation, or Branch Completion

• Memory Access or R-type instruction completion

• Write-back step

INSTRUCTIONS TAKE FROM 3 - 5 CYCLES!

Step 1: Instruction Fetch

• Use PC to get instruction and put it in the Instruction Register.

• Increment the PC by 4 and put the result back in the PC.
• Can be described succinctly using RTL "Register-Transfer Language"

IR = Memory[PC];
PC = PC + 4;

Can we figure out the values of the control signals?

What is the advantage of updating the PC now?

10
 Step 2: Instruction Decode and Register Fetch

• Read registers rs and rt in case we need them

• Compute the branch address in case the instruction is a branch
• RTL:

A = Reg[IR[25-21]];
B = Reg[IR[20-16]];
ALUOut = PC + (sign-extend(IR[15-0]) << 2);

• We aren't setting any control lines based on the instruction type

(we are busy "decoding" it in our control logic)

11

Step 3 (instruction dependent)

• ALU is performing one of three functions, based on instruction type

• Memory Reference:

ALUOut = A + sign-extend(IR[15-0]);

• R-type:

ALUOut = A op B;

• Branch:

if (A==B) PC = ALUOut;

12
 Step 4 (R-type or memory-access)

• Loads and stores access memory

MDR = Memory[ALUOut];
or
Memory[ALUOut] = B;

• R-type instructions finish

Reg[IR[15-11]] = ALUOut;

The write actually takes place at the end of the cycle on the edge

13

Write-back step

• Reg[IR[20-16]]= MDR;

What about all the other instructions?

14
 Summary:

Action for R-type Action for memory-reference Action for Action for
Step name instructions instructions branches jumps
Instruction fetch IR = Memory[PC]
PC = PC + 4
Instruction A = Reg [IR[25-21]]
decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)
Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] II
computation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)
jump completion
Memory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]
completion ALUOut or
Store: Memory [ALUOut] = B

Memory read completion Load: Reg[IR[20-16]] = MDR

15

Multi-Cycle DataPath Operation

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
RD2 M
U WA WD R 4
U
Add X X
15-11 BR
MEM Data COND
Out D Sign Shift
15-00
R Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

16
 LW Operation on Multi-Cycle Data Path: C1

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

17

LW Operation on Multi-Cycle Data Path: C2

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

18
 LW Operation on Multi-Cycle Data Path: C3

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

19

LW Operation on Multi-Cycle Data Path: C4

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

20
 LW Operation on Multi-Cycle Data Path: C5

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

21

SW Operation on Multi-Cycle Data Path: C1

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

22
 SW Operation on Multi-Cycle Data Path: C2

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

23

SW Operation on Multi-Cycle Data Path: C3

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

24
 SW Operation on Multi-Cycle Data Path: C4

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

25

R-TYPE Operation on Multi-Cycle Data Path: C1

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

26
 R-TYPE Operation on Multi-Cycle Data Path: C2

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

27

R-TYPE Operation on Multi-Cycle Data Path: C3

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

28
 R-TYPE Operation on Multi-Cycle Data Path: C4

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

29

BR Operation on Multi-Cycle Data Path: C1

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

30
 BR Operation on Multi-Cycle Data Path: C2

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

31

BR Operation on Multi-Cycle Data Path: C3

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

32
 JUMP Operation on Multi-Cycle Data Path: C1

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

33

JUMP Operation on Multi-Cycle Data Path: C2

M
U
25-00 X

PC 25-21 M
M RA1 A
RD1 U
U 20-16 R
I RA2 REG X
X R A
FILE ALU
L
M B U
M
U WA WD RD2 R 4
U
Add X X
15-11 BR
MEM Data D COND
Out R 15-00 Sign Shift
Ext Left 2 BNE
Data In M ALU
CON BEQ
U 05-00
X
ALUOP JUMP

31-26
CONTROL

34
 Simple Questions

• How many cycles will it take to execute this code?

lw $t2, 0($t3)
lw $t3, 4($t3)
beq $t2, $t3, Label #assume not
add $t5, $t2, $t3
sw $t5, 8($t3)
Label: ...

• What is going on during the 8th cycle of execution?

• In what cycle does the actual addition of $t2 and $t3 takes
place?

35

Implementing the Control

• Value of control signals is dependent upon:

– what instruction is being executed
– which step is being performed

• Use the information we’ve accumulated to specify a finite state

machine
– specify the finite state machine graphically, or
– use micro-programming

• Implementation can be derived from specification

36
 Deciding the Control

• In each clock cycle, decide all the action that needs to be taken
• The control signal can be 0 and 1 or x (don’t care)
• Make a signal an x if you can reduce control
• An action that may destroy any useful value be not allowed
• Control Signal required
– ALU: SRC1 (1 bit), SRC2(2 bits),
– operation (Add, Sub, or from FC)
– Memory: address (I or D), read, write, data in IR or MDR
– Register File: address rt/rd, data (MDR/ALUOUT), read, write
– PC: PCwrite, PCwrite-conditional, Data (PC+4, branch, jump)
• Control signal can be implied (register file read are values in A
and B registers (actually A and B need not be registers at all)
• Explicit control vs indirect control (derived based on input like
instruction being executed, or function code field) bits

37

Graphical Specification of FSM 0

MemRead
Instruction fetch
Instruction decode/

1
register fetch

ALUSrcA = 0
IorD = 0 ALUSrcA = 0
Start IRWrite ALUSrcB = 11
ALUSrcB = 01 ALUOp = 00
- How many ALUOp = 00
PCWrite
state bits PCSource = 00
e)
)

-typ
'
EQ

(Op = 'J')

=R
will we
'B

(Op
=

Memory address ')

'SW
p

= Branch Jump
(O

computation (Op
need? 2 (Op
= 'L
W')
or
6
Execution
8
completion
9
completion

ALUSrcA = 1
ALUSrcA = 1 ALUSrcA =1 ALUSrcB = 00
ALUSrcB = 10 PCWrite
ALUSrcB = 00 ALUOp = 01
PCSource = 10
- 4 bits. ALUOp = 00 ALUOp= 10 PCWriteCond
PCSource = 01
(O
(Op = 'LW')

p
=

- Why?
'S
W
')

Memory Memory
access access R-type completion
3 5 7

RegDst = 1
MemRead MemWrite RegWrite
IorD = 1 IorD = 1 MemtoReg = 0

Write-back step
4

RegDst = 0
RegWrite
MemtoReg =1

38
 Finite State Machine: Control Implementation
PCWrite
PCWriteCond
IorD
MemRead
MemWrite
IRWrite
Control logic
MemtoReg
PCSource
ALUOp
Outputs ALUSrcB
ALUSrcA
RegWrite
RegDst

NS3
NS2
NS1
Inputs NS0
Op5

Op4

Op3

Op2

Op1

Op0

S3

S2

S1

S0
Instruction register State register
opcode field

39

Final Words on Single and Multi-Cycle Systems

• Single cycle implementation

– Simpler but slowest
– Require more hardware
• Multi-cycle
– Faster clock
– Amount of time it takes depends on instruction mix
– Control more complicated
• Exceptions and Other conditions add a lot of complexity
• Other techniques to make it faster

40