Sit8008B: Features Applications
Sit8008B: Features Applications
Sit8008B: Features Applications
Electrical Characteristics
All Min and Max limits are specified over temperature and rated operating voltage with 15 pF output load unless otherwise
stated. Typical values are at 25°C and nominal supply voltage.
Table 1. Electrical Characteristics
Parameters Symbol Min. Typ. Max. Unit Condition
Frequency Range
Output Frequency Range f 1 – 110 MHz
Frequency Stability and Aging
Frequency Stability F_stab -20 – +20 ppm Inclusive of initial tolerance at 25°C, 1st year aging at 25°C, and
variations over operating temperature, rated power supply voltage
-25 – +25 ppm
and load.
-50 – +50 ppm
Operating Temperature Range
Operating Temperature Range T_use -20 – +70 °C Extended Commercial
-40 – +85 °C Industrial
Supply Voltage and Current Consumption
Supply Voltage Vdd 1.62 1.8 1.98 V Contact SiTime for 1.5V support
2.25 2.5 2.75 V
2.52 2.8 3.08 V
2.7 3.0 3.3 V
2.97 3.3 3.63 V
2.25 – 3.63 V
Current Consumption Idd – 3.8 4.5 mA No load condition, f = 20 MHz, Vdd = 2.8V to 3.3V
– 3.7 4.2 mA No load condition, f = 20 MHz, Vdd = 2.5V
– 3.5 4.1 mA No load condition, f = 20 MHz, Vdd = 1.8V
OE Disable Current I_OD – – 4.2 mA Vdd = 2.5V to 3.3V, OE = GND, Output in high-Z state
– – 4.0 mA Vdd = 1.8V, OE = GND, Output in high-Z state
Standby Current I_std – 2.1 4.3 A ST
̅ ̅ ̅ = GND, Vdd = 2.8V to 3.3V, Output is weakly pulled down
– 1.1 2.5 A ST
̅ ̅ ̅ = GND, Vdd = 2.5V, Output is weakly pulled down
– 0.2 1.3 A ST
̅ ̅ ̅ = GND, Vdd = 1.8V, Output is weakly pulled down
Notes:
1. In OE or ST
̅ ̅ ̅ mode, a pull-up resistor of 10 kΩ or less is recommended if pin 1 is not externally driven. If pin 1 needs to be left floating, use the NC option.
2. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Note:
3. Exceeding this temperature for extended period of time may damage the device.
Note:
4. Refer to JESD51 for JA and JC definitions, and reference layout used to determine the JA and JC values in the above table.
Note:
5. Datasheet specifications are not guaranteed if junction temperature exceeds the maximum operating junction temperature.
Vdd Vout
Test Point
tr tf
4 3
Power 80% Vdd
Supply 0.1 uF 15pF 50%
1 2 (including probe
and fixture 20% Vdd
capacitance) High Pulse
Low Pulse
(TH)
(TL)
Vdd Period
OE/ST Function 1 kΩ
Note:
6. Duty Cycle is computed as Duty Cycle = TH/Period.
Timing Diagrams
Vdd Vdd
90% Vdd
50% Vdd
T_start [7] T_resume
Pin 4 Voltage No Glitch ST Voltage
during start up
CLK Output
CLK Output HZ
HZ
Vdd Vdd
50% Vdd
OE Voltage
T_oe 50% Vdd
OE Voltage
T_oe
CLK Output CLK Output
HZ
HZ
T_oe: Time to re-enable the clock output T_oe: Time to put the output in High Z mode
Figure 6. OE Enable Timing (OE Mode Only) Figure 7. OE Disable Timing (OE Mode Only)
Note:
7. SiT8008 has “no runt” pulses and “no glitch” output during startup or resume.
Performance Plots[8]
DUT1 DUT2 DUT3 DUT4 DUT5
1.8 2.5 2.8 3.0 3.3
DUT6 DUT7 DUT8 DUT9 DUT10
6.0
20
5.5 15
Frequency (ppm)
10
5.0
5
Idd (mA)
4.5 0
-5
4.0
-10
3.5 -15
-20
3.0
-40 -30 -20 -10 0 10 20 30 40 50 60 70 80
0 10 20 30 40 50 60 70 80 90 100 110
1.8 V 2.5 V 2.8 V 3.0 V 3.3 V 1.8 V 2.5 V 2.8 V 3.0 V 3.3 V
55
54
RMS period jitter (ps)
53
52
(
51
ty cyc
50
49
48
47
46
45
0 10 20 30 40 50 60 70 80 90 100 110
Frequency (MHz) Frequency (MHz)
Figure 10. RMS Period Jitter vs Frequency Figure 11. Duty Cycle vs Frequency
Figure 12. 20%-80% Rise Time vs Temperature Figure 13. 20%-80% Fall Time vs Temperature
Performance Plots[8]
1.8 V 2.5 V 2.8 V 3.0 V 3.3 V
0.9
0.8
0.7
IPJ (ps)
0.6
0.5
0.4
10 30 50 70 90 110 10 30 50 70 90 110
Figure 14. RMS Integrated Phase Jitter Random Figure 15. RMS Integrated Phase Jitter Random
(12 kHz to 20 MHz) vs Frequency[9] (900 kHz to 20 MHz) vs Frequency[9]
Notes:
8. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
9. Phase noise plots are measured with Agilent E5052B signal source analyzer. Integration range is up to 5 MHz for carrier frequencies below 40 MHz.
0
trise=0.2
trise=0.25
1
trise=0.3 Max Frequency =
-10 trise=0.35 5 x Trf_20/80
Harmonic amplitude (dB)
trise=0.4
-20 trise=0.45
-30 where Trf_20/80 is the typical value for 20%-80% rise/fall time.
-40
-50 Example 1
-60
Calculate fMAX for the following condition:
-70
-80
Vdd = 1.8V (Table 7)
1 3 5 7 9 11
Harmonic number Capacitive Load: 30 pF
Figure 16. Harmonic EMI reduction as a Function Desired Tr/f time = 3 ns
of Slower Rise/Fall Time (rise/fall time part number code = E)
fMAX = 66.666660
Jitter Reduction with Faster Rise/Fall Time
Power supply noise can be a source of jitter for the down- Part number for the above example:
stream chipset. One way to reduce this jitter is to speed up
the rise/fall time of the input clock. Some chipsets may also SiT8008IE12-18E-66.666660
require faster rise/fall time in order to reduce their sensitivity
to this type of jitter. Refer to the Rise/Fall Time Tables
(Table 7 to Table 11) to determine the proper drive strength.
Drive strength code is inserted here. Default setting is “-”
High Output Load Capability
The rise/fall time of the input clock varies as a function of
the actual capacitive load the clock drives. At any given
drive strength, the rise/fall time becomes slower as the
output load increases. As an example, for a 3.3V SiT8008
device with default drive strength setting, the typical rise/fall
time is 1 ns for 15 pF output load. The typical rise/fall time
slows down to 2.6 ns when the output load increases to 45 pF.
One can choose to speed up the rise/fall time to 1.83 ns by
then increasing the drive strength setting on the SiT8008.
Table 9. Vdd = 2.8V Rise/Fall Times Table 10. Vdd = 3.0V Rise/Fall Times
for Specific CLOAD for Specific CLOAD
Rise/Fall Time Typ (ns) Rise/Fall Time Typ (ns)
Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF Drive Strength \ CLOAD 5 pF 15 pF 30 pF 45 pF 60 pF
L 3.77 7.54 12.28 19.57 25.27 L 3.60 7.21 11.97 18.74 24.30
A 1.94 3.90 7.03 10.24 13.34 A 1.84 3.71 6.72 9.86 12.68
R 1.29 2.57 4.72 7.01 9.06 R 1.22 2.46 4.54 6.76 8.62
B 0.97 2.00 3.54 5.43 6.93 B 0.89 1.92 3.39 5.20 6.64
T 0.55 1.12 2.08 3.22 4.08 T or "‐": default 0.51 1.00 1.97 3.07 3.90
E or "‐": default 0.44 1.00 1.83 2.82 3.67 E 0.38 0.92 1.72 2.71 3.51
U 0.34 0.88 1.64 2.52 3.30 U 0.30 0.83 1.55 2.40 3.13
F 0.29 0.81 1.48 2.29 2.99 F 0.27 0.76 1.39 2.16 2.85
1.5
YXXXX
0.5
#1 #2 #2 #1
1.0
0.75
1.1
0.75 ± 0.05
1.9
YXXXX
0.7
1.2
#1 #2 #2 #1
0.9
1.4
0.75 ± 0.05
2.54
5.0 ± 0.05 2.39
#4 #3 #3 #4
0.8
3.2 ± 0.05
2.2
YXXXX
1.1
1.6
#1 #2 #2 #1
1.15
0.75 ± 0.05 1.5
5.0 ± 0.05
2.6
3.81
YXXXX
1.1
2.0
1.4
2.2
0.90 ± 0.10
Notes:
10. Top marking: Y denotes manufacturing origin and XXXX denotes manufacturing lot number. The value of “Y” will depend on the as sembly location of
the device.
11. A capacitor of value 0.1 µF or higher between Vdd and GND is required.
Ordering Information
The Part No. Guide is for reference only. To customize and build an exact part number, use the SiTime
Part Number Generator.
SiT8008BC-12-18E- 66.666660D
Packing Method
Revision Letter
Temperature Range
al, -20ºC to
Supply Voltage
Package Size
Frequency Stability
Table 13. Ordering Codes for Supported Tape & Reel Packing Method
Device Size 16 mm T&R (3ku) 16 mm T&R (1ku) 12 mm T&R (3ku) 12 mm T&R (1ku) 8 mm T&R (3ku) 8 mm T&R (1ku)
(mm x mm)
2.0 x 1.6 – – – – D E
2.5 x 2.0 – – – – D E
3.2 x 2.5 – – – – D E
5.0 x 3.2 – – T Y – –
7.0 x 5.0 T Y – – – –
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© SiTime Corporation 2014-2018. The information contained herein is subject to change at any time without notice. SiTime assumes no responsibility or liability f or any loss, damage
or defect of a Product which is caused in whole or in part by (i) use of any circuitry other than circuitry embodied in a SiTime product, (ii) misuse or abuse including static discharge, neglect
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Supplemental Information
The Supplemental Information section is not part of the datasheet and is for informational purposes only.
SiTime 1,140
IDT 38
EPSN 28
[3]
Figure 3. Electro Magnetic Susceptibility (EMS)
Unlike quartz, MEMS oscillators have excellent long Why is SiTime Best in Class:
term aging performance which is why every new SiTime On-chip regulators and internal differential
product specifies 10-year aging. A comparison is shown architecture for common mode noise rejection
in Figure 2.
MEMS resonator is paired with advanced analog
Why is SiTime Best in Class:
CMOS IC
SiTime’s MEMS resonators are vacuum sealed
using an advanced EpiSeal™ process, which
SiTime EPSN KYCA
eliminates foreign particles and improves long
term aging and reliability
Inherently better immunity of electrostatically
driven MEMS resonator
8
8
Aging ( PPM)
4 3.5 [4]
3 Figure 4. Power Supply Noise Rejection
2 1.5
0
1-Year 10-Year
[2]
Figure 2. Aging Comparison
TXC
TXC EPS CW KYCA
KYCA SLAB EpiSeal
SiTime MEMS
100.0
Vibration Sensitivity (ppb/g)
10.0
1.0
0.1
0.0
10 100 1000
Vibration Frequency (Hz) KYCA EPSN TXC CW SLAB SiTime
[5] [6]
Figure 5. Vibration Robustness Figure 6. Shock Robustness
Figure labels:
TXC = TXC
Epson = EPSN
Connor Winfield = CW
Kyocera = KYCA
SiLabs = SLAB
SiTime = EpiSeal MEMS
Notes:
1. Data source: Reliability documents of named companies.
2. Data source: SiTime and quartz oscillator devices datasheets.
3. Test conditions for Electro Magnetic Susceptibility (EMS):
According to IEC EN61000-4.3 (Electromagnetic compatibility standard)
Field strength: 3V/m
Radiated signal modulation: AM 1 kHz at 80% depth
Carrier frequency scan: 80 MHz – 1 GHz in 1% steps
Antenna polarization: Vertical
DUT position: Center aligned to antenna
Devices used in this test: