191EC321/DIGITAL LOGIC CIRCUIT

DESIGN(A-Sec)
Unit-II Combinational Logic Circuits (Test-2)

1. 1’s complement of 11100110 is ………………. (1 point)

⚫ 00011001
◯ 10000001
◯ 00011010
◯ 00000000

2. 2’s complement of binary number 0101 is ……… (1 point)

◯ 1110
◯ 1101
◯ 1111
⚫ 1011

3. A carry look ahead adder is frequently used for addition because (1 point)
◯ uses fewer gates
◯ it costs less
◯ it is more accurate
⚫ it is faster

4. A device which converts BCD to seven segments is called ……. (1 point)

⚫ Decoder
◯ Encoder
◯ Multiplexer
◯ None of these
5. The BCD number 101011 has _______ priority. (1 point)
⚫ Even
◯ Odd
◯ Undefined
◯ Both Even and Odd

6. The output of a half adder is ………. (1 point)

◯ Sum
◯ none of these
⚫ Sum and Carry
◯ Carry

7. The minimum hardware required to realize a full subtractor is (1 point)

◯ Two half subtractor and one AND gate
◯ One half subtractor and one AND gate
⚫ Two half subtractor and one OR gate
◯ One half subtractor and one OR gate

8. A full adder can be made out of ………… (1 point)

◯ two half adders
◯ two half adders and a NOT gate
◯ three half adders
⚫ two half adders and a OR gate

9. Which of the following statement is true? (1 point)

4:16 decoder can be implemented using(with enable input):

◯ Two 3:8 decoders only(each with an enable input)
◯ Five 2:4 decoders and an inverter (each with an enable input)
⚫ Two 3:8 decoders and an inverter(each with an enable input)
◯ Four 2:4 decoders only(each with an enable input)
10. Convert binary number into gray code: 100101. (1 point)
◯ 101101
◯ 001110
⚫ 110111
◯ 111001

11. Excess-3 Code is known as (1 point)

◯ Cyclic redundancy code
⚫ Self-complementing code
◯ Weighted code
◯ Algebraic code

12. Which gates are ideal for checking the parity bits? (1 point)
⚫ EX-OR
◯ AND
◯ EX-NOR
◯ NAND

13. How many 2:1 multiplexer are required to generate 2n:1 Multiplexer (1 point)
n-1
◯2
n
◯2
n+1
◯2
⚫ 2n-1

14. How Many 3 to 8 line decoders are needed to construct a 6 to 64 line decoder (1 point)
without using any other logic gates?
◯7
◯6
◯8
⚫9
15. How many multiplexer are required to generate 512:1 multiplexer? (1 point)
◯ 172
◯ 170
◯ 169
⚫ 171

16. In a 7 segment display, LEDs b and c lit up. The decimal number displayed is (1 point)
……….
◯3
⚫1
◯7
◯9

17. In a half-subtractor circuit with X and Y as inputs, the Borrow (M) and Difference (1 point)
(N = X - Y) are given by
◯ M=X'Y, N=X ⨁ Y
⚫ M=X ⨁ Y, N=X'Y
◯ M=X ⨁ Y, N=X'Y'
◯ NONE

18. BCD input 1000 is fed to a 7 segment display through a BCD to 7 segment (1 point)
decoder/driver. The segments which will lit up are ………….
◯ a, b, d
◯ a, b, c
◯ a, b, g, c, d
⚫ All

19. The output Y of a 2-bit comparator is logic 1 whenever the 2-bit input A is greater (1 point)
than the 2-bit input B. The number of combinations for which the output is logic 1,
is
 ⚫6
◯4
◯8
◯ 10

20. What is the number of selection lines required in a signal input n output (1 point)
demultiplexer (1:n DMUX)
◯n
n
◯2
◯2
⚫ log2n

21. A 4-bit carry lookahead adder, which adds two 4-bit numbers, is designed using (2 points)
AND, OR, NOT, NAND, NOR gates only. Assuming that all the inputs are
available in both complemented and uncomplemented forms and the delay of each
gate is one time unit, what is the overall propagation delay of the adder? Assume
that the carry network has been implemented using two-level AND-OR logic.
⚫ 4 Time Units
◯ 7 Time Units
◯ 6 Time Units
◯ 5 Time Units

22. An even parity checker indicates a parity error for which of the following received (2 points)
data and parity bit?
⚫ Data =1110000 , Parity=0
◯ Data =1100111 , Parity=1
◯ Data =1001001 , Parity=1
◯ Data =1111110 , Parity=0

23. A circuit outputs a digit in the form of 4 bits. 0 is represented by 0000, 1 by 0001, (2 points)
..., 9 by 1001. A combinational circuit is to be designed which takes these 4 bits as
input and outputs 1 if the digit ≥ 5, and 0 otherwise. If only AND, OR and NOT
gates may be used, what is the minimum number of gates required?
 ◯4
◯2
⚫3
◯5

24. Consider the following combinational function block involving four Boolean (2 points)
variables x, y, a, b where x, a, b are inputs and y is the output.f (x, y, a, b)
{
if (x is 1) y = a;
else y = b;
}
Which one of the following digital logic blocks is the most suitable for
implementing this function?
◯ Priority Encoder
◯ Flip-Flop
⚫ Multiplexer
◯ Full Adder

25. Design a combination logic circuit with three input variables that will produce a (2 points)
logic 1 output when more than one input are logic 1
◯ A'C+BC+AB'
⚫ AC+BC+AB
◯ AC'+BC+A'B
◯ AC+BC'+AB'

26. In a look-ahead carry generator, the carry generate function Gi and the carry (2 points)
propagate function Pi for inputs Ai and Bi are given by:
Pi = Ai ⨁ Bi and Gi = AiBi
The expressions for the sum bit Si and the carry bit Ci+1 of the look-ahead carry
adder are given by:
Si = Pi ⨁ Ci and Ci+1 = Gi + PiCi , where C0 is the input carry.
Consider a two-level logic implementation of the look-ahead carry generator.
Assume that all Pi and Gi are available for the carry generator circuit and that the
AND and OR gates can have any number of inputs. The number of AND gates
and OR gates needed to implement the look-ahead carry generator for a 4-bit
adder with S3, S2, S1, S0 and C4 as its outputs are respectively:
 ◯ 10,5
◯ 6,4
⚫ 10,4
◯ 6,3

27. Find the input expressions (I0, I1, I2, I3) of a 4:1 multiplexer for the function (2 points)
f(A,B,C,D)=Σm(0,1,3,4,6,8,10,11,12,13,15). use a and b as selection line.
◯ I0=c+d’, I1=d’, I2=c+d’, I3=c’+d
◯ I0=c’+d, I1=d, I2=c+d’, I3=c’+d
⚫ I0=c’+d, I1=d’, I2=c+d’, I3=c’+d
◯ I0=c’+d, I1=d’, I2= c’+d, I3= c+d’

28. Which of the following statements are true: A multiplexer_______________ (2 points)

1. Selects one of the several inputs and transmits it to a single output.

2. Routes the data from a single input to one of many outputs.

3. Converts parallel data into serial data.

4. Is a combinational circuit
◯ 1&2 only
◯ 2 &4 only
◯ 2, 3 &4 only
⚫ 1,3 &4 only

29. The following truth table V=1 if and only if the input is valid (2 points)
 When function does the truth table represent?
⚫ Priority encoder
◯ Encoder
◯ Decoder
◯ Multiplexer

30. For the gate in the given figure the output will be ……….. (2 points)

◯A
⚫Ā
◯0
◯1

31. When Boolen function does the circuit below realize? (2

points)
 ⚫ X'Z+XZ'
◯ XZ+X'Z'
◯ XZ
◯ X'Z+XZ

32. Consider a 4-to-1 multiplexer with two select lines S1 and S0, given below (2
points)

The minimal sum-of-products form of the Boolean expression for the output F of
 the multiplexer is
⚫ P'Q+QR'+PQ'R
◯ P'Q+QR'+PQ'R+PQ
◯ P'Q+QR'+PQ'R+PQR'
◯ P'Q+QR'+PQ'R+PQR

33. Consider the following multiplexor where I0, I1, I2, I3 are four data input lines (2 points)
selected by two address line combinations A1A0 = 00, 01, 10, 11 respectively and
f is "the output of the

multiplexer . EN is the enable input. The function f(x, y, z) implemented by the

above circuit is :
◯ NONE
◯ XY+Z
⚫ XYZ'
◯ X+YZ

34 Consider the circuit in fig shown implements (2

. points)
 ⚫ A⨁B⨁C
◯ AB+BC+CA
◯ A+B+C
◯ A'B'C+A'BC'+ABC

35. For the truth table of the given figure Y = …………. (2 points)
◯ A+B+C
⚫ B'
◯ A'
◯ A' +BC