Theme Article: Chip Design 2020

Accelerating Chip Design

With Machine Learning
Brucek Khailany, Haoxing Ren, Steve Dai,
Saad Godil, Ben Keller, Robert Kirby,
Alicia Klinefelter, Rangharajan Venkatesan,
Yanqing Zhang, Bryan Catanzaro, and
William J. Dally
NVIDIA Corporation

Abstract—Recent advancements in machine learning provide an opportunity to transform

chip design workflows. We review recent research applying techniques such as deep
convolutional neural networks and graph-based neural networks in the areas of automatic
design space exploration, power analysis, VLSI physical design, and analog design. We
also present a future vision of an AI-assisted automated chip design workflow to aid
designer productivity and automate optimization tasks.

& AS MOORE’S LAW has provided an exponential Historically, these challenges have been met
increase in chip transistor density, the unique through levels of abstraction and automation.
features we can now include in large chips are Over the last few decades, electronic design auto-
no longer predominantly limited by area con- mation (EDA) algorithms and methodologies were
straints. Instead, new capabilities are increas- developed for all aspects of chip design—design
ingly limited by the engineering effort associated verification and simulation, logic synthesis, place-
with digital design, verification, and implementa- and-route, and timing and physical signoff analy-
tion. As applications demand more performance sis. With each increase in automation, total work
and energy efficiency from specialization in the per chip has increased, but more work was off-
post-Moore’s-law era, we expect required com- loaded from manual effort to software. With
plexity and design effort to increase. machine learning (ML) transforming software in
many domains, we envision this trend continuing
with ML-based automation of EDA.
Digital Object Identifier 10.1109/MM.2020.3026231 In this article, we highlight selected work from
Date of publication 24 September 2020; date of current our research group and the community applying
version 21 October 2020. ML to chip design tasks. We also present a vision

November/December 2020 Published by the IEEE Computer Society 0272-1732 ß 2020 IEEE
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 Chip Design 2020

for a future AI-assisted design flow, where GPU an alternative is to use unsupervised learning
acceleration, neural-network predictors, and rein- techniques.
forcement learning techniques combine to auto- One traditional ML technique familiar to the
mate the VLSI design. EDA community for optimization is autotuning
methods such as Bayesian Optimization.1 It is
effective when the parameter space is small and
ML OPPORTUNITY there is less benefit from transferring learning
DL has enabled tremendous advances in many from previous experience. With more compli-
application areas, including computer vision, cated problems, methods such as deep rein-
image processing, and natural language process- forcement learning (DRL) can be used. DRL
ing. Key drivers for these successes include large selects actions to perform in an environment.
available datasets for training, large and increas- Training data are generated on the fly through
ing model sizes, and accelerated computing trial and error as reward functions from the envi-
platforms such as GPUs. With ML, rather than ronment classify results of the actions. With
implementing hand-tuned algo- enough compute resources, DRL
rithms and heuristics for each appli- methods can scale to handle a
cation area, researchers train In this article, we
highlight selected work large space of potential actions.
models using general-purpose tech- Furthermore, with a transferable
from our research
niques to learn application-specific model architecture, DRL can
group and the
functions directly from millions of community applying learn weights during training that
examples. The goal is to ultimately ML to chip design can enable direct inference or
deploy a trained model in a produc- tasks. We also present fast retraining when a model is
tion flow to make accurate infer- a vision for a future AI- applied to a new environment or
ences on previously unseen data. assisted design flow, a new design. DRL has already
where GPU been applied to various games to
acceleration, neural-
achieve super-human perfor-
network predictors,
Learning Techniques mance levels.2 These games have
and reinforcement
Supervised learning is com- learning techniques
key attributes that make them
monly used in computer vision and combine to automate suitable for DRL: they are dis-
other fields. Researchers train a the VLSI design. crete, deterministic, fully observ-
model using many thousands to mil- able Markov decision processes
lions of examples of labeled data from which it is easy to gather
from a curated dataset. A trained model can later large amounts of data. Fortunately, many EDA
be used to make an inference on new data. problems also have such attributes, and could
Depending on the application, training labels can be well suited for DRL.
come from previous work, human annotations, or
ground-truth simulator data. The model’s infer- Models
ence accuracy ultimately depends on the quality Conventional ML models such as regressions,
of the training data, so significant attention must support vector machines, and gradient-boosted
be given to curation of high-quality labeled data- trees3 have been extensively studied for use in
sets. In EDA, supervised learning has often been the VLSI design.4 These models are fast during
proposed as a fast approximation for compli- training and inference, have well-supported soft-
cated, time-consuming tools. However, training ware libraries, and are often suitable for simple
data collection is often a challenge. Although prediction and correlation tasks.
many EDA tools produce a lot of data, it is not Recently, more complex DL models based on
always labeled or must be curated to be used artificial neural networks trade off more compu-
with DL. For example, data imbalance can be a tation for improved accuracy on many classifica-
problem since labeled outlier examples can easily tion and regression tasks. They can be trained
be overlooked with common training methods. In using backpropagation during supervised or
the absence of preexisting labeled training data, unsupervised learning. DL models can also

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 Figure 1. Neural network models. (a) CNN computation in AlexNet.5 (b) Graph convolutional networks
(GCNs).6

enable applications that cannot be easily formu- represented as graphs, such as circuits, logic
lated with conventional methods. For example, netlists, or RTL intermediate representations.
multilayer perceptrons (MLPs) often consist of
several fully connected layers with nonlinear
activation functions and can provide better ML-BASED PREDICTORS FOR THE
accuracy than traditional ML models on many
CHIP DESIGN
A typical chip design spec-to-layout flow is an
classification tasks.
iterative process. Large, complex SoCs are split
Convolutional neural networks (CNNs) such
into dozens of units. Each unit proceeds through
as AlexNet [see Figure 1(a)] are a class of DL
microarchitecture, RTL design and verification,
models commonly used for image classification
logic synthesis, timing analysis, power analysis,
or computer vision tasks. Deep CNNs learn to
floorplanning, placement, clock tree synthesis
recognize features in 2-D images and to make
(CTS), routing, and final signoff. Design teams typi-
predictions from learned combinations of image
cally overlap work on these steps of the flow by
features. Whenever EDA problems can be formu-
running each of these stages on a different chip
lated as structured 2-D data with spatial correla-
revision in a pipelined manner. However, prepar-
tion of features, such as during the VLSI physical
ing a chip for tapeout still takes many iterations.
design, CNNs are quite suitable. One benefit of
Each pipeline stage can often take days of manual
CNNs is that many pretrained models are pub-
effort even with EDA tool assistance. Complete
licly available that can be retrained for EDA
iterations through an RTL-to-layout flow often
tasks. Furthermore, they are fast during training
take weeks to months for complex chips.
and inference and run efficiently on accelerated
Trained ML models can help speed time to
computing platforms such as GPUs.
tapeout by predicting downstream results in a
Recently, graph neural networks (GNNs)
chip design flow, which can reduce time per itera-
have emerged as another class of DL models.
tion or improve the quality of results (QoR) such
They are suitable when the data are more natu-
as performance, power, or area. Rather than wait-
rally represented as a graph than as structured
ing hours or days for exact results, predictions
data in a 2-D Euclidian space. One recent
can be provided in seconds. We highlight four
example is a graph convolution network [see
ways predictions can be used: microarchitectural
Figure 1(b)].6 GNNs are based on two core
design space exploration, power analysis, VLSI
ideas: graph embedding and neighbor aggrega-
physical design, and analog design.
tion. Graph embedding learns by transforming
graph nodes, edges, subgraphs, and their cor-
responding features into a lower dimensional Microarchitectural Design Space Exploration
vector space representation. Neighbor aggre- Chip designers commonly write parameter-
gation learns a node’s embedding properties ized RTL to enable varying product specifica-
from information on neighboring nodes in the tions and to allow for microarchitectural tuning
graph. We expect GNNs to be suitable to many by exploring performance, area, and power
EDA problems where data are naturally tradeoffs. With only a few parameters, the design

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 Chip Design 2020

ML models, a linear regression, XGBoost, and a

simple MLP with a single hidden layer of 100
neurons, to predict the MAGNet performance
and power when running CNN layers from real
workloads. Our training dataset was taken from
our functional verification tests, readily avail-
able from our regression runs, while real work-
loads were used as the testing set. The input
features include the workload specification
(CNN layer shapes and sizes), parameters that
Figure 2. MAGNet tuning via Bayesian
control the mapping of the CNN layer onto the
optimization.7
accelerator, and analytical performance esti-
mates. Features were normalized with a stan-
space can become quite large. For accelerators dard scaler. We leveraged a validation set to
modeled in higher level RTL generator languages tune hyperparameters, such as the number and
or mapped to RTL through high-level synthesis size of MLP layers. The resulting simple models
(HLS), tool knobs can increase potential micro- are inexpensive to train and incur negligible
architectural choices. Navigating this large runtime overhead during inference.
design space is not always tractable with a We tested the models’ R2 accuracy on layers
brute-force search, especially with limited from real image classification CNNs. R2 is a com-
machine or license resources. mon metric used to evaluate regression tasks
As an alternative approach, we developed that quantifies the proportion of variance in the
MAGNet to automatically search the design prediction. When predicting chip utilization (a
space of CNN inference accelerators.7 It contains measure of performance) directly from the input
14 tunable design-time parameters controlling features, the linear, XGBoost, and MLP models
various memory sizes, parallel function units, achieve accuracies of 75.1%, 93.8%, and 93.9%,
datapath width, datatype precision, and other respectively. The models achieve accuracies of
microarchitectural parameters. The MAGNet 77.3%, 87.5%, and 84.6%, respectively, for pre-
flow measures performance by simulating HLS- dicting power dissipation. The XGBoost and
generated RTL and analyzes power on synthe- MLP models outperform the linear model due to
sized gate-level netlists. their handling of nonlinear data. XGBoost is the
MAGNet uses Bayesian optimization (BO) to most accurate power predictor, likely from MLP
explore this complex multidimensional design overfitting on small datasets. Incorporating
space. As shown in Figure 2, the BO engine starts these predictors into the MAGNet BO framework
with random hardware parameters, then itera- can enable even faster design space exploration.
tively optimizes the objectives (throughput and
energy efficiency) of generated designs. The BO Power and IR Drop Analysis
engine learns a probabilistic model to approxi- Pre-tapeout power estimation and optimiza-
mate the objectives of various parameters based tion is a critical aspect of all chip design flows
on previously evaluated configurations. In each today. Accurate analysis requires running logic
iteration, new parameters are selected to maxi- simulations on gate-level netlists with annotated
mize the expected improvement. The approach capacitive parasitics. However, these simula-
finds a desirable energy/performance point in a tions are very slow, typically running 10–1000
small number of runs. clock cycles per second, depending on activity
More recently, we have found that ML pre- factor and design size. To provide faster yet
dictors can further improve upon the published accurate power estimates, ML models can pre-
MAGNet results by estimating objectives dict dynamic power by estimating the propaga-
directly from workload characteristics, eliminat- tion of switching activity factors through a logic
ing many iterations of simulations and logic syn- netlist without simulation. For example, PRIMAL
thesis. As a proof of concept, we trained three trained a CNN model to infer power from RTL

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 Figure 3. Mapping circuits to GNNs. (a) GRANNITE9 representation of Boolean logic—logic gates as nodes
and wires as edges. (b) ParaGraph13 representation of an inverter circuit—heterogeneous nodes for
transistors and wires, edges for connectivity.

simulation traces.8 It scaled to large (~100k gate) input features. It is trained with supervised
designs at high accuracy, although the trained learning using ground-truth simulation results as
ML models can only infer power for a new work- labels to predict the maximum IR drop for each
load on the same design. cell across all timing windows. Because its fea-
GRANNITE9 builds upon the PRIMAL flow to tures and model follow first principles from the
enable model transferability to new designs with IR drop analysis, PowerNet can then infer IR
a GNN, shown in Figure 3(a). Gate netlists are drop on designs not seen during training. It is 9%
translated into graphs with per-node (gate) and more accurate than the best previously pro-
per-edge (net) features, such as each gate’s posed ML method for vectorless IR drop predic-
intrinsic state probabilities. GNNs can learn tion and achieves a 30 speedup compared to a
from both graph and input activation features, commercial IR drop analysis tool.
and likewise GRANNITE learns from both RTL
simulation trace data and input graph (netlist) Physical Design
data. In this way, the model becomes transfer- Detailed routing is perhaps the most time-
able to both new graphs (netlists) and new work- consuming stage of a modern physical design
loads. Results show GRANNITE achieving good flow. It is difficult to determine exactly whether a
accuracy (less than 5.5% error across a diverse synthesized or placed design will be DRC viola-
set of benchmarks) for fast (<1 second) average tion free while meeting timing constraints after
power estimation on designs up to 50k gates. performing detailed routing. However, the ear-
Once designs proceed to physical design, IR lier synthesis and placement stages have the
drop analysis becomes a critical part of power most leverage on a design’s routability. There-
signoff. Excessive IR drop prevents circuits from fore, it is desirable to predict routability from
running at targeted speeds. Accurate analysis these early stages. Today’s VLSI flows use con-
requires solving large systems of linear equa- gestion and other postplacement heuristics to
tions to obtain the voltage of every node in a cir- estimate routability. However, they are often
cuit, which can take days on large designs. inaccurate and require designer intuition to rule
Multiple iterations of analysis and mitigation are out false positives and identify real problems.
desirable during a VLSI flow, but conventional Image-based DL models provide an excellent
analysis is too slow to be used in this way. opportunity to predict routability compared to
PowerNet10 overcomes this challenge by predict- prior heuristic-based approaches. For example,
ing IR drop directly from per-cell power distribu- RouteNet11 leverages a fully convolutional net-
tions. PowerNet uses each cell’s switching work (FCN) to predict postdetailed-route DRCs
power consumption during a timing window as from post-placement global routing results.

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 Chip Design 2020

Figure 4. VLSI physical design implementation flows.

Because FCNs can access global information and The advancement of AI provides a good
local window information, their predictions are opportunity to automate the analog design pro-
more accurate than prior techniques based on cess. One recent example is ParaGraph,13 a GNN
local windows or congestion heuristics. Route- that predicts layout parasitics and device
Net is particularly well suited for designs with parameters directly from circuit schematics.
macros, which can profoundly impact routabil- Postlayout parasitic prediction is key to auto-
ity. For DRC hotspot prediction, RouteNet mating analog layout generation since it can
improved accuracy by 50% compared to conges- help with schematic and layout convergence,
tion heuristics and SVM-based methods. floorplan feasibility, or QoR estimates. Para-
In some cases, routability problems can be Graph makes accurate predictions by observing
identified even earlier in the flow, after logic syn- that similar circuit topologies and transistor
thesis. CongestionNet leverages a graph atten- configurations often have similar layouts and
tion network to estimate routing congestion therefore similar parasitics. Its GNN architecture
based only on the circuit graph.12 Its predictions uses a heterogeneous graph representation [see
are possible because some routing congestion Figure 3(b)] incorporating ideas from models
problems are highly correlated with certain digi- such as GraphSage, Relational GCNs, and graph
tal circuit topologies, with characteristics that attention networks. Trained on a large dataset of
can be recognized by GNNs. Compared to using industrial circuits, ParaGraph achieves an aver-
previous metrics for predicting congestion hot- age prediction R2 of 0.772 (110% better than
spots without placement information, Conges- XGBoost) and reduces average simulation errors
tionNet provides a 29% increase in the Kendall from over 100% to 10% compared to hand heuris-
ranking correlation score. tics currently used by designers.

Analog Layout AI-ASSISTED CHIP DESIGN

Analog design, and especially analog layout, Augmenting today’s semi-automated VLSI
is a labor-intensive process still lacking high- flows with ML-based predictors can provide
quality design automation tools. One difficulty immediate benefits. Looking to the future, we
is the larger degree of freedom compared to dig- expect even larger breakthroughs to come from
ital design, which is constrained to standard deploying AI to directly optimize chip designs
cell rows. Furthermore, analog circuit QoR met- without human intervention and to augment or
rics are design dependent, whereas digital QoR replace existing best-known algorithms in EDA
metrics such as timing, area, and power are tools. We highlight several promising research
universal. directions in these areas.

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 AI-Driven Floorplanning and Placement annealing.14 With a few hours of training, a
A central challenge in a baseline physical trained RL agent produced macro placements
design flow (see Figure 4) is that the backend with better QoR than the manual design done in
VLSI tools—placement, CTS, and routing must weeks. It further has the benefit of learning from
produce final design-rule and timing clean previous experience when placing macros in
designs in deeply scaled modern process tech- future designs. However, DRL typically requires
nologies. As a result, they act as complicated thousands to millions of trials during training, so
and slow black boxes from synthesized netlists it needs fast and accurate reward functions of
to final routed designs. The tools leave the floorplan quality that are highly predictive of
designer with minimal controllability or observ- downstream QoR.
ability and (due to time and license constraints) Directly predicting accurate postroute quality
limited opportunity for experimentation. How- from floorplans and timing constraints is difficult.
ever, the probability of success with good QoR Ideally, we would like to use a fast standard-cell
is also highly dependent on hand-crafted physi- placement engine that can run quickly and be eas-
cal constraints to the backend flow provided by ily integrated into DL training frameworks. Fortu-
the designer. nately, recent work has demonstrated this
To address this, we envision an AI-driven potential with GPU-accelerated VLSI placement.
physical design flow (see Figure 4) to intelli- DREAMPlace15 casts the analytical placement
gently explore the design space of potential problem to be equivalent to training a neural net-
physical floorplans, timing and work. Implemented in PyTorch,
tool constraints, and placements. with customized key kernels for
Directly predicting
This flow can leverage fast GPU- wirelength and density computa-
accurate postroute
accelerated placers and DL-based tions, DREAMPlace demonstrated
quality from floorplans
deep QoR predictors to enable over a 30 speedup without quality
and timing constraints
thousands of fast iterations is difficult. Ideally, we degradation compared to a state-of-
within the AI-driven loop and would like to use a fast the-art multi-threaded CPU-based
avoid costly iterations through standard-cell placer. ABCDPlace16 implements
downstream black-box tools. By placement engine that VLSI detailed placement using fast
running within a DRL optimiza- can run quickly and be GPU-accelerated graph algorithms
tion loop, the AI-driven flow can easily integrated into and achieves a 16 speedup over a
automatically and quickly find DL training frameworks.
state-of-the-art sequential detailed
high-quality floorplans, timing Fortunately, recent
placer. Together, these placers can
constraints, and standard cell work has demonstrated
place 1M cell designs in less than
this potential with
placements that can achieve 1 min and 10M cell designs in sev-
GPU-accelerated VLSI
good downstream QoR, then dis- eral minutes. These runtimes are
placement.
patch those candidate place- fast enough that many trial place-
ments to the downstream CTS ments of synthesized netlists can
and routing steps. This flow is enabled by three run with reasonable machine resources as part of
key technologies: 1) DRL for physical constraint a DRL optimization loop.
optimization; 2) fast VLSI placers running on Finally, DRL needs an accurate QoR predic-
accelerated computing platforms such as GPUs; tor: fast reward functions to evaluate candidate
and 3) DL-based deep QoR predictors to classify placements based on predictions of downstream
postplacement results. routability and QoR. In a prior RL-driven macro
First, we expect that DRL could explore the placement work,14 proxy wirelength and conges-
search space of physical design knobs (macro tion estimates were used as reward functions.
placement, pin placement, aspect ratio) and tool Although such metrics are easy to attain,
settings to find optimal realizations of a given rewards that better correlate with postroute
design. For example, recent work showed that design quality are preferred. For example, a
DRL with GNNs can improve the QoR of macro- detailed router may be able to fix DRC errors,
placement over manual design or simulated but at great runtime and area cost; conversely,

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 Chip Design 2020

during timing closure steps, tools tend to con- design flows across a variety of tools. In the
sume available positive timing slack by downsiz- future, we expect ML-based approaches such as
ing gates or swapping Vt flavors to save power. DRL to be suitable for many EDA optimization
A more robust algorithm might instead predict problems, especially when modeling the exact
pressure metrics, heuristics relating to how hard objective or constraints is difficult. DRL could
the tool must work to route a group of nets or become a new general-purpose algorithm for
close timing on a specific path. Designs with EDA, just like simulated annealing, genetic algo-
high aggregate pressure would likely have poor rithms, and linear/nonlinear programming.
overall QoR, while localized hotspots of high Since DL models are optimized to run efficiently
pressure might result in difficulty with routabil- on accelerated computing systems such as
ity or timing closure. It is an open research prob- GPUs, we expect to see a virtuous cycle of
lem to see if such deep QoR predictors can be exploiting the world’s most powerful computers
trained to evaluate postplacement results. How- for designing the next generation of chips,
ever, if such predictors can be developed and which in turn will improve the performance of
combined with DRL and GPU-accelerated place- future EDA algorithms.
ment, an AI-driven physical design flow could
benefit both designer productivity and QoR.
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 10. Z. Xie et al., “PowerNet: Transferable dynamic IR drop Steve Dai is currently a Research Scientist as part
of the ASIC & VLSI Research Group at NVIDIA. His
estimation via maximum convolutional neural network,”
research interests include energy-efficient DL accel-
in Proc. 25th Asia South Pacific Des. Autom. Conf.,
eration, high-level design methodologies, and ML-
2020.
assisted EDA. Dai received the B.S. degree in electri-
11. Z. Xie et al., “RouteNet: Routability prediction for mixed- cal engineering from the University of California at
size designs using convolutional neural network,” in Los Angeles in 2011, the M.S. degree in electrical
Proc. Int. Conf. Comput. Aided Des., 2018, pp. 1–8. engineering from Stanford University in 2013, and
12. R. Kirby et al., “CongestionNet: Routing congestion the Ph.D. degree in electrical and computer engi-
prediction using deep graph neural networks,” in Proc. neering from Cornell University in 2019. Contact him
IFIP/IEEE 27th Int. Conf. Very Large Scale Integr ., at [email protected].
2019, pp. 217–222.
13. H. Ren et al., “ParaGraph: Layout parasitics and
Saad Godil is the Director of Applied Deep Learn-
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reinforcement learning,” 2020. [Online]. Available: Design. Contact him at [email protected].
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15. Y. Lin et al., “DREAMPlace: Deep learning toolkit-
Ben Keller joined the ASIC & VLSI Research
enabled GPU acceleration for modern VLSI placement,”
Group, NVIDIA Corporation, in 2017, where he works
in Proc. 56th Des. Autom. Conf., 2019, pp. 1–6.
as a Senior Research Scientist. His research inter-
16. Y. Lin et al., “ABCDPlace: Accelerated batch-based ests include digital clocking and synchronization
concurrent detailed placement on multi-threaded techniques, fine-grained adaptive voltage scaling,
CPUs and GPUs,” IEEE Trans. Comput.-Aided Des. and hardware design productivity. Keller received
Integr. Circuits Syst., early access, Feb. 4, 2020, doi: the B.S. degree in engineering from Harvey Mudd
10.1109/TCAD.2020.2971531. College in 2010 and the M.S. and Ph.D. degrees in
electrical engineering and computer sciences from
the University of California at Berkeley in 2015 and
Brucek Khailany joined NVIDIA in 2009 and is the 2017, respectively. He is an IEEE member. Contact
director of the ASIC and VLSI Research Group. He him at [email protected].
leads research into innovative design methodologies
for IC development, ML and GPU-assisted EDA, and
energy-efficient ML accelerators. Khailany received Robert Kirby is a researcher on the Applied Deep
the Ph.D. degree in electrical engineering from Stan- Learning Research team at NVIDIA. His primary
ford University and the B.S.E. degree from the Uni- research interest is in applying deep learning and
versity of Michigan. He is a senior member of the reinforcement learning methods to solve challenging
IEEE. Contact him at [email protected]. engineering problems from across the full semicon-
ductor design flow. Kirby received the B.S. degree in
electrical and computer engineering from the Univer-
Haoxing Ren is currently a Principal Research sity of Illinois at Urbana-Champaign. Contact him at
Scientist with NVIDIA. His research interests include [email protected].
machine learning applications in design automation
and GPU accelerated EDA. He received many IBM
technical achievement rewards including the IBM Cor- Alicia Klinefelter joined NVIDIA in January 2017
porate Award for his work on improving microproces- and is currently a Senior Research Scientist with the
sor design productivity. He has received the best ASIC and VLSI Research Group. Her research inter-
paper awards at ISPD’13 and DAC’19. Ren received ests include low-power circuit design, design effort
the B.S/M.S. degrees in electrical engineering from reduction techniques, and emerging verification tech-
Shanghai Jiao Tong University, the M.S. degree in com- niques for high-level languages. Klinefelter received
puter engineering from Rensselaer Polytechnic Insti- the Ph.D. degree in electrical engineering from the
tute, and the Ph.D. degree in computer engineering University of Virginia in 2015. She is a member of the
from University of Texas at Austin. He is a senior mem- IEEE and the Solid-State Circuits Society. Contact her
ber of the IEEE. Contact him at [email protected]. at [email protected].

November/December 2020
31
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 Chip Design 2020

Rangharajan Venkatesan is a Senior Research Bryan Catanzaro is VP of Applied Deep Learning

Scientist with NVIDIA. His research interests include Research with NVIDIA. He leads a team that
machine learning accelerators, low-power VLSI researches in new ways to use deep learning for VLSI
design, and SoC design methodologies. He has and computing system design, computer graphics,
served as a member of the technical program com- natural language understanding, and speech. Cata-
mittees of several leading IEEE conferences includ- nzaro received the Ph.D. degree in electrical engi-
ing International Solid-State Circuits Conference, neering and computer sciences from the University of
International Symposium on Microarchitecture, California, Berkeley. He is a member of IEEE and
Design Automation Conference, and International ACM. Contact him at [email protected].
Symposium on Low Power Electronics and Design.
Venkatesan received the B.Tech. degree in electron- William J. Dally is a Chief Scientist and the Senior
ics and communication engineering from the Vice President of Research with NVIDIA Corporation
Indian Institute of Technology in 2009 and the Ph.D. and a Professor (Research) and the former Chair of
degree in electrical and computer engineering Computer Science with Stanford University. He is a
from Purdue University in 2014. Contact him at member of the National Academy of Engineering, a
[email protected]. Fellow of the IEEE, a Fellow of the ACM, and a Fellow
of the American Academy of Arts and Sciences. He
has received the ACM Eckert-Mauchly Award, the
IEEE Seymour Cray Award, the ACM Maurice Wilkes
Award, the IEEE-CS Charles Babbage Award, and
Yanqing Zhang joined NVIDIA, Inc., in January the IPSJ FUNAI Achievement Award. He currently
2014 and is currently a Senior Research Scientist. leads projects on computer architecture, network
His research interests include machine learning for architecture, circuit design, and programming sys-
EDA applications, digital VLSI methodology, varia- tems. He has published over 250 papers in these
tion resilient digital design, and latch-based timing. areas, holds over 160 issued patents, and is an
Zhang received the Ph.D. degree in electrical engi- author of the textbooks Digital Design: A Systems
neering from the University of Virginia in 2013. He Approach, Digital Systems Engineering, and Princi-
has been an IEEE member since 2013. Contact him ples and Practices of Interconnection Networks.
at [email protected]. Contact him at [email protected].

32 IEEE Micro

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