2 Design Planning

Learning Objectives

After completing this lab, you should be able to:

 Define the core and placement row structure
 Define locations for signal, P/G and corner pads
 Insert filler pad cells
 Manually place a few macros
 Apply macro placement constraints
 Place macros and standard cells using “virtual flat
placement”
 Analyze congestion
 Create power/ground rings around groups of macros
 Complete the power/ground rings and straps using
Power Network Synthesis (PNS)
 Analyze IR drop using Power Network Analysis (PNA)
 Analyze timing

Lab Duration:
100 minutes

Design Planning Lab 2-1

Lab 2

Introduction

The purpose of this lab is for you to become familiar with the design planning
capabilities in IC Compiler. For this lab you will use a slightly larger version of
ORCA, which is at the chip-level and includes IO pad cells as well as many more
macros. This makes the design planning steps more interesting.

Answers / Solutions
There is an ANSWERS / SOLUTIONS section at the back of this lab. You are
encouraged to refer often to this section to verify your answers, or to obtain help
with the execution of some steps.

Relevant Files and Directories

All files for this lab are located in the lab2_dp directory under your home directory.

lab2_dp/

orca_lib.mw/CEL
orca_setup The ORCA design after “data setup”, saved
in Milkyway format.
design_data/ Contains the ORCA design input data
ORCA_2.v Second-pass Verilog netlist
ORCA_2.sdc Second-pass SDC timing constraints

scripts/ Contains various floorplanning scripts

2ns_pass_setup.tcl Script to perform 2nd pass data setup
connect_pg.tcl Logically connect all P/G pins to nets
insert_pad_filler.tcl Insert pad fillers
keepout.tcl Placement keepout for all macros
macro_place_cons.tcl Macro placement constraints
macro_pg_rings.tcl Create P/G rings around macro groups
opt_ctrl.tcl Timing and optimization controls
pad_cell_cons.tcl Define pad cell locations
pns.tcl Power network constraints/synthesis
preplace_macros.tcl Place three macros connected to IO pads

If you encounter problems or get stuck, a complete command script is available

to help you recover: .solutions/run.tcl
Lab 2-2 Design Planning
 Lab 2

Instructions

Task 1. Load the Design

1. Change to the lab2_dp directory, invoke IC Compiler and start the GUI:

UNIX% cd lab2_dp
UNIX% icc_shell -gui -shared_license

2. Open the orca_setup cell from the orca_lib.mw design library.

Note: This cell has gone through “data setup”.

3. Take a look at the LayoutWindow. The large greenish-blue rectangles are the
macro and IO pad cells, and the small purple rectangles in the lower left
corner (zoom in if you want to see them more clearly), are the standard cells.
All of these cells are instantiated cells in the netlist. They are all stacked on
top of each other at the origin (0,0).
4. Apply timing and optimization controls which are specified
in ./scripts/opt_ctrl.tcl:
Note: Most of these settings are discussed in the Appendix of Unit 1. Some
are discussed in later Units. Do not spend time here trying to
understand them:

source scripts/opt_ctrl.tcl

5. Switch to the Design Planning task menu in the LayoutWindow by selecting:

File  Task  Design Planning

Task 2. Initialize the Floorplan

1. The logical netlist from synthesis does not contain physical-only cells such as
power and ground pad cells or corner pad cells. You have to therefore create
these extra cells before being able to physically place them in the periphery
area of your chip. Create the corner and P/G cells and define all pad cell
positions using a provided script:
Hint: When typing use the [Tab] key for command/option/file completion.

source –echo scripts/pad_cell_cons.tcl

Look at the log output to verify that these cells have been created and
constrained without any error or warning messages.
In a separate UNIX window look at the above script to help you answer the
following questions. Check your answers against the solution in the back.
Design Planning Lab 2-3
Lab 2

Question 1. What is the command to create a pad cell called VDD_TEST

using the reference cell pvdi? (Do not run this command!)

................................................................................................

Question 2. What “side” is used to define the location of the upper-right

corner cell (cornerur)?

................................................................................................

2. Initialize the floorplan:

Select FloorplanInitialize Floorplan…
Change the Core utilization to 0.8 (80%).
Change the Core to left/right/bottom/top spacing to 30.
Click OK.
3. Fit [F] the LayoutWindow and have a look at the chip‟s core and periphery
areas. The blue hash-marked rectangles outside the chip along the top edge are
the unplaced macro cells. The purple objects along the right edge are all the
standard cells.
Note: The corner cells are easily visible – look at the large blue
square that takes up the full layout view (labeled pfrelr).
There are four groups of four P/G pads placed in the middle
of each side.

4. Zoom into the periphery area of the chip and notice that the spacing between
all the pads is about equal.
Question 3. Will the pads always be spaced equally? Explain.

................................................................................................

................................................................................................

................................................................................................

5. Insert the pad fillers to fill the gaps between the pads. Depending on the
technology and library being used, this may be needed for N- or P-well and/or
for power/ground pad ring continuity. To keep the number of pad filler cells
required to a minimum, specify the larger filler cells first in the list. Otherwise,
a 1,000 um space will get filled with 200 x 5 um width cells, instead of one
1,000 um width cell. Enter the command in the box below or source the
provided script scripts/insert_pad_filler.tcl:

insert_pad_filler –cell "pfeed10000 pfeed05000 \

pfeed02000 pfeed01000 pfeed00500 pfeed00200 \
pfeed00100 pfeed00050 pfeed00010 pfeed00005"

Lab 2-4 Design Planning

 Lab 2

6. Zoom into the space between two pad cells and notice the filler cells that have
been inserted.
7. Make the “logical” connection (no physical routing) between the
power/ground signals and all power/ground pins of the I/O pads, macros and
standard cells, by executing the following script:

source –echo scripts/connect_pg.tcl

Note: There are 3 different power supplies in this design: VDD,

VDDQ and VDDO. The latter two are used in the periphery
of the chip.

8. Build the PAD area power supply ring:

create_pad_rings

Zoom into the area between the pads to see that metal routes have been added,
over the filler cells, to connect the existing power routes within each pad cell
to form continuous P/G pad rings.
9. Save the design as “floorplan_init”:

save_mw_cel –as floorplan_init

Task 3. Preplace the Macros Connected to I/O Pads

In this task you will identify the macros that are connected to I/O pad cells and you
will manually place them in the core area such that their connections to the I/O pads
are as short as possible.

1. Zoom in to see the top periphery area shown in Figure 1 below.

2. Identify macros that connect to I/O pads, as follows:
Choose Select  Cells  By Types…
Click the Uncheck All button in the top (Cell Type) section of the dialog box.
Select the Macro cell type check box.
Click the Select All button in lower left corner of the dialog box.
Click OK.
Notice that all the macros are now selected – highlighted in white.

Select the Flylines button from the top banner section of

the LayoutWindow.
In the “Show flylines” panel that appears on the right side of the window click
on the pull-down menu and choose Selected to IO and Apply.

Design Planning Lab 2-5

Lab 2

Reduce the “brightness” to 50% or less to better see the three flylines. The
three lower left macros show connections to the top IO pads.
3. Keep the “Show flylines” panel open and, if needed, adjust the viewing area
(pan/zoom) to see the picture below. If you accidentally unselect the macros
and the flylines disappear, use the [Ctrl] key to re-select the three circled
macros shown here, and the flylines will re-appear.

Figure 1. Flylines of the IO  macro connections.

4. The three macros with a direct connection to IO pad cells are called
I_CLOCK_GEN/I_PLL_PCI, I_CLOCK_GEN/I_PLL_SD and
I_CLOCK_GEN/I_CLKMUL. Hover your mouse arrow over a cell to see its
information window in the lower-left area. The two PLLs in this design should
be placed towards the top left and right corners of the chip so they are closer
to their respective clock pads.
Question 4. Which IO pad cells are these PLLs connected to?

................................................................................................

................................................................................................

Lab 2-6 Design Planning

 Lab 2

5. Now you will manually move the I_PLL_PCI macro, which is connected to
the left pad, into the core area. Keep in mind that you can use the undo
button to back track your steps.
a. Select just the I_PLL_PCI macro using Selection Tool button.

b. Select the Move/Resize Tool (M) button (may be in the left

banner of the window) to begin the moving process.
Drag the I_PLL_PCI macro to approximately the top-left corner of
the core area. Leave some room to the edges of the core.
c. With the PLL still selected, use the align functions to align the PLL to
the top and left edges of the core:
Click the Align Objects to Left button to
align it to the core‟s left edge
From the pull-down menu select the Align Objects
to Top button to align it to the core‟s top edge
The PLL is now aligned with the edges of the core.
d. To make sure that the cell is not moved by virtual
flat placement, click on the “padlock” button to
lock it down. You should see an X through the cell
now. This is an alternative to using
set_dont_touch_placement.

6. Try to move the “fixed” I_PLL_PCI macro. You should not be able to do so.
If you are able to move it, use the undo button to put it back and “fix” it in
place. Don‟t worry if you make a mistake since you will be provided with a
script to place these macros at the expected coordinates in a later step.
Use the [ESC] key as needed to return the cursor to the “select” mode.

Design Planning Lab 2-7

Lab 2

7. In the next steps you will repeat the steps above to move the other two macros
into the core area and near their respective IO pad cells. DO NOT spend too
much time on this step to get them perfectly placed. A script in the next step
will ensure correct placement:
Click on I_PLL_SD to select it.
Select and drag it to the top-right corner of the core area.
Align it to the top and right edges.
Rotate 180o  to reduce its wirelength.
Click the “padlock” button to lock it down.

Select and drag I_CLKMUL to the left side of I_PLL_SD.

Align it to the top edge.
From the”Rotate” pull-down menu select Y-axis to mirror along the Y-
direction (= flip in the X-direction) to reduce the wirelength.

To space I_CLKMUL 10 microns from I_PLL_SD:

Hold down the Ctrl key and select both I_CLKMUL and I_PLL_SD.
Specify a distribute offset of 10 .
Select the Distribute Objects to Right button  .
Lock down the I_CLKMUL macro.

Close the flylines panel on the right by clicking on the small “x” .

You should see an “X” in each of the three macros when they are selected.
The remaining macros will be placed concurrently with standard cells during
VF placement at a later step.
8. To ensure that the three macros are placed as expected, you can source the
following script:

source –echo scripts/preplace_macros.tcl

Lab 2-8 Design Planning

 Lab 2

Task 4. Perform Virtual Flat Placement

Normally, prior to performing virtual flat placement, any known macro placement
constraints as well as hard/soft placement blockages should be defined. We will
skip these steps initially so that you can observe the “default” VF placement
behavior. After the first placement the above constraint will be applied and VF
placement will be performed again. You will notice a marked difference.

1. Verify that the current VF placement strategy options have default settings:

report_fp_placement_strategy

Question 5. What is the current default sliver size distance?

................................................................................................

2. Apply a sliver size of 10 to prevent standard cells from being placed in narrow
channels (< 10 um) between macros:

set_fp_placement_strategy -sliver_size 10

3. Execute a timing-driven VF placement with “no hierarchy gravity” (to ensure

that the “logical hierarchy” does not affect placement of this non-hierarchical
or flat layout):

create_fp_placement –timing_driven \
–no_hierarchy_gravity

4. Examine the global route congestion map:

Click on the Global Route Congestion button .

Click the Reload button on the pop-up panel.
A dialog box appears which contains the command to be executed for
congestion analysis:
report_congestion -grc_based -by_layer \
-routing_stage global
Select “OK”.
5. An “Errors” box appears in the GUI – click OK.
If you scroll up in the log to the beginning of the congestion analysis output,
you will see an “Error” message (PSYN-348) about a macro that “is not
fixed”. You can safely ignore this. You could “fix” all macro placements prior
to the congestion analysis to avoid the PSYN-348 error. However, you will be
running create_fp_placement again to modify macro placement, so
you don‟t want fixed placement on the macros yet.

Design Planning Lab 2-9

Lab 2

You should not have any congestion issues. There are overflow GRCs but
they are scattered over the core area.
6. Close the Global Route Congestion panel on the right by clicking on the small
“x” in its upper right corner.
7. Routing of power and ground straps and macro rings for this design can be
made easier if we turn some of the macros into arrays. Source the script below
to apply macro placement constraints to accomplish the following goals:
 Place macros as close to the edges of the chip as possible
 Group macros together as much as possible
 Turn on virtual IPO to mimic timing optimization (and prevent
unnecessary placement optimization)
 Limit the legal placement orientation of some RAMs

source –echo scripts/macro_place_cons.tcl

8. Double check your settings. Suggestion: Use the up-arrow in the icc_shell
window to find and re-execute the “strategy” command:

report_fp_placement_strategy
report_fp_macro_options

9. Source the following script to set a hard keepout margin of 10 microns around
all macros. This will make it easier to create P/G rings around the macros and
avoid congestion as well as signal routing DRCs around the macros:

source –echo scripts/keepout.tcl

10. Take one last look at the macro placement before running the VF placer again:

create_fp_placement –timing_driven \
–no_hierarchy_gravity

Note: Notice that the macro placement is very different – a lot of

„grouping‟ of similar macros, except for the manually
placed ones, which are “fixed” in place.

11. Analyze the global route congestion map again. You need to click Reload 
OK to update the map. An “Error” box appears in the GUI - click OK (similar
to step5).
There should not be any congestion issues.
Close the analysis panel on the right by clicking on the small “x”.

Lab 2-10 Design Planning

 Lab 2

12. Lock down all macros:

set_dont_touch_placement [all_macro_cells]

13. Save the cell:

save_mw_cel –as floorplan_placed

Task 5. Create P/G Rings Around Macro Groups

In the task following this one you will use “Power Network Synthesis” (PNS) to
automate the creation of power/ground core and individual macro rings, as well as
vertical and horizontal straps. If you want to create rings around groups of macros,
that is done prior to PNS, which is what this task will accomplish.

1. We have created a script to create P/G rings around six groups of macros.
Take a look at the file located at ./scripts/macro_pg_rings.tcl. The P/G rings
are created by:
- Defining a rough “region” that encompasses a group of macros
- Defining the block ring layers, widths and offsets
- Creating (committing) the metal routes
2. Execute the script:

source ./scripts/macro_pg_rings.tcl

3. Take a look at the rings that have been created.

Notice that the “PLL” macro in the upper-left corner is the only macro that
does not have a P/G ring around it – this will be done by PNS.

Notice also that, in addition to the rings around the macro groups, there are
vertical/horizontal straps in between the macros. This is nice feature of the
create_fp_group_block_ring command. It can be disabled with the
–skip_strap option, if preferred.

Design Planning Lab 2-11

Lab 2

Task 6. Power Network Synthesis

The power “grid” needs to be completed. You could create P/G straps that feed the
center of the core, a core ring, as well as rings around individual macros “manually”
(similar to the way the macro group rings were created in the previous task), but to
do so would require you to guess the appropriate number and width of the straps, as
well as the width of the core ring to achieve acceptably low IR drop. Instead, you
will use IC Compiler‟s Power Network Synthesis (PNS) capability to automatically
determine the number and width of straps, as well as the core ring width, based on a
target IR drop. You can experiment with different goals, and when acceptable
results are achieved you then “commit” or physically implement the power grid.

If you are running short on time, you can source the scripts/pns.tcl to
perform steps 1-5 below. Skip steps 6-7 if you use this script.

First, you will use the PreroutePower Network Constraints menu to apply a
number of constraints for the core rings, the macro rings as well as the vertical and
horizontal straps:

1. Apply the strap constraints:

PreroutePower Network ConstraintsStrap Layers Constraints...
Note: If you don‟t see this menu switch the task menu to Design
Planning: File Task  Design Planning

Select the METAL5 Layer and set the Direction to Horizontal.

Set the “By strap number” Max to 24 and Min to 2.
Set the Width Max to 4 and the Min to 2.
Set the PG Spacing to Microns and enter 0.6.
Click the Set button.
Repeat the steps for METAL4 with direction Vertical, with the same
min/max number of straps, min/max widths, and spacing.
Set then Close the dialog.
2. Apply the core ring constraint:
PreroutePower Network ConstraintsRing Constraints...
Select METAL3 (Horizontal) and METAL2 (Vertical) for the core ring.
Select the Ring width option and choose Variable.
Set the Max to 12 and the Min to 10.

Click the Set button.

Close the dialog.

Lab 2-12 Design Planning

 Lab 2

3. Define a macro ring for the PLL macro without a ring:

PreroutePower Network Constraints Block Rings Constraints…
Select the Specified cell instances option.
In the LayoutWindow select the upper-left PLL macro.
Back in the Block Rings Power Network Constraints dialog, next to the
selected Specified cell instances radial, click the “Sets or appends
selected cells to the edit field” button to enter the selected macro cell name in
the field.
For Power Ground nets enter VDD VSS.
Set the vertical and horizontal layers to METAL4 and METAL5 respectively,
and change the width to 3 for both.
Click on Set, then Close.
4. Apply global constraints:
PreroutePower Network ConstraintsGlobal Constraints...
Keep the existing options selected.
Select the option “No routing over hard macros”.
Click on Set, then Close.
5. Invoke PNS as follows:

Open the PNS dialog using PrerouteSynthesize Power Network…

In the Synthesize power network by nets field enter: VDD VSS.
Change the Supply voltage (V) to 1.32 .
(The nominal voltage is 1.2 V; Use the maximum voltage of 1.32V)
Leave the Target IR Drop at 10% of supply voltage.
Change the Power budget (mW) to 350 (the power spec for this chip).
Under the Pads info section, select “Specified pad masters”.
Enter pv0i pvdi into the adjacent field.
Press Apply, and after some calculations you should see an IR drop map.
Question 6. What are the estimated maximum IR drops for VDD and VSS?
(look at the log output)

................................................................................................

................................................................................................

Question 7. How many horizontal and vertical VDD straps, and what
widths, were used to achieve the above IR drops? (look at the
log again)

................................................................................................

Design Planning Lab 2-13

Lab 2

6. Play with the “Target IR Drop” field to see its affect on the number and width
of the straps: Set it to “Lowest”, or set the Specified field to 100 mV, then
Apply again. Observe how the network changes, and along with it the IR drop.
7. When done experimenting, set the Target IR Drop back to 10%, then Apply.
8. Build the suggested power plan clicking on the Commit button, or by typing:

commit_fp_rail

Cancel the dialog if it is still open.

9. Zoom into your chip to see how all PG straps and rings were created.
Notice that there are no connections between the macros and the surrounding
power rings.
Notice also that there are no P/G rails along the standard cell placement rows.
10. To complete power plan we need to hook up the power pins on all macros,
and create the standard cell power rails. Execute the following commands to
accomplish this:

preroute_instances
preroute_standard_cells –fill_empty_rows \
-remove_floating_pieces

Note: The WARNING about “floating rail segments

removed” is expected because we used the
“–remove_floating_pieces” option.

11. Zoom in and notice the macro pin connections and the blue P/G rails on
metal1 (called METAL).
12. Now analyze the completed power plan using PrerouteAnalyze Power
Network…
Enter the same values for Power Ground nets (VDD VSS), Power budget
(350 mW), Supply voltage (1.32 V), and Specified pad masters (pv0i pvdi)
that were used previously for Power Network Synthesis, then press OK.
You will see another heat map.
Question 8. What are the final reported maximum VDD/VSS IR drops?
(from the log)

................................................................................................

................................................................................................

Lab 2-14 Design Planning

 Lab 2

Question 9. Can you explain why the final IR drops are smaller?

................................................................................................

................................................................................................

13. Close the PNA Voltage Drop on the right by clicking on its small “x”.
14. Save the cell:

save_mw_cel –as floorplan_pns

Task 7. Check the Timing

Now that the power plan is done, you have to perform a few more steps to complete
the placement and to verify max-delay (setup) timing.

1. If you are not able to see the standard cells in the LayoutWindow, go to the
“Visibility” panel in the left margin of the LayoutWindow, expand the “Cell”
listing by selecting the “+” sign, and make sure that “Standard” is checked.
2. PNS created many straps on METAL4 and METAL5, which were placed over
the standard cells. It can be advantageous to prevent standard cell placement
under the straps – this reduces the likelihood of congestion along the straps,
and reduces crosstalk effects on the power nets. Apply a “complete” power
net (pnet) blockage on the straps, then run the virtual flat placement again to
take pnet settings into account:

set_pnet_options -complete "METAL4 METAL5"

create_fp_placement –timing_driven \
–no_hierarchy_gravity

Verify that there are no longer any standard cells under the straps.
3. Since we are about to check timing, perform actual global routing by running
the following command:

route_zrt_global

4. Bring up the global route congestion map (no need to “Reload). There should
not be any congestion issues. Close the panel (click on small “x”).

Design Planning Lab 2-15

Lab 2

5. Generate a maximum-delay (setup) timing report using the “view” procedure

(it will take a few seconds to update the timing and generate the report):

v report_timing

Use the search mechanism to highlight or tag the word “slack”:

RE Search  type in “slack”  Tag. Scroll up/down. You should see the
words slack (MET) followed by a positive number at the end of each of
the 8 clock group paths. This design meets setup timing. Click on Close
Search then Close Window.
Question 10. Can you analyze timing without first performing an actual
global route? If so, should you?

................................................................................................

6. To fix any timing violations (and design rule violations), if there were any,
you would invoke the following command and repeat global route. Feel free
to do so, if you have the time, otherwise skip to the “Save the cell” step:

optimize_fp_timing –fix_design_rule

Repeat global routing, congestion analysis and timing analysis one last time.
The design should not have any congestion issues or timing violations.
7. Save the cell as floorplan_complete.

Task 8. Write Out the DEF Floorplan File

1. Remove all the placed standard cells then write out the floorplan file in DEF
format. The DEF floorplan file will be used by Design Compiler
Topographical to re-synthesize the design using the floorplan you just
designed, and will again be used by IC Compiler to re-create the floorplan
when reading in the re-synthesized netlist (next Task):

remove_placement -object_type standard_cell

write_def –version 5.6 –placed –all_vias –blockages \
-routed_nets –rows_tracks_gcells –specialnets \
–output design_data/ORCA.def

2. Verify that the DEF file has been created in the design_data directory.
3. Close the design library without saving the design in memory:
File  Close Library  Discard All

Lab 2-16 Design Planning

 Lab 2

Task 9. Create 2nd Pass Design Ready for Placement

We will now pretend that this design was re-synthesized from RTL code using
Design Compiler Topographical mode, along with the floorplan description
captured in the DEF file generated in the previous task. You have been given a 2 nd
pass netlist, ORCA_2.v, along with an updated constraints file, ORCA_2.sdc.

1. Perform data setup using the new ORCA netlist and constraints:

source scripts/2nd_pass_setup.tcl

This script executes the following standard data setup steps:

create_mw_lib orca_lib_2.mw -technology $tech_file \

-mw_reference_library $mw_ref_libs –open
import_designs design_data/ORCA_2.v \
-format verilog -cel ORCA -top ORCA
set_tlu_plus_files -max_tluplus $tlup_max \
-min_tluplus $tlup_min \
-tech2itf_map $tlup_map
source scripts/connect_pg.tcl
read_sdc design_data/ORCA_2.sdc
read_def design_data/ORCA_2.scandef
source scripts/opt_ctrl.tcl

2. Read the DEF file that was written out in the previous task:

read_def design_data/ORCA.def

Note: You should now see the same floorplan that you designed in
the previous tasks.

3. Re-apply the pnet options that you applied after Power Network Synthesis in
Task 6, step 1. These settings are not captured in the DEF file:

set_pnet_options -complete "METAL4 METAL5"

4. Save the cell as ready_for_placement.

5. Exit IC Compiler.

You have completed the Design Planning lab.

Design Planning Lab 2-17

Lab 2 Answers / Solutions

Answers / Solutions

Question 1. What is the command to create a pad cell called

VDD_TEST using the reference cell pvdi?

create_cell {VDD_TEST} pvdi

Question 2. What “side” is used to define the location of the upper-right
corner cell (cornerur)?

The upper right corner is defined as “-side 2”.

Question 3. Will the pads always be spaced equally? Explain.

No. If some pads defined in the tdf file contain an “offset”

value then the offset (with respect to the bottom or left core
edge) is met first before the remaining pads are spread
equally in the remaining space. If no offsets are used then
all the pads will be spread out as close to equal as possible.
Question 4. Which IO pad cells are these PLLs connected to?

The PLLs connect to the 2nd pad cell from the top, on the
left side (pclk_iopad), and the right most on the top
(sdr_clk_iopad).
Question 5. What is the current default sliver size distance?

0.00
Question 6. What are the estimated maximum IR drops for VDD and
VSS?

From the log (Your numbers may vary slightly):

Target IR drop : 132.00 mV

Net name : VDD
IR drop of the synthesized net : 127.32 mV
...
...
Target IR drop : 132.00 mV
Net name : VSS
IR drop of the synthesized net : 127.85 mV

Note: The strap calculations are based on meeting the IR

drop constraint for VDD. By default VSS inherits the same
number and width of straps as VDD. This is why it is
possible for the VSS IR drop to be different than VDD, and
possibly even violate the ”target” (not in this case).

Lab 2-18 Design Planning

Answers / Solutions Lab 2

Question 7. How many horizontal and vertical VDD straps, and what
widths, were used to achieve the above IR drops?

From the log: (Your numbers may vary slightly)

Net name : VDD

...
Layer: metal5, Direction: Horizontal, # of Straps: 10..
The maximum width of straps: 3.000 microns
The average width of straps: 2.501 microns
Layer: metal4, Direction: Vertical, # of Straps: 10..
The maximum width of straps: 3.000 microns
The average width of straps: 2.506 microns

Question 8. What are the final reported maximum VDD/VSS IR drops?

From the log: (Your numbers may vary slightly)

Net Name: VSS

...
Maximum IR drop: 74.218 mV
...
Net Name: VDD
...
Maximum IR drop: 71.358 mV

Question 9. Can you explain why the final IR drops are smaller?

This is primarily because of the standard cell rails, which

were not present during PNS. These help to further
distribute power and reduce the overall power network
“resistance”.
Question 10. Can you analyze timing without first performing an actual
global route? If so, should you?

You can, but without the global route, timing analysis will
be based on “virtual routes” – orthogonal route estimates
without specific layer or congestion information. Virtual
routes are less accurate and correlate less well with the
detailed routes to be performed later.

Design Planning Lab 2-19

Lab 2 Answers / Solutions

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Lab 2-20 Design Planning