M27C2001

2 Mbit (256Kb x 8) UV EPROM and OTP EPROM

■ 5V ± 10% SUPPLY VOLTAGE in READ

OPERATION
■ ACCESS TIME: 55ns
■ LOW POWER CONSUMPTION: 32 32

– Active Current 30mA at 5MHz

1 1
– Standby Current 100µA
FDIP32W (F) PDIP32 (B)
■ PROGRAMMING VOLTAGE: 12.75V ± 0.25V
■ PROGRAMMING TIME: 100µs/word
■ ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
– Device Code: 61h

DESCRIPTION LCCC32W (L)

The M27C2001 is a high speed 2 Mbit EPROM of-

fered in the two ranges UV (ultra violet erase) and
OTP (one time programmable). It is ideally suited
for microprocessor systems requiring large pro-
grams and is organised as 262,144 by 8 bits.
The FDIP32W (window ceramic frit-seal package) PLCC32 (C) TSOP32 (N)
and LCCC32W (leadless chip carrier package) 8 x 20 mm
have a transparent lids which allow the user to ex-
pose the chip to ultraviolet light to erase the bit pat- Figure 1. Logic Diagram
tern. A new pattern can then be written to the
device by following the programming procedure.
For applications where the content is programmed VCC VPP
only one time and erasure is not required, the
M27C2001 is offered in PDIP32, PLCC32 and
TSOP32 (8 x 20 mm) packages.
18 8
A0-A17 Q0-Q7

P M27C2001

VSS
AI00716B

November 2000 1/17

M27C2001

Figure 2A. DIP Connections Figure 2B. LCC Connections

VPP 1 32 VCC

VCC
VPP
A12
A15
A16

A17
A16 2 31 P

P
A15 3 30 A17
A12 4 29 A14 1 32
A7 A14
A7 5 28 A13
A6 6 27 A8 A6 A13
A5 A8
A5 7 26 A9
A4 8 25 A11 A4 A9
M27C2001 A3 9 M27C2001 25 A11
A3 9 24 G
A2 10 23 A10 A2 G
A1 A10
A1 11 22 E
A0 E
A0 12 21 Q7
Q0 13 20 Q6 Q0 Q7
17
Q1 14 19 Q5

Q1
Q2
VSS
Q3
Q4
Q5
Q6
Q2 15 18 Q4
VSS 16 17 Q3
AI00718
AI00717

Figure 2C. TSOP Connections Table 1. Signal Names

A0-A17 Address Inputs

Q0-Q7 Data Outputs

A11 1 32 G
E Chip Enable
A9 A10
A8 E G Output Enable
A13 Q7
P Program
A14 Q6
A17 Q5 VPP Program Supply
P Q4
VCC Supply Voltage
VCC 8 M27C2001 25 Q3
VPP 9 (Normal) 24 VSS VSS Ground
A16 Q2
A15 Q1
A12 Q0
A7 A0
A6 A1
A5 A2
A4 16 17 A3
AI01153B

2/17
 M27C2001

Table 2. Absolute Maximum Ratings (1)

Symbol Parameter Value Unit

TA Ambient Operating Temperature (3) –40 to 125 °C

TBIAS Temperature Under Bias –50 to 125 °C

TSTG Storage Temperature –65 to 150 °C

VIO (2) Input or Output Voltage (except A9) –2 to 7 V

VCC Supply Voltage –2 to 7 V

VA9 (2) A9 Voltage –2 to 13.5 V

VPP Program Supply Voltage –2 to 14 V

Note: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings” may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating condi-
tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual-
ity documents.
2. Minimum DC voltage on Input or Output is –0.5V with possible undershoot to –2.0V for a period less than 20ns. Maximum DC
voltage on Output is VCC +0.5V with possible overshoot to VCC +2V for a period less than 20ns.
3. Depends on range.

Table 3. Operating Modes

Mode E G P A9 VPP Q7-Q0

Read VIL VIL X X VCC or VSS Data Out

Output Disable VIL V IH X X VCC or VSS Hi-Z

Program VIL V IH VIL Pulse X VPP Data In

Verify VIL VIL VIH X VPP Data Out

Program Inhibit VIH X X X VPP Hi-Z

Standby VIH X X X VCC or VSS Hi-Z

Electronic Signature VIL VIL VIH VID VCC Codes

Note: X = VIH or VIL, VID = 12V ± 0.5V.

Table 4. Electronic Signature

Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data

Manufacturer’s Code VIL 0 0 1 0 0 0 0 0 20h

Device Code VIH 0 1 1 0 0 0 0 1 61h

3/17
M27C2001

Table 5. AC Measurement Conditions

High Speed Standard
Input Rise and Fall Times ≤ 10ns ≤ 20ns

Input Pulse Voltages 0 to 3V 0.4V to 2.4V

Input and Output Timing Ref. Voltages 1.5V 0.8V and 2V

Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit

1.3V
High Speed

3V 1N914

1.5V

0V 3.3kΩ

DEVICE
Standard UNDER OUT
TEST
2.4V CL
2.0V

0.8V
0.4V
CL = 30pF for High Speed
AI01822
CL = 100pF for Standard
CL includes JIG capacitance AI01823B

Table 6. Capacitance (1) (TA = 25 °C, f = 1 MHz)

Symbol Parameter Test Condit ion Min Max Unit
C IN Input Capacitance VIN = 0V 6 pF

COUT Output Capacitance VOUT = 0V 12 pF

Note: 1. Sampled only, not 100% tested.

DEVICE OPERATION dent of device selection. Assuming that the ad-

The operating modes of the M27C2001 are listed dresses are stable, the address access time
in the Operating Modes table. A single power sup- (tAVQV) is equal to the delay from E to output
ply is required in the read mode. All inputs are TTL (tELQV). Data is available at the output after a delay
levels except for VPP and 12V on A9 for Electronic of t GLQV from the falling edge of G, assuming that
Signature. E has been low and the addresses have been sta-
ble for at least tAVQV-tGLQV.
Read Mode
Standby Mode
The M27C2001 has two control functions, both of
which must be logically active in order to obtain The M27C2001 has a standby mode which reduc-
data at the outputs. Chip Enable (E) is the power es the supply current from 30mA to 100µA. The
control and should be used for device selection. M27C2001 is placed in the standby mode by ap-
Output Enable (G) is the output control and should plying a CMOS high signal to the E input. When in
be used to gate data to the output pins, indepen- the standby mode, the outputs are in a high imped-
ance state, independent of the G input.

4/17
 M27C2001

Table 7. Read Mode DC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA

ILO Output Leakage Current 0V ≤ VOUT ≤ VCC ±10 µA

E = VIL , G = VIL,
ICC Supply Current 30 mA
IOUT = 0mA, f = 5MHz
ICC1 Supply Current (Standby) TTL E = VIH 1 mA
ICC2 Supply Current (Standby) CMOS E > VCC – 0.2V 100 µA
IPP Program Current V PP = VCC 10 µA
VIL Input Low Voltage –0.3 0.8 V
(2) Input High Voltage 2 VCC + 1 V
VIH
VOL Output Low Voltage IOL = 2.1mA 0.4 V
Output High Voltage TTL IOH = –400µA 2.4 V
VOH
Output High Voltage CMOS IOH = –100µA VCC – 0.7V V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Maximum DC voltage on Output is VCC +0.5V.

Table 8A. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C2001
Symbol Alt Parameter Test Condition -55 (3) -70 -80 -90 Unit
Min Max Min Max Min Max Min Max
Address Valid to
tAVQV tACC E = VIL , G = V IL 55 70 80 90 ns
Output Valid
Chip Enable Low to
tELQV tCE G = VIL 55 70 80 90 ns
Output Valid
Output Enable Low
tGLQV tOE E = VIL 30 35 40 40 ns
to Output Valid
Chip Enable High to
tEHQZ (2) tDF
Output Hi-Z
G = VIL 0 30 0 30 0 30 0 30 ns

Output Enable High

t GHQZ (2) tDF
to Output Hi-Z
E = VIL 0 30 0 30 0 30 0 30 ns

Address Transition to
tAXQX tOH E = VIL , G = V IL 0 0 0 0 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurement conditions.

Two Line Output Control For the most efficient use of these two control
Because EPROMs are usually used in larger lines, E should be decoded and used as the prima-
memory arrays, this product features a 2 line con- ry device selecting function, while G should be
trol function which accommodates the use of mul- made a common connection to all devices in the
tiple memory connection. The two line control array and connected to the READ line from the
function allows: system control bus. This ensures that all deselect-
ed memory devices are in their low power standby
a. the lowest possible memory power dissipation,
mode and that the output pins are only active
b. complete assurance that output bus contention when data is required from a particular memory
will not occur. device.

5/17
M27C2001

Table 8B. Read Mode AC Characteristics (1)

(TA = 0 to 70 °C or –40 to 85 °C; VCC = 5V ± 5% or 5V ± 10%; VPP = VCC)
M27C2001
Symbol Alt Parameter Test Condition -10 -12 -15/-20/-25 Unit
Min Max Min Max Min Max
Address Valid to Output
tAVQV tACC E = VIL, G = VIL 100 120 150 ns
Valid
Chip Enable Low to
tELQV tCE G = VIL 100 120 150 ns
Output Valid
Output Enable Low to
tGLQV tOE E = VIL 50 50 60 ns
Output Valid
Chip Enable High to
tEHQZ (2) tDF G = VIL 0 30 0 40 0 50 ns
Output Hi-Z
Output Enable High to
tGHQZ (2) tDF E = VIL 0 30 0 40 0 50 ns
Output Hi-Z
Address Transition to
tAXQX tOH E = VIL, G = VIL 0 0 0 ns
Output Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

Figure 5. Read Mode AC Waveforms

A0-A17 VALID VALID

tAVQV tAXQX

tEHQZ
tGLQV

tELQV tGHQZ

Hi-Z
Q0-Q7

AI00719B

System Considerations output control and by properly selected decoupling

The power switching characteristics of Advanced capacitors. It is recommended that a 0.1µF ceram-
CMOS EPROMs require careful decoupling of the ic capacitor be used on every device between VCC
devices. The supply current, ICC, has three seg- and VSS. This should be a high frequency capaci-
ments that are of interest to the system designer: tor of low inherent inductance and should be
the standby current level, the active current level, placed as close to the device as possible. In addi-
and transient current peaks that are produced by tion, a 4.7µF bulk electrolytic capacitor should be
the falling and rising edges of E. The magnitude of used between VCC and VSS for every eight devic-
the transient current peaks is dependent on the es. The bulk capacitor should be located near the
capacitive and inductive loading of the device at power supply connection point. The purpose of the
the output. The associated transient voltage peaks bulk capacitor is to overcome the voltage drop
can be suppressed by complying with the two line caused by the inductive effects of PCB traces.

6/17
 M27C2001

Table 9. Programming Mode DC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Parameter Test Condition Min Max Unit

ILI Input Leakage Current 0 ≤ V IN ≤ VIH ±10 µA

ICC Supply Current 50 mA

IPP Program Current E = VIL 50 mA

VIL Input Low Voltage –0.3 0.8 V

VIH Input High Voltage 2 VCC + 0.5 V

VOL Output Low Voltage IOL = 2.1mA 0.4 V

VOH Output High Voltage TTL IOH = –400µA 2.4 V

VID A9 Voltage 11.5 12.5 V
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.

Table 10. Programming Mode AC Characteristics (1)

(TA = 25 °C; VCC = 6.25V ± 0.25V; VPP = 12.75V ± 0.25V)
Symbol Alt Parameter Test Condition Min Max Unit
tAVPL tAS Address Valid to Program Low 2 µs

tQVPL tDS Input Valid to Program Low 2 µs

tVPHPL tVPS VPP High to Program Low 2 µs

t VCHPL tVCS VCC High to Program Low 2 µs

tELPL tCES Chip Enable Low to Program Low 2 µs

tPLPH tPW Program Pulse Width 95 105 µs

tPHQX tDH Program High to Input Transition 2 µs

tQXGL tOES Input Transition to Output Enable Low 2 µs

tGLQV tOE Output Enable Low to Output Valid 100 ns

tGHQZ (2) tDFP Output Enable High to Output Hi-Z 0 130 ns

Output Enable High to Address

tGHAX tAH 0 ns
Transition
Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after V PP.
2. Sampled only, not 100% tested.

Programming light (UV EPROM). The M27C2001 is in the pro-

When delivered (and after each erasure for UV gramming mode when V PP input is at 12.75V, E is
EPROM), all bits of the M27C2001 are in the ’1’ at V IL and P is pulsed to VIL. The data to be pro-
state. Data is introduced by selectively program- grammed is applied to 8 bits in parallel to the data
ming ’0’s into the desired bit locations. Although output pins. The levels required for the address
only ’0’s will be programmed, both ’1’s and ’0’s can and data inputs are TTL. VCC is specified to be
be present in the data word. The only way to 6.25V ± 0.25V.
change a ’0’ to a ’1’ is by die exposure to ultraviolet

7/17
M27C2001

Figure 6. Programming and Verify Modes AC Waveforms

A0-A17 VALID

tAVPL

Q0-Q7 DATA IN DATA OUT

tQVPL tPHQX

VPP

tVPHPL tGLQV tGHQZ

VCC

tVCHPL tGHAX

tELPL

P
tPLPH tQXGL

PROGRAM VERIFY
AI00720

Figure 7. Programming Flowchart PRESTO II Programming Algorithm

PRESTO II Programming Algorithm allows the
whole array to be programmed with a guaranteed
margin, in a typical time of 26.5 seconds. Pro-
gramming with PRESTO II consists of applying a
VCC = 6.25V, VPP = 12.75V
sequence of 100µs program pulses to each byte
until a correct verify occurs (see Figure 7). During
n=0 programming and verify operation, a MARGIN
MODE circuit is automatically activated in order to
guarantee that each cell is programmed with
P = 100µs Pulse enough margin. No overprogram pulse is applied
NO
since the verify in MARGIN MODE provides the
necessary margin to each programmed cell.
++n NO Program Inhibit
= 25 VERIFY ++ Addr
Programming of multiple M27C2001s in parallel
YES YES with different data is also easily accomplished. Ex-
cept for E, all like inputs including G of the parallel
Last NO M27C2001 may be common. A TTL low level
FAIL Addr pulse applied to a M27C2001’s P input, with E low
and VPP at 12.75V, will program that M27C2001.
YES
A high level E input inhibits the other M27C2001s
CHECK ALL BYTES
from being programmed.
1st: VCC = 6V Program Verify
2nd: VCC = 4.2V
A verify (read) should be performed on the pro-
grammed bits to determine that they were correct-
AI00715C ly programmed. The verify is accomplished with E
and G at VIL, P at VIH, VPP at 12.75V and VCC at
6.25V.

8/17
 M27C2001

Electronic Signature ERASURE OPERATION (applies to UV EPROM)

The Electronic Signature (ES) mode allows the The erasure characteristics of the M27C2001 are
reading out of a binary code from an EPROM that such that erasure begins when the cells are ex-
will identify its manufacturer and type. This mode posed to light with wavelengths shorter than ap-
is intended for use by programming equipment to proximately 4000 Å. It should be noted that
automatically match the device to be programmed sunlight and some type of fluorescent lamps have
with its corresponding programming algorithm. wavelengths in the 3000-4000 Å range. Data
The ES mode is functional in the 25°C ± 5°C am- shows that constant exposure to room level fluo-
bient temperature range that is required when pro- rescent lighting could erase a typical M27C2001 in
gramming the M27C2001. To activate the ES about 3 years, while it would take approximately 1
mode, the programming equipment must force week to cause erasure when exposed to direct
11.5V to 12.5V on address line A9 of the sunlight. If the M27C2001 is to be exposed to
M27C2001 with VPP = VCC = 5V. Two identifier these types of lighting conditions for extended pe-
bytes may then be sequenced from the device out- riods of time, it is suggested that opaque labels be
puts by toggling address line A0 from VIL to VIH. All put over the M27C2001 window to prevent unin-
other address lines must be held at V IL during tentional erasure. The recommended erasure pro-
Electronic Signature mode. Byte 0 (A0 = VIL) rep- cedure for the M27C2001 is exposure to short
resents the manufacturer code and byte 1 wave ultraviolet light which has wavelength of
(A0 = VIH) the device identifier code. For the 2537 Å. The integrated dose (i.e. UV intensity x
STMicroelectronics M27C2001, these two identifi- exposure time) for erasure should be a minimum
er bytes are given in Table 4 and can be read-out of 15 W-sec/cm2. The erasure time with this dos-
on outputs Q7 to Q0. age is approximately 15 to 20 minutes using an ul-
traviolet lamp with 12000 µW/cm2 power rating.
The M27C2001 should be placed within 2.5 cm (1
inch) of the lamp tubes during the erasure. Some
lamps have a filter on their tubes which should be
removed before erasure.

9/17
M27C2001

Table 11. Ordering Information Scheme

Example: M27C2001 -55 X C 1 X

Device Type
M27

Supply Voltage
C = 5V

Device Function
2001 = 2 Mbit (256Kb x 8)

Speed
-55 (1)= 55 ns
-70 = 70 ns
-80 = 80 ns
-90 = 90 ns
-10 = 100 ns

Not For New Design (2)

-12 = 120 ns
-15 = 150 ns
-20 = 200 ns
-25 = 250 ns

V CC Tolerance
X = ± 5%
blank = ± 10%

Package
F = FDIP32W
B = PDIP32
L = LCCC32W
C = PLCC32
N = TSOP32: 8 x 20 mm

Temperature Range
1 = 0 to 70 °C
6 = –40 to 85 °C

Optio ns
X = Additional Burn-in
TR = Tape & Reel Packing

Note: 1. High Speed, see AC Characteristics section for further information.

2. These speeds are replaced by the 100ns.

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this de-
vice, please contact the STMicroelectronics Sales Office nearest to you.

10/17
 M27C2001

Table 12. Revision History

Date Revision Details
June 1998 First Issue

09/20/00 AN620 Reference removed

11/29/00 PLCC codification changed (Table 11)

11/17
M27C2001

Table 13. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A 5.72 0.225
A1 0.51 1.40 0.020 0.055
A2 3.91 4.57 0.154 0.180
A3 3.89 4.50 0.153 0.177
B 0.41 0.56 0.016 0.022
B1 1.45 – – 0.057 – –
C 0.23 0.30 0.009 0.012
D 41.73 42.04 1.643 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.06 13.36 0.514 0.526
e 2.54 – – 0.100 – –
eA 14.99 – – 0.590 – –
eB 16.18 18.03 0.637 0.710
L 3.18 0.125
S 1.52 2.49 0.060 0.098
∅ 7.11 – – 0.280 – –
α 4° 11° 4° 11°
N 32 32

Figure 8. FDIP32W - 32 pin Ceramic Frit-seal DIP, with window, Package Outline

A2 A3 A

A1 L α
B1 B e C
eA
D2
eB
D
S
N

∅ E1 E

1
FDIPW-a

Drawing is not to scale.

12/17
 M27C2001

Table 14. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max
A – 5.08 – 0.200
A1 0.38 – 0.015 –
A2 3.56 4.06 0.140 0.160
B 0.38 0.51 0.015 0.020
B1 1.52 – – 0.060 – –
C 0.20 0.30 0.008 0.012
D 41.78 42.04 1.645 1.655
D2 38.10 – – 1.500 – –
E 15.24 – – 0.600 – –
E1 13.59 13.84 0.535 0.545
e1 2.54 – – 0.100 – –
eA 15.24 – – 0.600 – –
eB 15.24 17.78 0.600 0.700
L 3.18 3.43 0.125 0.135
S 1.78 2.03 0.070 0.080
α 0° 10° 0° 10°
N 32 32

Figure 9. PDIP32 - 32 lead Plastic DIP, 600 mils width, Package Outline

A2 A

A1 L α
B1 B e1 C
eA
D2 eB

D
S
N

E1 E

1
PDIP

Drawing is not to scale.

13/17
M27C2001

Table 15. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Mechanical Data
mm inches
Symbol
Typ Min Max Typ Min Max

A 2.28 0.090
B 0.51 0.71 0.020 0.028
D 11.23 11.63 0.442 0.458
E 13.72 14.22 0.540 0.560
e 1.27 – – 0.050 – –
e1 0.39 – 0.015 –
e2 7.62 – – 0.300 – –

e3 10.16 – – 0.400 – –
h 1.02 – – 0.040 – –
j 0.51 – – 0.020 – –
L 1.14 1.40 0.045 0.055
L1 1.96 2.36 0.077 0.093
K 10.50 10.80 0.413 0.425
K1 8.03 8.23 0.316 0.324
N 32 32

Figure 10. LCCC32W - 32 lead Leadless Ceramic Chip Carrier, Package Outline

e2
D e j x 45o

N
1
L1
K E e3 e1
B

K1

A h x 45o L

LCCCW-a

Drawing is not to scale.

14/17
 M27C2001

Table 16. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 2.54 3.56 0.100 0.140
A1 1.52 2.41 0.060 0.095
A2 0.38 0.015
B 0.33 0.53 0.013 0.021
B1 0.66 0.81 0.026 0.032
D 12.32 12.57 0.485 0.495
D1 11.35 11.56 0.447 0.455
D2 9.91 10.92 0.390 0.430
e 1.27 0.050
E 14.86 15.11 0.585 0.595
E1 13.89 14.10 0.547 0.555
E2 12.45 13.46 0.490 0.530
F 0.00 0.25 0.000 0.010
R 0.89 0.035
N 32 32
Nd 7 7
Ne 9 9
CP 0.10 0.004

Figure 11. PLCC32 - 32 lead Plastic Leaded Chip Carrier, Package Outline

D A1
D1 A2

1 N
B1

e
Ne E1 E F D2/E2
B
0.51 (.020)

1.14 (.045)

Nd A

R CP
PLCC

Drawing is not to scale.

15/17
M27C2001

Table 17. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Mechanical Data
mm inches
Symb
Typ Min Max Typ Min Max

A 1.20 0.047
A1 0.05 0.15 0.002 0.007
A2 0.95 1.05 0.037 0.041
B 0.15 0.27 0.006 0.011
C 0.10 0.21 0.004 0.008
D 19.80 20.20 0.780 0.795
D1 18.30 18.50 0.720 0.728

E 7.90 8.10 0.311 0.319

e 0.50 - - 0.020 - -
L 0.50 0.70 0.020 0.028
α 0° 5° 0° 5°
N 32 32
CP 0.10 0.004

Figure 12. TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20 mm, Package Outline
A2

1 N
e

B
N/2

D1 A
D CP

DIE

TSOP-a A1 α L
Drawing is not to scale.

16/17
 M27C2001

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in lif e support devices or systems without express written approval of STMicroelectronics.

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17/17
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