© Copr. 1949-1998 Hewlett-Packard Co.

HEWLETT-PACKARDJOURNAL
Technical Information from the Laboratories of Hewlett-Packard Company

OCTOBER 1979 Volume 30 • Number 10

Contents:

Microprocessor Lab Teaches Operation and Troubleshooting, by Barry Bronson and

Michael Slater Here's a complete course of study that's especially beneficial for those who
service today's microprocessor-based equipment.

An Economical Network Analyzer for the 4-to-1 300-MHz Range, by James P. Zellers
Thorough analysis of RF circuit behavior is now possible at low cost with this compact
instrument.

Expanding Logic Analyzer Capabilities by Means of the HP-IB, by Roben G. Wickiiff, Jr.
and Richard A. Nygaard, Jr. HP Interface Bus options enable programmed control of
logic analyzers with state-flow analysis by computers.

A Serial Data Analyzer for Locating Faults in Decentralized Digital Systems, by Robert
E. Erdmann, Jr. Tracking down faults in systems tied together by the RS-232C (V.24) data
communications bus is much simpler with this monitor-simulator.

In this Issue:
Microprocessors — those tiny computers contained on single chips of silicon or silicon-on-
sapphire — are contributing to our quality of life in more and more ways. They're in microwave
f -.<£?%•;,. i tor ovens, stereo equipment, handheld calculators, electronic games, all kinds of industrial
equipment, and some automobiles. With all these microprocessor-based products in service,
some month's bound to fail and need fixing. The product featured on this month's cover, Model
5036A Microprocessor Lab, is designed to teach service technicians how microprocessors
work and teaching to troubleshoot microcomputer systems. It's the only microprocessor teaching
a* aid methods. available that emphasizes the latest troubleshooting and service methods.
Besides service personnel, the microprocessor lab should be valuable to computer hobbyists and to technicians
and scientists in many disciplines who want to learn about microprocessors. It's designed for home study or
classroom use.
The article on page 9 is about the design of a new network analyzer, Model 8754A. Network analyzers tell
system components how electronic circuits and devices will behave as components of larger systems. For
example, and network analyzers can measure how much of the power that goes into a device is transmitted and
how much is reflected at various frequencies. Some network analyzers can measure the time relationship, or
phase shift, between the input signal and the transmitted or reflected signal. Model 8754A measures both
magnitude good phase over the frequency range of 4 to 1300 MHz. Its contributions include surprisingly good
performance for its price, and surprisingly small size for a complete network analysis system.
The HP Interface Bus, or HP-IB, is an HP-pioneered method of putting together automatic test systems by
connecting instruments to each other and to a computer or other controller. A new interface option now makes
either of become HP logic state analyzers compatible with the HP-IB (page 18). Logic state analyzers have become
important tools for designing and servicing computers and other digital systems. With the HP-IB connection,
computer power can be added to these analyzers' capabilities, opening up many new possibilities.
Described on page 23 is a new kind of logic state analyzer. Model 1 640A Serial Data Analyzer. This analyzer
can tap be a serial data link and either monitor the data traffic or pretend to be a computer or terminal talking
on the line. It's useful for troubleshooting data networks.

-fl. P. Do/an

Editorial Danielson Howard L Roberts • Managing Editor. Richard P. Dolan • Art Director, Photographer, Arvid A. Danielson
Illustrator, Nancy S. Vanderbloom • Administrative Services, Typography, Anne S. LoPresti • European Production Manager, Dick Leeksma

2 H E W L E T T - P A C K A R D J O U R N A L O C T O B E R 1 9 7 9 Â © H e w l e t t - P a c k a r d C o m p a n y 1 9 7 9 P r i n t e d i n U S A

© Copr. 1949-1998 Hewlett-Packard Co.

Microprocessor Lab Teaches Operation
and Troubleshooting
This entry level course for home study or the classroom
includes a microcomputer in a briefcase and a 20-lesson
textbook.
by Barry Bronson and Michael Slater

THE PAST FEW YEARS have seen a flood of new came clear to us that there was a strong, perhaps urgent,
products designed around microprocessors. This need to bring the service industry up to speed on micro
trend is expected to continue, with the micro processors. Drawing especially on our experience with the
processor finding its way into not only more products but 5035T Logic Lab course on digital logic,1 we established a
also a widening spectrum of applications. project team with the goal of producing a similar product
While there are many educational alternatives available (both hardware and text] to fill the gap in microprocessor
to teach engineers how to design microprocessors into training.
products, little has been done to train the people who will The goal of the new product, Model 5036A Microproces
have to repair these products. There are, for example, over sor Lab (Fig. 1 ), is to stress practical hardware and software
100,000 service technicians who will soon be confronting concepts to provide students with a strong general under
the microprocessor on a daily basis. Few of them have even standing of how a microprocessor system works. The trou
a general understanding of microprocessors. One reason for bleshooting portion presents signature analysis and other
this is that most courses on microprocessors stress design specific troubleshooting tools and techniques so that the
considerations, applications, and/or programming, but not student will be prepared to use these important new tools to
troubleshooting or functional hardware operation for repair almost any microprocessor system. Special junipers
novices. in the microprocessor lab hardware make it possible to
For years HP has been developing test instruments for the introduce a variety of typical faults into the system. The
service market that help technicians and engineers trou- student learns to troubleshoot these faults using the per
bleshoot electronic products. Serving this market, it be formance verification self-tests, diagnostics, and signature

Fig. 1. Model 5036 A Micro

processor Lab includes a key
board-controlled microcomputer
and a comprehensive textbook
that contains both text and ex
periments.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 3

© Copr. 1949-1998 Hewlett-Packard Co.

 Fig. 2. Graphics on the micro
processor board highlight function
blocks and signal flow.

analysis stimulus built into the product. started with the course and to understand the general na
The course is intended to be self-instructional, like the ture of the microprocessor lab, we have included demon
5035T Logic Lab, and to be an enjoyable experience for the stration programs permanently stored in the product to
student. The textbook is friendly and includes hands-on simulate such things as controllers and games.
experiments using industrial-quality hardware. In creating design goals for the hardware, we realized that
what was needed was a complete, but very small micro
The Hardware computer system, generalized to have as "classical" a struc
At the time the 5036A Microprocessor Lab project was ture as possible. Other aids to the student that we have
begun there were dozens of small single-board microcom included are:
puters available. For the most part, these boards were 1. A topology that is easily related to a microcomputer
merely assemblies of parts that allowed a student to pro system block diagram and schematic
gram particular microprocessor chips and see what they 2. Liberal use of graphics to highlight function blocks and
did. These boards could also be used to control an external signal flow (Fig. 2)
circuit. The boards were generally sufficient to learn the 3. The use of LED indicators on all main bus lines
basic programming and application of a particular micro 4. A programmable speaker to provide an audible output.
processor, but they were of little benefit in relating funda The speaker is used by the operating system to indicate
mental microprocessor design concepts to circuit hardware errors, and can also be used by demonstration or user
and system software, and of practically no benefit whatever programs for signaling, playing music, and the like.
in learning the techniques of hardware troubleshooting. 5. The ability to introduce hardware faults into the circuit
We also felt that many of these boards suffered from to provide realistic troubleshooting examples. The stu
monitor program personalities that varied from unfriendly dent can introduce nondestructive electrical faults by
to hostile. Since the monitor provides the human interface means of removable jumper plugs located at various
to a microcomputer and controls the storing, modifying, points on the microprocessor board. These faults simu
running, and debugging of the user's programs, we felt that late a variety of common faults that can be classified
it was important to create a monitor with a friendly person generally as either 1) stuck or open integrated circuit
ality that was logical, consistent, and tolerant of a wide inputs or outputs or 2) broken or shorted board traces.
range of operator command sequences. To help the user get Specific faults simulated are:

4 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

 Address Bus

Fig. 3. 5036A microcomputer

Input has a generalized, "classical" ar
Switches chitecture.

Shorted address bus lines were avoided in the interest of preserving a generalized or
Bad ROM output line classical system design. Fig. 3 is a block diagram of the
Stuck ALE control signal 5036A Microprocessor Lab hardware.
Bad RAM decoding
Bad address decoder Program Protection
Bad memory protect circuit Much consideration was given to protecting user pro
Stuck Ready line grams stored in read/write memory (RAM). In typical mi
Stuck Hold line croprocessor training products, relatively simple pro
Broken buffered data bus line gramming errors can result in the unintentional modifica
Shorted buffered data bus line tion or even total destruction of the user's program.
Open keyboard scan line To protect the user's program, the microprocessor lab has
Shorted keyboard/display lines. a hardware latch circuit that is automatically set by the
monitor program whenever a student's program is run. This
The Microprocessor latch protects the first three-quarters of RAM program stor
Implementing a classical microcomputer with real age area from modification. The remaining quarter of the
hardware meant that some compromise must take place, RAM is still available for data storage and the stack.
particularly in the case of the microprocessor. The Intel The microprocessor lab's power-up program performs a
8085A microprocessor was chosen for the microprocessor system self-test and memory initialization sequence when
lab because it has a straightforward and typical architecture the system is turned on. In many microcomputer systems,
and very few unusual features, and requires only a minimal common programming errors involving the microproces
amount of support hardware. Also, the 8085A is a 5V-only sor's stack pointer can cause the initialization program to
system, can be used with general-purpose peripheral cir execute, possibly wiping out the student's program. To
cuitry, and along with its predecessor the 8080, has sub prevent this, the microprocessor lab uses software interro
stantial industry acceptance. gation of the status of the memory protect latch to determine
The major feature of the 8085A that we had to design whether the product is powering-up or executing a faulty
around for instructional clarity was its multiplexed data program sequence. In the latter case an error message is
and address buses. A simple eight-bit latch was used to displayed and the user's program is preserved. Additional
separate these into two separate buses. Once this was done, memory protection is afforded by the use of two separate 5V
generic chips could be used with the processor: static power supplies, one for the memory portion of the micro
random-access read/write memories (RAMs), a read-only processor lab and the other for external circuit expansion.
memory (ROM), eight-bit latches for output ports and An accidental short on one supply does not affect the other;
eight-bit three-state buffers for input ports. Family- thus the risk of a program loss because of a hardware failure
dependent large-scale integrated-circuit peripheral chips is reduced.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 5

© Copr. 1949-1998 Hewlett-Packard Co.

Single-Step Modes processor systems and their applications. It also allows a
Because the purpose of the course was to teach a basic wide variety of students to adapt the course to their needs.
understanding of both hardware and software, two types For example, a student interested principally in trou
of single-step modes were implemented. The first mode, bleshooting microprocessor-based systems can omit the de
called hardware single-step, sets up the system to begin tailed software material and concentrate on the hardware
user program execution at a specified address and then and the troubleshooting chapters. On the other hand, a
stops all system activity at that address. The system can student whose main interest is software can skip the de
then be made to advance a single machine cycle each time tailed hardware lessons and the troubleshooting section.
the HDWR STEP key is pressed. Address, data, and control Because of the course's top-down structure, both of these
activities are monitored using LEDs on the address bus, data students will get a good overview of microprocessor
bus, and control lines. Thus the program instructions that hardware and software while learning the details of their
result in data transfers, branches, and other system opera particular areas of interest. A study guide, shown in Fig. 4,
tions can be visually observed as the program is executed, helps the student decide which lessons to study.
one machine cycle at a time. At any point in this sequence, The book is divided into six sections, as shown in Fig. 4.
the user can return to the system monitor program by pres Each section is divided into lessons, which are the main
sing RESET. This allows the user to examine and modify structural units of the course. There are twenty lessons in
memory, register contents, or the program itself. the complete course, each requiring l'/2 to 2l/2 hours to
In the second single-step mode, called software single- complete. Each lesson is self-contained, enhancing the
step, an entire instruction is executed, regardless of the course's modular structure.
number of machine cycles, and then system control returns Each lesson consists of text and experiments intermixed.
to the monitor program. Thus the program sequence can be Instead of placing the experiments in a separate workbook,
observed instruction-by-instruction on the display. we have included them in the text at appropriate points to
Branches, loops, and register and memory contents can be illustrate the concepts being discussed. Thus students
readily observed and modified at any point in the program. should have a microprocessor lab available as they read the
The user can conveniently alternate between these two coursebook, since they will alternate between reading and
single-step modes at any point in the program. performing experiments. Fig. 5 shows a typical page of text
As an additional aid for debugging programs, a software and Fig. 6 shows a typical page from one of the experiments.
breakpoint feature is provided. To use this feature, the user At the end of each lesson is a summary, followed by a
stores a special breakpoint instruction code at strategic quiz. This allows students to review the material learned in
points in the program. Whenever the program reaches a the lesson, and then test themselves by taking the quiz.
breakpoint instruction, microprocessor activity transfers Answers to all quiz questions are in Appendix A. By
from the user's program back to the monitor program. The
user can then examine and modify data in the registers and
memory. Execution of the user's program can then be re Hardware Softwar

sumed from that point, if desired. I. MirroprocÃ-iior Funda men 111»

Lesson 1 Introduction lo Microprt

Lesson 2 Number Systems

The Textbook Lesson 3 Solt

Among our major goals for the 5036A Microprocessor II. Introduction lo

Lab coursebook were that it be complete and easy to read, Lesson 4 Using Ihe Microprocessor Lab

L e s s o n 5 S o l l w a r e C o n c e p t s

and describe microprocessors from a practical point of L e s s o n 6 I n s i d e I h e M i c r o p r o c e s s o r

view. The aim of the course is to enable the student to III. Microprocessor Syslem Hardware

understand and troubleshoot microprocessor-based sys Lesson 7 Basic Microprocessor System Circuitry . . .

L e s s o n B A d d r e s s D e c o d i n g
tems. The course is not intended to teach system design to L e s s o n 9 M e m o r i e s a n d P e r i p h e r a l s

digital design engineers. L e s s o n 1 0 C o n t r o l C i r c u l i s

Unlike many microprocessor texts, the new textbook, IV. Programming Microprocessors

"Practical Microprocessors," takes a top-down approach.

L e s s o n 1 2 T h e I n s t r u c t i o n S e t
This approach starts by describing the big picture, and Lesson 13 Software Design Techniques

gradually works down to the details. Thus the course begins Lesson 14 Software Control ot Peripherals

by describing microprocessor applications and overall sys Lesson 15 Number Representations and Algorithms -

tem concepts. The hardware and software for typical sys V. Troubleshooting Microprocessor Systems

Lesson 16 Hand-Held Troubleshooting Tools

tems is then described, with each chapter going into suc Lesson 1 7 Signature and Logic Analyzers

cessively more detail. Lesson 18 Troubleshooting Microprocessor Systems

Four lessons are devoted to troubleshooting techniques

VI Other Microprocessors
for microprocessor-based systems. A number of specialized Lesson 20 Microprocessor Survey

tools are described, including logic probes, logic pulsers, Legend

current tracers, signature analyzers, and logic analyzers. j | •- . | [::• ;iai but helpful

General troubleshooting strategies are described and then Microprocessor Lab Study Guide

demonstrated using the fault jumpers. This enables the

student to gain actual troubleshooting experience with the Fig. 4. Study guide from textbook indicates which sections
guidance of the textbook. must be studied to learn microprocessor hardware, software,
This structure provides a clear, logical picture of micro or troubleshooting.

6 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

 I nput ports are connected in a simrtar manner, as shown in Figure 7-9. The output INPUT PORTS
of the address decoder is ANDed with READ instead of WRÃTE to generate the E X P—EX..AJ
R I*«^l
M HIE VN1N_IT>i I 1 6 - 3
port enable. The input port is an eight-line three-state driver which places the
input the on the data bus when enabled The microprocessor can read the
input signáis by performing the read operation from the appropriate address. The
Stimulus-Response Testing
processor then stores this data in one of its internal registers Using the Probe and the Pulser

D e m o n s t r a t e s h o w t i i e p u i s e r c a r - â € ¢ : = c o m -
~~e logic pulser injects a =' f
signal the a node, and the logic probe monitors tne response of other circuit nodes in the signal
propagat : n patf

PROCEDURE
I. Tracing Logic Flow
Figure Address Input Data Placed on Data Bus Whenever Microprocessor Heads Address
Assigned to Tnree-State Driver A) Clear the /¿Lab memory by turning the power off and then on Fetch the first RAM address
r — \ • — ^
Suppose that an address decoder is required to control eight I/O ports instead of ADDRESS (0800) 0800 pressing rvf] Press ':-"" to enter the hardware single-step mode at address 0800
just 7-7 Eight address decoders similar to the one in Figure 7-7 could be used, DECODING Verify since the bus LEDs are reading RAM data 00 at address 0800 The display is blank since
but there ts a simpler method. Figure 7-10 shows an address decoder which
generales select signals for addresses 3000, 3001, 3002. . . . 3007. For these eight FOR MULTIPLE the system has stopped
addresses, only the three low-order address bits (AO, A1, and A2) of the 16-bit DEVICES
B) Using the logic probe, verity logic 0 levels on the DO data bus line and the RAM enable ime
address are changed. The upper thirteen bits can therefore be decoded by a
(IC5-8) This tells you that the RAM is enabled and that the data present on its DO output isO
common circuit similar to the one in Figure 7-7. The output of this circuit is used
Now insert the probe into the DO test hole (see Figure 16-10] and leave it there
to enable a decoder such as a 74LS138. This decoder then generates eight
separate outputs, one for each possible combination of AO, A1 , and A2. The
decoder is disabled all outputs are false if the upper thirteen address bits

Figure 7-10. Decoder 1C Provides Simple Way ol Extending Number oÃ- D

Fig. 5. A typical page of text from the 5036A textbook. Fig. 6. A typical experiment page from the 5036 A textbook.

answering each quiz question and reviewing the material in coursebook went through three major drafts before its final
the lesson as needed, the student can be sure of having form. This allowed us to tailor the course to the needs of
learned the important points covered in that lesson. various students, and to debug the text and experiments
A thorough set of appendices is also provided for refer thoroughly. An experienced technical writer and an ex
ence material. A complete description of the 8085 instruc perienced book editor assisted in polishing the text.
tion set is included as a programming reference. A com
Acknowledgments
prehensive glossary of microprocessor and troubleshooting
terminology is also provided. Other appendices include Many people from diverse areas of specialty contributed
signature tables, demonstration and utility programs, a to the design and development of the 5036A hardware and
complete listing of the monitor program, directions for ex text. The original product concept was inspired by Bill
panding the microprocessor lab hardware, and data sheets Cardwell, and Gary Gordon helped refine this concept
for the LSI (large-scale integrated) circuits used in the throughout the development process. Mechanical and in
hardware. Finally, an annotated bibliography tells the dustrial design was performed by Gary Schultheis and Kuni
Masuda. Endless pages of text drafts were typed by Mia
student where to find additional information on micro
Aaron and Chris Hewett. Careful technical reviews were
processor systems and troubleshooting techniques.
performed by Gary Sasaki and Ken Rothmuller, and Ed
Refining the Text and Experiments
Dwyer and Barbara Carpenter contributed considerable
Since the course is designed for self-study, it was impor writing and editing assistance. Bill Kampe and Ray Morgan
managed the production of the book, which was designed
tant to us that the text be clear and easy to understand, and
by Jodi Smith. Irene Chan was the chief illustrator. Bruce
that the experiments be as foolproof as possible. To help
Hanson provided marketing expertise, and the smooth
reach this goal, numerous people took the course at various
transition of the product from the lab to production was
stages of its development. These people were chosen to
assisted by Roy Criswell, Dick Harris, Bill Feeley, and Rich
represent a cross-section of our intended students: service
Endo.
technicians, marketing engineers, technical instructors,
supervisors, and design engineers were among the par Reference
ticipants. In addition, several experts in the field reviewed 1. J.A. Marrocco and B. Bronson, "A Quality Course in
the material for technical accuracy. As a result of the com Digital Electronics," Hewlett-Packard Journal, November
ments and criticisms that came from these reviewers, the 1974.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 7

© Copr. 1949-1998 Hewlett-Packard Co.

 Michael Slater
SPECIFICATIONS
HP Model 5036A Microprocessor Lab A native of Los Angeles, California,
Michael Slater came to HP in 1977 after
TIME BASE OUTPUT: 2 MHz ±0.05%, crystal controlled receiving his BS degree in electrical
I/O PORTS: engineering/computer science from the
OUTPUT DRIVE: Each output will drive a minimum of one LS TTL load.
University of California at Berkeley. He
INPUT LOADING: Each input equals no more than 3 LS TTL loads.
POWER SUPPLY:
contributed to the hardware design of
SUPPLY 1: 5V dc ±10%, 250 mA available for external circuitry. the microprocessor lab and is the prin
SUPPLY 2: 5V dc ±10%, 175 mA available for external circuitry. cipal author of "Practical Microproces
POWER REQUIREMENTS:! 00/1 20/220/240V ac ± 10%; 48lo66 Hz line; 50 VA maximum. sors." Two evenings a week, he
OPERATING TEMPERATURE: 0-55°C.
teaches continuing-education classes
DIMENSIONS: 514.4 mm L x 371.5 mm W x 177.8 mm H (20.25 x 14.625 x 7.0 in).
WEIGHT: Shipping: 7.7 kg (17 Ib). Net: 6.73 kg (14 Ib 10 oz). in microprocessor system design and
design for serviceability. Now a resi
Supplemental Operating Characteristics dent of Menlo Park (with his two cats),
MICROPROCESSOR: 8085A Michael's favorite leisure activities are
ROM: 231 6E; 2K byles.
organic gardening and backpacking.
RAM: Two 2114/4045's; 1K bytes.
DISPLAYS:
ADDRESS/REGISTER DISPLAY: 4 digits: 7-segment LED displays.
DATA DISPLAY: 2 digits; 7-segment LED displays.
OUTPUT PORT: 8 LED's; one per output line.
ADDRESS BUS: 16 LED's: one per line.
DATA BUS: 8 LED's; one per line.
STATUS LINES: 6 LED's; one per line.
I/O: port latched output port with LED indicators. 8-bit input port with DIP switch.
SIGNATURE ANALYSIS:
8-bit DIP switch used to disconnect MPU data lines from data bus.
"SA Loop" switch selects test loop program.
"Free-Run" switch selects free-run test mode.
TROUBLESHOOTING JUMPERS: 12 user-programmable fault jumpers on circuit board
simulate various hardware faults
TROUBLESHOOTING DOCUMENTATION: Troubleshooting tree, block diagram, schematic,
signature tables provided to determine faulty nodes.
RECOMMENDED ACCESSORIES:
Model 5024A Troubleshooting Kit (545A Probe, 546A Pulser, 547A Current Tracer, and
Vinyl Case).
Model 5004A Signature Analyzer.
PRICES IN U.S.A.:
5036A, one microprocessor system, briefcase with integral power supply, and one
copy of $990. book, "Practical Microprocessors", $800. 5024A, $625. 5004A, $990.
MANUFACTURING DIVISION: SANTA CLARA DIVISION
5301 Stevens Creek Boulevard
Santa Clara, CA 95050 U.S.A.

Barry Bronson
I Project leader for the 5036A Micro-
! processor Lab, Barry Bronson has
been with HP since 1971. He was the
principal hardware designer of the
5036A and co-author of "Practical Mi
croprocessors." A graduate of the Uni
versity of California at Los Angeles, he
received his BS degree in engineering
in 1970. His MSEE degree is from Stan
ford University (1975). Barry was pro
ject leader for the 546A Logic Pulser
and is named inventor on a patent on
that product. He was also design en
gineer forthe5035T Logic Lab, and has
! developed several automatic produc
tion test systems. Born in Los Angeles, California, Barry is married,
has two daughters, and lives in Saratoga, California. He spends his
spare time teaching a class in microprocessor design at the Univer
sity of Santa Clara, pursuing his interest in electronic projects,
photography, and stereo, and working on miscellaneous projects for
the family's recently acquired home. Fig. 7. The microprocessor lab is contained in a briefcase
that also has space for logic probes.

8 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

An Economical Network Analyzer for
the 4-to-1 300-MHz Frequency Range
777/s compact, moderately-priced instrument has a built-in
sweeping source and a two-channel receiver that
enables simultaneous swept measurements of magnitude
ratio and phase angle as well as measurements of absolute
power and reflection coefficient.

by James R. Zellers

MEASUREMENTS OF SIGNIFICANT NETWORK ranges have been limited to about 60 dB and their broad
characteristics — such as gain, phase shift, and in band inputs are sensitive to the harmonics of the driving
put/output impedance — are essential in designing source. Tuned-receiver systems, on the other hand, mea
a circuit to meet performance objectives. Swept displays of sure magnitude and phase accurately over dynamic ranges
these parameters as a function of frequency provide lucid up to 100 dB, but they have tended in the past to be complex
insights into overall circuit behavior and make the effects and expensive.
of adjustments or other circuit alterations immediately Model 8754A, pictured in Fig. 1, is a new, cost-effective
visible. Network analyzers provide this kind of display. network analyzer for RF network measurements in the
The alternatives available for swept network measure 4-to-1300-MHz frequency range. It is an all-in-one instru
ment in the HF-to-UHF range have generally been classified ment that includes a swept signal source, a dual-channel,
into two types. The most common type is the amplitude- tuned, tracking receiver, and a CRT display — all in a 51/*-
only measurement system using crystal detectors to sense inch-high cabinet. It performs measurements of magnitude
the RF power. These systems tend to be compact, easy to ratio, phase, absolute power, and polar reflection over an
operate, and relatively inexpensive but their dynamic 80-dB dynamic range. Its accuracy, versatility, and ease of

Fig. 1. Model 8754A Network

Analyzer makes swept measure
ments of absolute power, gain/
loss, phase, and reflection coeffi
cient over a frequency range of 4
to 1300MHz. Dual-channel opera
tion permits display of two
parameters simultaneously in the
rectilinear display mode, or mag
nitude and phase angle in the
polar display mode.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 9

© Copr. 1949-1998 Hewlett-Packard Co.

 Receiver

Fig. 2. Basic network analyzer

measures device characteristics
by comparing the signal entering
the device (incident) with the sig
nals leaving the device (reflected
or transmitted) and displaying the
difference in dB or degrees.

use suit it to a broad range of laboratory and production vide the interconnections required for almost any mea
applications while its compact size permits its use in the surement need in both 50fi and 75fi systems. For example,
field for measurements on devices such as antennas. Al Fig. 2 shows a typical test set-up for measuring the trans
though its cost approaches that of the moderately-priced mission gain or loss (B/R) in a filter, amplifier, or attenuator,
amplitude-only instruments, its phase-measurement capa the phase shift through the device (PHASE B/R), and the
bility, 80-dB dynamic range, and better than -80 dBm reflection coefficient (AIR). The external elements required
sensitivity, are comparable to more expensive network for this measurement (power splitter, directional bridge,
analyzer systems. and suitable attenuators and pads) are provided in the
The built-in 4-to- 13 00-MHz source has flexible sweep- Model 8502A/B Transmission/Reflection Test Sets. Also
frequency capability with less than 7-kHz residual FM, and available are a three-way power splitter that enables the
with output power calibrated to +10 dBm. The user may response of a device to be compared to a standard, an
select either a START or CENTER frequency and the fre s-parameter test set that allows transmission and reflection
quency is indicated on a SVi-digit LED display. It can sweep measurements on both ports of two-port devices, transistor
over the full 4-to-1300-MHz frequency range or provide fixtures for the s-parameter test set, and high-impedance
narrower sweep widths ranging from 1 MHz to 1 GHz. It probes for in-circuit tests (power for active probes is pro
also has a CW mode. Crystal-controlled markers provide vided at the front panel).
accurate frequency calibration. The measurement capabilities of Model 8754A are illus
The receiver has three RF inputs and two independent trated by the displays shown in Fig. 3. The display at left
display channels so that two parameters, such as gain and shows the transmission loss and input match of a 1-GHz
phase, can be viewed at the same time (on alternate sweeps) high-pass filter over a greater-than-80-dB dynamic range.
with a single test set-up. Each channel has precision offset Note that the — 30-dB source harmonics have negligible
and measurement-range controls. Equalization of differing effect on the dynamic range, a result of using a narrow-band
RF cable lengths in the measurement channels is possible tuned receiver. The display at right is a polar display of the
over a 16-cm range with built-in adjustable length compen reflection from the input of a transistor amplifier over a
sation. A polar display mode is also provided for imped 4-to-1300-MHz range. For this measurement, a Smith chart
ance measurements. overlay (supplied with the instrument) is installed on the
Since this instrument is capable of a broad range of mea face of the CRT to permit direct readout of R + jX.
surements, a number of accessories have been developed to
give the user flexibility in measurement setups. These pro

Fig. 3. Display at /eft shows the

transmission characteristics of a
1 -GHz high-pass filter measured
over a frequency range of 4 to
1300 MHz by Model 8754A. The
vertical scale is 10 dB/div. The
display at right was made in the
polar mode with a Smith chart
overlay installed on the CRT. This
shows the input impedance of a
transistor amplifier to be near 50ÃÃ
at low frequencies, becoming in
creasingly inductive at the higher
end of the 4-to- 1300-MHz mea
surement range.

10 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

Making a Measurement
When measurements are made with the 8754A, the TUN
ING control sets either the START or CENTER frequency of
the frequency sweep, as selected by the operator, and the
SWEEP WIDTH control determines the width of the fre
quency sweep. The LED frequency display, derived from
the tuning voltage, is easily calibrated to the crystal markers
by using the FREQUENCY CAL control.
To prepare the instrument for magnitude and phase mea
Fig. 5. Thin-film source has two varactor-tuned oscillators
surements, a reference line is first established on the CRT installed in separate cavities to avoid potential injection-lock
graticule by pressing the REFERENCE POSITION pushbutton problems. Between them is a modulator (in the left cavity), a
for the selected channel. As shown in Fig. 4, this discon 5-GHz low-pass filter (in the connecting channel), and a mixer.
nects any signal input to the CRT. The REFERENCE POSI
TION control may then be used as a vertical-position control to use the REFERENCE lever switch to bring the signal as
to place the displayed horizontal line where desired on the close as possible to the reference line (the lever switch adds
graticule, usually the top or center graticule line. This is the a calibrated offset to the displayed signal). The signal level
position around which the display will expand. With the may then be determined with three-digit resolution by ad
REFERENCE POSITION pushbutton released, absolute power ding the two-digit lever switch setting to the value of the
measurement may now be made by reading the value di residual displacement of the signal from the reference line,
rectly from the CRT. For higher precision, the procedure is as determined by interpolating between the CRT graticule
lines.
(Magnitude Ratio For ratio measurements, a calibration run is made with
Power
the measurement circuit connected without the test device
Phase To CRT
Vertical in the circuit. With the REFERENCE lever switch set to zero,
Channel A, B
Deflection the REFERENCE OFFSET control is used to bring the dis
Circuits played line to the reference line. The test device is then
connected and the measurement made and evaluated with
the aid of the lever switch and graticule interpolation.
Further conveniences for high-resolution measurements
can be obtained by using the 8754A with either the Model
8750A or 8501A Storage/Normalizer.1 These devices can
store the results of a calibration sweep in their digital
memories and then subtract the calibration trace from sub
sequent measurements to present a normalized trace. Fast
Uncalibrated repetitive readouts from their memories assure bright,
dc Offset flickerless displays even when sweeps are made very
slowly. An interface connector for these instruments is
provided on the rear panel of the 8754A.
Fig. 4. Offsets added to the measurement voltage enable
calibration of the CRT graticule for direct readout of power, RF Source
magnitude ratio, and phase. Extensive use of thin-film microelectronics enables the

DC Tuning

0-1.3 GHz
Output

Fig. 6. The RF output is a differ

ence frequency derived from the
two varactor-tuned microwave
oscillators.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 1 1

© Copr. 1949-1998 Hewlett-Packard Co.

Model 8754A to achieve the objective of high performance
at moderate cost in a small package. For example, the source
(Fig. a uses two thin-film varactor oscillators that have a
residual FM (7 kHz) approaching that of YIG sources but
that are considerably smaller and lower in cost.
As shown in the block diagram of Fig. 6, one varactor
oscillator sweeps up in frequency from 3.6 to 4.3 GHz and
the other sweeps down from 3.6 to 3.0 GHz. The difference
of the two frequencies is taken from a mixer and amplified
for the output. A wideband sweep is thereby obtained from
two relatively narrowband oscillators.
Each of the varactors has a nonlinear frequency-versus-
tuning-voltage characteristic. A 13-point diode shaping
network modifies each tuning-voltage ramp so the RF out
put frequency is always linear within ±2 MHz. Overall
stability is not degraded by the shaping networks and is
typically within 300 kHz/°C or 100 kHz/hour after a half-
hour warm-up.

Markers for Frequency Calibration Fig. 8. Thin-film sampler is housed in a low-cost stripline
The LED FREQUENCY display and the SWEEP WIDTH con package mounted to the printed-circuit board containing the
trol may both be calibrated with the aid of markers that preamplifier circuits.
occur at harmonics of 1, 10, or 50 MHz. The basic reference
is a 50-MHz crystal oscillator that is accurate within 0.01%. on the display.
A programmable divider yields a 1, 10, or 50-MHz square Alternatively, an external marker frequency may be
wave, according to front-panel selector pushbuttons, that is applied at a rear-panel connector. This will appear on the
shaped into harmonic-rich narrow pulses by a step- display as a single marker at the position corresponding to
recovery diode. The pulse train is mixed with a sample of the frequency of the marker. Also, when the instrument is
the RF output signal producing a zero-beat "birdie" sweeping the full 4-to-1300-MHz frequency scan, a single
whenever the RF output frequency is equal to one of the marker occurs at the frequency selected by the TUNING
pulse-train harmonics. control. This then becomes the START or CENTER frequency
The birdies are shaped into clean-looking rectangular on narrower sweeps.
pulses by the digital detector shown in Fig. 7 and added to
the video waveform applied to the CRT display for recti Swept Vector Voltmeter Receiver
linear displays, or to the Z-axis signal to give brightened The receiver uses the sampling technique to down-
pips on polar displays. The width of the marker pulses is convert the RF at each of its three inputs to a 1-MHz IF. The
controlled by the sweep width selector so they are always samplers (Fig. 8) achieve — 80-dbm sensitivity, which is
relatively narrow for most sweep widths. The calibrated about midway between the sensitivities of simple diode
marker frequency occurs at the center of each marker pulse detectors and the more expensive heterodyne-mixer sys
tems. Frequency response is within ±0.3 dB. A block dia
gram is shown in Fig. 9.
The basic sampler design was derived from the principles
D Latch
XT. used in the Model 8405A Vector Voltmeter.2 Each RF input
Marker is sampled by a four-diode gate that is switched on by
Output
repetitive 300-ps pulses. Diode isolation networks in each
pulse line (series diodes biased off, shunt diodes biased on)
prevent one RF channel from interfering with another.
Each sample is stored on a holding capacitor until the
next sample occurs. The sampling rate is automatically
controlled so each sample occurs at an earlier point on the
waveform during a subsequent recurrence of the waveform.
Fig. 7. Pulse-width discriminator generates a marker pulse
whenever the RF frequency sweeps through a harmonic of the
Hence, over a period of several waveform cycles, the
reference. The negative-going edge of the amplified mixer waveform is reconstructed on the holding capacitor. How
output (birdie) triggers a one-shot multivibrator and the ever, the reconstructed waveform has a much lower fre
positive-going edge clocks a D flip-flop. When the birdie fre quency, which makes it possible to perform precision phase
quency approaches zero, the one-shot pulse will have cleared measurements. The three pulse trains are phase-coherent so
by the time the next positive transition occurs, and a zero will the IF signals in all three channels have the same phase
be latched into the flip-flop. A marker is then generated. When relationships as the RF inputs.
the birdie frequency is high (far away from zero beat), the The sampling effect is analogous to a harmonic mixer that
one-shot will not have cleared when the flip-flop is clocked and mixes the RF input with a harmonic-rich pulse train to
no marker pulse results. In this case, the N AND gate resets the
produce an output at a frequency fRF~nfpulse> where n is a
one-shot.

12 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

 Fig. phase magnitude-ratio receiver has a reference channel (R) for phase and magnitude-ratio mea
surements anda time-shared channel. The alternate sweep switch allows two quantities, applied
through down-converted A and B inputs, to be displayed simultaneously. All three inputs are down-converted
by samplers serving as mixers.

harmonic number. wider sweeps are desired. In these cases, the analyzer func
The pulses that drive the three samplers are generated by tions in a multiband mode, switching to higher harmonics
a step-recovery diode driven by a 5-to-30-MHz voltage- of the VTO so sweeps can be continued beyond the 1%-
tuned oscillator (VTO). A 1-MHz intermediate frequency at octave limit. Digital logic controls the VTO operation, RF
the sampler outputs is maintained automatically by a sweep, and CRT display to present a continuous trace that
phase-lock loop that controls the VTO frequency. A has no gaps or transients where bandswitching occurs.
frequency/phase detector compares the output of the sam Before a sweep starts, the VTO is tuned to approximately
pler in the R channel to a 1-MHz reference (Fig. 9). The 8 MHz and the tuning adjusted to phase lock one of the VTO
resulting error voltage tunes the VTO as the RF input signal harmonics to the RF start frequency. The sweep then starts,
sweeps such that one of the VTO's harmonics is 1 MHz and the VTO tracks the RF signal until the VTO frequency
higher than the RF signal. reaches 30 MHz. When that occurs, the sweep stops, the
A limiting amplifier preceding the frequency/phase de display is held and blanked, the VTO is retuned to 8 MHz,
tector allows the system to operate with any R-signal and it is allowed to phase lock on a higher harmonic. The
amplitude within a range of 0 to -40 dBm. The use of two sweep then continues with the CRT unblanked until the
integrators (not shown in Fig. 9) in the feedback loop results VTO again reaches 30 MHz, and the cycle repeats. For a
in a third-order system that is able to maintain the 1-MHz IF 4-to-1300-MHz full-band sweep, four such lock points oc
within ±1 kHz as the RF signal sweeps at rates in excess of cur.
130 MHz/ms. The lock points are practically invisible on the CRT (Fig.
10) because the sweep is back-stepped about 4% during the
Continuous Trace VTO retuning interval. When the sweep resumes, the CRT
The VTO phase-lock system works over an RF sweep remains blanked until the sweep reaches its old value.
range of IVi octaves. There are, however, many times when Thus, display transients associated with an abrupt start of a

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 13

© Copr. 1949-1998 Hewlett-Packard Co.

 0.3 ns

Fig. 11. Sampling circuit uses a positive feedback loop

around the amplifier to boost the charge on holding capacitor
Cx to full value.

Fig. 10. Wide 4-to-1300-MHz-sweep display of magnitude amplifier gain, can be adjusted to equal the RF input vol
(upper trace, 0.25 dB/div) and phase (lower trace, 2.5°/div) tage. As a result, when making absolute power measure
shows no transients where the four frequency relock points ments with Model 8754A, the RF-to-IF conversion effi
occur. The tunable marker is positioned at 1 GHz. ciency varies less than 0.1 dB over the 5-30-MHz VTO
range. In a ratio mode, the IF outputs of two samplers track
sweep are blanked. typically within 0.02 dB.
One problem with some wide-sweeping sampling sys
tems is the change in amplitude response caused by a
change in the sampling frequency. This is a result of series Usable with External Sources
resistance in the sampling circuit that prevents the holding One of the advantages of the 8754 A's sampling receiver is
capacitor from fully charging to the new value of the RF that it can be used with external sources. The receiver
signal during the short sampling pulse. Thus, the IF output automatically locks to any suitable signal at the R input and
amplitude drops as the sampling rate drops. This appears tracks it while the signal sweeps. In this mode, the obtain
on the display as an abrupt discontinuity at harmonic re- able spectral purity and frequency accuracy is determined
lock points. by the source used. For example, precision swept mea
In the Model 8754A, a feedback circuit prevents this surements of narrowband devices like crystal filters can be
from happening by boosting the charge on the holding made by using a high-stability signal generator, such as the
capacitor between samples. A circuit diagram is shown in HP Model 8640A/B,3 with a de-coupled FM input that can
Fig. 11. Because of its limited bandwidth, the amplifier be driven by the 8754A's sweep output. Or, synthesizers
does not respond to a new value on holding capacitor Cx with highly accurate internal digital sweep may be used
during the sampling pulse, but responds later. The ampli provided they supply an analog sweep output for control of
fier's noninverting output is fed back to its input through the CRT horizontal axis and a blanking signal during fre
a capacitive divider formed by C^ and Cy, boosting the quency transients.
charge on Cx. The final value, determined by Cx, Cy, and For proper phase lock, the receiver need only know the

Fig. 12. Magnitude detector has a

AC Feedback full-wave rectifier within an ac
feedback loop. Rectifier current is
D C D C L Â ° 9 compared to the IF signal current
at the input to the amplifier, which
- v v v * - \ \ v - ^ 4 - * Output
Vdc
drives the diodes to make the two
currents equal. Diode capaci
tance would cause an error in the
Variable
Gain
diode current, limiting accuracy at

-o-^ Amplifier

Hr
low signal levels, but injection of
an equal but opposite current into
the summing node compensates
for this. Also, the diodes' impe
dance changes with the input
level. This affects the open-loop
gain, giving rise to stability prob
-r* A\V-t^VvV- lems. Gain variations are reduced
Rectifiers by a PIN-diode network within the
Diode Capacitance
Compensation
5 amplifier that adjusts the gain ac
cording to the signal level.

14 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

approximate frequency range of the external signal. For Frequency
Ramp
narrowband sweeps, tuning the LED frequency readout to
the start frequency of the external source is sufficient. For
sweeps wider than I1 2 octaves, both the TUNING and SWEEP
WIDTH controls are set on the 8754A to agree with the
external source. For sweeps faster than 10 ms/div, the
8754A should supply the sweep voltage for the external
source so the display transients at the relock points may be
removed. For sweeps slower than 10 ms/div, as might be
obtained from a sweeping synthesizer, there is no need to
Output to
stop the sweep for relocking since the relocking occurs so Detectors
quickly that it is barely visible on the display.
The sampling receiver is also capable of operating with
input frequencies well above 1.3 GHz, though possibly with
degraded performance. A modified version of the instru
1 MHz Uimiter
ment, that will soon be available, will operate up to 2.6 GHz R-IF Input
when using an external frequency doubler driven from the
built-in source. Optional versions of the accessories Fig. 14. Phase shifter consists of a 1-MHz voltage-tuned oscil
(transmission/reflection test set, power splitters, etc.) will lator (VTO) that is phase-locked to the R-channel signal with a
also be able to operate up to 2.6 GHz. phase offset.

When the analyzer is displaying absolute power (dBm),

Magnitude Detectors the precision reference voltage discussed earlier is sub
As was shown in Fig. 9, the A and B inputs time-share a tracted from the AJE channel output and the difference is
detector. Channel switching is performed by an electronic amplified for presentation on the CRT. For ratio measure
switch that has 100-dB on/off isolation, assuring negligible ments, the R-channel voltage is subtracted from the A/B
IF cross-talk between channels. channel before the reference is subtracted. As shown by Fig.
The magnitude detectors are average-responding and use 13, this technique results in excellent dynamic accuracy.
full-wave rectifiers in a feedback loop (Fig. 1 2) . This assures Devices can be measured with an uncertainty of only 0.01
a highly linear transfer function. The output current is dB/dB at levels within -10 to -40 dBm, and ±0.3 dBovera
processed through a logarithmic amplifier to derive a volt range of 0 to -50 dBm.
age proportional to the log of the IF level so the CRT's
vertical scale can be in dB units. The basic circuitry was
adapted from that used in the Model 8505A Network Phase Detector
Analyzer.4 An important design goal for any phase measuring in
strument is retention of phase accuracy as the signal
amplitude changes. In the 8754A, the two IF signals for the
phase detector are processed through cascaded ECL line
receivers to limit the amplitude excursions. The signals are
thus subject to less than 2° phase shift over a 50-dB dynamic
range.
The R-channel signal is processed through the phase-
shifting circuit shown in Fig. 14. The signal is applied to a
commercially available 720° phase detector where it is
compared to the output of a 1-MHz voltage-tuned oscillator
(VTO). The error voltage is summed with dc offset voltages
and then used to control the VTO. The result is a 1-MHz
signal that is phase-locked to the R-channel signal but offset
in phase. The offsets come from the front-panel REFERENCE
lever switch and the sweep tuning voltage. The front-panel
switch enables a phase shift of up to ±199° to be introduced,
and the attenuated sweep tuning voltage introduces a simu
lated time delay that can be adjusted to compensate for up to
16 cm of electrical length difference between the input
cables.
Fig. 13. Oscilloscope display of magnitude detector error
Phase detection is accomplished with a conventional
versus signal level over a range of +10 dBm (left) to -90 dBm
(right). The error voltage is derived by comparing the detector
edge-triggered flip-flop.
output to a reference. This measurement, which shows the The polar display is derived from a conventional resolver
accuracy of the magnitude detectors, was made on a consisting of two analog multipliers in phase quadrature.
sweeping-attenuator test system developed for the 8754A The radius of the polar display, which is linearly propor
production line. (Vertical scale: 0.25 dB/div.) tional to the amplitude ratio, is obtained by processing the

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 15

© Copr. 1949-1998 Hewlett-Packard Co.

 ABRIDGED SPECIFICATIONS
HP Model 8754 A Network Analyzer

Source Magnitude
FREQUENCY RANGE: 4 MHz to 1300 MHz. FREQUENCY RESPONSE (flatness): Absolute (A, B): s±1 dB.
MARKERS:
SPACING: 1, 10, and 50 MHz.
ACCURACY: ±0.01%.
DIGITAL FREQUENCY READOUT: indicates frequency of variable tuning
marker in linear FULL SWEEP mode, and start or center frequency in START
and CENTER sweep modes.
RESOLUTION: 1 MHz.
ACCURACY: ±10 MHz (20° to 30°C). Readout is adjustable for calibration
to internal crystal markers.
SWEEP WIDTH: selectable sweep widths from 1 to 1000 MHz in a 1, 2, 5 sequence, plus
CW. Vernier allows continuous adjustment of sweep width within each range and 5 0 0 1 0 0 0 1 3 0 0
calibration to internal crystal markers. Frequency (MHz)
ACCURACY: typically ±2% (500 to 1000 MHz), typically ±5% (50 to 200 MHz), typically
±8% (1 to 20 MHz). RATIO (A/R, B/R): s ±0.3 dB.
STABILITY:
TEMPERATURE: typically ±400 kHzfC.
TIME: typically ±100 kHz/hour.
OUTPUTIMPEDANCE: 50!!. Source match typically less than 1 .4 SWR ( > 16 dB return loss).
POWER RANGE: calibrated 0 to +10 dBm. Uncalibrated to typically +13 dBm.
ACCURACY: ±0.8 dB at 50 MHz.
FLATNESS: ±0.5 dB.
SPECTRAL PURITY ( + 10 dBm RF output level):
SWEPT RESIDUAL FM (also applies to CW mode): «7 kHz rms (10-kHz bandwidth).
HARMONICS: -28 dBc (typically -35 dBc).
SPURIOUS: 4-500 MHz: -65 dBc (typically -75 dBc). 5 0 0 1 0 0 0 1 3 0 0
500-1300 MHz: -50 dBc (typically -60 dBc). Frequency (MHz)
SWEEP TIME: typically 10 ms to 500 ms on FAST range, typically 1 s to 50 s on SLOW
range.
DYNAMIC ACCURACY (20-30'C):
TRIGGER MODES: AUTO (repetitive) and TRIG (single sweep triggered by front-panel
button or rear-panel programming connector).
RF OUTPUT CONNECTOR: Type N female. 2.5
Note:
m Referred to -20 dBm
T3 2 0
-H
Receiver
£• 1.5
FREQUENCY RANGE: 4 MHz to 1300 MHz.
INPUT CHANNELS: three inputs, R, A. and B. Two test inputs (A and B) with 80-dB dynamic
range, and a reference input (R) with 40-dB dynamic range. 1'0 Specification
INPUT CONNECTORS: Type N female U

IMPEDANCE: 50Ã!. Input port match s20 dB. Return loss («1.22 SWR). 0.3
MAXIMUM INPUT LEVEL: 0 dBm.
NOISE LEVEL: < -80 dBm, A and B inputs. - 2 0 - 4 0 - 6 0 -80
MINIMUM R INPUT LEVEL: -40 dBm (s-40 dBm required to operate R input phase-
lock). Input Level (dBm)
CROSSTALK BETWEEN CHANNELS: >83 dB
ERROR LIMITS: Phase
FREQUENCY RESPONSE: «±2.5°.

100 O)

i
t
iI
D
3
U!
c
0.01 <
-20 -40 -60 -80
RANGE: ±180=.
Test Input Level DYNAMIC ACCURACY:
(dB relative to highest level applied to other inputs) ±2' from 0 to -50 dBm.
±4C from -50 to -70 dBm.
REFERENCE OFFSET:
REFERENCE OFFSET:
RANGE: for in r steps. Vernier provides typically ±20° of variable offset used for
RANGE: ±199dBin 1-dB steps. Vernier provides typically ±80dBof variable offset used
phase calibration.
for calibration in ratio measurements.
ACCURACY: ±1%.
ACCURACY: included in Dynamic Accuracy above. Typically <±0.1% of value.
DISPLAY RESOLUTION: 90, 45, 10, 2.5°/major division.
DISPLAY RESOLUTION: 10, 2.5, 1, 0.25 dB/major division.
DISPLAY ACCURACY: ±2%. ±0.05 major division. DISPLAY ACCURACY: ±2% ±0.05 division.
ERROR RESULTING FROM CHANGE IN HARMONIC NUMBER: ELECTRICAL LENGTH ADJUSTMENT RANGE: typically 160 mm.
RATIO (A/R and B/R): typically «0.05 dB. PHASE ERROR RESULTING FROM A CHANGE IN HARMONIC NUMBER: typically
ABSOLUTE (A, B, AND R): typically sO.2 dB. «0.5°.
ABSOLUTE POWER (A, B, AND R) : calibrated in dBm, typically < ±0.5 dBm with 0 dBm, Polar
50 MHz input. See Magnitude and Phase specifications for frequency response, dynamic accuracy,

16 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

 reference offset, and errors resulting from a change in harmonic number listed above. VERTICAL: 0.1 V div (±0.4 V full scale).
DISPLAY ACCURACY: actual value is within 2.5 mm of displayed value. PENLIFT BLANKING: -5 V blanking and penïft; -5 V intensifies crystal markers.
ELECTRICAL LENGTH ADJUSTMENT RANGE: typically 160 mm. resulting in an 80-mm EXTERNAL MARKER INPUT: typically - 1 3 dBm RF signal into EXTERNAL MARKER Input
adjustment to the reference plane in a reflection measurement. produces amplitude (rectiinear) or intensity (polar) marker on trace at frequency of RF
signal. BNC female connector, 50!1.
Display MAGNITUDEPHASE OUTPUT: -10 mV/degree and -100 mV/dB at BNC female con
MEASUREMENT FUNCTIONS: CRT displays either polar trace or two independent recti nector. use by TTL level or contact closure at pin of programming connector for use
linear traces. with external digital voltmeter.
CHANNEL 1: A, R magnitude absolute (dBm): A.'R. B/R magnitude ratio (dB). ACCURACY: see magnitude dynamic accuracy specifications
CHANNEL 2: B magnitude absolute (dBm); B R magnitude rato (dB); B/R phase (degrees). PHASE SCALE ERROR: =1.5% («170'): r2% (±180=).
POLAR: A.R magnitude ratio (dB) and phase (degrees). PROBE POWER: -15 Vdc and -12.6 Vdc, for use with HP 10855A Preamp or HP 1121 A

REFERENCE POSITION: reference lines for Channel 1 and Channel 2 and polar center can AC Probe. Two probe power jacks are provided.
be independently set to any position on the CRT for calibration. Display resolution expands STORAGE-NORMALIZER INTERFACES: directly compatible with both the HP 8750A
about the reference position line. Storage-Normalizer and the HP 8501A Storage-Normalizer. All 8501A features except
VIDEO FILTER: typically 100 Hz (10 kHz without filter). CRT labels and graphics are available when 8501A is used in conjunction with 8754A.

GRATICULE SIZE: rectilinear, 100 mm horizontal by 80 mm vertical; polar 80 mm in PROGRAMMING CONNECTOR:

diameter. Both graticules internal to CRT. FUNCTION: 25-pin Amphenol connector (with mating connector), includes magnitude
SMITH CHART OVERLAYS: 2, 1, 0.2, and 0.1 full scale. phase and sweep outputs and inputs described above and measurement mode selec
PHOSPHOR: P39 tion by TTL levels or contact closures.
CRT PHOTOGRAPHY: Electronic flash is required in the camera for graticule illumination.
Ultraviolet (UV) illumination does not excite the P39 phosphor for graticule exposure. General
OPERATING TEMPERATURE: 0' to 55=C except where noted.
Inputs/Outputs SAFETY: conforms to requirements of IEC 348.
SWEEP OUTPUT: -5 V to ~5 V nominal. BNC female connector, used to frequency modu POWER: 100, 120, 220 and 240 V, + 5% -10%. 48 to 66 Hz, 200 VA max.
late (sweep) external generator. SIZE: 133 mm H x 425 mm W x 505 mm D (5'/4 x 16-3/4 x 19'/n in).
EXTERNAL SWEEP INPUT: 0 to 10 V nominal. BNC female connector, used to sweep CRT WEIGHT: 17.7 kg (39 Ib).
display frequency receiver is used with external swept source, or to remotely program frequency PRICE IN U.S.A.: $11,500.
of internal RF source from external digital-to-analog converter. MANUFACTURING DIVISION: SANTA ROSA DIVISION
X-Y RECORDER/EXTERNAL CRT OUTPUT: 1400 Fountain Grove Parkway
HORIZONTAL: 0.1 V/div (0 to 1 V). Santa Rosa, California 95404 U.S.A.

logarithmic outputs of the magnitude detectors through an Network and Spectrum Analyzers," Hewlett-Packard Jour
exponential amplifier. nal, January 1978.
2. F.K. Weinert, "The RF Vector Voltmeter— An Important
Semi-automated System Capability New Instrument for Amplitude and Phase Measurements
Although the 8754A is intended primarily for use as a from 1 MHz to 1000 MHz," Hewlett-Packard Journal, May
manually operated bench instrument, provisions were 1966.
made for its use in semiautomatic systems. The RF source 3. R.M. Shannon, K.L. Astrof, M.S. Marzalek, and L.C.
can be swept by an externally supplied voltage over the Sanders, "A Solid-State VHF Signal Generator for Today's
frequency range selected on the front panel. This voltage Exacting Requirements," Hewlett-Packard Journal, Feb
could be provided by a digital-to-analog converter. A rear- ruary 1973.
panel output proportional to log magnitude ratio or phase 4. H. Vifian, "A Direct-Reading Network Analyzer for the
angle, as selected by a TTL programming voltage supplied 500-kHz-to-1.3 GHz Frequency Range," Hewlett-Packard
to a rear-panel connector, is available. This output could be Journal, July 1976.
applied to a digital voltmeter (outputs for an X-Y recorder
are also provided). Techniques for configuring the 8754A
for operation on the HP Interface Bus are described in HP
Application Note No. 294.

Acknowledgements
Fred Rawson designed the power supplies, sweep cir James ft. Zellers
cuitry, display circuits, marker generator, and polar/phase A native of Los Angeles, California, Jim
detectors. Mike Sohigian was responsible for the source and Zellers earned a BSEE degree from the
amplifier/detector microcircuits. Fred Woodhull designed University of California at Berkeley in
the magnitude detector. Phil Luque did the initial receiver 1966, then designed crystal oscillators
investigation before transferring to HP's Boise Division. Jim for a year, returned to school to obtain
an MSEE degree (University of Michi
Jones and Steve Sparks developed the phase-lock system.
gan, 1968), and shortly thereafter
Dick Barg did the product design and Chuck Compton joined Hewlett-Packard in Palo Alto.
provided production engineering support. Thanks are also At HP he worked initially on cesium-
due Bill Kabage, Russ Johnson, Joe Williams, Sam Zuck, Jim beam frequency standards, and then
Stead, Roy Church, and Bill Simmons, and special thanks to became involved in automatic network
Doug Rytting, lab section manager, who inspired the initial analyzers, microwave signal genera-
concept and provided support along the way. iE tors and sweepers before taking on pro-
J ject leadership of the 8754A Network
References i··fiÉ Analyzer. Now living in Santa Rosa,
California, with his wife and two young children (ages 3 and 5), Jim
1. M.D. Roos, J.H. Egbert, R.P. Oblad, and J.T. Barr, "Add-
enjoys tent camping with his family, photography, woodworking,
On Digital Signal Processing Enhances the Performance of music, and hi-fi.
•Hewlett-Packard's implementation of ANSI/IEEE 488-1978

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 17

© Copr. 1949-1998 Hewlett-Packard Co.

Expanding Logic Analyzer Capabilities by
Means of the HP-IB
Augmenting the power of a logic state/timing analyzer
with a desktop computer gives automated testing capability
along with display in user-definable assembly language.
by Robert G. Wickliff, Jr. and Richard A. Nygaard, Jr.

BY PROVIDING A MEANS of monitoring the sequen the mnemonics of that particular microprocessor, regard
tial states of digital processor systems, logic state less of what type it is, and then passed back to the analyzer
analyzers, first introduced in 1973, J quickly estab for display. With the conversion to mnemonics, interpreta
lished themselves as indispensable tools for the design, tion of data becomes much easier than it would be if it were
development, and servicing of digital systems. left on binary. Also, statistical analyses can be performed on
Later versions of the logic state analyzer made it easier to the data, such as the percentage of time spent in a given
monitor complex state flow involving program branching, address range, the number of read errors encountered dur
looping, and subroutines.2 Logic timing analysis has also ing mass storage access, and the number of calls to a sub
been incorporated so that glitches and other transients that routine.
derail correct state flow can be located.3 "Babysitting" an intermittent problem is another task
Now, by equipping two of HP's logic analyzers, Models that is greatly simplified by analyzer-computer interaction.
1610A/B2 (Fig. 1) and 1615A3 (Fig. 2), to operate with the HP Measurements may be set up for repetition under program
interface bus, another step forward in capability has been control. Twenty-four hours a day, the computer can com
added. The ability to communicate over the HP-IB enables pare automatically acquired measurement results with
the analyzer to interact with a computer, making pro stored data and accumulate information about occasional
grammed control of the analyzer possible for both labora errors. No one has to stay there to note the fault, and restart
tory and production-line applications. For example, state- the measurement.
flow data captured by either of these analyzers from a mi Easy documentation is another advantage. Any part or all
croprocessor system can be converted by the computer to of an analyzer's memory can be printed out by the computer
•Hewlett-Packard's implementation of ANSI/IEEE 488-1978 for inclusion in lab notebooks. Accurate diagrams of signal

o e o

-<-

Fig. 1. Model 16WA/B Logic State Analyzer traces the flow of Fig. 2. Model 76)5/4 Logic Analyzer can function as a 24-bit
simultaneous digital events in as many as 32 bus lines in digital state analyzer, an 8-bit timing analyzer with glitch triggering
systems at clock rates up to 10 MHz. Its selective triggering capability, or as a combination 16-bit state and 8-bit timing
capabilities enable it to restrict data capture to specific loops analyzer that captures time and state activity simultaneously.
or branches in complex programs. Keyboard control and an Cross triggering between timing and state modes enables
interactive display that uses menus enable rapid set up of study of the interaction between timing problems and particu
complex measurement parameters. The Model 161 OB shown lar states, especially useful where the system under test has
here can have data strobed in by three different clocks. both synchronous and asynchronous elements.

18 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

timing as well as any glitches that are present (when using the remote unit can be effectively slaved to another unit at
the Model 1615A) can be plotted for before-after compari the central site, enabling the service engineer to run traces
sons pertaining to a design change. and see the results without leaving the central site.
Straightforward Programming
Automated Measurements
Faster prototype development can result from use of the In the design of the HP-IB interfaces for the Models
analyzer-computer combination. Complex measurement 1610A/B and 1615A. programming convenience was a
set-ups and the expected results are easily stored within the major consideration. Experience has shown that two-
character mnemonics provide sufficient program readabil
computer for later use. For example, operation of a fairly
ity along with conciseness. With instruments, the
simple module in the breadboard stage recently required
mnemonics usually are associated with specific front-panel
nearly half a day for verification. Most of this time was spent
in manually setting up trace conditions on the logic controls and are generally printed right on the front panel
analyzer and checking the captured data. A simple program next to the associated control. The Models 1610A/B and
incorporating the setup conditions and data was then writ 1615A, however, are each controlled by a simplified
ten. As a result, when the prototype boards came back from keyboard and use a CRT to display the control settings (Fig.
the shop, the analyzer-computer system needed only five 3). There is no direct association between the front-panel
minutes to determine that the prototypes functioned just controls and instrument functions. Therefore, the
like the breadboard. mnemonics that were selected for the HP-IB interfaces are
Production-line testing is an obvious application of the associated with specific data fields within the menus that
analyzer-computer combination. Tests developed in the lab the instrument displays.
Each mnemonic was chosen to provide ready association
during the design phase to verify performance, such as in
with the function it controls. For example, a trace point
the preceding example, can be used in production. This has
specification begins with the mnemonic TP and a sequence
an additional advantage in that production tests can be
term begins with SQ. Additional information is supplied
traced back to the design engineer and when special prob
with an operand and/or parameters. The operand in the
lems arise, the design engineer won't have to spend extra
trace-point command specifies whether the designated
time understanding unfamiliar production test equipment
trigger state is the start, center, or end point of the trace.
and procedures.
Also on the production line, troubleshooting can be Thus, TPi,0500 starts the trace on the occurrence of state
0500 in the logic-state flow while TP3.0500 ends the trace on
simplified by the use of interactive test selection, employ
ing the analyzer's CRT to present options and suggested the same state.
procedures to the test technician. Multiple parameters within a command are separated by
Servicing procedures in the field can also be improved by commas. In many cases, the parameters are loaded directly
use of an analyzer equipped with the HP-IB option. An into the data fields in the displayed menus. For example,
HP-IB-to-RS-232C(V.24) interface that would enable com the string LSAAAAAAAA,AAAAAAAA,CCCCCCCC would set
munications between a logic analyzer in the field and a up the label-select field as shown in Fig. 4.
computer at a central site would make the expertise of a Commands that require an operand or parameter(s) also
service engineer at the central site available to a technician require an explicit terminator to signify the end of a com
in the field. The analyzer in the field can display messages mand and initiate its execution. Because a terminator is
sent from the central site and, if the analyzer is a 1610A/B, required, hexadecimal characters may be used for operands
the analyzer's keyboard can be used to respond. In addition, and parameters; no confusion can occur with the mnemonic
of a following command because it cannot be executed until
the current command has been terminated.

FORMAT SPECIFICATION POWER UP COMPLETE

CLOCK SLOPE
POD3 POD2 PODI

LABEL SELECT

LOGIC POLARITY ~9f\

BASE diiaSfc dïiaa

Fig. 3. Menus display fields (highlighted by inverse video)

that may be changed by the keyboard in setting up instrument
controls- The menu shown here tells the analyzer it must first Fig. 4. Two-letter mnemonic commands sent over the HP-IB,
find state OOOA and then OOOB in that order before allowing shown in column at right, are alphabetically related to specific
state 29B6 to start data capture. data fields within the menus.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 19

© Copr. 1949-1998 Hewlett-Packard Co.

 more, the test setup and test results may be stored in arrays
and do not need to be written as part of a program. A single
control program that calls up the stored arrays may then be
used for many different tests, thus keeping software costs at
U S E R ' S D I S P L A Y . . P O U E R U P - C O M P L E T E
REHOTE-LISTEN
a minimum.
The HP-IB interfaces also provide a TALK-ONLY mode,
selected by a rear-panel switch. In this mode, the analyzers
i OR 2 OUT OF RANGE
respond normally to their keyboards but when the PRINT
key is pressed (STOP/PRINT on the 161 5A), if a trace is not in
process the analyzer will output the current display in
to RESUME OPERATION, PRESS ANY KEY
ASCII over the HP-IB. This enables hard-copy output with
out requiring a controller (Model 1610A/B also has an out
put for driving an HP Model 9866A/B thermal line printer
directly, a standard feature).
The HP-IB interface for Model 161 5A can also output its
timing diagram display using the HP graphics language
Fig. 5. When an illegal command is sent over the HP-IB to (HP-GL)4 to generate plots and labels for the plots on any of
Model 1610A/B, the analyzer displays an error message. In the HP plotters that interface to the HP-IB (Fig. 6). The other
the one shown here, number 3 is the highest value that can
follow the mnemonic TP (trace point).
TIMING DIAGRAM TRACF-COMPLETE
TALK ONLY
Line feeds and carriage returns are ignored in most cases EXPAND INDICATOR ION ] 50NS/CLK
GLITCH DISPLAY CON ) 1US/DIV
since they are usually difficult to suppress. The exceptions MAGNIFICAT I OH [XI ] t 350. NS1
l i l i l à -
are commands containing data, in which a carriage return
would be valid data, or text strings in which a line feed
would be a valid terminator.
When the logic analyzer receives a command over the
HP-IB, the menu to which it refers is displayed automati
cally and the referenced field is updated. By watching the
display, a programmer gets immediate feedback about the
effects of programmed commands. Programming these
analyzers over the HP-IB is therefore very much like operat
ing them from the front panel.
If the Model 161 5A detects an error in a programmed
command, the display flashes ERROR-INVALID ENTRY just
TRACE SPECIFICATION TRACE-COMPLETE
as it would under local control. If Model 1610A/B detects an TALK ONLY
error in a command, such as an out-of-range operand, it [8 BIT TRIGGERS 16 BIT]
displays the entire command, with the erroneous operand
[ END ] TRACE
highlighted in inverse video, along with an error number
and description. Operation may be resumed by pressing a CLOCK QUALIFIER XXXXXX

key. Alternatively, Model 1610A/B can be programmed to

generate a service request when an error is detected. The
einor number can then be read and program execution re
sumed by reading a status byte over the HP-IB (Fig. 5).

Past Programmed Setup

The HP-IB interfaces also provide a "learn" mode for the
TRACE LIST TRACE-COMPLETE
analyzers. Sending the learn command causes either TALK ONLY
analyzer to output a packed binary string containing the tl6 BIT)
LINE C
status of all analyzer control functions preceded by an iden NO. HEX
tifier. When the string is returned to the analyzer at a later
244 030A
time, the identifier sets the analyzer to receive the packed 245 090B
setup information and the analyzer control functions are set 246 090C
as they were when the string was originally sent. Thus, the 247
248
090D
0004
analyzer may be set up manually and the controller, usually 249 0005
a desktop computer, can read and store the complete setup. 250 090E
Ã51 090F
Consequently, programs need only a few commands to con 252 0005
trol the analyzer completely. Tests may be performed on a 253 0004
254 0018
device that is known to be good and the test results saved 255 0019
along with the setup information. Tests on other units may
then be performed by first sending the learn string and then Fig. 6. Timing plots and labels can be sent from Model 1615A
comparing the new test results to the stored data. Further over the HP-IB to a digital plotter.

20 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

 HP-IB
Buffer Drivers

REMOTE LISTEN

Interface
Control
FAILURE OF THIS TEST INDICATES A Chip
FAULT IN THE MEMORY CONTROL SECTION. A0-A2 Register Select

CHANGE PROBE TO TEST POINT 3 AND

RUN TEST 122

Interface
Memory
A0-A,o Memory Address

Fig. 7. Automatic test programs for controlling a logic System Data Bus
analyzer over the HP-IB can include messages that are dis
played on the analyzer's CRT for the test technician.
Fig. 8. Generalized block diagram of the interface between
logic analyzer and the HP-IB.
displays (menus and data lists) are output in 7-bit ASCII and
require a separate printer (except for the HP Model 7245A
Plotter/Printer that can provide both types of copy5). These
same outputs are also available under program control the interface firmware passes control back to the analyzer's
through the print (PR) command. operating system.
The controller may also write messages directly on the The interface code is implemented using formatters (sub
analyzer display (Fig. 7). The display characters (DC) com routines) and table descriptions of each command. Each
mand can access all but the top two lines on the display, formatter handles several functions that are basically simi
which are reserved for status and error messages including lar. Hence, only five formatters are required for the 1615A,
HP-IB status information. Three parameters following the and nine for the 1610A/B.
DC command specify normal, inverse, or blinking charac A look-up table links each mnemonic to a table contain
ters, and the line and column where the message is to start. ing the address of the proper formatter and instruction bytes
ASCII-coded text can then follow these parameters. for that formatter. The instruction bytes point to the menu
and field prescribed and any restrictions on parameter val
Hardware Approach ues. The code required for a given command thus consists
The HP-IB interfaces were designed so as to impact the of only a few table entries rather than a long subroutine.
existing logic analyzer designs as little as possible. Con The operating system in the Model 1610A/B was mod
sequently, each interface consists of a single printed-circuit ified to allow interaction between the 1610A/B's operating
board and associated cabling. It is thus possible to retrofit system and the HP-IB interface firmware. To allow the
the interfaces to analyzers already in the field. firmware modules to interact correctly, the addresses of all
The interfaces were also designed so as not to interfere global routines are included in tables within the ROM space
with the normal operation of the host analyzer. Each inter of each. These tables start at a known location within each
face therefore has its own firmware package. module and include jump instructions that transfer a sub
A block diagram is shown in Fig. 8. Asynchronous con routine call to the correct address within the module. The
trol logic for the HP-IB functions is implemented by an calling location thus is unaware of the ultimate destination.
interface control 1C chip (MC 68488 in the 1615A, HP's PHI The practical advantage of using tables rather than directly
chip6 in the 1610A/B). The analyzer's microprocessor con calling the routines arises in the event that software modifi
trols the interface chip by writing to a bank of registers cations and relocations are required. Only the jump address
internal to the chip. All communications between the HP-IB needs to be modified to accommodate the change. Many
and the microprocessor flow through these internal regis ROMs that otherwise would have to be replaced may thus
ters. be left unchanged.
To enable either analyzer's operating system to detect
whether or not the HP-IB interface is installed, during the Acknowledgments
normal keyboard scan routine the analyzer addresses the Many people participated in the design of these inter
first byte in the HP-IB ROM. The analyzer's data bus has faces. Don Corson helped in the functional definitions. Jus
pull-up resistors so if the data lines are pulled low in re tin Morrill, project leader for the 1610A/B, provided guid
sponse to the address, the analyzer's operating system ance and a discerning ear to new ideas and John Hansen
knows that the interface is installed. The operating system helped with the hardware design of the 1610A/B HP-IB
will execute a jump to the HP-IB area only if the interface is interface. Harry Short did the mechanical design for the
present. Locating the interface check ahead of the keyboard 1615A HP-IB interface, and project leader John Scharrer
scan routine allows keyboard operation to be inhibited until provided design help and encouragement.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 21

© Copr. 1949-1998 Hewlett-Packard Co.

References Journal, February 1978.
1. W. A. Farnbach, "The Logic State Analyzer — Displaying 4. M.P. Trego, "Plotter-Printer Interface Languages: HP-GL
Complex Digital Processes in Understandable Form," and ASCII," Hewlett-Packard Journal, September 1978.
Hewlett-Packard Journal, January 1974. 5. M. Azmoon, J.H. Bohorquez, and R.A. Warp, "Desktop
2. G. A. Haag, "A Logic State Analyzer for Evaluating Com Plotter-Printer Does Both Vector Graphic Plotting and Fast
plex State Flow," Hewlett-Packard Journal, February 1978. Text Printing," Hewlett-Packard Journal, September 1978.
3. J.A. Scharrer, R.G. Wickliff, Jr., and W.D. Martin, "In 6. J.W. Figueroa, "PHI, the HP-IB Interface Chip,"
teractive Logic State and Timing Analyses for Tracking Hewlett-Packard Journal, July 1978.
Down Problems in Digital Systems," Hewlett-Packard

Richard A. Nygaard. Jr. Robert G. Wickliff, Jr.

Rick Nygaard came to work for the Col Bob Wickliff joined HP in 1974, initially
orado Springs Division of HP im working on CRT design, then the Logic
mediately after he completed his Analyzers, and most recently the
Bachelor's degree in EE at Georgia hardware and firmware for the 1 61 5A's
Tech in 1977. His first project at HP was HP-IB interface. A native of Columbus,
contributing firmware modifications for Ohio, Bob obtained BSEE (1969) and
the 1610B Logic State Analyzer. Then MSEE (1970) degrees from Ohio State
Rick was assigned to preparing the University and worked on electronic
hardware and firmware for the HP-IB countermeasures as a graduate re
option for the 1610. Rick bicycles to and search associate before joining HP.
from work, and rides his bike for plea In off hours, Bob spends time on
sure, too. He also enjoys woodworking, photography. When time permits, Bob
hiking and camping. and his wife like to fly to far away places
like Alaska and go camping there.

ABBREVIATED SPECIFICATIONS

HP Model 1610A/B Logic State Analyzer CLOCK PULSE WIDTH: 20 ns at threshold level.
SETUP TIME: 20 ns.
CLOCK AND DATA INPUTS
HOLD TIME: 0 ns.
REPETITION RATE: to 10 MHz.
SYNCHRONOUS OPERATION
INPUT THRESHOLD: TTL, fixed at approximately +1.5 V; variable, ±10 Vdc.
TRIGGER DELAY: to 999,999 clocks.
MINIMUM INPUT
TRIGGER OCCURRENCE: to 999.999.
SWING: 0.6 V.
ASYNCHRONOUS OPERATION
CLOCK PULSE WIDTH: 20 ns at threshold level.
SAMPLE RATE: 2 Hz to 20 MHz.
DATA SETUP TIME: 20 ns.
MINIMUM DETECTABLE GLITCH: 5 ns with 30% peak overdrive or 250 mV, whichever
HOLD TIME: 0 ns.
is greater.
MULTIPHASE CLOCKS (1610B only): Data is strobed in on either or both edges of up to
GLITCH ANDed on any selected channel(s), if glitch is captured, glitch is ANDed with
three qualified clocks. Used separately, clock 1 strobes in 16 bits, clock 2 strobes in
asynchronous pattern trigger.
8 bits, and clock 3 strobes in 8 bits. Clocks may be logically ORed.
EXTERNAL TRIGGER PULSE WIDTH: 5 ns minimum with 30% peak overdrive or
TRIGGER AND MEASUREMENT ENABLE OUTPUTS
250 mV, whichever is greater.
TRIGGER OUTPUT (rear panel): 50 ns ± 1 0 ns positive TTL level trigger pulse is generated
PATTERN 50, any 8-bit pattern. Trigger duration required is selectable 15, 50,
each time trace position is recognized.
100, 200, 500, 1000. or 2000 ns ±15 ns or 15%, whichever is greater.
MEASUREMENT ENABLE OUTPUT (rear panel): Positive TTL level measurement
DELAY TIME: to 1. 048, 575 x sample period.
enable position goes high and remains high when 1610A is looking for trace position and
TRIGGER OUTPUTS (rear panel)
goes low when trace position is recognized or if STOP key is pressed.
16/24 BIT TRIGGER OUTPUT
MEMORY keys 64 data transactions; 20 transactions are displayed on screen. Roll keys
LEVEL: high, ^2 V into 50Ã1; low, «0.4 V into 50Ãœ.
permit viewing all 64 data transactions.
16/24 BIT TRACE POINT OUTPUT
TIME time, Resolution, 100 ns; accuracy, 0.01%; maximum time, 429.4 seconds.
LEVEL: high, s2 V into 50Ã!; low, «0.4 V into 50Ã1.
EVENTS COUNT: 0 to 232-1 events.
PULSE (pattern starts at beginning of trace and ends at trigger point (pattern
DIMENSIONS: 230 mm H x 425 mm W x 752 mm D (9.063 x 16.75 x 29.625 in).
trigger plus delay).
WEIGHT: 1610A, 26.5 kg (58.5 Ib). 1610B, 23.8 kg (52.5 Ib).
8-BIT PATTERN OUTPUT
ACCESSORIES SUPPLIED: four 10248A data probes, one 10247A clock probe.
LEVEL: high, »2 V into 50f!; low «0.4 V into 50Ü.
OPTION (HP-IB). Adapts analyzer for use in systems linked by the HP Interface Bus (HP-IB).
PULSE DURATION: pattern duration minus asynchronous trigger duration width.
It receives commands via the HP-IB that stimulate front-pane! keyboard entries and cause
MEMORY are 256 data transactions (in timing display mode, 249 samples are
the analyzer to assume a measurement configuration, execute traces, and configure itself
displayed).
to transmit results to other instruments on the HP-IB.
POWER: 100, 120, 220, 240 Vac; -10% to +5%; 48 to 66 Hz; 230 VA max.
PRICES or U.S.A.: 1610A, $11,000; 1610B, $12,500; Opt 003, $800 (1610A) or
DIMENSIONS: 189 mm H x 426 jmm W x 664 mm D (7.438 x 16.75 x 26.125 in).
$700 (1610B).'
WEIGHT: 19.1 kg (42 Ib).
•When included with initial order. Model 10494A Field Kit ($1200) retrofits 1610A's with ACCESSORIES SUPPLIED: three 8-bit Model 10248B data probes and one Model 10248B
serial retrofits prefixes below 01610-1813, Model 10495A Field Kit ($900) retrofits
opt 001 qualifiers, probe with probe leads and tips (three for data and one for clock, qualifiers,
1610A'swith serial number prefixes above01610-1821, and Model 10496A Field Kit ($800) and external trigger).
retrofits all 1610B's. OPT 001: Adapts analyzer for use in systems linked by the HP Interface Bus (HP-IB). It
receives commands via the HP-IB that stimulate front-panel keyboard entries and cause
HP Model 1615A Logic Analyzer the analyzer to assume a measurement configuration, execute traces, and configure itself
CLOCK QUALIFIER AND DATA INPUTS to transmit results to other instruments on the HP-IB.
REPETITION RATE: to 20 MHz. PRICES $400. U.S.A.: 1615A, $6800; Opt 001, $400; 10069A HP-IB Field Kit, $400.
INPUT THRESHOLD: TTL, fixed at approximately +1.4 V; variable ±10 Vdc. MANUFACTURING DIVISION: COLORADO SPRINGS DIVISION
MINIMUM INPUT 1900 Garden of the Gods Road
SWING: .6 V. Colorado Springs, Colorado 80901 U.S.A.

22 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

A Serial Data Analyzer for Locating
Faults in Decentralized Digital Systems
Interfaced to the RS-232C (V.24) data communications bus,
this instrument can monitor data traffic on the bus to help
identify an operational problem. It can then assume an
active role and substitute for the CPU, a terminal, a
peripheral, or a modem to help isolate the problem.

by Robert E. Erdmann, Jr.

THE TROUBLESHOOTING OF computer systems RS-232C-compatible link. Connected into a system, Model
is becoming increasingly difficult as more and more 1 640A can function like a logic state analyzer to capture and
use is made of serial data links to tie a system store data being transmitted on the RS-232C link beginning
together. For example, if a terminal at a remote location or ending with the occurrence of a specified trigger se
cannot communicate with the central processing unit quence or other trigger (trapping) event. It may thus display
(CPU), does the fault lie in the terminal, in the CPU, or selected blocks of activity on the link, showing both the
in the serial data link? And if the data link involves a received and transmitted data to help identify the source of
phone line and modems, is the fault in one of the modems a problem. In this monitor mode, it bridges the RS-232C bus
or the phone link itself? and has no influence on system operation. It is essentially
The Model 1640A Serial Data Analyzer (Fig. 1) was de transparent to the units communicating on the link.
veloped to track down faults in multi-unit systems of this In its simulate mode, Model 1640A can substitute for a
nature. This instrument has an RS-232C (V.24) connector CPU, or modem peripheral to help isolate a fault. If a termi
that allows it to be connected into a system wherever the nal is suspected, the terminal can be disconnected from the
data has been put into serial form for transmission over an system and connected to the 1640A which then "talks" to

Fig. 1. Model 1640 A Serial Data

Analyzer is a portable logic
analyzer tailored for the troub
leshooting and analysis of sys
tems tied together by serial data
communications buses. Its capa
bility for both monitoring and simu
lation enables it to analyze a whole
spectrum of problems associated
with malfunctioning systems that
use communications buses.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 23

© Copr. 1949-1998 Hewlett-Packard Co.

the terminal using a language and handshaking protocol ment can perform — and the permutations and interactions
that the terminal can respond to. If it turns out the terminal of functions — a key-per-function arrangement of the con
is not at fault, the 1640A may be connected to the system in trol panel would have been overly complicated. Instead, a
place of the terminal, and it can interact with the system as "menu" approach with directive displays and a simplified
the terminal would by generating and responding to keyboard is used.
specific messages. Similarly, it may be used at the CPU end The top line of the display identifies the menu selected by
to simulate the transmission link in tests of the CPU, or keys in the DISPLAY group (see Fig. 1). The second line
exercise the transmission link in place of the CPU. contains any messages for the user concerning incorrect
Appropriate messages for the simulation tests may be operation. On the next lines, the blocks (fields) in inverse
entered into the 1640A by way of the 1640A's keyboard, or video (black on white) indicate where entries are to be made
copies of actual network protocol captured in the 1640A's from the ENTRY section of the keyboard. Annotation adja
monitor memory may be entered automatically into its cent to the inverse-video blocks explains the meaning of
transmit memory and edited for subsequent use. Compli each block (Fig. 2).
cated messages that are used frequently may be stored in The user inputs data by first using the CURSOR keys,
PROMs and plugged into the 1640A for quick recall when which move a blinking cursor to the desired entry field.
needed. Brackets in an entry field indicate that inputs to this field
are controlled by the FIELD SELECT key. Pressing this key
Response to Timing Errors causes the entry field identified by the cursor to cycle
Among the several fault-finding capabilities provided in through its allowable choices. Data for other fields is en
this instrument is a timing capability. The 1640A may be set tered through the hexadecimal keypad.
to time the interval between a handshake signal and the The FORMAT menu is used to configure the 1640A for
response to it, or the time between the start of a block of compatibility with the incoming or outgoing serial data
transmit data and the start of the subsequent block of re stream. This includes code set, baud rate, sync or async
ceive data. operation, specification of the sync character, resync
Timing violations can be used as triggers to initiate the specification, and error checking/generation capabilities.
capture and display of characters preceding and following The MODE menu is used to tell the 1640A what to do. This
the timing violation to assist in tracking down the causes of includes monitor or simulate, half- or full-duplex opera
faults. tion, and or receive first, trigger (trapping) source, and
Other triggering modes that are available include trigger the trigger sequence. It also includes the reply-on-character
ing on the occurrence of a data or parity error, triggering on sequence (in the simulate mode, tells the 1640A the charac
a specified character (up to 8 bits) , and triggering only when ter sequence that, when received, should cause the 1640A
a specified character contains an error. to transmit back a user-defined response), run mode (trigger
starts display, trigger ends display, count triggers, etc.), and
Coding Flexibility what data should be suppressed to save memory space,
The 1640A can work with various code sets. ASCII, such as syncs, nulls, idles, and all but the trigger and N
EBCDIC, and hexadecimal are standard and the capability characters following.
for working with other codes is available. The instrument The TX ENTRY menu allows the user to define what is to
can operate synchronously or asynchronously at rates up to be transmitted in the simulate mode. The message may be
19.2 kb/s with error checking on odd or even parity or entered through the hexadecimal keypad or automatically
without parity. Cyclic redundancy error checking (CRC-16, copied from data previously received and stored in the
LRC, CRC-CCITT) is available as an option, as is full SDLC/
monitor memory. The copied data may be edited and may
HDLC (synchronous data link control/high level data link
be broken up into as many as eleven blocks if so desired.
control) capability. In the synchronous mode, there is a
The LIST menu shows what was captured and stored in
choice of character framing on either one or two syn
the monitor memory. TX and RX data may be viewed sepa
chronizing characters that are user definable, as is the re-
rately or both can be viewed together, interleaved according
synchronizing capability.
to the relative time of occurrence of each character. In this
Menu Control case, the TX data is displayed in normal video and the RX
Because of the large number of functions that this instru data in inverse video (Fig. 3). Only about one-fourth of the

* * F O R M f i T * * ** LIST "K* «HAL Fig. 2. (Left) Typical menu shows

the selections to be made, in this
DRTR CODE: TIME INT-00S6 MSEC
TRIG COUNT-0000B TRIG- case the format for configuring the
REPERT COUNT -00008
instrument to match the format of
C c S S a g S M S S ^ ^ V ^ T H E Q U I C K B R O W S F O the data in the RS-232C bus. The
SYNC CHftR X J U M P S O V E R R L R Z Y D O G 0 1 2 3 4 5 6 7
blinking cursor is positioned here
S M W ^ W T H E Q U I C K B R O W N
SERRCH ON F O X J U M P S O V E R R L R Z Y D O G 0 1 2 3 4 5 in the DATA CODE field. Fig.
S789^aSB%£«3%3"*IirVrHE QUICK BROM
P L U S a n I D L E S N F O X J U M P S O V E R P I L A Z Y D O G 0 1 2 3 3. (Right) In the LIST mode, the
4 5 & 7 e S ^ ^ S B ^ M ^ ' i r ' y V n - E Q U I C K B R
O W N F O X J U M P S O V E R R L R Z Y D O G 0 1 contents of the data-acquisition
ERROR 2345S7S9Ã-<«aBB«^a»^*vrHE QUICK memory are displayed with RX data
BROWN FOX JUMPS OVER R LHZY DOG
CHECK 012a45S78SSc3£^raB&**%^-*Vn-E QUI (inverse video) interleaved with TX
data (normal video).

24 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

 Fig. 4. The pin matrix enables the
connection of any lead in the RS-
232C bus to any input or output of
the 1640A by insertion of a metal
pin where the leads cross. The pin
configuration shown here is the
one most often used.

memory can be displayed at one time but the rest can be with a rear-panel switch. Often-used setups may thereafter
brought on display by using the up-down CURSOR keys to be recalled simply by pressing a single key.
scroll the data past the display.
Pin-Matrix Connector
External Control Because of the variety of uses for the Model 1640A, a
With the optional HP-IB interface installed, the 1640A pin-matrix interface is included with the instrument for
can be operated by an external controller. Each of the entry making the connections to the RS-232C bus. This matrix
fields on the menus can be programmed individually (Fig. 4) allows any lead on the RS-232C bus to be connected
through the HP-IB or the 1640A can be completely pro to the appropriate input or output of the 1640A just by
grammed all at once by sending it a "learn" string from the inserting a metal pin where the particular RS-232C lead
controller. crosses the 1640A input or output. For example, for asyn
HP-IB control not only permits remote operation of the chronous monitoring, pin 2 (transmitted data) of the RS-
1640A, but it also enables more sophisticated testing. Data 232Cbusis connected to the TX output of the 1640A, pin 3
acquired by the 1640A can be transferred over the HP-IB to a (received data) is connected to the RX input, and pin 7
controller for mass storage, for statistical analyses, or for (common return) to ground. All others are left open.
examination to find particular sequences. The controller The diagram of Fig. 5 illustrates the pin-matrix organiza
can make decisions on what message to transmit based on tion. LED indicators show the status of any of the 1640A's
the messages received, or repetitively alter messages to inputs or outputs. Besides the normal RS-232C connections
check for pattern sensitivity. to the 1640A, inputs are provided that allow any line in the
An additional capability of the HP-IB interface is that it RS-232C bus to start or stop a time-interval measurement or
allows up to ten user-defined instrument setups to be stored to supply a trigger for data acquisition. To simplify inter
in PROM in the instrument and then selected and loaded connections for often-made measurements, Mylar overlays
are provided. Some of these have prepunched holes where
•Hewlett-Packard's implementation of ANSI/IEEE 488/1978 pin connections are to be made, and others are left blank so

Hardwired To External Circuit

Normal configuration

Left
Half
of
Matrix

Right Fig. 5. Organization of the pin

Half matrix. The 24 leads of the RS-
of 232C bus form the vertical col
Matrix
umns and the 1640A inputs/
outputs form the horizontal rows.
For clarity, the left half of the matrix
is shown stacked on the right half.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 25

© Copr. 1949-1998 Hewlett-Packard Co.

 F i r s t C h a r a c t e r I n c o m i n g
R e c e i v e d C h a r a c t e r S t r e a m As an example of NOT triggering, let us assume that the
Shift Register response of a terminal to a computer occasionally garbles
B C D E F G H the fourth character. If the correct response were A B C D E F

TTuuu RAM
G H and occasionally the terminal sent ABC55EFGH where
Ã-! is the garbled character, then the user can trigger on this
event without any a priori knowledge of what the garbled
character will be. The NOT character is indicated on the
Undefined
Result: No Trigger 1640A display in inverse video thus:
= Compare
TRIG ABCfflEFGH
Eighth Character Received This is interpreted as follows:
Shift Register
GH trigger when A is immediately followed by
B A B C D E

uuu
B C D
RAM
E F G H
B immediately followed by
C immediately followed by
anything but D immediately followed by
E immediately followed by
etc.
Result: No Trigger
Use of NOT triggering thus restricts data capture to those
times when a particular sequence contains an error in a
Tenth Character Received particular character.
Shift Register
A B
Data Combing

uuuu
A B C D E F G H
An important feature of the 1640A's triggering capability
is that it performs true combing of the data stream when
B C D E F G H
triggering on character sequences. Suppose that the trigger
RAM
sequence was defined as ABCDEFGH and that the
Result: Trigger Occurs sequence ABABCDEFGH appeared in the data stream.
Fig. 6. Combing of the data stream assures a trigger when This sequence of events might then occur:
ever a trigger sequence occurs in the data stream regardless 1 . The first A is detected and accepted as a valid start of a
of what precedes it. trigger sequence.
2. B is detected. This is a valid second character of the
the user can establish particular pin configurations by trigger sequence.
punching holes where appropriate. 3. The second A is detected. This is not a valid third
Flexible Triggering
character, so the system starts looking again for a valid first
character.
To effectively troubleshoot and analyze problems on a
serial data bus, a data analyzer should be able to capture Thus, the first three characters are thrown away because
data in response to a variety of trigger conditions. These they do not satisfy the requirements for the first three
should include triggering on specified characters or bit characters in the trigger sequence. This includes the second
patterns on the transmit or receive lines of the RS-232C bus, A even of it satisfies the first-character requirement of
triggering on errors such as parity or cyclic redundancy- the following character sequence. To prevent this, Model
check errors, and triggering on invalid time intervals such 1640A combs the data using a shift-register-RAM
as excessive time between handshake parameters. The technique. As shown in Fig. 6, the trigger sequence is
1640A is capable of all of these triggering modes. In addi loaded into the RAM during instrument setup. As each
tion, it has NOT triggering. character in the incoming stream is detected, the character

HP-IB System
Transmit Monitor
Bus RAM and
RAM RAM ROM

Fig. 7. Simplified block diagram

of Model 1640 A. It is micro
processor-based (8080-4), which
enables it to perform a wide
variety of measurements without
a lot of software.

26 HEWLETT-PACKARD JOURNAL OCTOBER 1979

© Copr. 1949-1998 Hewlett-Packard Co.

is loaded into the shift register and then shifted left when
the next one is entered. Each time a character is entered, the
shift register contents are compared to the RAM contents. Robert E. Erdmann, Jr.
and when a 100% coincidence is detected, a trigger is gen Bob Erdmann designed radar test
erated. No characters are inadvertently thrown away. equipment for a year before joining
HP's Colorado Springs Division in 1969.
Instrument Organization At HP, he was involved in the design of
A block diagram of the Model 1640A is shown in Fig. 7. oscilloscope vertical amplifiers (1 805A,
The interface to the RS-232C bus is by way of two 8251 1834A, 1835A) before joining the
USARTs (universal synchronous/asynchronous receiver- 1 640A project. Bob earned a BSEE de
gree at Purdue University (Indiana) in
transmitters). The microprocessor performs real-time data
1968. In off hours, he indulges in model
acquisition in software by interleaved polling of the railroading, woodworking, and as
USARTs. The data-acquisition software is all in-line code tronomy. He designed and built his own
for speed of execution but most of the rest of the software is 8-inch Newtonian telescope and his
table driven. •own home computer. Bob and his wife
The trigger recognition circuitry is shown in the block have two children, 8 and 3.
diagram of Fig. 8. For the sake of simplicity, this shows a
scaled-down version that works with sequences of four
4-bit characters. Operation is as follows:
1. The specified trigger sequence initially is loaded into
A O A I A 2 A 3

Fig. circuitry. Scaled-down representation of the trigger recognition circuitry.

OCTOBER 1979 HEWLETT-PACKARD JOURNAL 27

© Copr. 1949-1998 Hewlett-Packard Co.

the shift registers by placing the first four-bit character on loaded into the shift registers. A memory read (MEMR) is
the lower four bits of the microprocessor's address lines then executed at the address of the trigger gate (CS2). If all
(A0-A3) and executing a microprocessor memory read the RAMs have a one at the address specified by the shift
(MEMR) from the address of the shift registers (CSÃ). This is register, the trigger gate will then output a one, indicating
repeated for the remaining three characters. that the trigger sequence has occurred.
2. The outputs of the shift registers (C^-On) are connected This system also enables NOT triggering and "don't care"
to the address lines of the RAMs. The bit pattern in the shift triggering merely by appropriate placement of ones on the
registers thus defines a unique address in each of the RAMs. data lines (D0-D3) during the trigger specification se
At this time, the microprocessor places ones on all the data quence at the time that zeros are normally loaded.
lines (D0-D3) and does a memory write (MEMW). The RAMs
now contain ones at the addresses specified by the shift
register contents. Acknowledgments
3. All four-bit sequences except the trigger sequence are John Poss was the project leader. Rick Vestal did the
now entered into the shift registers and zeros written into hardware design and product design was by Bobby J. Self.
the RAMs at the addresses specified by these sequences. HP-IB software was by Dave Novotny, data acquisition
4. When an incoming character arrives, it is placed on the software by Paul Sherwood, and system software by the
lower four bits of the microprocessor's address lines and author.

SPECIFICATIONS
HP Model 1640 A Serial Data Analyzer

INPUT IMPEDANCE: -30 Ml on all interface connections except ground REPEAT occurrence END ON TRIGGER, a message block is transmitted after each occurrence
tri-stale LED may be used lo monitor any pin 2 through 25. The matrix also provides ol the REPLY ON condition until all message blocks have been sent. The process repeals
Format and automatically stops when the trigger event occurs with Ihe last 2048
and buffered power supplies (±12 V, ground]. characters prior to the trigger event retained t n memory.
TEST RESULTS: after any ol The three run modes (monitor and simúlale) is slopped, the TRANSMIT MODES
DATA addition ASCII. Hex. or EBCDIC Olher optional code sets in addition to of
following tesi results are displayed; TRANSMIT FIRST: the first message block is sent by pressing RUN. Succeeding blocks are
m heu 01 EBCDIC are available.
DATA MODES 1 Last time interval measured, or the lime interval trigger event, between u ser -de finable sent following each occurrence ol the REPLY ON condition.
ASYNCHRONOUS1 I of 2 slop bits m addition lo tntoimation and parrty bits RECEIVE FIRST a message block is sent after each occurrence of the REPLY ON
SYNCHRONOUS 1 of 2 user-entered syncnromzing characters Sync search may be 2. Number of tngget events counted during the 'run.
initialed on a user -entered character immediate^ followed by a user-enlered number of 3 Numoer of messages transmitted by (he 1640A (simulate only). TRANSMIT MESSAGE ENTRY: a total of 1 024 characters including block delimiter continue
Idle characters from 0 to 99 Idle is defined as a steady mark {kjglc 1 'SI in all bit poslUlns SUPPRESSION: allows caplunng only the information of interest for efficient use of symbols (i -) and the end symbol I—), may be entered The transmit memory may
SPEED memory (all easier data analysis. Synchronizing characters, idles (all togic ones), be loaded through! the hex keyboard, by transferring the contents of the monitor memory to
EXTERNAL CLOCK (Synchronous) nulls (all logic zero's), or everything bul the trigger and the next n characters (with n the transmit memory with a single keystroke, or. with Option 001 (HP-IB), through a
(rom O lo 99| may be suppressed remote ASCII keyboard or user -definable PROMS (1029A).
C H A R A C T E R N O R M A L O P E R A T I O N H I G H S P E E D M O D E -
MESSAGE EDITING KEYS
Monitor Mode CONTINUE: places a | • symbol >n the message as a block delimiter Up to 10 continue
RUN (EXECUTE) MOOES symbols may be entered. The continue symbol is recognized only by the 1640A and is
COUNT TRIGGERS, continuo and records data and counts the number not sent as part of the data
Ol trigger occurrences: recor END places a |— symbol as a message terminator. Additional messages may be
ord ol 2048 characters added alter the end symbol as user instructions but will not be transmitted. The end
symbol is not sent as part ol the dala.
TRIGGER ENDS DISPLAY: (rigger stops a continuous record A built-in delay of INSERT: inserts a space for an additional character at Ihe point indicated by a movable
64 characters captures 64 characters after the trigger event. cursor to automatically shilling all following characters one cell to Ihe right
DELETE: deletes the character immediately above a movable cursor All following
•Memory data is noi displayed while a s in progress. High speed switch located 01 characters are automatically shifted one space left
of patch panel matrix
Simulate Mode
The 1640A can simulate a CPU. terminal, or the digital side ol a modem.
OUTPUT: '3 V into 3-kll load. Output rows on the patch panel matrix are General
INTERNAL CLOCK (Asynchronous). 50. 75. 110, 134.5, 150. 200. 300. 400. 600. 900. MEMORY: 2048 characters ot monitor bu ffer and 1024 char
TX (Transmit Dala), HTS (Request to Send), and DTH (Data Terminal Ready).
1200, 1800. 2400. 4800. and 9600 Dps. r 1%. Also, any external -1 clock to a mam mum of buffer.
INTERFACE CONTROL SIGNALING: automatic with additional control available
9600 bps may be used lor asynchronous operation. POWER: 100. 120. 220. 240, Vac. -10% +5%, 48 to 440
Ihrough the matrix.
ERROR CHECK: odd. even, or no parity; optional (003) BCC generation and checking Cased DIMENSIONS: 251 mm H x 335 mm W x 5 mm D (9 7/8 x 13 3/16 x 17 1/2 in).
STATE:ONis -.3V,OFFis- -3V Nominal values of driven leads are ±8V lo ±12 V.
on LHC-8. CRC- 16, or CRC-CCITT from a user-entered beginning lo a user-entered end WEIGHT: 11.4 kg (25 Ib)
ing characler. Optional (002) SDLC frame check sum (PCS) generation and error checking HDX: REQUEST TO SEND is on only during iransmission.
OPERATING ENVIRONMENT
for SDLC frames.
Triggering (Trap) Modes HUMIDITY: to 95% relative humidily at + 40°C.
transmissions is a steady mark (asynchronous) or Ihe user-entered sync character
CHARACTER SEQUENCE: up to 8 sequential characters including NOT and DON'T CAR6 (synchronous).
REPLY ON: similar to, but separate from, trigger. A REPLY ON sequence ol Irom 1 to 8 Options
NOTE character CARE is me set of all possible bit patterns of any given character characters, including DON'T CARE and NOT characters, immediately followed by an 001: HP-IB Interface*
length The NOT characler is Ihe set of all characters except Ihe one specified 002: Link (Synchronous Dala Link Control) /HDLC (High Level Data Link Control) Interface*
internally generated time delay from 0 to 6553 ms may be entered; this enables a message
TIME be lime intervals between two HS-232C events may be used as a trigger 003: LR C . C H C -16, and C R C -C C I TT C hec k / Generat ion'
H07: Adds capability lor up lo five additional internal code seis
RUN (EXECUTE) MODES
ERROR: may errors, as defined in the FORMAT menu under ERROR CHECK, may •Field installed Options 002 and 003 reside in the same location so cannot be installed
SINGLE occurrence COUNT TRIGGERS, a message block is transmitted after each occurrence
be used as a trigger Ol the REPLY ON condilion until all message blocks have been sent once. The run
EXTERNAL: trigger supplied from user hardware or RS-232C ON conditions (^+3V). automatically stops when a total of 2048 characters (including the transmitted message) PRICES opt U.S.A.: Model 1640A. $5800. Opt 001, $475: opt 002. $200. opt 003. $150:
have been recorded m ihe momior buffer. H07. $100 (chech nearasi HP held office lor pnce of code-set ROMs).
MANUFACTURING DIVISION: COLORADO SPRINGS DIVISION
Supplemental Characteristics REPEAT AND COUNT TRIGGERS a message block is transmrtted afler each occurrence
PATCH PANEL MATRIX: permits the 1640A lo be configured lo a variety of system inter Of the REPLY ON conddon until all message blocks have been sent The process 1900 Garden of the Gods
face are depending on the application. Mylar overlays are provided with prepared repeats unlil manually stopped with Ihe lasl 2048 characters retained m memory Colorado Springs. Colorado 8O901 U.S.A

Bulk Rate
Hewlett-Packard Company, 1501 Page Mill U.S. Postage
Road, Palo Alto, California 94304 Paid
Hewlett-Packard
Company

OCTOBER 1979 Volume 30 • Number 10

Technical Information from the Laboratories of 0200020blO&t£BLAC6CAOO
Hewlett-Packard Company
MR C A BLACKBURN
Hewlett-Packard Company, 1501 Page Mill Road
Palo Alto, California 94304 U.S.A.
JOHN HOPKINS UNIV
Hewlett-Packard Central Mailing Department APPLIED PHYSICS LAB
Van Heuven Goedhartlaan 121 JOHNS HOPKINS RD
1180AM Amstelveen The Netherlands
••- LAUREL
Yokogawa-Hewlett-Packard Ltd.. Suginami-Ku
Tokyo 168 Japan

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© Copr. 1949-1998 Hewlett-Packard Co.