NATIONAL UNIVERSITY OF HO CHI MINH CITY
UNIVERSITY OF INFORMATION TECHNOLOGY
FACULTY OF COMPUTER ENGINEERING
CHAPTER 7: TASKS & FUNCTIONS
Lecturer: Ho Ngoc Diem
Agenda
Chapter 1: Introduction
Chapter 2: Modules and hierarchical structure
Chapter 3: Fundamental concepts
Chapter 4: Structural modeling (Gate- and switch-level modeling)
Chapter 5: Dataflow modeling (Expression)
Chapter 6: Behavioral modeling
Chapter 7: Tasks and Functions
Chapter 8: State machines
Chapter 9: Testbench and verification
Chapter 10: VHDL introduction
UIT Circuit Design with HDL - Chapter 7 2
Introduction
Procedures/Subroutines/Functions in SW programming
languages
The same functionality, in different places
Verilog equivalence:
Tasks and Functions
Used in Behavioral Modeling
Provide the ability to execute common procedures from
several different places in a description.
UIT Circuit Design with HDL - Chapter 7 3
Contents
Definition of Functions
Definition of Tasks
Differences between Tasks and Functions
UIT Circuit Design with HDL - Chapter 7 4
Functions
Keyword: function, endfunction
Can be used if the procedure
does not have any timing control constructs
returns exactly a single value
has at least one input argument (Functions can not have
output or inout argument)
UIT Circuit Design with HDL - Chapter 7 5
Functions
Function Declaration and Invocation Must be written inside a
module declaration
Declaration syntax:
function <range_or_type> func_name (<func_port_list>);
<input declaration(s)> //either <func_port_list>
//or <input declaration> is used
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end
endfunction
UIT Circuit Design with HDL - Chapter 7 6
Functions
Semantics
much like function in Pascal
An internal implicit reg is declared inside the
function with the same name
The return value is specified by setting that implicit
reg
<range_or_type> defines width and type of the
implicit reg
<type> can be integer, real, time, realtime
default bit width is 1
UIT Circuit Design with HDL - Chapter 7 7
Functions
Function Declaration and Invocation
Invocation syntax:
<func_name> (<argument(s)>);
UIT Circuit Design with HDL - Chapter 7 8
Function rules
A function:
shall not contain any time-controlled statements (#, @, or
wait);
shall not enable tasks;
shall not have any nonblocking assignments or procedural
continuous assignments;
shall not have any event triggers
UIT Circuit Design with HDL - Chapter 7 9
Function Example - Parity Generator
module parity; function calc_parity;
reg [31:0] addr; input [31:0] address;
reg parity; begin
Reg 1 bit calc_parity = ^address;
initial begin end
… endfunction
end
Same name
endmodule
always @(addr)
begin
parity = calc_parity(addr);
$display("Parity calculated = The implicit reg 1 bit
%b", calc_parity(addr) ); width as default
end
UIT Circuit Design with HDL - Chapter 7 10
Function Example - Controllable Shifter
module shifter;
`define LEFT_SHIFT 1'b0
`define RIGHT_SHIFT 1'b1 function [31:0] shift;
reg [31:0] addr, left_addr, input [31:0] address;
right_addr; input control;
reg control; begin
shift = “32 bit width”
initial (control==`LEFT_SHIFT) ?
begin (address<<1):
…… (address>>1);
end end
endfunction
always @(addr)
begin endmodule
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr, `RIGHT_SHIFT);
end
UIT Circuit Design with HDL - Chapter 7 11
FUNCTIONS
Functions are always combinatorial, so there is no doubt
about what type of logic is being modeled.
The same function can be used more than once within the
same module.
UIT Circuit Design with HDL - Chapter 7 12
Tasks
Keywords: task, endtask
Be used if the procedure has:
any timing control constructs
zero or more than one output arguments
UIT Circuit Design with HDL - Chapter 7 13
Tasks
Task declaration and invocation Must be written inside a
module declaration
Declaration syntax
task <task_name> (<task_port_list>);
<I/O declarations> // either (<task_port_list>) or
//<I/O declaration> is used
<variable and event declarations>
begin // if more than one statement needed
<statement(s)>
end // if begin used!
endtask
UIT Circuit Design with HDL - Chapter 7 14
Tasks
Task declaration and invocation
Task invocation syntax
<task_name>;
<task_name> (<arguments>);
input and inout arguments are passed into the task
output and inout arguments are passed back to the
invoking statement when task is completed
UIT Circuit Design with HDL - Chapter 7 15
Tasks
I/O declaration in modules vs. tasks
Both used keywords: input, output, inout
In modules, represent ports
connect to external signals
In tasks, represent arguments
pass values to and from the task
UIT Circuit Design with HDL - Chapter 7 16
Disabling tasks
task proc_a;
begin
...
...
if(a == 0)
disable proc_a; // return if true
...
...
end
endtask
UIT Circuit Design with HDL - Chapter 7 17
Task example -
Usages of Input and Output arguments
module operation;
parameter delay = 10; task bitwise_oper;
reg [15:0] A, B; output [15:0] ab_and, ab_or,
reg [15:0] AB_AND, AB_OR, B_XOR; ab_xor;
input [15:0] a, b;
initial begin
$monitor( …); #delay ab_and = a & b;
ab_or = a | b;
initial ab_xor = a ^ b;
begin end
… endtask
end
endmodule
always @(A or B)
begin
bitwise_oper(AB_AND, AB_OR,
AB_XOR, A, B);
end
UIT Circuit Design with HDL - Chapter 7 18
Task example
Usage of Module Local Variables
module sequence; task init_sequence;
reg clock; clock = 1'b0;
endtask
initial
begin task asymmetric_sequence;
… begin
end #12 clock = 1'b0;
#5 clock = 1'b1;
initial #3 clock = 1'b0;
init_sequence; #10 clock = 1'b1;
end
always endtask
asymmetric_sequence; endmodule
UIT Circuit Design with HDL - Chapter 7 19
Difference
Functions Tasks
◦ Can enable (call) just ◦ Can enable other tasks
another function (not task) and functions
◦ Execute in 0 simulation ◦ May execute in non-zero
time simulation time
◦ No timing control ◦ May contain any timing
statements allowed control statements
◦ At least one input ◦ May have arbitrary
◦ Return only a single value input, output, or inout
◦ Do not return any value
UIT Circuit Design with HDL - Chapter 7 20
Difference
Tasks can be used for almost any common Verilog code
Function are used when the common code is purely
combinational
Functions are typically used for conversions and
commonly used calculations
UIT Circuit Design with HDL - Chapter 7 21
Sameness
Both of Tasks and Functions:
are defined in a module
are local to the module
can have local variables (registers, but not nets) and events
contain only procedural assignment
do not contain initial or always statements
are called from initial or always statements or other
tasks or functions
UIT Circuit Design with HDL - Chapter 7 22
System tasks & functions
Appear in form: $<keyword>
They are considered part of the Verilog HDL. These system tasks and
functions are divided into some categories as follows:
- Display tasks : $display, $monitor, $strobe, $writ, $dumpfile,
$dumpvars…
- File I/O tasks : $fclose, $fdisplay, $swrite, $fread, $sdf_annotate,
$readmemb, $readmemh…
- Simulation control tasks: $finish, $stop
- Math functions: $ln, $log10, $exp, $sqrt, $sin, $cos, $asin, $acos…
(many more in Verilog IEEE standard…)
Ex:
$display (“Hello world”);
UIT Circuit Design with HDL - Chapter 7 23
System tasks & functions
- $time - returns the current simulation time
- $display - displaying on screen
- $stop - stops simultion
- $finish - ends simulation
- $monitor –monitor signal values, display signal wherever they change
value
…
Ex: always @ (posedge clk)
$display (“data is %h at time %t”, data, $time);
UIT Circuit Design with HDL - Chapter 7 24
Summary
How to define Tasks and Functions
Where to use each of them
The same purpose as subroutines in software programing
Provide more readability, easier code management
Parts of design hierarchy in Behavioral Modeling
Tasks are more general than functions
is used for both combinational and sequential logic
Functions can only model purely combinational calculations
System tasks and functions
UIT Circuit Design with HDL - Chapter 7 25