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    CH 4 e F08

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    Abdullah maten

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    © All Rights Reserved
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    CH 4 e F08

    Uploaded by

    Abdullah maten
    15 views4 pages

    Original Title

    ch4eF08

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    © All Rights Reserved
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    15 views4 pages

    CH 4 e F08

    Uploaded by

    Abdullah maten

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Cache Replacement Algorithms

    Replacement algorithms are only needed for associative and set associative techniques.

    1. Least Recently Used (LRU) – replace the cache line that has been in the cache the
    longest with no references to it

    2. First-in First-out (FIFO) – replace the cache line that has been in the cache the
    longest

    3. Least Frequently Used (LFU) – replace the cache line that has experienced the fewest
    references

    4. Random – pick a line at random from the candidate lines

    Note1: LRU is probably the most effective

    Note2: Simulations have shown that random is only slightly inferior to an algorithms
    based on usage

    Cache Write Policies

    If a cache line has not been modified, then it can be overwritten immediately; however,
    if one or more words have been written to a cache line, then main memory must be
    updated before replacing the cache line.

    There are two main potential write problems:

    • If an I/O module is able to read/write to memory directly, then if the cache has
    been modified a memory read cannot happen right away. If memory is written to,
    then the cache line becomes invalid.

    • If multiple processors each have their own cache, if one processor modifies its
    cache, then the cache lines of the other processors could be invalid.

    1. write through – this is the simplest technique where all write operations are made to
    memory as well as cache ensuring main memory is always valid. This generates a lot of
    main memory traffic and creates a potential bottleneck

    2. write back – updates are made only to the cache and not to main memory until the
    line is replaced

    cache coherency – keeps the same word in other caches up to date using some
    technique. This is an active field of reseach.

    Cache Line Size

    Cache lines sizes between 8 to 64 bytes seem to produce optimum results


    1
    Multilevel Caches

    An on-chip cache reduces the processor's external bus activity. Further, an off-chip
    cache is usually desirable. This is the typical level 1 (L1) and level 2 (L2) cache design
    where the L2 cache is composed of static RAM.

    As chip densities have increased, the L2 cache has been moved onto the on-chip area
    and an additional L3 cache has been added.

    Unified vs Split Caches

    Recent cache designs have gone from a unified cache to a split cache design (one for
    instructions and one for data).

    Unified caches have the following advantages:

    1. unified caches typically have a higher hit rate

    2. only one cache is designed and implemented

    Split caches have the following advantages:

    1. parallel instruction execution and prefetching is better handled because of the


    elimination of contention between the instruction fetch/decode unit and execution unit.

    2
    3
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