Chapter 2.

Machine
Instructions and
Programs
Objectives
l Machine instructions and program execution,
including branching and subroutine call and return
operations.
l Number representation and addition/subtraction in
the 2’s-complement system.
l Addressing methods for accessing register and
memory operands.
l Assembly language for representing machine
instructions, data, and programs.
l Program-controlled Input/Output operations.
Indexing and Arrays
l Index mode – the effective address of the operand is
generated by adding a constant value to the
contents of a register.
l Index register
l X(Ri): EA = X + [Ri]
l The constant X may be given either as an explicit
number or as a symbolic name representing a
numerical value.
l If X is shorter than a word, sign-extension is needed.
Indexing and Arrays
l In general, the Index mode facilitates access
to an operand whose location is defined
relative to a reference point within the data
structure in which the operand appears.
l Several variations:
(Ri, Rj): EA = [Ri] + [Rj]
X(Ri, Rj): EA = X + [Ri] + [Rj]
Relative Addressing
l Relative mode – the effective address is determined
by the Index mode using the program counter in
place of the general-purpose register.
l X(PC) – note that X is a signed number
l Branch>0 LOOP
l This location is computed by specifying it as an
offset from the current value of PC.
l Branch target may be either before or after the
branch instruction, the offset is given as a singed
num.
Additional Modes
l Autoincrement mode – the effective address of the operand is
the contents of a register specified in the instruction. After
accessing the operand, the contents of this register are
automatically incremented to point to the next item in a list.
l (Ri)+. The increment is 1 for byte-sized operands, 2 for 16-bit
operands, and 4 for 32-bit operands.
l Autodecrement mode: -(Ri) – decrement first
Move N,R1
Move #NUM1,R2 Initialization
Clear R0
LOOP Add (R2)+,R0
Decrement R1
Branch>0 LOOP
Move R0,SUM

Figure 2.16. The Autoincrement addressing mode used in the program of Fig
Assembly Language
Types of Instructions
l Data Transfer Instructions
Name Mnemonic Data value is
Load LD not modified
Store ST
Move MOV
Exchange XCH
Input IN
Output OUT
Push PUSH
Pop POP
 Data Transfer Instructions
Mode Assembly Register Transfer
Direct address LD ADR AC ← M[ADR]
Indirect address LD @ADR AC ← M[M[ADR]]
Relative address LD $ADR AC ← M[PC+ADR]
Immediate operand LD #NBR AC ← NBR
Index addressing LD ADR(X) AC ← M[ADR+XR]
Register LD R1 AC ← R1
Register indirect LD (R1) AC ← M[R1]
Autoincrement LD (R1)+ AC ← M[R1], R1 ← R1+1
 Data Manipulation Instructions
l Arithmetic Name Mnemonic
Increment INC
l Logical & Bit Manipulation Decrement DEC
Add ADD
l Shift Subtract SUB
Multiply MUL
Divide DIV
Name Mnemonic Add with carry ADDC
Clear CLR Subtract with borrow SUBB
Complement COM Negate NEG
Name Mnemonic
AND AND Logical shift right SHR
OR OR Logical shift left SHL
Exclusive-OR XOR Arithmetic shift right SHRA
Clear carry CLRC Arithmetic shift left SHLA
Set carry SETC Rotate right ROR
Complement carry COMC Rotate left ROL
Enable interrupt EI Rotate right through carry RORC
Disable interrupt DI Rotate left through carry ROLC
Program Control Instructions
Name Mnemonic
Branch BR
Jump JMP
Skip SKP
Subtract A – B but
Call CALL don’t store the result

Return RET
Compare
CMP
(Subtract) 10110001
Test (AND) TST
00001000

Mask
00000000
Conditional Branch
Instructions

Mnemonic Branch Condition Tested Condition

BZ Branch if zero Z=1
BNZ Branch if not zero Z=0
BC Branch if carry C=1
BNC Branch if no carry C=0
BP Branch if plus S=0
BM Branch if minus S=1
BV Branch if overflow V=1
BNV Branch if no overflow V=0
 Additional
Instructions
Logical Shifts
l Logical shift – shifting left (LShiftL) and shifting right
(LShiftR)
C R0 0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(a) Logical shift left LShiftL #2,R0

0 R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 0 0 0 1 1 1 0 . . . 0 1

(b) Logical shift

ight
r LShiftR #2,R0
Arithmetic Shifts

R0 C

before: 1 0 0 1 1 . . . 0 1 0 0

after: 1 1 1 0 0 1 1 . . . 0 1

(c) Ar
ithmetic shift
ight
r AShiftR #2,R0
 C R0

. . .

Rotate
before: 0 0 1 1 1 0 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 1

(a) Rotate left without

y carr RotateL #2,R0

C R0

before: 0 0 1 1 1 0 . . . 0 1 1

after: 1 1 1 0 . . . 0 1 1 0 0

(b) Rotate left withy carr RotateLC #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 1 0 1 1 1 0 . . . 0 1

(c) Rotateight
r without carr
y RotateR #2,R0

R0 C

before: 0 1 1 1 0 . . . 0 1 1 0

after: 1 0 0 1 1 1 0 . . . 0 1

(d) Rotate
ight
r with carr
y RotateRC #2,R0

Figure 2.32. Rotate instructions.

Multiplication and Division
l Not very popular (especially division)
l Multiply Ri, Rj
Rj ← [Ri] х [Rj]
l 2n-bit product case: high-order half in R(j+1)
l Divide Ri, Rj
Rj ← [Ri] / [Rj]
Quotient is in Rj, remainder may be placed in R(j+1)
Encoding of Machine
Instructions
Encoding of Machine
Instructions
l Assembly language program needs to be converted into machine
instructions. (ADD = 0100 in ARM instruction set)
l In the previous section, an assumption was made that all
instructions are one word in length.
l OP code: the type of operation to be performed and the type of
operands used may be specified using an encoded binary pattern
l Suppose 32-bit word length, 8-bit OP code (how many instructions
can we have?), 16 registers in total (how many bits?), 3-bit
addressing mode indicator.
l Add R1, R2 8 7 7 10
l Move 24(R0), R5
OP code Source Dest Other info
l LshiftR #2, R0
l Move #$3A, R1
l Branch>0 LOOP (a) One-word instruction
Encoding of Machine
Instructions
l What happens if we want to specify a memory
operand using the Absolute addressing mode?
l Move R2, LOC
l 14-bit for LOC – insufficient
l Solution – use two words

OP code Source Dest Other info

Memory address/Immediate operand

(b) Two-word instruction

Encoding of Machine
Instructions
l Then what if an instruction in which two operands
can be specified using the Absolute addressing
mode?
l Move LOC1, LOC2
l Solution – use two additional words
l This approach results in instructions of variable
length. Complex instructions can be implemented,
closely resembling operations in high-level
programming languages – Complex Instruction Set
Computer (CISC)
Encoding of Machine
Instructions
l If we insist that all instructions must fit into a single
32-bit word, it is not possible to provide a 32-bit
address or a 32-bit immediate operand within the
instruction.
l It is still possible to define a highly functional
instruction set, which makes extensive use of the
processor registers.
l Add R1, R2 ----- yes
l Add LOC, R2 ----- no
l Add (R3), R2 ----- yes
Types of Instructions
• Arithmetic Instructions
l Use only register operand

• Data Transfer Instructions

• Logical Instructions
• Branch Instructions
l Conditional/Unconditional jump instructions
 MIPS Arithmetic

• All MIPS arithmetic instructions have 3 operands

• Operand order is fixed (e.g., destination first)

• Example:

C code: A = B + C
compiler’s job to associate
variables with registers
• MIPS code: add $s0, $s1, $s2
MIPS Arithmetic
• Of course this complicates some things...
C code: A = B + C + D;
E = F - A;
MIPS code add $t0, $s1, $s2 Allowing variable number
of operands would
(arithmetic): add $s0, $t0, $s3 simplify the assembly
sub $s4, $s5, $s0 code but complicate the
hardware.
Load/Store Instructions
• Load and Store instructions
• Example:
C code: A[8] = h + A[8];
l
value offset address

MIPS code (load): lw $t0, 32($s3)

(arithmetic): add $t0, $s2, $t0
(store): sw $t0, 32($s3)
• Load word has destination first, store has destination last
• Remember MIPS arithmetic operands are registers, not memory
locations
l therefore, words must first be moved from memory to registers using
loads before they can be operated on; then result can be stored back to
memory
 So far we’ve learned:

• MIPS
l loading words but addressing bytes
l arithmetic on registers only

l Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3

sub $s1, $s2, $s3 $s1 = $s2 – $s3
lw $s1, 100($s2) $s1 = Memory[$s2+100]
sw $s1, 100($s2) Memory[$s2+100]= $s1
 Machine Language
• Instructions, like registers and words of data, are also 32 bits long
l Example: add $t0, $s1, $s2
l registers are numbered, e.g., $t0 is 8, $s1 is 17, $s2 is 18

• Instruction Format R-type (“R” for aRithmetic):

000000 10001 10010 01000 00000 100000

op rs rt rd shamt funct
opcode – first second register shift function field -
operation register register destin- amount selects variant
source source ation of operation
operand operand operand

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

op rs rt rd shamt funct
MIPS Encoding: R-Type

31 26 25 21 20 16 15 11 10 6 5 0

opcode rs rt rd shamt funct

rd

rt
add $4, $3, $2

rs

31 26 25 21 20 16 15 11 10 6 5 0
0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0
opcode rs rt rd shamt funct

0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0

Encoding = 0x00622020
29
 Machine Language

• Consider the load-word and store-word instructions,

l what would the regularity principle allow us to do?
l we would have only 5 or 6 bits to determine the offset from a base
register - too little…

• Design Principle 3: Good design demands a compromise

• Introduce a new type of instruction format
l I-type (“I” for Immediate) for data transfer instructions
l Example: lw $t0, 1002($s2)
100011 10010 01000 0000001111101010
6 bits 5 bits 5 bits 16 bits
op rs rt 16 bit offset
MIPS Encoding: I-Type

31 26 25 21 20 16 15 0

opcode rs rt Immediate Value

rt
Immediate
lw $5, 3000($2)

rs

31 26 25 21 20 16 15 0
1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
opcode rs rt Immediate Value

1 0 0 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0

Encoding = 0x8C450BB8
31
MIPS Encoding: I-Type

31 26 25 21 20 16 15 0

opcode rs rt Immediate Value

rt
Immediate
sw $5, 3000($2)

rs

31 26 25 21 20 16 15 0
1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0
opcode rs rt Immediate Value

1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 1 1 0 0 0

Encoding = 0xAC450BB8
32
The immediate value is signed
Immediate Operands

• Example: addi $sp, $sp, 4 # $sp = $sp + 4

001000 11101 11101 0000000000000100

6 bits 5 bits 5 bits 16 bits

op rs rt 16 bit number
Shift Operations
op rs rt rd shamt funct
6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

• shamt: how many positions to shift

• Shift left logical (SLL $S1,$S2,10)

l Shift left and fill with 0 bits
l sll by i bits multiplies by 2i

• Shift right logical (SRL $S1,$S2,10)

l Shift right and fill with 0 bits
l srl by i bits divides by 2i (unsigned only)
 Control: Conditional Branch
• Decision making instructions
l alter the control flow,
l i.e., change the next instruction to be executed

• MIPS conditional branch instructions:

bne $t0, $t1, Label I-type
beq $t0, $t1, Label
instructions

000100 01000 01001 0000000000011001 beq $t0, $t1, Label

(= addr.100)
l Example: if (i==j) h = i + j;
word-relative addressing:
bne $s0, $s1, Label 25 words = 100 bytes;
add $s3, $s0, $s1 also PC-relative (more…)
Label: ....
BEQ/BNE uses I-Type

31 26 25 21 20 16 15 0

opcode rs rt Signed Offset Value

(encoded in words, e.g. 4-bytes)
rs
Offset
beq $0, $9, 40 Encoded by
40/4 = 10
rt

31 26 25 21 20 16 15 0
0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0
opcode rs rt Immediate Value

0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

Encoding = 0x1009000A
36
Control: Unconditional Branch
(Jump)
l MIPS unconditional branch instructions:
j Label
l Example:
if (i!=j) beq $s4, $s5, else
h=i+j; add $s3, $s4, $s5
else j exit
h=i-j; else: sub $s3, $s4, $s5
exit: ...
l J-type (“J” for Jump) instruction format
l Example: j Label # addr. Label = 100 word-relative
addressing:
25 words = 100 bytes
000010 00000000000000000000011001
6 bits 26 bits
op 26 bit number
l Any Queries?