HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.

K.Venkateswarlu, Asst. Prof

INDEX

1. Introduction
2. List of experiments
3. General guidelines for conducting an experiment
3.1 Simulation
3.1.1 Creating a project
3.1.2 VHDL design entry
3.1.3 VERILOG design entry
3.1.4 Functional verification
3.2 Implementation
3.2.1 Creating timing constraints
3.2.2 Verification of constraints
3.2.3 Assigning pin location constraints
3.2.4 Downloading design to Spartan-3 demo kit
3.3 Do’s and Don’ts
4. Experiments
4.1 HDL code to realize all the logic gates
4.1.1 AIM
4.1.2 VHDL simulation
4.1.3 VERILOG simulation
4.1.4 Design implementation
4.2 Design of 2 – to – 4 decoder
4.2.1 AIM
4.2.2 VHDL simulation
4.2.3 VERILOG simulation
4.2.4 Design implementation
4.3 Design of 8-to-3 encoder (with Priority and without priority)
4.3.1 Aim
4.3.2 VHDL simulation
4.3.3 VERILOG simulation
4.3.4 Design implementation
4.4 Design of 8-to-1 multiplexer and 1-to-8 de-multiplexer
4.4.1 Aim
4.4.2 VHDL simulation
4.4.3 VERILOG simulation
4.4.4 Design implementation
4.5 Design of 4 bit binary to gray code converter
4.5.1 Aim
4.5.2 VHDL simulation
4.5.3 VERILOG simulation
4.5.4 Design implementation
4.6 Design of 4 bit comparator
4.6.1 Aim
4.6.2 VHDL simulation
4.6.3 VERILOG simulation
4.6.4 Design implementation

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4.7 Design of full adder using 3 modeling styles

4.7.1 Aim
4.7.2 VHDL simulation
4.7.3 VERILOG simulation
4.7.4 Design implementation
4.8 Design of flip flops: RS, D, JK, T
4.8.1 Aim
4.8.2 VHDL simulation
4.8.3 VERILOG simulation
4.8.4 Design implementation
4.9 Design of 4 bit binary, BCD converter (Synchronous/ asynchronous)
4.9.1 Aim
4.9.2 VHDL simulation
4.9.3 VERILOG simulation
4.9.4 Design implementation
4.10 Finite state machine design
4.10.1 Aim
4.10.2 VHDL simulation
4.10.3 VERILOG simulation
4.10.4 Design implementation

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

1.Introduction
HDL simulation lab is for B.Tech III ,I- semester. It is a part of IC Applications and HDL
simulation lab (code : A50488, Part-II ). Students learn the theory subject (DDVHDL) in II
year II semester. This lab experiments are meant to give hands on experience to the students
on the subject, DDVHDL. HDL is meant for designing, testing, debugging and prototyping
simple to complex digital circuits. HDL is having two languages namely, VHDL and
VERILOG.

There are ten experiments in this lab. All the experiments are provided with VHDL and
VERILOG codes and the procedure to prototype on FPGA according to JNTUH R-13
syllabus, out of which at least seven experiments have to be performed.
The list of experiments is given in section -2. Section-3 deals with general guidelines to
conduct an experiment. The VHDL, VERILOG program codes of each experiment along
with the expected waveforms and procedure to prototype on FPGA is provided in section – 4.

2. List of Experiments
1. HDL code to realize all the logic gates.

2. Design of 2-to-4 decoder

3. Design of 8-to-3 encoder (without and with parity)

4. Design of 8-to-1 multiplexer and 1-to-8 de-multiplexer

5. Design of 4 bit binary to gray code converter

6. Design of 4 bit comparator

7. Design of full adder using 3 modeling styles

8. Design of flip flops: SR, D, JK, T

9. Design of 4 bit binary, BCD counters (Synchronous/ asynchronous reset)

10. Finite state machine design

Additional experiments beyond the syllabus

1. Ripple carry adder

2. Modeling of shift registers

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3.0 General guidelines and procedures to conduct an experiment

Each experiment has to be first simulated using XILINX, both with VHDL and VERILOG.
Then the circuit has to be tested using a test bench in simulation level. After simulation is
over, the circuit has to be implemented on FPGA Spartan -3 startup kit.
Each experiment will have to follow the following steps:
- Design description/Design entry (Design is described in various levels of
abstraction)
- Functional verification (functionality of the design is tested by test benches)
- Synthesis (converting the design description in to gate level netlist)
- Implementation (The synthesized circuit is mapped on to FPGA via proper
interface and programming)

3.1 Simulation
3.1.1 Creating a new project
Create a New Project
Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit
demo board.
To create a new project:
1. Select File > New Project... The New Project Wizard appears.
2. Type tutorial in the Project Name field.
3. Enter or browse to a location (directory path) for the new project. A tutorial
subdirectory is created automatically.
4. Verify that HDL is selected from the Top-Level Source Type list.
5. Click Next to move to the device properties page.
6. Fill in the properties in the table as shown below:
♦ Product Category: All
♦ Family: Spartan3
♦ Device: XC3S200
♦ Package: FT256
♦ Speed Grade: -4
♦ Top-Level Source Type: HDL
♦ Synthesis Tool: XST (VHDL/Verilog)
♦ Simulator: ISE Simulator (VHDL/Verilog)
♦ Preferred Language: Verilog (or VHDL)
♦ Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:

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Figure 2: Project Device Properties

7. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.
Create an HDL Source
In this section, you will create the top-level HDL file for your design. Determine the
language that you wish to use for the tutorial. Then, continue either to the “Creating a
VHDL Source” section below, or skip to the “Creating a Verilog Source” section.

3.1.2 VHDL design entry

Creating a VHDL Source

Create a VHDL source file for the project as follows:
1. Click the New Source button in the New Project Wizard.
2. Select VHDL Module as the source type.
3. Type in the file name counter.
4. Verify that the Add to project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown
below:
7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete
the new source file template.
8. Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below:

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Figure 3:

7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete
the new source file template.
8. Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and the
counter displays in the Source tab, as shown below:

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Using Language Templates (VHDL)

The next step in creating the new source is to add the behavioral description for the
counter. To do this you will use a simple counter code example from the ISE Language
Templates and customize it for the counter design.
1. Place the cursor just below the begin statement within the counter architecture.
2. Open the Language Templates by selecting Edit → Language Templates…
Note: You can tile the Language Templates and the counter file by selecting Window → Tile
Vertically to make them both visible.
3. Using the “+” symbol, browse to the following code example:
VHDL → Synthesis Constructs → Coding Examples → Counters → Binary →
Up/Down Counters → Simple Counter
4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in
File toolbar button. This step copies the template into the counter source file.
5. Close the Language Templates.
Final Editing of the VHDL Source
1. Add the following signal declaration to handle the feedback of the counter output
below the architecture declaration and above the first begin statement:
signal count_int : std_logic_vector(3 downto 0) := "0000";
2. Customize the source file for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
♦ replace all occurrences of <clock> with CLOCK
♦ replace all occurrences of <count_direction> with DIRECTION
♦ replace all occurrences of <count> with count_int
3. Add the following line below the end process; statement:
COUNT_OUT <= count_int;
4. Save the file by selecting File → Save.
When you are finished, the counter source file will look like the following:
library IEEE;

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use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitive in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity counter is
Port ( CLOCK : in STD_LOGIC;
DIRECTION : in STD_LOGIC;
COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0));
end counter;
architecture Behavioral of counter is
signal count_int : std_logic_vector(3 downto 0) := "0000";
begin
process (CLOCK)
begin
if CLOCK='1' and CLOCK'event then
if DIRECTION='1' then
count_int <= count_int + 1;
else
count_int <= count_int - 1;
end if;
end if;
end process;
COUNT_OUT <= count_int;
end Behavioral;
You have now created the VHDL source for the tutorial project. Skip past the Verilog
sections below, and proceed to the “Checking the Syntax of the New Counter
Module”section.

3.1.3 VERILOG design entry

Creating a Verilog Source

Create the top-level Verilog source file for the project as follows:
1. Click New Source in the New Project dialog box.
2. Select Verilog Module as the source type in the New Source dialog box.
3. Type in the file name counter.
4. Verify that the Add to Project checkbox is selected.
5. Click Next.
6. Declare the ports for the counter design by filling in the port information as shown
below:

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7. Click Next, then Finish in the New Source Information dialog box to complete the new
source file template.
8. Click Next, then Next, then Finish.
The source file containing the counter module displays in the Workspace, and the counter
displays in the Sources tab, as shown below:

Using Language Templates (Verilog)

The next step in creating the new source is to add the behavioral description for counter.
Use a simple counter code example from the ISE Language Templates and customize it for
the counter design.

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1. Place the cursor on the line below the output [3:0] COUNT_OUT; statement.
2. Open the Language Templates by selecting Edit → Language Templates…
Note: You can tile the Language Templates and the counter file by selecting Window → Tile
Vertically to make them both visible.
3. Using the “+” symbol, browse to the following code example:
Verilog → Synthesis Constructs → Coding Examples → Counters → Binary →
Up/Down Counters → Simple Counter
4. With Simple Counter selected, select Edit → Use in File, or select the Use Template in
File toolbar button. This step copies the template into the counter source file.
5. Close the Language Templates.
Final Editing of the Verilog Source
1. To declare and initialize the register that stores the counter value, modify the
declaration statement in the first line of the template as follows:
replace: reg [<upper>:0] <reg_name>;
with: reg [3:0] count_int = 0;
2. Customize the template for the counter design by replacing the port and signal name
placeholders with the actual ones as follows:
♦ replace all occurrences of <clock> with CLOCK
♦ replace all occurrences of <up_down> with DIRECTION
♦ replace all occurrences of <reg_name> with count_int
3. Add the following line just above the endmodule statement to assign the register value
to the output port:
assign COUNT_OUT = count_int;
4. Save the file by selecting File → Save.
When you are finished, the code for the counter will look like the following:
module counter(CLOCK, DIRECTION, COUNT_OUT);
input CLOCK;
input DIRECTION;
output [3:0] COUNT_OUT;
);
reg [3:0] count_int = 0;
always @(posedge CLOCK)
if (DIRECTION)
count_int <= count_int + 1;
else
count_int <= count_int - 1;
assign COUNT_OUT = count_int;
endmodule
You have now created the Verilog source for the tutorial project.
Checking the Syntax of the New Counter Module
When the source files are complete, check the syntax of the design to find errors and typos.
1. Verify that Implementation is selected from the drop-down list in the Sources
window.
2. Select the counter design source in the Sources window to display the related
processes in the Processes window

3. Click the “+” next to the Synthesize-XST process to expand the process group.
4. Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for errors in the
Console tab of the Transcript window. If you continue without valid syntax, you will not be able to
simulate or synthesize your design.
5. Close the HDL file.

3.1.4 Functional verification

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Design Simulation
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the
functionality of the counter module. The test bench waveform is a graphical view of a test
bench.
Create the test bench waveform as follows:
1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project → New Source.
3. In the New Source Wizard, select Test Bench WaveForm as the source type, and type
counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench waveform
with the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays
the source directory, type, and name. Click Finish.
7. You need to set the clock frequency, setup time and output delay times in the Initialize
Timing dialog box before the test bench waveform editing window opens.
The requirements for this design are the following:
♦ The counter must operate correctly with an input clock frequency = 25 MHz.
♦ The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
♦ The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.
The design requirements correspond with the values below.
Fill in the fields in the Initialize Timing dialog box with the following information:
♦ Clock High Time: 20 ns.
♦ Clock Low Time: 20 ns.
♦ Input Setup Time: 10 ns.
♦ Output Valid Delay: 10 ns.
♦ Offset: 0 ns.
♦ Global Signals: GSR (FPGA)
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.
♦ Initial Length of Test Bench: 1500 ns.
Leave the default values in the remaining fields.

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Figure 7: Initialize Timing

8. Click Finish to complete the timing initialization.

9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the
Input Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to
define the input stimulus for the counter design as follows:
♦ Click on the blue cell at approximately the 300 ns to assert DIRECTION high so
that the counter will count up.
♦ Click on the blue cell at approximately the 900 ns to assert DIRECTION low so
that the counter will count down.
Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar buttons

Figure 8: Test Bench Waveform

10. Save the waveform.
11. In the Sources window, select the Behavioral Simulation view to see that the test
bench waveform file is automatically added to your project

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Figure 9: Behavior Simulation Selection

Simulating Design Functionality
Verify that the counter design functions as you expect by performing behavior simulation
as follows:
1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources
window.
2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and
double-click the Simulate Behavioral Model process.
The ISE Simulator opens and runs the simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the
transitions.

The simulation waveform results will look like the following:

Figure 10: Simulation Results

Note: You can ignore any rows that start with TX.
4. Verify that the counter is counting up and down as expected.
5. Close the simulation view. If you are prompted with the following message, “You have
an active simulation open. Are you sure you want to close it?“, click Yes to continue.
You have now completed simulation of your design using the ISE Simulator.

3.2 Design Implementation

The design implementation is having the following steps.
- Creating timing constraints
- Verifying constraints
- Assigning pin location constraints
- Downloading design to Spartan-3 demo kit
3.2.1 Creating timing constraints

Create Timing Constraints

Specify the timing between the FPGA and its surrounding logic as well as the frequency
the design must operate at internal to the FPGA. The timing is specified by entering
constraints that guide the placement and routing of the design. It is recommended that you
enter global constraints. The clock period constraint specifies the clock frequency at which

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your design must operate inside the FPGA. The offset constraints specify when to expect
valid data at the FPGA inputs and when valid data will be available at the FPGA outputs.

Entering Timing Constraints

To constrain the design do the following:
1. Select Implementation from the drop-down list in the Sources window.
2. Select the counter HDL source file.
3. Click the “+” sign next to the User Constraints processes group, and double-click the
Create Timing Constraints process.
ISE runs the Synthesis and Translate steps and automatically creates a User
Constraints File (UCF). You will be prompted with the following message:

Figure 11: Prompt to Add UCF File to Project

4. Click Yes to add the UCF file to your project.
The counter.ucf file is added to your project and is visible in the Sources window.
The Xilinx Constraints Editor opens automatically.
Note: You can also create a UCF file for your project by selecting Project → Create New
Source.
5. In the Timing Constraints dialog, enter the following in the Period, Pad to Setup, and
CLock to Pad fields:
♦ Period: 40
♦ Pade to Setup: 10
♦ Clock to Pad: 10
6. Press Enter.
After the information has been entered, the dialog should look like what is shown
below..

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Figure 12: Creating Timing Constraints

7. Select Timing Constraints under Constraint Type in the Timing Constraints tab and
the newly created timing constraints are displayed as follows:

Figure 13: Timing Constraints

8. Save the timing constraints. If you are prompted to rerun the TRANSLATE or XST
step, click OK to continue.
9. Close the Constraints Editor.

3.2.2 Verification of constraints

Implement Design and Verify Constraints

Implement the design and verify that it meets the timing constraints specified in the
previous section.
Implementing the Design
1. Select the counter source file in the Sources window.
2. Open the Design Summary by double-clicking the View Design Summary process in
the Processes tab.
3. Double-click the Implement Design process in the Processes tab.
4. Notice that after Implementation is complete, the Implementation processes have a
green check mark next to them indicating that they completed successfully without
Errors or Warnings.

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Figure 14: Post Implementation Design Summary

6. Locate the Performance Summary table near the bottom of the Design Summary.
7. Click the All Constraints Met link in the Timing Constraints field to view the Timing
Constraints report. Verify that the design meets the specified timing requirements

Figure 15: All Constraints Met Report

8. Close the Design Summary.

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3.2.3 Assigning Pin location constraints

Assigning Pin Location Constraints

Specify the pin locations for the ports of the design so that they are connected correctly on
the Spartan-3 Startup Kit demo board.
To constrain the design ports to package pins, do the following:
1. Verify that counter is selected in the Sources window.
2. Double-click the Floorplan Area/IO/Logic - Post Synthesis process found in the
User Constraints process group. The Xilinx Pinout and Area Constraints Editor
(PACE) opens.
3. Select the Package View tab.
4. In the Design Object List window, enter a pin location for each pin in the Loc column
using the following information:
♦ CLOCK input port connects to FPGA pin T9 (GCK0 signal on board)
♦ COUNT_OUT<0> output port connects to FPGA pin K12 (LD0 signal on board)
♦ COUNT_OUT<1> output port connects to FPGA pin P14 (LD1 signal on board)
♦ COUNT_OUT<2> output port connects to FPGA pin L12 (LD2 signal on board)
♦ COUNT_OUT<3> output port connects to FPGA pin N14 (LD3 signal on board)
♦ DIRECTION input port connects to FPGA pin K13 (SW7 signal on board)
Notice that the assigned pin locations are shown in blue:

Figure 16: Package Pin Locations

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5. Select File → Save. You are prompted to select the bus delimiter type based on the
synthesis tool you are using. Select XST Default <> and click OK.
6. Close PACE.
Notice that the Implement Design processes have an orange question mark next to them,
indicating they are out-of-date with one or more of the design files. This is because the UCF
file has been modified.
Reimplement Design and Verify Pin Locations
Reimplement the design and verify that the ports of the counter design are routed to the
package pins specified in the previous section.
First, review the Pinout Report from the previous implementation by doing the following:
1. Open the Design Summary by double-clicking the View Design Summary process in
the Processes window.
2. Select the Pinout Report and select the Signal Name column header to sort the signal
names. Notice the Pin Numbers assigned to the design ports in the absence of location
constraints.

Figure 17: Package Pin Locations Prior to Pin Location Constraints

3. Reimplement the design by double-clicking the Implement Design process.
4. Select the Pinout Report again and select the Signal Name column header to sort the
signal names.
5. Verify that signals are now being routed to the correct package pins.

Figure 18: Package Pin Locations After Pin Location Constraints

6. Close the Design Summary.

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3.2.4 Downloading design to Spartan-3 demo kit

Download Design to the Spartan™-3 Demo Board

This is the last step in the design verification process. This section provides simple
instructions for downloading the counter design to the Spartan-3 Starter Kit demo board.
1. Connect the 5V DC power cable to the power input on the demo board (J4).
2. Connect the download cable between the PC and demo board (J7).
3. Select Implementation from the drop-down list in the Sources window.
4. Select counter in the Sources window.
5. In the Process window, double-click the Configure Target Device process.
6. The Xilinx WebTalk Dialog box may open during this process. Click Decline.
iMPACT opens and the Configure Devices dialog box is displayed.

Figure 19: iMPACT Welcome Dialog Box

7. In the Welcome dialog box, select Configure devices using Boundary-Scan (JTAG).
8. Verify that Automatically connect to a cable and identify Boundary-Scan chain is
selected.
9. Click Finish.
10. If you get a message saying that there are two devices found, click OK to continue.
The devices connected to the JTAG chain on the board will be detected and displayed
in the iMPACT window.
11. The Assign New Configuration File dialog box appears. To assign a configuration file
to the xc3s200 device in the JTAG chain, select the counter.bit file and click Open.

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Figure 20: Assign New Configuration File

12. If you get a Warning message, click OK.
13. Select Bypass to skip any remaining devices.
14. Right-click on the xc3s200 device image, and select Program... The Programming
Properties dialog box opens.
15. Click OK to program the device.
When programming is complete, the Program Succeeded message is displayed.

On the board, LEDs 0, 1, 2, and 3 are lit, indicating that the counter is running.
16. Close iMPACT without saving.
You have completed the ISE Quick Start Tutorial. For an in-depth explanation of the ISE
design tools, see the ISE In-Depth Tutorial on the Xilinx® web site at:
http://www.xilinx.com/support/techsup/tutorials/

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3.3 Do’s and Don’ts

The students are to follow the given general Do’s and Don’ts for simulation lab.
Do’s:
1. Enter in to the simulation lab in time.
2. Wear student identity badges round your neck before entering the lab.
3. Keep silence in the lab
4. Follow the instructions of the lab in-charges and lab supervisor.
5. Always save your input files and results in the prescribed directory.
Don’ts:
1. Do not use internet or open any other programs other than MATLAB.
2. Do not mishandle or rough handle the keyboard of CPU.
3. Do not use pen drive or card reader without the permission of the lab in-charge.
4. Do not make noise in the lab.

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4.0 EXPERIMENTS

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Experiment No:1

4.1 HDL Code to realize all the logic gates

4.1.1 Aim: To Design Logic Gates using VHDL and simulate the same using
Xilinx ISE Simulator

Tools Required: 1.PC

2. Xilinx ISE

4.1.2 VHDL simulation

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity logic_gates is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
AND1 : out STD_LOGIC;
OR1 : out STD_LOGIC;
NOT1 : out STD_LOGIC;
XOR1 : out STD_LOGIC;
NAND1 : out STD_LOGIC;
NOR1 : out STD_LOGIC;
XNOR1 : out STD_LOGIC);
end logic_gates;
architecture Behavioral of logic_gates is
begin
AND1<=A AND B;
OR1<=A OR B;
NOT1<=NOT A;
XOR1<=A XOR B;
NAND1<= A NAND B;
NOR1<=A NOR B;
XNOR1<=A XNOR B;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

end Behavioral;

Synthesis Report
A) Final Report:
Final Results
RTL Top Level Output File Name : logic_gates.ngr
Top Level Output File Name : logic_gates
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
B) Design Statistics
# IOs :9
Cell Usage :
# BELS :7
# INV :1
# LUT2 :6
# IO Buffers :9
# IBUF :2
# OBUF :7
=====================================================================
====
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 4 out of 2448 0%
Number of 4 input LUTs: 7 out of 4896 0%
Number of IOs: 9
Number of bonded IOBs: 9 out of 172 5%
C) TIMING REPORT:
Delay: 5.998ns (Levels of Logic = 3)
Source: A (PAD)
Destination: NOR1 (PAD)
Data Path: A to NOR1
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 7 1.106 0.754 A_IBUF (A_IBUF)
LUT2:I0->O 1 0.612 0.357 OR11 (OR1_OBUF)
OBUF:I->O 3.169 OR1_OBUF (OR1)
----------------------------------------
Total 5.998ns

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_logic_gates_vhd IS

END tb_logic_gates_vhd;

ARCHITECTURE behavior OF tb_logic_gates_vhd IS

COMPONENT logic_gates

PORT(

A : IN std_logic;

B : IN std_logic;

AND1 : OUT std_logic;

OR1 : OUT std_logic;

NOT1 : OUT std_logic;

XOR1 : OUT std_logic;

NAND1 : OUT std_logic;

NOR1 : OUT std_logic;

XNOR1 : OUT std_logic

);

END COMPONENT;

SIGNAL A : std_logic := '0';

SIGNAL B : std_logic := '0';

SIGNAL AND1 : std_logic;

SIGNAL OR1 : std_logic;

SIGNAL NOT1 : std_logic;

SIGNAL XOR1 : std_logic;

SIGNAL NAND1 : std_logic;

SIGNAL NOR1 : std_logic;

SIGNAL XNOR1 : std_logic;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

BEGIN

uut: logic_gates PORT MAP(

A => A,

B => B,

AND1 => AND1,

OR1 => OR1,

NOT1 => NOT1,

XOR1 => XOR1,

NAND1 => NAND1,

NOR1 => NOR1,

XNOR1 => XNOR1

);

A<='1' AFTER 10NS,'0' AFTER 20NS,'1' AFTER 30NS;

B<='1' AFTER 20NS;

END;

Simulation Results:

#1-TITLE: AND gate

LOGIC GATE SYMBOL:

X
Y Z

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

7408N
TRUTH TABLE:

x y z

0 0 0

0 1 0

1 0 0

1 1 1

VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;

entity AND2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
); end
AND2;

--Dataflow model

architecture behav1 of AND2 is

begin

Z<= x and y; --Signal Assignment Statement

end behav1;

-- Behavioral model

architecture behav2 of AND2 is

begin

process (x, y)
begin

if (x='1' and y='1') then -- Compare with truth table

Z <= '1';
else
Z <= '0'; end
if;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

end process;

end behav2;
OUTPUT WAVEFORM:

#2-TITLE: OR gate

LOGIC GATE SYMBOL:

X 7432
Z
Y

TRUTH TABLE:

x y z

0 0 0

0 1 1

1 0 1

1 1 1
VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;

entity OR2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
);
end OR2;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

--Dataflow model architecture

behav1 of OR2 is begin

Z <= x or y; --Signal Assignment Statement

end behav1;
-- Behavioral model

architecture behav2 of OR2 is

begin

process (x, y)
begin

if (x='0' and y='0') then -- Compare with truth table

Z <= '0';
else
Z<= '1';
end if;

end process;
end behav2;
OUTPUT WAVEFORM:

#3-TITLE: NOT gate

LOGIC GATE SYMBOL:

X Y

7404
VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;

ECE department, Mahaveer institute of science and technology, Hyderabad Page 29

HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

entity not1 is
port(
X: in STD_LOGIC; Z:
out STD_LOGIC
); end
not1;

--Dataflow model
architecture behav1 of not1 is
begin

Z<= not X; --Signal Assignment Statement

end behav1;

-- Behavioral model
architecture behav2 of not1 is
begin

process (X)
begin

if (x='0') then -- Compare with truth table

Z <= '1';
else
Z<= '0';
end if;

end process;

end behav2;

OUTPUT WAVEFORM:

#4-TITLE: NAND gate

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

LOGIC GATE SYMBOL:

X
Z
Y
7400
TRUTH TABLE:

x y z

0 0 1

0 1 1

1 0 1

1 1 0
VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;

entity nand2 is
port(
x : in STD_LOGIC;
y : in STD_LOGIC;
z : out STD_LOGIC
); end
nand2;

--Dataflow model

architecture behav1 of nand2 is

begin

z<= x nand y; --Signal Assignment Statement

end behav1;

-- Behavioral model

architecture behav2 of nand2 is

begin

Process (x, y)
Begin

If (x='1' and y='1') then -- Compare with truth table

Z <= '0';

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

else
Z <= '1';
end if;

end process;

end behav2;
OUTPUT WAVEFORM:

#5- TITLE: NOR gate

LOGIC GATE SYMBOL:

X
Z
Y
TRUTH TABLE: 7402

x y z

0 0 1

0 1 0

1 0 0

1 1 0

VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;

ECE department, Mahaveer institute of science and technology, Hyderabad Page 32

HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

entity nor2 is Port

(
X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC
);
end nor2;
--Dataflow model

architecture behav1 of nor2 is

begin

Z<= x nor y; --Signal Assignment Statement

end behav1;

-- Behavioral model

architecture behav2 of nor2 is

begin

process (x, y)
begin

If (x='0' and y='0') then -- Compare with truth table

Z <= '1';
else
Z <= '0';
end if;

end process;

end behav2;

OUTPUT WAVEFORM:

#6-TITLE: EX-OR gate

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

LOGIC GATE SYMBOL:

X
Z
Y
7486
TRUTH TABLE:

x y z

0 0 0

0 1 1

1 0 1

1 1 0

VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;

entity xor2 is Port

(
X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC
);
end xor2;

--Dataflow model

architecture behav1 of xor2 is

begin

Z<= x xor y; --Signal Assignment Statement

end behav1;
Behavioral model

architecture behav2 of xor2 is

begin

process (x, y)
begin

If (x/=y) then -- Compare with truth table

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Z <= '1';
else
Z<= '0';
end if;

end process;

end behav2;

OUTPUT WAVEFORM:

#7-TITLE: EX-NOR gate

LOGIC GATE SYMBOL:

X
Z
Y

TRUTH TABLE:

x y z

0 0 1

0 1 0

1 0 0

1 1 1

VHDL CODE:

Library IEEE;
use IEEE.std_logic_1164.all;

ECE department, Mahaveer institute of science and technology, Hyderabad Page 35

HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

entity xnor2 is
Port (
X: in STD_LOGIC;
Y: in STD_LOGIC;
Z: out STD_LOGIC
); end
xnor2;

--Dataflow model

architecture behav1 of xnor2 is

begin

Z<= x xnor y; --Signal Assignment Statement

end behav1;

-- Behavioral model

architecture behav2 of xnor2 is

begin

process (x, y)
begin
If (x=y) then -- Compare with truth table
Z <= '1';
else
Z<= '0';
end if;

end process;

end behav2;

OUTPUT WAVEFORM:

ECE department, Mahaveer institute of science and technology, Hyderabad Page 36

HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

4.1.3 Verilog simulation

// Design description for all the basic gates

module allgates(not1,or2,and3,nor4,nand5,xor6,xnor7,A,B);
input A, B;
output not1,or2,and3,nor4,nand5,xor6,xnor7;
reg not1,or2,and3,nor4,nand5,xor6,xnor7;
always@(Aor B)
begin
not1 = ~A;
or2 = A|B;
and3 = A&B;
nor4 = ~(A|B);
nand5 = ~(A&B);
xor6 = (A^B);
xnor7 = ~(A^B);
end
endmodule

// Test bench for all gates

module allgatestest;
reg a,b;
allgates gg(not1,or2,and3,nor4,nand5,xor6,xnor7,a,b); //instatiation of module allgates
always
begin
a = 1’b0, b=1’b0;
#3 a=1’b1,b=1’b0;
#3 a=1’b1,b=1’b1;
#3 a=1’b0,b=1’b1;
#3 a=1’b0,b=1’b0;
#3 a=1’b1,b=1’b1;
end
initial
$minotor($time, “a=%b, b=%b, not1 = %b,
or2=%b,and3=%b,nor4=%b,nand5=%b,xor6=%b,xnor7=%b”,
a,b,not1,or2,and3,nor4,nand5,xor6,xnor7);
Initial #24 $stop;
endmodule
4.1.4 Implementation:
Implementation can be done on Spartan-3 FPGA kit as described in section -3

Result:
Logic Gates are designed using VHDL , VERILOG and simulated the same using Xilinx ISE
Simulator

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Experiment No:2

4.2 Design of 2-to-4 decoder

4.2.1 Aim: To Design 2-To-4 decoder using VHDL and simulate the same
using Xilinx ISE Simulator

Tools Required: 1.PC

2. Xilinx ISE

4.2.3 VHDL simulation

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity decoder is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (1 downto 0);
Y : out STD_LOGIC_VECTOR (3 downto 0));
end decoder;
architecture Behavioral of decoder is
begin
process(En,I)
begin
if En='0' then Y<="0000";
else
case I is
when "00" =>Y<="0001";
when "01" =>Y<="0010";
when "10" =>Y<="0100";
when "11" =>Y<="1000";
when others =>Y<="ZZZZ";
end case;
end if;
end process;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

end Behavioral;
Synthesis Report
Final Report:
Final Results
RTL Top Level Output File Name : decoder.ngr
Top Level Output File Name : decoder
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :7
Cell Usage :
# BELS :4
# LUT3 :4
# IO Buffers :7
# IBUF :3
# OBUF :4
=========================================================================

Device utilization summary:

Selected Device : 3s250eft256-5

Number of Slices: 2 out of 2448 0%
Number of 4 input LUTs: 4 out of 4896 0%
Number of IOs: 7
Number of bonded IOBs: 7 out of 172 4%
TIMING REPORT:

Delay: 5.895ns (Levels of Logic = 3)

Source: I<1> (PAD)
Destination: Y<3> (PAD)

Data Path: I<1> to Y<3>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 I_1_IBUF (I_1_IBUF)
LUT3:I0->O 1 0.612 0.357 Y<3>1 (Y_3_OBUF)
OBUF:I->O 3.169 Y_3_OBUF (Y<3>)
----------------------------------------
Total 5.895ns

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_decoder_vhd IS
END tb_decoder_vhd;
ARCHITECTURE behavior OF tb_decoder_vhd IS
COMPONENT decoder
PORT(
En : IN std_logic;
I : IN std_logic_vector(1 downto 0);
Y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL En : std_logic := '0';
SIGNAL I : std_logic_vector(1 downto 0) := (others=>'0');
SIGNAL Y : std_logic_vector(3 downto 0);
BEGIN
uut: decoder PORT MAP(
En => En,
I => I,
Y => Y
);
En<='1' after 10ns;

I<="01" after 20ns,"10" after 30ns,"11" after 40ns;

END;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Simulation Results:

Schematic Diagram:

3x8 DECODER
AIM: Write a VHDL code for IC74138 -3X8 Decoder

TITLE: IC74138—3x8 Decoder.

BLOCK DIAGRAM:

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

TRUTH TABLE:
S.No Enable inputs Encoded inputs Decoded
g1 g2a_l g2b_l A B C output
1 0 X X X X X 11111111
2 1 1 X X X X 11111111
3 1 X 1 X X X 11111111
4 1 0 0 0 0 0 01111111
5 1 0 0 0 0 1 10111111
6 1 0 0 0 1 0 11011111
7 1 0 0 0 1 1 11101111
8 1 0 0 1 0 0 11110111
9 1 0 0 1 0 1 11111011
10 1 0 0 1 1 0 11111101
11 1 0 0 1 1 1 11111110
VHDL CODE:
library IEEE;
use IEEE.std_logic_1164.all;
entity decoder3X8 is
port (
g1 : in STD_LOGIC; --g1, g2a_l, g2b_l cascade i/ps g2a_l
: in STD_LOGIC;
g2b_l : in STD_LOGIC;
a : in STD_LOGIC_VECTOR (2 downto 0); y_l : out
STD_LOGIC_VECTOR (0 to 7)

);
end decoder3X8;

architecture deco38 of decoder3X8 is

begin
process (a,g1,g2a_l,g2b_l)
begin
if (g1 and not g2a_l and not g2b_l)='1'then if a
<= "000"then y_l<= "01111111";
elsif a <= "001"then y_l <= "10111111"; elsif
a <= "010"then y_l<= "11011111"; elsif a <=
"011"then y_l <= "11101111"; elsif a <=
"100"then y_l <= "11110111"; elsif a <=
"101"then y_l <= "11111011"; elsif a <=
"110"then y_l <= "11111101"; elsif a <=
"111"then y_l <= "11111110"; else y_ l<=
"11111111";
end if;
else y_l <= "11111111";
end if;
end process;
end deco38;

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

WAVEFORMS

Result: 2-To-4 Decoder is designed using VHDL and simulated the same using Xilinx ISE
Simulator
4.2.3 Verilog simulation

// Code for 2-4 decoder simulation

module decoder(data,code);
output [3:0] data;
input [1:0] code;
reg [3:0] data;

always @ (code)
begin
if (code ==0) data = 4’b0001; else
if(code ==1) data = 4’b0010; else
if(code==2) data=4’b0100; else
data = 4’b1000;
end

/* Alternate description is
always @ (code)
case(code)
0 : data=4’b0001;
1 : data=4’b0010;
2 : data=4’b0100;
3 : data=4’b1000;
Endcase
*/

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Endmodule

//Test bench for 2-4 decoder

module decodertest;
reg [1:0]code;
decoder gg(data, code); // Instatiation of decoder block
always
begin
code = 2’b00;
#3 code = 2’b01;
#3 code=2’b10;
#3 code=2’b11;
end
$monitor($time, “code=%b, data = %b”,code,data);
Initial #24 $stop
endmodule

-----------------X-------------X---------------X-----------------X----------------X---------------

4.2.4 Implementation:

The decoder can be implemented on Spartan-3 FPGA kit as described in

section-3.

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Experiment No:3

4.3 Design of 8-to-3 encoder (without and with priority)

4.3.1 Aim: To Design 8-To-3 Encoder with and without Priority using VHDL and
simulate the same using Xilinx ISE Simulator.
Tools Required: 1.PC
2. Xilinx ISE

4.3.2 VHDL simulation

(A)Design of 8-to-3 encoder (without priority)

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encoder_without_priority is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end encoder_without_priority;
architecture Behavioral of encoder_without_priority is
begin
process(En,I)
begin
if En='0' then Y<="XXX";
else
case I is
when "00000001"=>Y<="000";
when "00000010"=>Y<="001";
when "00000100"=>Y<="010";
when "00001000"=>Y<="011";
when "00010000"=>Y<="100";
when "00100000"=>Y<="101";
when "01000000"=>Y<="110";
when "10000000"=>Y<="111";

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

when others=>Y<="ZZZ";
end case;
end if;
end process;
end Behavioral;

Simulation Results:

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_encoder_without_priority_vhd IS
END tb_encoder_without_priority_vhd;
ARCHITECTURE behavior OF tb_encoder_without_priority_vhd IS
COMPONENT encoder_without_priority
PORT(
En : IN std_logic;
I : IN std_logic_vector(7 downto 0);
Y : OUT std_logic_vector(2 downto 0)
);

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

END COMPONENT;
SIGNAL En : std_logic := '0';
SIGNAL I : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL Y : std_logic_vector(2 downto 0);
BEGIN

uut: encoder_without_priority PORT MAP(

En => En,
I => I,
Y => Y
);
En<='1' after 10ns;
I<="00000010" after 10ns,"00001000" after 20ns,"01000000" after 30ns;

Schematic Diagram:

Synthesis Report
Final Report:
Final Results
RTL Top Level Output File Name : encoder_without_priority.ngr
Top Level Output File Name : encoder_without_priority
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 12
Cell Usage :
# BELS : 15
# LUT3 :6
# LUT4 :9
# IO Buffers : 12
# IBUF :9
# OBUFT :3
Device utilization summary:
Selected Device : 3s250eft256-5

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Number of Slices: 9 out of 2448 0%

Number of 4 input LUTs: 15 out of 4896 0%
Number of IOs: 12
Number of bonded IOBs: 12 out of 172 6%
TIMING REPORT:
Delay: 9.315ns (Levels of Logic = 6)
Source: I<0> (PAD)
Destination: Y<2> (PAD)
Data Path: I<0> to Y<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 I_0_IBUF (I_0_IBUF)
LUT3:I0->O 2 0.612 0.532 Y_mux0000<0>41 (Y_mux0000<0>_bdd4)
LUT3:I0->O 2 0.612 0.449 Y_not0001_inv21 (Y_not0001_inv_bdd3)
LUT4:I1->O 1 0.612 0.509 Y_not0001_inv59 (Y_not0001_inv_map17)
LUT4:I0->O 3 0.612 0.451 Y_not0001_inv93 (Y_not0001_inv)
OBUFT:T->O 3.169 Y_2_OBUFT (Y<2>)
----------------------------------------
Total 9.315ns

Result: 8-To-3 Encoder without Priority is designed using VHDL and simulated the same
using Xilinx ISE Simulator
(B) Design of 8-to-3 encoder (with priority)

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Encoder_with_priority is
Port ( En : in STD_LOGIC;
I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC_VECTOR (2 downto 0));
end Encoder_with_priority;
architecture Behavioral of Encoder_with_priority is
begin
process(En,I)
begin
if En='0' then Y<="XXX";
elsif I(7)='1' then Y<="111";
elsif I(6)='1' then Y<="110";
elsif I(5)='1' then Y<="101";

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elsif I(4)='1' then Y<="100";

elsif I(3)='1' then Y<="011";
elsif I(2)='1' then Y<="010";
elsif I(1)='1' then Y<="001";
elseif I(0)=’1’ thenY<="000";
else Y<=”ZZZ”;
end if;
end process;
end Behavioral

Simulation Results:

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_encoder_with_priority_vhd IS
END tb_encoder_with_priority_vhd;
ARCHITECTURE behavior OF tb_encoder_with_priority_vhd IS
COMPONENT encoder_with_priority
PORT(
En : IN std_logic;
I : IN std_logic_vector(7 downto 0);

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Y : OUT std_logic_vector(2 downto 0)

);
END COMPONENT;
SIGNAL En : std_logic := '0';
SIGNAL I : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL Y : std_logic_vector(2 downto 0);
BEGIN
uut: encoder_with_priority PORT MAP(
En => En,
I => I,
Y => Y
);
En<='1' after 10ns;
I<="00000010" after 10ns,"00001000" after 20ns,"01000000" after 30ns;
Schematic Diagram:

Synthesis Report
Final Report:
Final Results
RTL Top Level Output File Name : Encoder_with_priority.ngr
Top Level Output File Name : Encoder_with_priority
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 12
Cell Usage :
# BELS :8
# LUT3 :1
# LUT4 :5
# MUXF5 :2
# IO Buffers : 11
# IBUF :8
# OBUF :3

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Device utilization summary:

Selected Device : 3s250eft256-5
Number of Slices: 3 out of 2448 0%
Number of 4 input LUTs: 6 out of 4896 0%
Number of IOs: 12
Number of bonded IOBs: 11 out of 172 6%
TIMING REPORT:
Delay: 6.846ns (Levels of Logic = 4)
Source: I<5> (PAD)
Destination: Y<1> (PAD)

Data Path: I<5> to Y<1>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- - -----------------------------------
IBUF:I->O 3 1.106 0.603 I_5_IBUF (I_5_IBUF)
LUT4:I0->O 1 0.612 0.387 Y<1>_SW0 (N8)
LUT4:I2->O 1 0.612 0.357 Y<1> (Y_1_OBUF)
OBUF:I->O 3.169 Y_1_OBUF (Y<1>)
------------------------------------------------------------------------------
Total 6.846ns

4.3.3 VERILOG simulation

(A)Design of 8-to-3 encoder (without priority)

module encoder(code,data);
output [2:0]code;
input [7:0]data;
reg [2:0]code;
always @ (data)
begin
if(data==8’b00000001) code =0; else
if(data==8’b00000010) code =1; else
if(data==8’b00000100) code =2; else
if(data==8’b00001000) code =3; else
if(data==8’b00010000) code =4; else
if(data==8’b00100000) code =5; else
if(data==8’b01000000) code =6; else
if(data==8’b10000000) code =7; else code=3’bx;
end
/* Alternate description is given below
always @(data)
case(data)

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8’b00000001 : code=0;
8’b00000010 : code=1;
8’b00000100 : code=2;
8’b00001000 : code=3;
8’b00010000 : code=4;
8’b00100000 : code=5;
8’b01000000 : code=6;
8’b10000000 : code=7;
endcase */
endmodule
// test bench for 8-3 encoder without priority
module encodertest;
reg [7:0]data;
wire [2:0] code;
encoder gg(core,data);//instantiation of encoder
always
begin
data = 8’b00000000;
#3 data = 8’b00000001;
#3 data = 8’b00000010;
#3 data = 8’b00000100;
#3 data = 8’b00001000;
#3 data = 8’b00010000;
#3 data = 8’b00100000;
#3 data = 8’b01000000;
#3 data = 8’b10000000;
end
$monitor($time, “data = $b, code = %b”,data,code);
initial #100 $stop
endmodule
(B)Design of 8-to-3 encoder (with priority)

module priorityencoder(code,valid_data,data);
output [2:0] code;
output valid_data;

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input [7:0] data;

input [2:0] code;
assign valid_data = |data; //reduction ‘or’ operation
always @ (data)
begin
if (data[7]) code = 7; else
if (data[6]) code = 6; else
if (data[5]) code = 5; else
if (data[4]) code = 4; else
if (data[3]) code = 3; else
if (data[2]) code = 2; else
if (data[1]) code = 1; else
if (data[0]) code = 0; else
code=3’bx;
end
/* //Alternate description is given below
always @(data)
casex (data)
8’b1xxxxxxx : code=7;
8’b01xxxxxx : code=6;
8’b001xxxxx : code=5;
8’b0001xxxx : code=4;
8’b00001xxx : code=3;
8’b000001xx : code=2;
8’b0000001x : code=1;
8’b00000001 : code=0;
default : code=3’bx;
endcase
*/
endmodule
// test bench for 8-3 encoder with priority
module priorityencodertest;
reg [7:0]data;
wire [2:0] code;
priorityencoder gg(code,valid_data,data); //instantiation of encoder

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always
begin
data = 8’bxxxxxxxx;
#3 data = 8’b00000001;
#3 data = 8’b0000001x;
#3 data = 8’b000001xx;
#3 data = 8’b00001xxx;
#3 data = 8’b0001xxxx;
#3 data = 8’b001xxxxx;
#3 data = 8’b01xxxxxx;
#3 data = 8’b1xxxxxxx;
end
$monitor($time, “valid_data = %b, data = $b, code = %b”,valid_data,data,code);
initial #100 $stop
endmodule

4.3.4 Implementaion
The decoder can be implemented on Spartan-3 FPGA kit as described
in section-3.

Result: 8-To-3 Encoder with Priority is designed using VHDL, VERILOG and simulated the
same using Xilinx ISE Simulator

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Experiment No:4

4.4 Design of 8-to-1 multiplexer

4.4.1 Aim: To Design 8-To-1 Multiplexer using VHDL and simulate the same using
Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

4.4.2 VHDL Simulation

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Mux_8_1 is
Port ( En_L : in STD_LOGIC;
S : in STD_LOGIC_VECTOR (2 downto 0);
I : in STD_LOGIC_VECTOR (7 downto 0);
Y : out STD_LOGIC);
end Mux_8_1;
architecture Behavioral of Mux_8_1 is
begin
process(S,I,En_L)
begin
if En_L='1' then Y<='0';
else
case S is
when "000"=>Y<=I(0);
when "001"=>Y<=I(1);
when "010"=>Y<=I(2);
when "011"=>Y<=I(3);
when "100"=>Y<=I(4);
when "101"=>Y<=I(5);
when "110"=>Y<=I(6);
when "111"=>Y<=I(7);

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when others=>Y<='Z';
end case;
end if;
end process;
end Behavioral;
Schematic Diagram:

Synthesis Report
Final Report:
Final Results
RTL Top Level Output File Name : Mux_8_1.ngr
Top Level Output File Name : Mux_8_1
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 13
Cell Usage :
# BELS :8
# LUT3 :1
# LUT4 :5
# MUXF5 :2
# IO Buffers : 13
# IBUF : 12
# OBUF :1
=========================================================================
Device utilization summary:
Selected Device : 3s250eft256-5

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Number of Slices: 3 out of 2448 0%

Number of 4 input LUTs: 6 out of 4896 0%
Number of IOs: 13
Number of bonded IOBs: 13 out of 172 7%
TIMING REPORT:

Delay: 7.512ns (Levels of Logic = 6)

Source: S<0> (PAD)
Destination: Y (PAD)
Data Path: S<0> to Y
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 4 1.106 0.651 S_0_IBUF (S_0_IBUF)
LUT4:I0->O 1 0.612 0.000 Y97_F (N85)
MUXF5:I0->O 2 0.278 0.449 Y97 (Y_map27)
LUT3:I1->O 1 0.612 0.000 Y1241 (N89)
MUXF5:I1->O 1 0.278 0.357 Y124_f5 (Y_OBUF)
OBUF:I->O 3.169 Y_OBUF (Y)
----------------------------------------
Total 7.512ns
VHDL Test bench:
LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_Mux_8_1_vhd IS
END tb_Mux_8_1_vhd;
ARCHITECTURE behavior OF tb_Mux_8_1_vhd IS
COMPONENT Mux_8_1
PORT(
En_L : IN std_logic;
S : IN std_logic_vector(2 downto 0);
I : IN std_logic_vector(7 downto 0);
Y : OUT std_logic
);
END COMPONENT;
SIGNAL En_L : std_logic := '0';
SIGNAL S : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL I : std_logic_vector(7 downto 0) := (others=>'0');
SIGNAL Y : std_logic;

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BEGIN
uut: Mux_8_1 PORT MAP(
En_L => En_L,
S => S,
I => I,
Y => Y
);
En_L<='1' after 80ns;
I<="10101010" after 10ns;
S<="001" after 10ns,"010" after 20ns,"011" after 30ns,"100" after 40ns,"101" after
50ns,"110" after 60ns,"111" after 70ns;
END;

Simulation Results:

Result: 8-To-1 Multiplexer is designed using VHDL and simulated the same using Xilinx ISE
Simulator.
8x1 MULTIPLEXER

AIM: Write a VHDL code for IC74151—8x1 multiplexer.

TITLE: IC74151—8x1 multiplexer.

BLOCK DIAGRAM:

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TRUTH TABLE:

S.No en_l Data select lines Output

A B C Y
1 0 0 0 0 I(0)

2 0 0 0 1 I(1)

3 0 0 1 0 I(2)

4 0 0 1 1 I(3)

5 0 1 0 0 I(4)

6 0 1 0 1 I(5)

7 0 1 1 0 I(6)

8 0 1 1 1 I(7)

9 1 X X X 0

VHDL CODE:
library IEEE;
use IEEE.std_logic_1164.all;

entity mux151 is
port (
I :in STD_LOGIC_VECTOR (7 downto 0); --8 i/p lines
S :in STD_LOGIC_VECTOR (2 downto 0); --3 data select lines
en_l:in STD_LOGIC; --active low enable i/p
y :out STD_LOGIC --output line
); end
mux151;

architecture mux151 of mux151 is

begin
process (I,s,en_l)
begin
if en_l='0' then case
s is
when "000" => y <= I(0);
when "001" => y <= I(1);
when "010" => y <= I(2);
when "011" => y <= I(3);
when "100" => y <= I(4);

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when "101" => y <= I(5);

when "110" => y <= I(6);
when "111" => y <= I(7);
when others=>null;
end case;
else y <= '0'; --y=0 when en_l=1
end if;
end process;
end mux151;
WAVEFORMS:

16X1 MULTIPLEXER

AIM: Write a VHDL code for IC74150—16x1 multiplexer.

TITLE: IC74150—16x1 multiplexer.

BLOCK DIAGRAM:

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TRUTH TABLE:

S.No. Data select lines output

strobe A B C D Y
1 0 0 0 0 0 d’(0)
2 0 0 0 0 1 d’(1)
3 0 0 0 1 0 d’(2)
4 0 0 0 1 1 d’(3)
5 0 0 1 0 0 d’(4)
6 0 0 1 0 1 d’(5)
7 0 0 1 1 0 d’(6)
8 0 0 1 1 1 d’(7)
9 0 1 0 0 0 d’(8)
10 0 1 0 0 1 d’(9)
11 0 1 0 1 0 d’(10)
12 0 1 0 1 1 d’(11)
13 0 1 1 0 0 d’(12)
14 0 1 1 0 1 d’(13)
15 0 1 1 1 0 d’(14)
16 0 1 1 1 1 d’(15)
17 1 X X X X 1
VHDL CODE:
library IEEE;
use IEEE.std_logic_1164.all;

entity mux16 is
port(
strobe : in STD_LOGIC; --active low enable i/p
D : in STD_LOGIC_VECTOR(15 downto 0); --16 i/p lines
Sel : in STD_LOGIC_VECTOR(3 downto 0); --4 data select lines Y :
out STD_LOGIC --output line
); end
mux16;

architecture mux16 of mux16 is

signal Y_L:std_logic;
begin
with Sel select
Y_L <= D(0) when "0000", D(1)
when "0001", D(2) when
"0010", D(3) when "0011",
D(4) when "0100", D(5)
when "0101", D(6) when
"0110", D(7) when "0111",
D(8) when "1000", D(9)
when "1001", D(10) when
"1010", D(11) when "1011",

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D(12) when "1100", D(13)

when "1101", D(14) when
"1110", D(15) when "1111",
unaffected when others;
Y<= not Y_L when (strobe='0') else '1';
end mux16;
WAVEFORMS:

4.3 VERILOG simulation

Verilog code for 32 bit, 8-1 multiplexer

module mux_8-1-32bit(out,in1,in2,in3,in4,in4,in5,in6,in7,in8,select,enable);
output [31:0]out;
input [31:0] in1,in2,in3,in4,in5,in6,in7,in8;
input [2:0] select;
input enable;
reg [31:0] out1;

assign out=enable?out1:32’bz;
always @(in1 or in2 or in3 or in4 or in5 or in6 or in7 or in8 or select)
if(select == 0) out1 = in1; else
if(select == 1) out1 = in1; else
if(select == 2) out1 = in1; else
if(select == 3) out1 = in1; else
if(select == 4) out1 = in1; else
if(select == 5) out1 = in1; else
if(select == 6) out1 = in1; else
if(select == 7) out1 = in1; else
out1=32’bx;
endmodule

Another way of writing the code with nested continuous assignment

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module mux_8-1-32bit(out,in1,in2,in3,in4,in4,in5,in6,in7,in8,select,enable);
output [31:0]out;
input [31:0] in1,in2,in3,in4,in5,in6,in7,in8;
input [2:0] select;
input enable;
reg [31:0] out1;

assign out=enable?out1:32’bz;
assign out1 = (select==0)?in1:
(select==1)?in2:
(select==2)?in3:
(select==3)?in4:
(select==4)?in5:
(select==5)?in6:
(select==6)?in7:

(select==7)?in8:32’bx;
endmodule

test bench for multiplexer

module muxtest;
reg [31:0] in1,in2,in3,in4,in5,in6,in7,in8;
reg [2:0] select;
wire [31:0] out;
mux_8-1-32bit gg(out,in1,in2,in3,in4,in4,in5,in6,in7,in8,select,enable);
initial eneble=1’b1;
always
begin
select = 3’b0;
#3 select = 3’b001
#3 select = 3’b010
#3 select = 3’b011
#3 select = 3’b100
#3 select = 3’b101
#3 select = 3’b110
#3 select = 3’b111
End
$monitor ($time, “select = %b, out\%b”,select,out);
Initial #100 $stop
endmodule

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Experiment No:5

5.1 Design of 4 bit Binary to Gray code converter

5.1.1 Aim: To Design Binary-To-Gray Code Converter using VHDL and simulate the
same using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

5.1.2 VHDL simulation

VHDL Code:
library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Binary_to_gray is

Port ( B : in STD_LOGIC_VECTOR (3 downto 0);

G : out STD_LOGIC_VECTOR (3 downto 0));

end Binary_to_gray;

architecture Behavioral of Binary_to_gray is

begin

G(3)<=B(3);

G(2)<=B(3) XOR B(2);

G(1)<=B(2) XOR B(1);

G(0)<=B(1) XOR B(0);

end Behavioral;

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Simulation Results:

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_Binary_to_gray_vhd IS
END tb_Binary_to_gray_vhd;
ARCHITECTURE behavior OF tb_Binary_to_gray_vhd IS
COMPONENT Binary_to_gray
PORT(
B : IN std_logic_vector(3 downto 0);
G : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL G : std_logic_vector(3 downto 0);

BEGIN
uut: Binary_to_gray PORT MAP(
B => B,
G => G
);
B<="1010" after 10ns,"1000" after 20ns;
END;

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Schematic Diagram:

Synthesis Report
HDL Synthesis Report
Macro Statistics
# Xors :3
1-bit xor2 :3
Advanced HDL Synthesis Report
Macro Statistics
# Xors :3
1-bit xor2 :3
Final Report:
RTL Top Level Output File Name : Binary_to_gray.ngr
Top Level Output File Name : Binary_to_gray
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :8
Cell Usage :
# BELS :3
# LUT2 :3
# IO Buffers :8
# IBUF :4
# OBUF :4
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 2 out of 2448 0%
Number of 4 input LUTs: 3 out of 4896 0%
Number of IOs: 8
Number of bonded IOBs: 8 out of 172 4%
TIMING REPORT:
Data Path: B<2> to G<2>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 B_2_IBUF (B_2_IBUF)
LUT2:I0->O 1 0.612 0.357 Mxor_G<2>_Result1 (G_2_OBUF)
OBUF:I->O 3.169 G_2_OBUF (G<2>)
----------------------------------------

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Total 5.776ns

Result: Binary-To-Gray Code Converter is designed using VHDL and simulated the same
using Xilinx ISE Simulator
module binary2gray();
reg clk;
reg rstn;
reg [5:0] counter_binary, counter_binary_reg, counter_gray, co
unter_gray_reg;
integer count, file_wr;

/* Initial block to generate clock and reset */

initial begin
clk = 0; rstn = 0; #100 rstn = 1;
forever begin
#10 clk = !clk;
end end

/* Synchronous Logic for registering the data and incrementing

the counter for binary data */
always @ (posedge clk or negedge rstn)
begin
if (!rstn) begin
counter_binary_reg <= 'b0;
counter_gray_reg <= 'b0; end
else begin
counter_binary_reg <= counter_binary + 1;
counter_gray_reg <= counter_gray;
$display("binary number= 6'b%b : gray en-coded binary
number = 6'b%b", counter_binary_reg, counter_gray_reg);
end end

/* Logic is to get Gray code from Binary code */

function[5:0] binary2gray ;
input[5:0] value;
integer i;
begin
binary2gray[5] = value[5];

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for (i=5; i>0; i = i - 1)

binary2gray[i-1] = value[i] ^ value[i - 1];
end
endfunction

/* Get gray encoded output */

always @(*)
begin
counter_gray = counter_gray_reg;
counter_binary = counter_binary_reg;
counter_gray = binary2gray(counter_binary_reg); end
endmodule

// Another simple code for binary to gray code conversion

module bcd2gray(o,i);
output [3:0]o;
input [3:0]i;
reg [3:0]o;
always @(i)
begin
o[3]=i[3];
o[2]=i[3]^i[2];
o[1]=i[2]^i[1];
o[0]=i[1]^i[0];
end
endmodule

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Experiment No:6

4.6 4 – bit Comparator

4.6.1 Aim: To Design 4-Bit Comparator using VHDL and simulate the same
using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

4.6.2 VHDL Simulation

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
AEQB : out STD_LOGIC;
AGTB : out STD_LOGIC;
ALTB : out STD_LOGIC);
end comparator;
architecture Behavioral of comparator is
begin
process(A,B)
begin
if A=B then AEQB<='1';AGTB<='0';ALTB<='0';
elsif A>B then AEQB<='0';AGTB<='1';ALTB<='0';
else AEQB<='0';AGTB<='0';ALTB<='1';
end if;
end process;
end Behavioral;

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Simulation Results:

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_comparator_vhd IS
END tb_comparator_vhd;
ARCHITECTURE behavior OF tb_comparator_vhd IS
COMPONENT comparator
PORT(
A : IN std_logic_vector(3 downto 0);
B : IN std_logic_vector(3 downto 0);
AEQB : OUT std_logic;
AGTB : OUT std_logic;
ALTB : OUT std_logic
);
END COMPONENT;
SIGNAL A : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL B : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL AEQB : std_logic;
SIGNAL AGTB : std_logic;
SIGNAL ALTB : std_logic;

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BEGIN
uut: comparator PORT MAP(
A => A,
B => B,
AEQB => AEQB,
AGTB => AGTB,
ALTB => ALTB);
A<="1010" after 10ns,"1000" after 20ns;
B<="1000" after 10ns,"1010" after 20ns;
END;
Schematic Diagram:

Synthesis Report
HDL Synthesis Report
Macro Statistics
# Comparators :2
4-bit comparator equal :1
4-bit comparator greater :1
Final Report:
RTL Top Level Output File Name : comparator.ngr
Top Level Output File Name : comparator
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs : 11
Cell Usage :
# BELS : 12
# LUT4 :9
# MUXF5 :3
# IO Buffers : 11
# IBUF :8
# OBUF :3
Device utilization summary:
Selected Device: 3s250eft256-5
Number of Slices: 5 out of 2448 0%
Number of 4 input LUTs: 9 out of 4896 0%

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Number of IOs: 11
Number of bonded IOBs: 11 out of 172 6%

TIMING REPORT:
Data Path: B<1> to AGTB
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 3 1.106 0.603 B_1_IBUF (B_1_IBUF)
LUT4:I0->O 2 0.612 0.532 AGTB31 (AGTB_bdd2)
LUT4:I0->O 1 0.612 0.000 AGTB111 (N14)
MUXF5:I1->O 1 0.278 0.357 AGTB11_f5 (AGTB_OBUF)
OBUF:I->O 3.169 AGTB_OBUF (AGTB)
----------------------------------------
Total 7.269ns

Result: 4-Bit Comparator Converter is designed using VHDL and simulated the same using
Xilinx ISE

IC 74x85 – 4-BIT COMPARATOR

AIM: Write a VHDL code for IC 74x85 –4-bit comparator .

BLOCK DIAGRAM:

TRUTH TABLE:

S.No. Cascade Present input AGTBOUT AEQBOUT ALTBOUT

inputs condition
A>B A=B A<B
1 AGTBIN=1 X X X 1 0 0
1 0 0 1 0 0
2 AEQBIN=1 0 1 0 0 1 0
0 0 1 0 0 1
5 ALTBIN=1 X X X 0 0 1

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VHDL CODE:
library IEEE;
use IEEE.std_logic_1164.all;
entity comp is
port (
altbin: in STD_LOGIC;
aeqbin: in STD_LOGIC;
agtbin: in STD_LOGIC;
a: in STD_LOGIC_VECTOR (3 downto 0);
b: in STD_LOGIC_VECTOR (3 downto 0);
agtbout: out STD_LOGIC;
aeqbout: out STD_LOGIC;
altbout: out STD_LOGIC
);
end comp;
architecture comp of comp is begin
process(a,b,agtbin,aeqbin,altbin)
begin
agtbout<='0'; --initializes the outputs to ‘0’
aeqbout<='0';
altbout<='0'; if
aeqbin='1' then
if a=b then aeqbout<='1'; elsif
a>b then agtbout<='1'; elsif
(a<b) then altbout<='1'; end if;
elsif (altbin/=agtbin)then
agtbout<=agtbin;
altbout<=altbin;
end if;
end process ; end
Comp;

WAVEFORMS:

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4.6.4 VERILOG simulation

/*Module for 4-bit comparator.

Module for 2-bit comparator is prepared first.
Using two 2-bit comparators, 4-bit comparator is built */
//module for 2-bit comparator
module comparator_2bit(A_gt_B,A_lt_B,A_eq_B,A0,A1,B0,B1);
output A_gt_B,A_lt_B,A_eq_B;
input A0,A1,B0,B1;
nor (A_gt_B,A_lt_B,A_eq_B);
or (A_lt_B,w1,w2,w3);
and (A_eq_B,w4,w5);
and (w1,w6,B1);
and(w2,w6,w7,B0);
and(w3,w7,B0,B1);
not(w6,A1);
not(w7,B0);
xnor(w4,A1,B1);
xnor(w5,A0,B0);
endmodule

//module for 4 bit comparator using 2-bit comparators

module comparator_4bit(A_gt_B,A_lt_B,A_eq_B,A3,A2,A1,A0,B3,B2,B1,B0);
output A_gt_B,A_lt_B,A_eq_B;
input A3,A2,A1,A0,B3,B2,B1,B0;
wire w1,w0;
comparator_2bit m1(A_gt_B_M1,A_lt_B_M1,A_eq_B_M1,A3,A2,B3,B2);
comparator_2bit m0(A_gt_B_M0,A_lt_B_M0,A_eq_B_M0,A1,A0,B1,B0);
or (A_gt_B,A_gt_B_M1,w1);
and (w1,A_eq_B_M1,A_gt_B_M0);
and (A_eq_B,A_eq_B_M1,A_eq_B_M0)
or (A_lt_B,A_lt_B_M1,A_eq_B_M0);
and (w0,A_eq_B_M1,A_lt_B_M0);
endmodule

_____
//test bench for 4-bit comparator
module comparator_4bittest
reg [3:0] a,b;
wire a_gt_b , a_lt_b, a_eq_b;
comparator_4bit gg(a_gt_b,a_lt_b,a_eq_b,a[3],a[2],a[1],a[0],b[3],b[2],b[1],b[0]);
initial

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begin
a_gt_b=1’b0;
a_lt_b=1’b0;
a_eq_b=1’b0;
end
always
begin
a=4’b0000;b=4’b0000;
#3 a=4’b0100;
#3 b=4’b0101;
#3 b=4’b0011;
#3 a=4’b1010;
#3 b=4’b1010;
#3 a=4’b1001;
End
$monitor($time,
“a=%b,b=%b,a_gt_b=%b,a_lt_b=%b,a_eq_b=%b”,a,b,a_gt_b,a_lt_b,a_eq_b);
Initial #100 $stop;
endmodule

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HDL simulation lab manual prepared by, Nakka. Ravi kumar, Asst. Prof, Lakshman Asst.prof and K.Venkateswarlu, Asst. Prof

Experiment No:7
4.7 Full Adder Using three design Styles

4.7.1 Aim: To Design Full Adder in three design Styles using VHDL and
VERILOG and simulate the same using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

4.7.2 VHDL simulation

VHDL Code (data flow style):

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Full_Adder_Dataflow is

Port ( A : in STD_LOGIC;

B : in STD_LOGIC;

Cin : in STD_LOGIC;

Sum : out STD_LOGIC;

Cout : out STD_LOGIC);

end Full_Adder_Dataflow;

architecture Dataflow of Full_Adder_Dataflow is

signal X: STD_LOGIC;

begin

X<= (A xor B) and Cin;

Sum<= A xor B xor Cin;

Cout<=X or (A and B);

end Dataflow;

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Schematic Diagram:

Synthesis Report
HDL Synthesis Report:
Macro Statistics
# Xors :2
1-bit xor2 :2
Final Report:
Final Results
RTL Top Level Output File Name : Full_Adder_Dataflow.ngr
Top Level Output File Name : Full_Adder_Dataflow
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 1 out of 2448 0%
Number of 4 input LUTs: 2 out of 4896 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 172 2%
TIMING

Delay: 5.776ns (Levels of Logic = 3)

Source: B (PAD)
Destination: Cout (PAD)

Data Path: B to Cout

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Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 B_IBUF (B_IBUF)
LUT3:I0->O 1 0.612 0.357 Cout1 (Cout_OBUF)
OBUF:I->O 3.169 Cout_OBUF (Cout)
----------------------------------------
Total 5.776ns
VHDL Test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_Full_Adder_Dataflow_vhd IS
END tb_Full_Adder_Dataflow_vhd;
ARCHITECTURE behavior OF tb_Full_Adder_Dataflow_vhd IS
COMPONENT Full_Adder_Dataflow
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Sum : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL Cin : std_logic := '0';
SIGNAL Sum : std_logic;
SIGNAL Cout : std_logic;
BEGIN
uut: Full_Adder_Dataflow PORT MAP(
A => A,
B => B,
Cin => Cin,

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Sum => Sum,

Cout => Cout
);
A<='1' after 40ns;
B<='1' after 20ns,'0' after 40ns,'1'after 60ns;
Cin<='1' after 10ns,'0' after 20ns,'1' after 30ns,'0' after 40ns,'1' after 50ns, '0' after 60ns,'1'
after 70ns;

Simulation Results:

Result: Full Adder Using Dataflow Style is designed using VHDL and simulated the same using
Xilinx ISE Simulator

(B)Full Adder Using Behavioral Style

Aim: To Design Full Adder Using Behavioral Style using VHDL and simulate the same using
Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Full_Adder_Behavioral is
Port ( A : in STD_LOGIC;

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B : in STD_LOGIC;
Cin : in STD_LOGIC;
Sum : out STD_LOGIC;
Cout : out STD_LOGIC);
end Full_Adder_Behavioral;
architecture Behavioral of Full_Adder_Behavioral is
signal P:Std_logic_vector(2 downto 0);
begin
P<=A&B&Cin;
process(A,B,p,Cin)
begin
case p is
when "000"=>Sum<='0';Cout<='0';
when "001"=>Sum<='1';Cout<='0';
when "010"=>Sum<='1';Cout<='0';
when "011"=>Sum<='0';Cout<='1';
when "100"=>Sum<='1';Cout<='0';
when "101"=>Sum<='0';Cout<='1';
when "110"=>Sum<='0';Cout<='1';
when "111"=>Sum<='1';Cout<='1';
when others=>Sum<='Z';Cout<='Z';
end case;
end process;
end Behavioral;

Schematic Diagram:

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Synthesis Report
HDL Synthesis Report
Macro Statistics
# ROMs :1
8x2-bit ROM :1
Final Report:
Final Results
RTL Top Level Output File Name : Full_Adder_Behavioral.ngr
Top Level Output File Name : Full_Adder_Behavioral
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO

Design Statistics
# IOs :5
Cell Usage :
# BELS :2
# LUT3 :2
# IO Buffers :5
# IBUF :3
# OBUF :2
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 1 out of 2448 0%
Number of 4 input LUTs: 2 out of 4896 0%
Number of IOs: 5
Number of bonded IOBs: 5 out of 172 2%
TIMING REPORT:

Delay: 5.776ns (Levels of Logic = 3)

Source: B (PAD)
Destination: Cout (PAD)
Data Path: B to Cout
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 2 1.106 0.532 B_IBUF (B_IBUF)
LUT3:I0->O 1 0.612 0.357 Mrom_P_rom000011 (Mrom_P_rom0000)
OBUF:I->O 3.169 Cout_OBUF (Cout)

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----------------------------------------
Total 5.776ns

VHDL Test bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY tb_Full_Adder_Behavioral_vhd IS
END tb_Full_Adder_Behavioral_vhd;
ARCHITECTURE behavior OF tb_Full_Adder_Behavioral_vhd IS
COMPONENT Full_Adder_Behavioral
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
Sum : OUT std_logic;
Cout : OUT std_logic
);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL Cin : std_logic := '0';
SIGNAL Sum : std_logic;
SIGNAL Cout : std_logic;
BEGIN
uut: Full_Adder_Behavioral PORT MAP(
A => A,
B => B,
Cin => Cin,
Sum => Sum,
Cout => Cout
);
A<='1' after 40ns;
B<='1' after 20ns,'0' after 40ns,'1'after 60ns;

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Cin<='1' after 10ns,'0' after 20ns,'1' after 30ns,'0' after 40ns,'1' after 50ns, '0' after 60ns,'1'
after 70ns;

Simulation Results:

Result: Full Adder Using Behavioral Style is designed using VHDL and simulated the same
using Xilinx ISE Simulator

(C)Full Adder Using Structural Style

Aim: To Design Full Adder Using Structural Style using VHDL and simulate the same
using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

VHDL Code:

-------VHDL Code for Xor Gate----

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity or_gate is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end or_gate;
architecture Behavioral of or_gate is
begin
c<=a or b;
end Behavioral;
-------VHDL Code for and Gate----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity and_g is

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Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end and_g;
architecture Behavioral of and_g is
begin
c<=a and b;
end Behavioral;
-------VHDL Code for Or Gate----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity xor_g is
Port ( a : in STD_LOGIC;
b : in STD_LOGIC;
c : out STD_LOGIC);
end xor_g;
architecture Behavioral of xor_g is
begin
c<=a xor b;
end Behavioral;
-------VHDL Code for Full Adder----
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder_structural is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
SUM : out STD_LOGIC;
Cout : out STD_LOGIC);
end fulladder_structural;
architecture Behavioral of fulladder_structural is
component or_gate is
port(a,b:in std_logic;
c:out std_logic);
end component;
component and_g is
port(a,b:in std_logic;
c:out std_logic);
end component;
component xor_g is

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port(a,b:in std_logic;
c:out std_logic);
end component;
signal y1,y2,y3:std_logic;
begin
x1:xor_g port map(A,B,y1);
a1:and_g port map(A,B,y2);
x2:xor_g port map(y1,Cin,sum);
a2:and_g port map(y1,Cin,y3);
r1:or_gate port map(y2,y3,Cout);
end Behavioral;

Simulation Results:

VHDL Test bench:

ENTITY tb_fulladder_structural_vhd IS
END tb_fulladder_structural_vhd;
ARCHITECTURE behavior OF tb_fulladder_structural_vhd IS
COMPONENT fulladder_structural
PORT(
A : IN std_logic;
B : IN std_logic;
Cin : IN std_logic;
SUM : OUT std_logic;
Cout : OUT std_logic

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);
END COMPONENT;
SIGNAL A : std_logic := '0';
SIGNAL B : std_logic := '0';
SIGNAL Cin : std_logic := '0';
SIGNAL SUM : std_logic;
SIGNAL Cout : std_logic;

BEGIN
uut: fulladder_structural PORT MAP(
A => A,
B => B,
Cin => Cin,
SUM => SUM,
Cout => Cout
);

A<='1' after 40ns;

B<='1' after 20ns,'0' after 40ns,'1'after 60ns;
Cin<='1' after 10ns,'0' after 20ns,'1' after 30ns,'0' after 40ns,'1' after 50ns, '0' after 60ns,'1' after 70ns;
END;

Schematic Diagram:

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Design of full adder circuit in 3 different design styles in VERILOG

1. Gate level modeling

//module for half adder

module halfadder(sum,carry,a,b);
input a,b;
output sum,carry;
xor (sum,a,b);
and (carry,a,b);
endmodule

//module for full adder with half adder circuits

module fa(sum,cout,a,b,cin);
input a,b,cin;
output sum, cout;
wire s,c1,c2;
halfadder ha1(s,c1,a,b), ha2(sum,c2,s,cin);
or(cout,c1,c2);
endmodule

2. Dataflow level modeling

//module for half adder

module halfadder(sum,carry,a,b);
input a,b;
output sum,carry;
wire sum,carry;
assign sum = a^b; carry=a&&b;
endmodule

//module for full adder with half adder circuits

module fa(sum,cout,a,b,cin);
input a,b,cin;
output sum, cout;
wire s,c1,c2;
halfadder ha1(s,c1,a,b), ha2(sum,c2,s,cin);
assign cout=c1||c2;
endmodule

3. Behavior level modeling

//module for half adder

module halfadder(sum,carry,a,b);
input a,b;
output sum,carry;
always @(a or b)
begin
sum = a^b;

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carry = a&&b;
end
endmodule

//module for full adder circuit

module fa(sum,cout,a,b,cin);
input a,b,cin;
output sum, cout;
reg sum,cout;
always @(a or b or cin)
begin
sum = (a^b)^cin;
cout = (a&&b)||((a^b)&&cin);
end
endmodule

TEST BENCH FOR FULL ADDER CIRCUIT can be used for all design styles

module fatest();
reg a,b,cin;
fa ff(sum,cout,a,b,cin);
initial

begin
a=0; b=0; cin=0;
end
always
begin
#2 a=1;b=1;cin=0 #2 a=1;b=0;cin=1;
#2 a=1;b=1;cin=1 #2 a=1;b=0;cin=0;
#2 a=0;b=0;cin=0 #2 a=0;b=1;cin=0;
#2 a=0;b=0;cin=1 #2 a=0;b=1;cin=1;
#2 a=1;b=0;cin=0 #2 a=1;b=1;cin=0;
#2 a=0;b=1;cin=0 #2 a=1;b=1;cin=1;
end
initial
%monitor($time,”a=%b,b=%b,cin=%b,outsum=%b,outcar=%b”,a,b,cin,sum,cout);

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initial #30 $stop;

endmodule

Result: Full Adder Using Structural Style is designed using VHDL and simulated the same
using Xilinx ISE Simulator

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Experiment No:8

4.8 Design of flipflops: SR, D, Jk, T

4.8.1 Aim: To Design D Flip Flop with Asynchronous “Reset” using VHDL and
simulate the same using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

4.8.2 VHDL Simulation

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF_Asyn is
Port ( clk : in STD_LOGIC;
Rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF_Asyn;
architecture Behavioral of DFF_Asyn is
begin
process(clk,D,Rst)
begin
if Rst='1' then Q<='0';
elsif clk'event and clk='1' then
Q<=D;
end if;
end process;
end Behavioral;

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Schematic Diagram:

Synthesis Report
HDL Synthesis Report

Macro Statistics
# Registers :1
1-bit register :1
Advanced HDL Synthesis Report
Macro Statistics
# Registers :1
Flip-Flops :1
Final Register Report
Macro Statistics
# Registers :1
Flip-Flops :1
Final Report:
Final Results
RTL Top Level Output File Name : DFF_Asyn.ngr
Top Level Output File Name : DFF_Asyn
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :4
Cell Usage :
# FlipFlops/Latches :1
# FDC :1
# Clock Buffers :1
# BUFGP :1

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# IO Buffers :3
# IBUF :2
# OBUF :1
=========================================================================
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 0 out of 2448 0%
Number of Slice Flip Flops: 1 out of 4896 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 172 2%
IOB Flip Flops: 1
Number of GCLKs: 1 out of 24 4%
TIMING REPORT:
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |1 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Rst | IBUF |1 |
-----------------------------------+------------------------+-------+
Timing Summary:
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 1.731ns
Maximum output required time after clock: 4.040ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'

Total number of paths / destination ports: 1 / 1

-------------------------------------------------------------------------
Offset: 1.731ns (Levels of Logic = 1)
Source: D (PAD)
Destination: Q (FF)
Destination Clock: clk rising
Data Path: D to Q
Gate Net

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Cell:in->out fanout Delay Delay Logical Name (Net Name)

---------------------------------------- ------------
IBUF:I->O 1 1.106 0.357 D_IBUF (D_IBUF)
FDC:D 0.268 Q
----------------------------------------
Total 1.731ns (1.374ns logic, 0.357ns route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.040ns (Levels of Logic = 1)
Source: Q (FF)
Destination: Q (PAD)
Source Clock: clk rising
Data Path: Q to Q:
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 1 0.514 0.357 Q (Q_OBUF)
OBUF:I->O 3.169 Q_OBUF (Q)
----------------------------------------
Total 4.040ns
Simulation Results:

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_DFF_Asyn_vhd IS

END tb_DFF_Asyn_vhd;

ARCHITECTURE behavior OF tb_DFF_Asyn_vhd IS

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COMPONENT DFF_Asyn

PORT(clk : IN std_logic;

Rst : IN std_logic;

D : IN std_logic;

Q : OUT std_logic

);

END COMPONENT;

SIGNAL clk : std_logic := '0';

SIGNAL Rst : std_logic := '0';

SIGNAL D : std_logic := '0';

SIGNAL Q : std_logic;

BEGIN

uut: DFF_Asyn PORT MAP(

clk => clk,

Rst => Rst,

D => D,

Q => Q );

Rst<='1' after 40ns;

clk<= not clk after 10ns;

D<='1' after 20ns;END;

Result: D Flip Flop with Asynchronous “Reset” is designed using VHDL and simulated the
same using Xilinx ISE Simulator

(B) D Flip Flop with Synchronous “Reset”

Aim: To Design D Flip Flop with Synchronous “Reset” using VHDL and simulate the same
using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

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use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DFF_Syn is
Port ( clk : in STD_LOGIC;
Rst : in STD_LOGIC;
D : in STD_LOGIC;
Q : out STD_LOGIC);
end DFF_Syn;
architecture Behavioral of DFF_Syn is
begin
process
begin
wait until clk’event and clk=’1’;
if Rst='1' then Q<='0';
elsif clk'event and clk='1' then
Q<=D;
end if;
end process;
end Behavioral;

Schematic Diagram:

Simulation Results:

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VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_DFF_Syn_vhd IS

END tb_DFF_Syn_vhd;

ARCHITECTURE behavior OF tb_DFF_Syn_vhd IS

COMPONENT DFF_Syn

PORT(clk : IN std_logic;

Rst : IN std_logic;

D : IN std_logic;

Q : OUT std_logic

);

END COMPONENT;

SIGNAL clk : std_logic := '0';

SIGNAL Rst : std_logic := '0';

SIGNAL D : std_logic := '0';

SIGNAL Q : std_logic;

BEGIN

uut: DFF_Syn PORT MAP(

clk => clk,

Rst => Rst,

D => D,

Q => Q );

Rst<='1' after 40ns;

clk<= not clk after 10ns;

D<='1' after 20ns;

END;

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(C) T Flip Flop with Asynchronous “Reset”

Aim: To Design T Flip Flop with Asynchronous “Reset” using VHDL and simulate the same
using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TFF_Asyn is
Port ( Rst : in STD_LOGIC;
clk : in STD_LOGIC;
T : in STD_LOGIC;
Q : out STD_LOGIC);
end TFF_Asyn;
architecture Behavioral of TFF_Asyn is
begin
process(Rst,Clk,T)
begin
if Rst='1' then Q<='0';
elsif clk'event and Clk='1' then Q<=not T;
end if;
end process;
end Behavioral;

Schematic Diagram:

Synthesis Report

HDL Synthesis Report

Macro Statistics

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# Registers :1
1-bit register :1
Advanced HDL Synthesis Report
Macro Statistics
# Registers :1
Flip-Flops :1
Final Register Report
Macro Statistics
# Registers :1
Flip-Flops :1
Final Report:
Final Results
RTL Top Level Output File Name : DFF_Asyn.ngr
Top Level Output File Name : DFF_Asyn
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :4
Cell Usage :
# BELS :1
# INV :1
# FlipFlops/Latches :1
# FDC :1
# Clock Buffers :1
# BUFGP :1
# IO Buffers :3
# IBUF :2
# OBUF :1
=========================================================================
Device utilization summary:
Selected Device : 3s250eft256-5
Number of Slices: 1 out of 2448 0%
Number of Slice Flip Flops: 1 out of 4896 0%
Number of IOs: 4
Number of bonded IOBs: 4 out of 172 2%

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IOB Flip Flops: 1

Number of GCLKs: 1 out of 24 4%
TIMING REPORT:
Clock Information:
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |1 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Rst | IBUF |1 |
-----------------------------------+------------------------+-------+
Timing Summary:
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: 2.7004ns
Maximum output required time after clock: 4.040ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 2.700ns (Levels of Logic = 2)
Source: T (PAD)
Destination: Q (FF)
Destination Clock: clk rising
Data Path: T to Q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 1.106 0.357 T_IBUF (T_IBUF)
INV:I->O 1 0.612 0.357 Q_not00011_INV_0 (Q_not0001)
FDC:D 0.268 Q
----------------------------------------
Total 2.700ns
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Total number of paths / destination ports: 1 / 1
-------------------------------------------------------------------------
Offset: 4.040ns (Levels of Logic = 1)
Source: Q (FF)
Destination: Q (PAD)
Source Clock: clk rising

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Data Path: Q to Q
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 1 0.514 0.357 Q (Q_OBUF)
OBUF:I->O 3.169 Q_OBUF (Q)
----------------------------------------
Total 4.040ns
=========================================================================

Simulation Results:

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_TFF_Asyn_vhd IS
END tb_TFF_Asyn_vhd;
ARCHITECTURE behavior OF tb_TFF_Asyn_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TFF_Asyn
PORT(

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Rst : IN std_logic;
clk : IN std_logic;
T : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
SIGNAL Rst : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL T : std_logic := '0';
SIGNAL Q : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TFF_Asyn PORT MAP(
Rst => Rst,
clk => clk,
T => T,
Q => Q
);
Clk<= not Clk after 10ns;
Rst<='1' after 40ns;
T<='1' after 10ns,'0' after 30ns;

Result: T Flip Flop with Asynchronous “Reset” is designed using VHDL and simulated the
same using Xilinx ISE Simulator.

(D)T Flip Flop with Synchronous “Reset”

Aim: To Design T Flip Flop with Synchronous “Reset” using VHDL and simulate the same
using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TFF_Syn is

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Port ( Clk : in STD_LOGIC;

Rst : in STD_LOGIC;

T : in STD_LOGIC;

Q : out STD_LOGIC);

end TFF_Syn;

architecture Behavioral of TFF_Syn is

begin

process

begin

wait until clk'event and clk='1';

if Rst='1' then Q<='0';

elsif Clk'event and clk='1' then Q<= not T;

end if;

end process;

end Behavioral;

Schematic Diagram:

Simulation Results:

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VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_TFF_Syn_vhd IS
END tb_TFF_Syn_vhd;
ARCHITECTURE behavior OF tb_TFF_Syn_vhd IS
COMPONENT TFF_Syn
PORT(
Clk : IN std_logic;
Rst : IN std_logic;
T : IN std_logic;
Q : OUT std_logic
);
END COMPONENT;
SIGNAL Clk : std_logic := '0';
SIGNAL Rst : std_logic := '0';
SIGNAL T : std_logic := '0';
SIGNAL Q : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TFF_Syn PORT MAP(

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Clk => Clk,

Rst => Rst,
T => T,
Q => Q
);
Clk<= not Clk after 10ns;
Rst<='1' after 40ns;
T<='1' after 10ns,'0' after 30ns;
END;

4.8.3 VERILOG simulation

Verilog code for SR Flip-Flop

module srff(s,r,clk,rst, q,qb);

input s,r,clk,rst;
output q,qb;
reg q,qb;
reg [1:0]sr;
always@(posedge clk,posedge rst)
begin
sr={s,r}; //concatenate S&R to a 2 bit value
if(rst==0) // when reset is not asserted
begin
case (sr)
2'd1:q=1'b0;
2'd2:q=1'b1;
2'd3:q=1'b1;
default: begin end
endcase
end
else // when reset is asserted
begin
q=1'b0;
end

qb=~q;
end
endmodule

Verilog code for JK Flip Flop

`define TICK #2 //Flip-flop time delay 2 units

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module jkflop(j,k,clk,rst,q);
input j,k,clk,rst;
output q;
reg q;
always @(posedge clk)begin
if(j==1 & k==1 & rst==0)begin
q =`TICK ~q; //Toggles
end
else if(j==1 & k==0 & rst==0)begin
q = `TICK 1; //Set
end
else if(j==0 & k==1)begin
q = `TICK 0; //Cleared
end
end
always @(posedge rst)begin
q = 0; //The reset normally has negligible delay and hence ignored.
end
endmodule

Verilog Code for D-Flip Flop

// code for dff

module Dff(input d,input clk,output reg q);
always @(posedge clk) // note: lines whithin the always block are executed sequententialy
begin
q=d;
end
endmodule

VERILOG code for T FlipFlop

module tff(t,clk,rst, q,qb);
input t,clk,rst;
output q,qb;
reg q,qb;
reg temp=0;
always@(posedge clk,posedge rst)
begin
if (rst==0) begin
if(t==1) begin
temp=~ temp;
end
else
temp=temp;
end
q=temp;qb=~temp; end
endmodule

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Experiment No:9
4.9 BCD Counter with Asynchronous Reset

4.9.1 Aim: To Design BCD Counter with Asynchronous Reset using VHDL and
simulate the same using Xilinx ISE Simulator

Tools Required: 1.PC

2. Xilinx ISE

4.9.2 VHDL simulation

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity BCD_Counter_Asyn is
Port ( Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Count : Buffer STD_LOGIC_VECTOR (3 downto 0));
end BCD_Counter_Asyn;
architecture Behavioral of BCD_Counter_Asyn is
begin
process(Rst,Clk,Count)
begin
if Rst='1' then Count<="0000";
elsif Clk'event and clk='1' then
Count<=Count+1;
if count="1111" then count<="0000";
end if;
end if;
end process;
end Behavioral;

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Schematic Diagram:

Synthesis Report
HDL Synthesis Report
Macro Statistics
# Counters :1
4-bit up counter :1
Final Register Report
Macro Statistics
# Registers :4
Flip-Flops :4
Final Report:
Final Results
RTL Top Level Output File Name : BCD_Counter_Asyn.ngr
Top Level Output File Name : BCD_Counter_Asyn
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : NO
Design Statistics
# IOs :6
Cell Usage :
# BELS :4
# INV :1
# LUT2 :1
# LUT3 :1
# LUT4 :1
# FlipFlops/Latches :4
# FDC :4
# Clock Buffers :1
# BUFGP :1
# IO Buffers :5
# IBUF :1
# OBUF :4
Device utilization summary:

Selected Device : 3s250eft256-5

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Number of Slices: 2 out of 2448 0%

Number of Slice Flip Flops: 4 out of 4896 0%
Number of 4 input LUTs: 4 out of 4896 0%
Number of IOs: 6
Number of bonded IOBs: 6 out of 172 3%
Number of GCLKs: 1 out of 24 4%
TIMING REPORT:

Clock Information:

-----------------------------------+--------------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Clk | BUFGP |4 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:

-----------------------------------+------------------------+-------+
Control Signal | Buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
Rst | IBUF |4 |
-----------------------------------+------------------------+-------+
Timing Summary:
Speed Grade: -5
Minimum period: 2.289ns (Maximum Frequency: 436.862MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.221ns
Timing constraint: Default period analysis for Clock 'Clk'
Clock period: 2.289ns (frequency: 436.862MHz)
Total number of paths / destination ports: 10 / 4
-------------------------------------------------------------------------
Delay: 2.289ns (Levels of Logic = 1)
Source: Count_0 (FF)
Destination: Count_0 (FF)
Source Clock: Clk rising
Destination Clock: Clk rising
Data Path: Count_0 to Count_0
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 5 0.514 0.538 Count_0 (Count_0)
INV:I->O 1 0.612 0.357 Mcount_Count_xor<0>11_INV_0
(Mcount_Count)
FDC:D 0.268 Count_0
----------------------------------------
Total 2.289ns

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Timing constraint: Default OFFSET OUT AFTER for Clock 'Clk'

Total number of paths / destination ports: 4 / 4
-------------------------------------------------------------------------
Offset: 4.221ns (Levels of Logic = 1)
Source: Count_0 (FF)
Destination: Count<0> (PAD)
Source Clock: Clk rising

Data Path: Count_0 to Count<0>

Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDC:C->Q 5 0.514 0.538 Count_0 (Count_0)
OBUF:I->O 3.169 Count_0_OBUF (Count<0>)
----------------------------------------
Total 4.221ns

Simulation Results:

VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_BCD_Counter_Asyn_vhd IS
END tb_BCD_Counter_Asyn_vhd;
ARCHITECTURE behavior OF tb_BCD_Counter_Asyn_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BCD_Counter_Asyn

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PORT(
Rst : IN std_logic;
Clk : IN std_logic;
Count :Buffer std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL Rst : std_logic := '0';
SIGNAL Clk : std_logic := '0';
--Outputs
SIGNAL Count : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: BCD_Counter_Asyn PORT MAP(
Rst => Rst,
Clk => Clk,
Count => Count
);
Clk<= not clk after 10ns;
Rst<='1' after 10ns,'0' after 20ns,'1' after 360ns;
END;

Result: BCD Counter with Asynchronous Reset is designed using VHDL and simulated the
same using Xilinx ISE Simulator

B)BCD Counter with synchronous Reset

Aim: To Design BCD Counter with Synchronous Reset using VHDL and simulate the same
using Xilinx ISE Simulator
Tools Required: 1.PC
2. Xilinx ISE

VHDL Code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity BCD_Counter_Syn is
Port ( Rst : in STD_LOGIC;
Clk : in STD_LOGIC;
Count : Buffer STD_LOGIC_VECTOR (3 downto 0));
end BCD_Counter_Syn;
architecture Behavioral of BCD_Counter_Syn is
begin
process
begin
wait until clk’event and clk=’1’;;
if Rst='1' then Count<="0000";
elsif Clk'event and clk='1' then
Count<=Count+1;
if count="1111" then count<="0000";
end if;
end if;
end process;
end Behavioral;

Schematic Diagram:

Simulation Results:

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VHDL Test bench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

USE ieee.std_logic_unsigned.all;

USE ieee.numeric_std.ALL;

ENTITY tb_BCD_Counter_Syn_vhd IS
END tb_BCD_Counter_Syn_vhd;
ARCHITECTURE behavior OF tb_BCD_Counter_Syn_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT BCD_Counter_Asyn
PORT(
Rst : IN std_logic;
Clk : IN std_logic;
Count :Buffer std_logic_vector(3 downto 0)
);
END COMPONENT;
--Inputs
SIGNAL Rst : std_logic := '0';
SIGNAL Clk : std_logic := '0';
--Outputs
SIGNAL Count : std_logic_vector(3 downto 0);
BEGIN

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-- Instantiate the Unit Under Test (UUT)

uut: BCD_Counter_Asyn PORT MAP(
Rst => Rst,
Clk => Clk,
Count => Count
);
Clk<= not clk after 10ns;
Rst<='1' after 10ns,'0' after 20ns,'1' after 360ns;
END;

Result: BCD Counter with Synchronous Reset is designed using VHDL and simulated the
same using Xilinx ISE Simulator
IC 74x90 – DECADE COUNTER

AIM:To write the VHDL code for IC 74x90 – decade counter.

CIRCUIT DIAGRAM OF IC 74x90:

TRUTH TABLE:

Q(0) Q(3) Q(2) Q(1)

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0

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VHDL CODE:

--To work as a decade counter

library IEEE;
Use IEEE.std_logic_1164.all;

entity count is
port (
S0, s1, r0, r1: in STD_LOGIC; --set and reset i/ps for mod2 and
-- Mod5 counters
Clk0: in STD_LOGIC; --Clock signal for mod2 counter

Clk1: inout STD_LOGIC; --Clock signal for mod5 counter

q : inout STD_LOGIC_VECTOR(3 downto 0) --o/p of

-- mod2 X mod5= mod10
);
end count;

architecture count of count is

component jk_ff -- jk flip flop instantiation

port (
jk : in STD_LOGIC_VECTOR(1 downto 0);
clk,pr_l,clr_l : in STD_LOGIC;
q,nq : inout STD_LOGIC

);
end component;

signal preset,clear,S, q3bar:STD_LOGIC;

begin

preset <= s0 nand s1; -- common preset inputs for mod2 and mod5 counters
clear <=r0 nand r1; -- common reset inputs for mod2 and mod5 counters
S<=q(2) and q(1); -- to set the last flip flop
q3bar <= not q(3); -- complemented output of q(3)
clk1<=q(0); --to work as asynchronous mod10 counter

jk1:jk_ff port map("11",clk0,preset,clear,q(0),open);

jk2:jk_ff port map(jk(1)=> q3bar,
jk(0)=>'1',
clk=>clk1,
pr_l=>preset,
clr_l=>clear,
q=>q(1),

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nq=>open); -- jk1.jk2,jk3,jk4 create four JK flip flops

jk3:jk_ff port map("11",q(1),preset,clear,q(2),open);
jk4:jk_ff port map(jk(0)=>q(3),
jk(1)=>s,
clk=>clk1,
pr_l=>preset,
clr_l=>clear,
q=>q(3), nq=>
q3bar);

end count;

WAVEFORMS:

--Program for JK flip-flop

library IEEE;
use IEEE.std_logic_1164.all;

entity jk_ff is
port (
jk : in STD_LOGIC_VECTOR(1 downto 0);

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--jk(1)=J;jk(0)=K;
clk,pr_l,clr_l : in STD_LOGIC; q,nq :
inout STD_LOGIC );

end jk_ff;

architecture jk of jk_ff is
begin
process(clk,pr_l,clr_l,jk)
variable temp:std_logic:='0';
begin
q<='0';nq<='1';
if (pr_l='1' and clr_l='0') then
q<='0';nq<='1';
elsif (pr_l='0' and clr_l ='1') then
q<='1';nq<='0';
elsif (pr_l='1' and clr_l='1') then
if (clk 'event and clk='0') then --performs during the falling edge of clock

case jk is
when "00"=>temp:=temp; when
"01"=>temp:='0'; when
"10"=>temp:='1'; when
"11"=>temp:=not temp; when
others=>null;
end case;

end if; q<=temp;

nq<= not temp;
end if;
end process;
end jk;
WAVEFORMS:

IC 74x93 – 4 -BIT BINARY COUNTER

AIM:To write the VHDL code for IC 74x93 – 4 -bit binary counter.

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TRUTH TABLE:
Q(3) Q(2) Q(1) Q(0)
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
CIRCUIT DIAGRAM OF IC74X93:

VHDL CODE:
--Program for 4-bit counter

library IEEE;
use IEEE.std_logic_1164.all;

entity cnt is port

(
clk0: in STD_LOGIC; mr0: in
STD_LOGIC; mr1: in
STD_LOGIC; clk1: inout
STD_LOGIC;
Q:inout STD_LOGIC_VECTOR(3 downto 0)

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); end
cnt;

architecture cnt of cnt is

Component tff -- T- flip flop instantiation

port (
t : in STD_LOGIC; clk : in
STD_LOGIC; clr_l : in
STD_LOGIC; q,nq : out
STD_LOGIC

);
end component; signal
clear : std_logic; begin

clear<= mr0 nand mr1; -- common reset inputs for mod2 and mod8 --
counters
CLK1<=q(0); --to work as asynchronous mod16 counter
t1:tff port map('1',clk0,clear,Q(0),open);--t1,t2,t3,t4 create four T-flip flops
t2:tff port map('1',clk1,clear,Q(1), open);
t3:tff port map('1',Q(1),clear,Q(2), open);
t4:tff port map('1',Q(2),clear,Q(3), open);

end cnt;
WAVEFORMS:

--Program for T flip-flop

library IEEE;
use IEEE.std_logic_1164.all;
entity tff is port (
t : in STD_LOGIC;--input to the T-flip flop
clk : in STD_LOGIC;--Clock signal for T-flip flop clr_l
: in STD_LOGIC;--active low clear input
q,nq : out STD_LOGIC--actual and complemented outputs of T-flip flop

);

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end tff;

architecture tff of tff is

begin process(t,clk,clr_l)
variable temp:STD_LOGIC:='0';
begin
if (clr_l='0') then
temp:='0';
elsif ((clr_l='1') and (clk'event and clk='0')) then--perfoms during falling edge if (
t='0') then
temp:=temp;
else temp:= not temp;
end if;
end if; q<=
temp;
nq<= not temp;
end process; end tff;

WAVEFORMS:

4.9.3 VERILOG simulation

Verilog code for a 4-bit unsigned down counter with synchronous set.

module counter (clk, s, q);

input clk, s;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (s)
tmp <= 4’b1111;
else
tmp <= tmp - 1’b1;
end
assign q = tmp;
endmodule

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Verilog code for a 4-bit unsigned up counter with an asynchronous load from the
primary input.

module counter (clk, load, d, q);

input clk, load;
input [3:0] d;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge load)
begin
if (load)
tmp <= d;
else
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Verilog code for a 4-bit unsigned up counter with a synchronous load with a constant.

module counter (clk, sload, q);

input clk, sload;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk)
begin
if (sload)
tmp <= 4’b1010;
else
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Verilog code for a 4-bit unsigned up counter with an asynchronous clear and a clock
enable.

module counter (clk, clr, ce, q);

input clk, clr, ce;
output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else if (ce)
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Verilog code for a 4-bit unsigned up/down counter with an asynchronous clear.

module counter (clk, clr, up_down, q);

input clk, clr, up_down;

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output [3:0] q;
reg [3:0] tmp;
always @(posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else if (up_down)
tmp <= tmp + 1’b1;
else
tmp <= tmp - 1’b1;
end
assign q = tmp;
endmodule

e Verilog code for a 4-bit signed up counter with an asynchronous reset.

module counter (clk, clr, q);

input clk, clr;
output signed [3:0] q;
reg signed [3:0] tmp;
always @ (posedge clk or posedge clr)
begin
if (clr)
tmp <= 4’b0000;
else
tmp <= tmp + 1’b1;
end
assign q = tmp;
endmodule

Verilog code for a 4-bit signed up counter with an asynchronous reset and a modulo
maximum.

module counter (clk, clr, q);

parameter MAX_SQRT = 4, MAX = (MAX_SQRT*MAX_SQRT);
input clk, clr;
output [MAX_SQRT-1:0] q;
reg [MAX_SQRT-1:0] cnt;
always @ (posedge clk or posedge clr)
begin
if (clr)
cnt <= 0;
else
cnt <= (cnt + 1) %MAX;
end
assign q = cnt;
endmodule

//Another design of binary counter

module bin_as(clk,clr,dir, temp);

input clk,clr,dir;
output reg[3:0] temp;
always@(posedge clk,posedge clr)
begin
if(clr==0)

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begin
if(dir==0)
temp=temp+1;
else temp=temp-1;
end
else
temp=4'd0;
end
end module

// BCD counter verilog code

module bcd(clr,clk,dir, tc, q);

input clr,clk,dir;
output reg tc;
output reg[3:0] q;
always@(posedge clk,posedge clr)
begin
if(clr==1)
q=4'd0;
else
begin
if (dir==1)
q=q+1;
else if(dir==0)
q=q-1;
if(dir==1 & q==4'd10)
begin
q=4'd0;tc=1'b1;
end
else if(dir==0 & q==4'd15)
begin
q=1'd9;tc=1'b1;
end
else tc=1'b0;
end
end

end module

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EXPEREIMENT -10

4.10 To design a Finite state machine for “1011” overlapping sequence detector
4.10.1 Aim: To Design BCD Counter with Asynchronous Reset using VHDL and
simulate the same using Xilinx ISE Simulator

Tools Required: 1.PC

2. Xilinx ISE

4.10.2 VHDL simulation

Finite State Machine (FSM) Coding In VHDL

There is a special Coding style for State Machines in VHDL as well as in Verilog.

Let us consider below given state machine which is a “1011” overlapping sequence detector. Output
becomes ‘1’ when sequence is detected in state S4 else it remains ‘0’ for other states.

VHDL Code for FSM:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

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--Sequence detector for detecting the sequence "1011".

--Overlapping type.
entity seq_det is
port( clk : in std_logic; --clock signal
reset : in std_logic; --reset signal
S_in : in std_logic; --serial bit Input sequence
S_out : out std_logic); -- Output
end seq_det;
architecture Behavioral of seq_det is
--Defines the type for states in the state machine
type state_type is (S0,S1,S2,S3,S4);
--Declare the signal with the corresponding state type.
signal Current_State, Next_State : state_type;
begin
-- Synchronous Process
process(clk)
begin
if( reset = '1' ) then --Synchronous Reset
Current_State <= 'S0';
elsif (clk'event and clk = '1') then --Rising edge of Clock
Current_State <= Next_State
end if;
end process;
-- Combinational Process
Process(Current_State, S_in)
begin
case Current_State is
when S0 =>
S_out <= '0';
if ( s_in = '0' ) then
Next_State <= S0;
else
Next_State <= S1;
end if;
when S1 =>
S_out <= '1';
if ( S_in = '0' ) then
Next_State <= S3;
else
Next_State <= S2;
end if;
when S2 =>
S_out <= '0';
if ( S_in = '0' ) then
Next_State <= S0;

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else
Next_State <= S3;
end if;
when S3 =>
S_out <= '1';
if (S_in = '0' ) then
Next_State <= S2;
else
Next_State <= S4;
end if;
when S4 =>
S_out <= '1';
if ( S_in = '0' ) then
Next_State <= S2;
else
Next_State <= S1;
end if;
when others =>
NULL;
end case;
end if;
end process;

4.10.3 Verilog Code for FSM:

// 4-State Moore state machine

// A Moore machine's outputs are dependent only on the current state.
// The output is written only when the state changes. (State
// transitions are synchronous.)
module seq_dect
(
input clk, data_in, reset,
output reg data_out
);
// Declare state register
reg [2:0]state;
// Declare states
parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3, S4 = 4;

// Determine the next state

always @ (posedge clk or posedge reset) begin
if (reset)
state <= S0;
else

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case (state)
S0:
if (data_in)
state <= S1;
else
state <= S0;
S1:
if (data_in)
state <= S1;
else
state <= S2;
S2:
if (data_in)
state <= S3;
else
state <= S2;
S3:
if (data_in)
state <= S4;
else
state <= S2;
S4:
if (data_in)
state <= S1;
else
state <= S2;
endcase // case (state)
end // always @ (posedge clk or posedge reset)
// Output depends only on the state
always @ (state) begin
case (state)
S0:
data_out = 1'b0;
S1:
data_out = 1'b1;
S2:
data_out = 1'b0;
S3:
data_out = 1'b1;
S4:
data_out = 1'b1;
default:
data_out = 1'b0;
endcase // case (state)

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end // always @ (state)

endmodule

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Additional experiments beyond the syllabus

1. RIPPLE CARRY ADDER
AIM: To write and simulate a vhdl program for a ripple carry adder and verify the results

CIRCUIT DIAGRAM:

PROGRAM:-

library IEEE;

Use IEEE.STD_LOGIC_1164.All;

Use IEEE.STD_LOGIC_ARITH.All;

Use IEEE.STD_LOGIC_UNSIGNED.All;

entity rea is

Port (a: in std_logic _vector (3 downto 0); b: in std_logic _vector (3 downto 0);
ci:in std_logic;

s: out std_logic _vector (3 downto 0); co:in out std_logic);

end rea;

architecture structural of rea is

signal c:std_ logic vector(3 downto 1);

component fa is

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port (a,b,cin: in std_logic; s : out std_logic; cout: in out

std_logic);
end component;

begin

f1: fa port map( a(0), b(0), ci, s(0),c(1)); f2: fa port map(a(1), b(1), c(1),
s(1),c(2)); f3: fa port map(a(2), b(2), c(2), s(2),c(3));

f4: fa port map(1)p(a(3), b(3), c(3), s(3),c(0));

end structural;

2. MODELING OF SHIFT REGISTERS

AIM :-To write VHDL Program for realizing Shift Registers

Serial-in Serial-out
SHIFT REGISTERS

Serial in serial out (SISO)

PROGRAM:

library IEEE;

Use IEEE.STD_LOGIC_1164.All;
UseIEEE.STD_LOGIC_ARITH.Al;
UseIEEE.STD_LOGIC_UNSIGNED.Al; Entity siso is

Port (si: in std_logic; clk: in

std_logic; so:in out std_logic);

end siso;

architecture structural of siso is

component d_ff is

Port( d,clk: in std_logic; q,qbar :in out

std_logic);

end component;

Signal a1, a2, a3, d1, d2, d3, d4:std_logic;

begin

11:d_ff port map (si, clk, a1,d1);

12:d_ff port map (a1, clk,a2,d2);

13:d_ff port map (a2, clk,a3,d3); 14:d_ff port

map (a3, clk,so,d4); end structural;

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