APL5934

3A, Ultra Low Dropout (0.23V Typical) Linear Regulator

Features General Description

• Ultra Low Dropout The APL5934 is a 3A ultra low dropout linear regulator.
- 0.23V(typical) at 3A Output Current The IC needs two supply voltages, one is a control voltage
• Low ESR Output Capacitor (Multi-layer (VCNTL) for the control circuitry, the other is a main supply
voltage (VIN) for power conversion, to reduce power dissi-
Chip Capacitors (MLCC)) Applicable
pation and provide extremely low dropout voltage.
• 0.8V Reference Voltage
The APL5934/B integrates many functions. A Power-On-
• High Output Accuracy
Reset (POR) circuit monitors both supply voltages on
- ±1.5% over Line, Load, and Temperature Range VCNTL and VIN pins to prevent erroneous operations.
• Fast Transient Response The functions of thermal shutdown and current-limit pro-
• Adjustable Output Voltage tect the device against thermal and current over-loads. A
• Power-On-Reset Monitoring on Both VCNTL and POK indicates the output voltage status with a delay time
VIN Pins set internally. It can control other converter for power
• Internal Soft-Start sequence. The APL5934/B can be enabled by other power

• Current-Limit and Short Current-Limit Protections

systems. Pulling and holding the EN/ENB voltage below
0.4V shut/enable off the output.
• Thermal Shutdown with Hysteresis
The APL5934 is available in a SOP-8P package which
• Open-Drain VOUT Voltage Indicator (POK)
features small size as SOP-8 and an Exposed Pad to
• Low Shutdown Quiescent Current reduce the junction-to-case resistance to extend power
• Shutdown/Enable Control Function range of applications.
• Simple SOP-8P and TDFN3x3-10 Packages with
Exposed Pad Applications
• Lead Free and Green Devices Available
(RoHS Compliant)
• Front Side Bus VTT (1.2V/3A)
• Note Book PC Applications
• Motherboard Applications

Simplified Application Circuit

VCNTL

VIN
VCNTL
POK POK VIN

VOUT VOUT
APL5934
EN EN FB
Enable GND

Optional

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.

Copyright  ANPEC Electronics Corp. 1 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Pin Configuration

APL5934/C APL5934/C
POK 1 10 VCNTL
GND 1 8 EN
FB 2 9 EN
FB 2 7 POK GND
VOUT 3 8 VIN
VOUT 3 6 VCNTL VOUT 4 7 VIN
VOUT 4 5 VIN VOUT 5 6 VIN

SOP-8P (Top View) TDFN3X3-10

(Top View)
= Exposed Pad = Exposed Pad
(connected to VIN or ground plane (connected to ground plane for better heat dissipation)
for better heat dissipation)

APL5934B/D APL5934B/D

POK 1 8 GND VOUT 1 10 VCNTL

VOUT 2 9 VIN
EN 2 7 FB
VOUT 3 GND 8 VIN
VIN 3 6 VOUT FB 4 7 VIN
VCNTL 4 5 NC POK 5 6 EN

SOP-8P (Top View) TDFN3X3-10

(Top View)
= Exposed Pad = Exposed Pad
(connected to ground plane (connected to ground plane for better heat dissipation)
for better heat dissipation)

APL5934E
VOUT 1 8 VCNTL
VOUT 2 7 VIN
GND
FB 3 6 VIN
POK 4 5 EN

TDFN2X2-8
(Top View)
= Exposed Pad
(connected to ground plane for better heat dissipation)

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Rev. A.7 - Oct., 2018
APL5934

Ordering and Marking Information

APL5934 Product Code (Enable Function)

Blank : Avtive High/Initial On B : Active High / Intitial On
Assembly Material C : Active High/Initial Off D : Active High / Initial Off
Handling Code E: Active High / Initial Off
Package Code
Temperature Range
KA : SOP-8P QB : TDFN3x3-10 QB : TDFN2x2-8
Package Code Operating Ambient Temperature Range
EN Function I : -40 to 85oC
Handling Code
TR : Tape & Reel
Assembly Material
G: Halogen and Lead Free Device

APL5934 APL
APL5934 KA: XXXXX XXXXX – Date Code APL5934 QB: 5934 XXXXX – Date Code
XXXXX

APL5934B APL
APL5934B KA: XXXXX XXXXX – Date Code APL5934B QB: 5934B XXXXX – Date Code
XXXXX

APL5934C APL
APL5934C KA: XXXXX XXXXX – Date Code APL5934C QB: 5934C XXXXX – Date Code
XXXXX

APL5934D APL
APL5934D KA: APL5934D QB: 5934D
XXXXX XXXXX – Date Code XXXXX XXXXX – Date Code

L34E
APL5934E QB: X – Date Code
X

Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).

Copyright  ANPEC Electronics Corp. 3 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Absolute Maximum Ratings (Note 1)

S ymbol Pa ram ete r Rating Unit

V IN VIN Su pply Vo ltag e (VIN to GND) -0.3 ~ 6 V
VCN TL VCNTL Su pply Vo ltag e ( VCNTL to GND) -0.3 ~ 6 V
VOUT VOUT to GND Vo ltag e -0.3 ~ VIN +0.3 V
POK to GND Voltage -0.3 ~ 6 V
EN, FB to G ND Volta ge -0.3 ~ VC NTL +0.3 V
PD Power Dissipation, T A=25oC 1 .8 W
I OUT(PK) VOUT Peak Cu rrent (<3 0µs) 9 A
o
TJ Ma xim um Junction Tempera tu re 15 0 C
o
T STG Sto rage Temperature -65 ~ 1 50 C
o
T SDR Ma xim um Le ad So lderin g Tempe ratu re, 1 0 S econd s 26 0 C

Note1: Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stre-
ss ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommen-
ded operating conditions" is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device
reliability.

Thermal Characteristics
S ymbol Pa ramete r Typica l Value Unit
(No te 2 )
Ju nctio n-to-Ambi ent Resistance in Fre e Ai r
SOP- 8P 50 o
θ JA C/W
TDFN3 x3- 10 50
TDFN2x2 -8 75
(Note 2)
Ju nctio n-to-Case Resistance in Free Air o
θ JC C/W
SOP- 8P 18

Note 2: θJA and θJC is measured with the component mounted on a high effective thermal conductivity test board in free air. The
exposed pad of SOP-8P/ TDFN3x3-10/TDFN2x2-8 is soldered directly on the PCB.

Recommended Operating Conditions

Sym bol Param eter Range Unit
VC NTL VCNTL Sup ply Vo ltag e 3.0 ~ 5.5 V
VIN VIN Su pply Vo ltag e 1.2 ~ 5.5 V
VOUT VOUT Output Voltage (whe n VCNTL-V OUT>1.9V) 0 .8 ~ V IN – VD ROP V
Con tin uous Curren t 0~3
I OUT VOUT Output Cur rent A
P eak Cu rrent 0~4
I OUT = 3 A at 25% nomin al VOUT 8 ~ 1100
C OUT VOUT Output Capa citan ce I OUT = 2 A at 25% nomin al VOUT 8 ~ 17 00 µF
I OUT = 1 A at 25% nomin al VOUT 8 ~ 24 00
ES RC OUT ESR of V OUT Ou tpu t Capacitor 0 ~ 200 mΩ
o
TA Ambie nt Tempera tur e -40 ~ 85 C
o
TJ Ju nctio n Tempe rature -4 0 ~ 125 C

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Rev. A.7 - Oct., 2018
APL5934

Electrical Characteristics (Cont.)

Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values
are at TA=25oC.

APL593 4
Symbol Parameter Test Conditions Unit
Min. Typ. Ma x.
S UPPLY CURRENT
I VCN TL VCNTL Su pply Cu rrent EN = High or ENB = Low, I OUT =0A - 100 1 20 µA
I SD VCNTL Sup ply Curre nt at S hutdown EN = Low, or ENB = High - - 3 µA
VIN Su pply Cu rrent at Sh utd own EN = Low, or ENB = High - - 1 µA
P OWER-O N- RESET (PO R)
Ri sin g VCNTL PO R Threshol d 2.5 2.7 2.9 V
VCNTL POR Hystere sis - 0.4 - V
Ri sin g VIN PO R Thresho ld 0.8 0.9 1.0 V
VIN POR Hystere sis - 0.5 - V
O UTPUT VOLTAG E
V REF Re fe rence Volta ge FB=VOUT - 0.8 - V
VCN TL=3.0 ~ 5.5V, IOUT = 0~3A,
Output Vo lta ge Accura cy o -1 .5 - +1.5 %
TJ= -40~125 C
Load Reg ulation IOUT =0 A ~3A - 0.06 0.25 %
Line Regu lation IOUT =1 0mA, V CNTL= 3.0 ~ 5.5V - 0.15 - + 0 .15 %/V
VOUT Pull-lo w Resistan ce VCN TL=5V, VEN=0V, VOUT< 0.8V - 85 - Ω
FB Inp ut Curre nt VFB=0.8V -10 0 - 1 00 nA
DROPOUT VOLTAGE
o
T J=2 5 C - 0.26 0.31
VOUT =2 .5V
o
T J=-4 0~1 25 C - - 0.42
VCN TL=5.0V, o
VDR OP VIN- to -VOUT Dro pout Vo ltag e T J=25 C - 0.24 0.29 V
IOUT =3 A VOUT =1.8V
o
T J=-4 0~1 25 C - - 0.40
o
T J=25 C - 0.23 0.28
VOUT =1.2V o
T J=-4 0~1 25 C - - 0.38
o
TJ=25 C 4.7 5.7 6.7
I LIM Cu rrent-Li mit Level A
TJ= -40 ~ 125 oC 4.2 - -
P ROTECTIONS
I SHORT Shor t Curren t- Limit Le ve l VFB<0.2V - 1.1 - A
Shor t Curren t- Limit Bl anking Time Fr om b egin ning of soft-start 0.6 1.5 - ms
o
TSD Th ermal Sh utd own Temp erature TJ rising 1 45 150 - C
o
Th ermal Sh utd own Hyste resis - 50 - C

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Rev. A.7 - Oct., 2018
APL5934

Electrical Characteristics (Cont.)

Unless otherwise specified, these specifications apply over VCNTL=5V, VIN=1.8V, VOUT= 1.2V and TA= -40 ~ 85 oC. Typical values
are at TA=25oC.

APL5 934
S ymbol Param eter Test Conditions Unit
Min. Typ. Max.

ENABLE AND SOFT-START

EN Log ic High Thresho ld
Voltage
V EN/VENB VEN rising o r V ENB ri sin g 0.5 0.8 1.1 V
ENB L ogic Low Thre sh old
Voltage
EN/ENB Hystere sis - 0.1 - V
EN/ENB Pu ll-High Curre nt EN=GND or ENB = GND
- 3 - µA
EN/ENB Pu ll-Low Curren t EN=VCNTL or ENB = VCNTL
VOUT =10 % to 90 % (AP L593 4/B/C) 0.3 0.6 1.2
t SS Soft-Sta rt Interval ms
VOUT =10 % to 90 % (AP L593 4D/E ) 1 2 4
From being e nabl ed to VOUT risi ng 1 0%
60 120 230 µs
(AP L593 4/C)
t ON Turn On Dela y From being e nabl ed to VOUT risi ng 1 0%
1 2.5 4 ms
(AP L593 4B/D/E )
PO WER-OK AND DE LAY

VTHPOK Rising POK Th reshold Voltage VFB r isin g 90 92 94 %

POK Th reshold Hystere sis - 8 - %

POK Pull -low Vol tag e POK sin ks 5mA - 0 .25 0.4 V
POK Debou nce Interval VFB<falli ng POK voltage thresho ld - 10 - µs
POK Delay Time From VFB =VTHPOK to r isin g edge of th e V POK 1 2 4 ms

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Rev. A.7 - Oct., 2018
APL5934

Pin Description
PIN
NO .
FUNCTION
SO P-8P TDFN3x 3-10 TDFN2x2- 8 NAME
APL593 4B/D APL5 934/C AP L5 934 B/D AP L5 934/C APL593 4E
G roun d pin of the circuitry.
8 1 - - - GND A ll voltage l eve ls are measure d wi th
r espect to th is pin .
V oltage Feed back Pin . Conne cting this pin
7 2 4 2 3 FB to an exte rnal resistor divider receive s the
fee dback vol ta ge of the reg ulator.
O utput pin of the reg ulator. Conne ctin g
thi s pin to l oad and ou tpu t capacitors
( 10µF a t l east) is requ ired for stability and
im proving tra nsi ent respon se . The o utput
vol tag e is p rogra mm ed by the
6 3,4 1 ,2 ,3 3,4,5 1,2 VOUT
r esistor -divider co nnected to FB pin . Th e
V OUT can provide 3A (max.) loa d cur rent
to lo ads. Dur ing shutdown, the o utput
vol tag e is quickly d ischa rged b y an
i nternal pu ll-low MOSFET.
Ma in suppl y in put pin for voltage
co nve rsions. A decoup ling cap acito r
( ≥10µF re co mmende d) is u su ally
3 5 7 ,8 ,9 6,7,8 6,7 VIN co nnected nea r this pin to filter th e voltag e
n oise an d improve transie nt re sp onse.
Th e vo lta ge on this p in is moni tore d fo r
P ower-On-Reset purpo se .
B ias voltage inpu t p in for in te rnal con tro l
cir cu itry. Connect this pin to a voltag e
so urce (+5V r eco mmende -
4 6 10 10 8 VCNTL d ). A d ecoupli ng ca pacitor (0.1µF typ ica l)
i s usua lly conn ecte d n ear th is pi n to filte r
the voltage no ise . The vol ta ge a t th is pin is
m onitored for Power- On-Reset purp ose.
P ower-OK signal o utput pin. Th is pin is a n
o pen- drain outpu t used to indicate th e
status of output voltage by se nsing FB
1 7 5 1 4 POK
vol tag e. This pin is pulle d l ow whe n o utput
vol tag e is not with in the P owe r-OK voltag e
win dow.
A ctive-h igh ena ble control pin. Applying
a nd hol ding the vo lta ge on th is pin be low
the ena ble vol tag e thresh old shu ts d own
the output. W hen r e-ena bled, the IC
2 8 6 9 5 EN
u nder goes a new soft-sta rt process. Whe n
l eave this pin ope n, a n interna l pull-u p/low
cu rrent (3µA typical) pulls th e EN voltage
a nd ena bles/sh uts down the regu lator.

5 - - - - NC No Con necti on.

G roun d pin of the circu itr y. Connect th e

e xp osed pad to th e system gro und plan
Expo se d P ad - Exposed Pad Expo se d Pad Expo se d Pad GND
with la rge copp er are a fo r dissipating h eat
i nto the amb ient a ir.
Co nnect th is p ad to syste m VIN or g round
- Exposed P ad - - - -
p lane for goo d the rmal co nductivity.

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Rev. A.7 - Oct., 2018
APL5934

Typical Operating Characteristics

Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current
400 400
VCNTL=5V VCNTL=3.3V
VOUT=1.2V VOUT=1.2V
SOP-8P

Dropout Voltage, VDROP (mV)

SOP-8P
Dropout Voltage, VDROP (mV)

300 300
O TJ=125OC
TJ=125 C

200 200
TJ=25OC TJ=25OC

100 100
O TJ=-40OC
TJ=-40 C

0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Output Current, IOUT (A) Output Current, IOUT (A)

Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current
400 400
VCNTL=5V VCNTL=5V
VOUT=1.8V VOUT=2.5V
SOP-8P SOP-8P
Dropout Voltage, VDROP (mV)

Dropout Voltage, VDROP (mV)

300 300
O TJ=125OC
TJ=125 C

200 200
TJ=25OC TJ=25OC

100 100
TJ=-40OC TJ=-40OC

0 0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Output Current, IOUT (A) Output Current, IOUT (A)

Reference Voltage vs. Junction VIN Power Supply Rejection Ratio

Temperature (PSRR)
0.81 0
VCNTL =5V
Power Supply Rejection Ratio (dB)

VIN=1.2V
Reference Voltage, VREF (V)

-20
0.805 VINPK-PK=100mV
VOUT =0.8V
RL=10Ω
-40
CIN=10µF
0.8 COUT =10µF
-60

0.795
-80

0.79 - 100
-50 -10 30 70 110 150 20 100 1k 10k 200k
O
Junction Temperature ( C) Frequency (Hz)

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Rev. A.7 - Oct., 2018
APL5934

Typical Operating Characteristics (Cont.)

VCNTL Power Supply Rejection Dropout Voltage vs. Output Current
Ratio (PSRR)
0 400
VCNTL =4.6~5.4V VOUT=1.05V
Power Supply Rejection Ratio (dB)

VIN=1.2V TJ=25OC
-20 VOUT =0.8V SOP-8P

Dropout Voltage, VDROP (mV)

RL=10Ω 300
CIN=10µF
-40 VCNTL=3V
COUT =10µF
200
-60

100
-80
VCNTL=5V

- 100 0
20 100 1k 10k 200k 0 2.5
0.5 1 1.5 2 3
Frequency (Hz)
Output Current, IOUT (A)

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Rev. A.7 - Oct., 2018
APL5934

Operating Waveforms

Power On Power Off

VCNTL VCNTL
1 1
VIN

VIN
2 2
VOUT VOUT
3 3

VPOK VPOK
4 4

COUT=10µF,CIN=10µF COUT=10µF,CIN=10µF
CH1:VCNTL,5V/Div, DC CH1:VCNTL,5V/Div, DC
CH2:VIN,1V/Div, DC CH2:VIN,1V/Div, DC
CH3:VOUT,1V/Div, DC CH3:VOUT,1V/Div, DC
CH4:VPOK,5V/Div, DC CH4:VPOK,5V/Div, DC
TIME:4ms/Div TIME:40ms/Div

Over Current Protection Shutdown

V EN
1
VOUT
1 VOUT

2
V POK
3
IOUT
IOUT
2 4

C OUT =10µF,C IN=10µF C OUT =10 µF,C IN=10µF

CH1:V OUT,500 mV/Div, DC CH1:VEN,5V/Div, DC
CH2:I OUT ,2 A/Div, DC CH2:VOUT ,1V /Div, DC
TIME:100 µs/Div CH3:VPOK,5V /Div, DC
CH4:IOUT ,2A/Div, DC
TIME:2µs/Div

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Rev. A.7 - Oct., 2018
APL5934

Operating Waveforms (Cont.)

Enable

VEN
1

VOUT
2
VPOK
3

IOUT
4

COUT=10µF,CIN=10µF
CH1:VEN,5V/Div, DC
CH2:VOUT,1V/Div, DC
CH3:VPOK,5V/Div, DC
CH4:IOUT,2A/Div, DC
TIME:1ms/Div

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Rev. A.7 - Oct., 2018
APL5934

Block Diagram
APL5934/B
VCNTL

Thermal Power-On-
VCNTL POR
Shutdown Reset
(POR )
3µA

EN Turn on Enable
Delay Control Logic
and
0.8V Soft -Start

Enable
S oft -S tart
POK VIN

Enable

VREF
0.8V VOUT
POK Error Amplifier
Delay

IS EN
PWOK
GND
VREF_OK Current-Limit
92% Short Current -Limit
VREF

FB

APL5934C/D/E

VCNTL

Thermal Power-On-
POR
Shutdown Reset
(POR )

EN Turn on Enable
Delay Control Logic
and
3µA 0.8V Soft -Start
Enable
S oft -S tart

POK VIN

Enable

VREF
0.8V VOUT
POK Error Amplifier
Delay
IS EN

PWOK
GND
VREF_OK Current-Limit
92% Short Current -Limit
VREF

FB

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Rev. A.7 - Oct., 2018
APL5934

Typical Application Circuit

VCNTL
(+5V is preferred)

CCNTL
0.1µF
VIN
+1.8V
R3 CIN
5.1kΩ VCNTL 10µF
POK VIN
POK

VOUT VOUT
+1.2V / 3A
COUT
APL5934 10µF
EN EN FB (X5R/X7R Recommended)
Enable GND R1
R2 12kΩ
24kΩ

C1
Optional
(X5R/X7R Recommended)

10µF: GRM31MR60J106KE19 Murata

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Rev. A.7 - Oct., 2018
APL5934

Function Description
Power-On-Reset Thermal Shutdown

A Power-On-Reset (POR) circuit monitors both of supply A thermal shutdown circuit limits the junction tempera-
voltages on VCNTL and VIN pins to prevent wrong logic ture of APL5934. When the junction temperature exceeds
controls. The POR function initiates a soft-start process +150oC, a thermal sensor turns off the output NMOS, al-
after both of the supply voltages exceed their rising POR lowing the device to cool down. The regulator regulates
voltage thresholds during powering on. The POR func- the output again through initiation of a new soft-start pro-
tion also pulls low the POK voltage regardless the output cess after the junction temperature cools by 50oC, result-
status when one of the supply voltages falls below its ing in a pulsed output during continuous thermal over-
falling POR voltage threshold. load conditions. The thermal shutdown is designed with
a 50oC hysteresis to lower the average junction tempera-
Internal Soft-Start
ture during continuous thermal overload conditions, ex-
An internal soft-start function controls rise rate of the out- tending lifetime of the device.
put voltage to limit the current surge during start-up. The For normal operation, the device power dissipation should
typical soft-start interval is about 0.6 ms. be externally limited so that junction temperatures will
not exceed +125oC.
Output Voltage Regulation
Enable Control
An error amplifier works with a temperature-com-
pensated 0.8V reference and an output NMOS regulates The APL5934 has a dedicated enable pin (EN). A logic
output to the preset voltage. The error amplifier is de- low signal applied to this pin shuts down the output. Fol-
signed with high bandwidth and DC gain provides very lowing a shutdown, a logic high signal re-enables the
fast transient response and less load regulation. It com- output through initiation of a new soft-start cycle. When
pares the reference with the feedback voltage and ampli- left open, this pin is pulled up/low by an internal current
fies the difference to drive the output NMOS which pro- source (3µA typical) to enable/shutdown normal
vides load current from VIN to VOUT. operation. It’s not necessary to use an external transistor
to save cost.
Current-Limit Protection

The APL5934 monitors the current flowing through the Power-OK and Delay
output NMOS and limits the maximum current to prevent The APL5934 indicates the status of the output voltage by
load and APL5934 from damages during current over- monitoring the feedback voltage (VFB) on FB pin. As the
load conditions. VFB rises and reaches the rising Power-OK voltage thresh-
old (VTHPOK), an internal delay function starts to work. At
Short Current-Limit Protection
the end of the delay time, the IC turns off the internal
The short current-limit function reduces the current-limit NMOS of the POK to indicate that the output is ok. As the
level down to 1.1A (typical) when the voltage on FB pin V FB falls and reaches the falling Power-OK voltage
falls below 0.2V (typical) during current overload or short- threshold, the IC turns on the NMOS of the POK (after a
circuit conditions. debounce time of 10µs typical).
The short current-limit function is disabled for success-
ful start-up during soft-start interval.

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Rev. A.7 - Oct., 2018
APL5934

Application Information
Power Sequencing However, if the drop of the input voltage is not cared, the
The power sequencing of VIN and VCNTL is not neces- input capacitance can be less than 10µF. More capaci-
sary to be concerned. However, do not apply a voltage to tance reduces the variations of the supply voltage on VIN
VOUT for a long time when the main voltage applied at pin.
VIN is not present. The reason is the internal parasitic Setting Output Voltage
diode from VOUT to VIN conducts and dissipates power
The output voltage is programmed by the resistor divider
without protections due to the forward-voltage.
connected to FB pin. The preset output voltage is calcu-
Output Capacitor lated by the following equation :
The APL5934 requires a proper output capacitor to main-  R1 
VOUT = 0.8 ⋅ 1 +  ........... (V)
tain stability and improve transient response. The output  R2 
capacitor selection is dependent upon ESR (equivalent
Where R1 is the resistor connected from VOUT to FB with
series resistance) and capacitance of the output capaci-
Kelvin sensing connection and R2 is the resistor con-
tor over the operating temperature.
nected from FB to GND. A bypass capacitor(C1) may be
Ultra-low-ESR capacitors (such as ceramic chip
connected with R1 in parallel to improve load transient
capacitors) and low-ESR bulk capacitors (such as solid
response and stability.
tantalum, POSCap, and Aluminum electrolytic capacitors)
can all be used as output capacitors.
During load transients, the output capacitors, depending
on the stepping amplitude and slew rate of load current,
are used to reduce the slew rate of the current seen by
the APL5934 and help the device to minimize the varia-
tions of output voltage for good transient response. For
the applications with large stepping load current, the low-
ESR bulk capacitors are normally recommended.
Decoupling ceramic capacitors must be placed at the
load and ground pins as close as possible and the im-
pedance of the layout must be minimized.

Input Capacitor
The APL5934 requires proper input capacitors to supply
current surge during stepping load transients to prevent
the input voltage rail from dropping. Because the para-
sitic inductor from the voltage sources or other bulk ca-
pacitors to the VIN pin limit the slew rate of the surge
currents, more parasitic inductance needs more input
capacitance. Ultra-low-ESR capacitors (such as ceramic
chip capaci- tors) and low-ESR bulk capacitors (such as
solid tantalum, POSCap, and Aluminum electrolytic
capacitors) can all be used as an input capacitor of VIN.
For most applications, the recommended input capaci-
tance of VIN is 10µF at least.

Copyright  ANPEC Electronics Corp. 15 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Layout Consideration
1. Please solder the Exposed Pad on the ground pad Thermal Consideration
on the top-layer of PCBs. The ground pad must have
Refer to the figure 2, the SOP-8P is a cost-effective pack-
wide size to conduct heat into the ambient air through age featuring a small size like a standard SOP-8 and a
the ground plane and PCB as a heat sink.
bottom exposed pad to minimize the thermal resistance
2. Please place the input capacitors for VIN and VCNTL of the package, being applicable to high current applica-
pins near the pins as close as possible for
tions. The exposed pad must be soldered to the top-layer
decoupling high-frequency ripples. VIN plane. The copper of the VIN plane on the Top layer
3. Ceramic decoupling capacitors for load must be
conducts heat into the PCB and ambient air. Please en-
placed near the load as close as possible for large the area of the top-layer pad and the VIN plane to
decoupling high-frequency ripples.
reduce the case-to-ambient resistance (θCA).
4. To place APL5934 and output capacitors near the
load reduces parasitic resistance and inductance 102 mil

for excellent load transient response.

5. The negative pins of the input and output capacitors 1 8
and the GND pin must be connected to the ground 2 7
plane of the load. 118 mil SOP-8P
3 6
6. Large current paths, shown by bold lines on the fig- 4 5
ure 1, must have wide tracks.
7. Place the R1, R2, and C1 near the APL5934 as close
Exposed Pad
as possible to avoid noise coupling. Top VOUT plane
Die Top ground
8. Connect the ground of the R2 to the GND pin by us- plane
ing a dedicated track.
Ambient
9. Connect the one pin of the R1 to the load for Kelvin Air
PCB
sensing.
10. Connect one pin of the C1 to the VOUT pin for reli-
able feedback compensation. Figure 2

Recommended Minimum Footprint

0.024
VCNTL
8 7 6 5
0.072

CCNTL
CIN
VCNTL
VIN VIN
APL5934 VOUT
0.138
0.212

0.118

VOUT

COUT
C1

FB
Load
GND R1
R2
1 2 3 4

0.050 Unit : Inch

Figure 1
SOP-8P

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Rev. A.7 - Oct., 2018
APL5934

Application Information (Cont.)

Recommanded Minimum Footprint (Cont.)

Layout

Package outline

0.06 Unit: Inch

0.04

1 10 0.011

2 9

0.1 3 8

4 7

5 6
0.011

0.06
0.029 The via diameter = 0.012
Hole size = 0.008
TDFN3x3-10

Thermal Via diameter

12mil X 5 Ground plane for Thermal PAD
0.222mm
0.572mm

0.241mm
1.295mm

0.508mm

0.8mm

TDFN2X2-8 Land Pattern Recommendation

Copyright  ANPEC Electronics Corp. 17 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Package Information
SOP-8P

SEE VIEW A

D1 E2

THERMAL
E1
PAD E

h X 45o

e b c
A2

0.25
A1

GAUGE PLANE
SEATING PLANE
L
θ

VIEW A

S SOP-8P
Y
M
B
MILLIMETERS INCHES
O
L MIN. MAX. MIN. MAX.
A 1.30 1.60 0.051 0.063

A1 0.00 0.15 0.000 0.006

A2 1.25 1.45 0.049 0.057

b 0.31 0.51 0.012 0.020
c 0.17 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
D1 2.50 3.50 0.098 0.138

E 5.80 6.20 0.228 0.244

E1 3.80 4.00 0.150 0.157
E2 2.00 3.00 0.079 0.118
e 1.27 BSC 0.050 BSC
h 0.25 0.50 0.010 0.020
L 0.40 1.27 0.016 0.050

0 0° 8° 0° 8°

0.10 0.004

Note : 1. Followed from JEDEC MS-012 BA.

2. Dimension "D" does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .
3. Dimension "E" does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 10 mil per side.

Copyright  ANPEC Electronics Corp. 18 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Package Information
TDFN3x3-10

D A

E
Pin 1

b
A1
D2
A3

Pin 1 Corner
E2
K
L

S TDFN3x3-10
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
A 0.70 0.80 0.028 0.031
A1 0.00 0.05 0.000 0.002
A3 0.20 REF 0.008 REF
b 0.18 0.30 0.007 0.012
D 2.90 3.10 0.114 0.122
D2 2.20 2.70 0.087 0.106
E 2.90 3.10 0.114 0.122
E2 1.40 1.75 0.055 0.069
e 0.50 BSC 0.020 BSC
L 0.30 0.50 0.012 0.020
K 0.20 0.008
Note : 1. Followed from JEDEC MO-229 VEED-5.

Copyright  ANPEC Electronics Corp. 19 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Carrier Tape & Reel Dimensions

OD0 P0 P2 P1 A

E1
F

W
B0

K0 A0 OD1 A
B B
SECTION A-A

T
SECTION B-B

d
H
A

T1

Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
SOP-8P P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.40±0.20 5.20±0.20 2.10±0.20
-0.00 -0.40
Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
TDFN3x3-10 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 3.30±0.20 3.30±0.20 1.30±0.20
-0.00 -0.40

(mm)

Devices Per Unit

Package Type Unit Quantity
SOP- 8P Tape & Reel 2500
TDFN-3x3-10 Tape & Reel 3000

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Rev. A.7 - Oct., 2018
APL5934

Taping Direction Information

SOP-8P

USER DIRECTION OF FEED

TDFN3x3-10

USER DIRECTION OF FEED

Copyright  ANPEC Electronics Corp. 21 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Classification Profile

Copyright  ANPEC Electronics Corp. 22 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly
Preheat & Soak
100 °C 150 °C
Temperature min (Tsmin)
150 °C 200 °C
Temperature max (Tsmax)
60-120 seconds 60-120 seconds
Time (Tsmin to Tsmax) (ts)

Average ramp-up rate

3 °C/second max. 3°C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
3 3
Package Volume mm Volume mm
Thickness <350 ≥350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
Thickness <350 350-2000 >2000
<1.6 mm 260 °C 260 °C 260 °C
1.6 mm – 2.5 mm 260 °C 250 °C 245 °C
≥2.5 mm 250 °C 245 °C 245 °C

Reliability Test Program

Test item Method Description
SOLDERABILITY JESD-22, B102 5 Sec, 245°C
HOLT JESD-22, A108 1000 Hrs, Bias @ 125°C
PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C
TCT JESD-22, A104 500 Cycles, -65°C~150°C
HBM MIL-STD-883-3015.7 VHBM≧2KV
MM JESD-22, A115 VMM≧200V
Latch-Up JESD 78 10ms, 1tr≧100mA

Copyright  ANPEC Electronics Corp. 23 www.anpec.com.tw

Rev. A.7 - Oct., 2018
APL5934

Customer Service

Anpec Electronics Corp.

Head Office :
No.6, Dusing 1st Road, SBIP,
Hsin-Chu, Taiwan, R.O.C.
Tel : 886-3-5642000
Fax : 886-3-5642050

Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
Tel : 886-2-2910-3838
Fax : 886-2-2917-3838

Copyright  ANPEC Electronics Corp. 24 www.anpec.com.tw

Rev. A.7 - Oct., 2018