electronics

Review
Design Architectures of the CMOS Power Amplifier
for 2.4 GHz ISM Band Applications: An Overview
Mohammad Arif Sobhan Bhuiyan 1, * , Md Torikul Islam Badal 2,3 , Mamun Bin Ibne Reaz 3 ,
Maria Liz Crespo 4 and Andres Cicuttin 4
1 Electrical and Electronics Engineering, Xiamen University Malaysia, Bandar Sunsuria, Sepang 43900,
Selangor, Malaysia
2 Electronic and Telecommunication Engineering, RMIT University, Melbourne, VIC 3000, Australia;
[email protected]
3 Electrical, Electronic and Systems Engineering, Universiti Kebangsaan Malaysia, Bangi 43600, Selangor,
Malaysia; [email protected]
4 International center for Theoretical Physics (ICTP), Via Beirut 31, 34100 Trieste, Italy;
[email protected] (M.L.C.); [email protected] (A.C.)
* Correspondence: [email protected]; Tel.: +60-182851-271




Received: 20 February 2019; Accepted: 1 April 2019; Published: 29 April 2019


Abstract: Power amplifiers (PAs) are among the most crucial functional blocks in the radio frequency
(RF) frontend for reliable wireless communication. PAs amplify and boost the input signal to the
required output power. The signal is amplified to make it sufficiently high for the transmitter to
propagate the required distance to the receiver. Attempted advancements of PA have focused on
attaining high-performance RF signals for transmitters. Such PAs are expected to require low power
consumption while producing a relatively high output power with a high efficiency. However,
current PA designs in nanometer and micrometer complementary metal–oxide semiconductor
(CMOS) technology present inevitable drawbacks, such as oxide breakdown and hot electron effect.
A well-defined architecture, including a linear and simple functional block synthesis, is critical in
designing CMOS PA for various applications. This article describes the different state-of-the art
design architectures of CMOS PA, including their circuit operations, and analyzes the performance of
PAs for 2.4 GHz ISM (industrial, scientific, and medical) band applications.

Keywords: CMOS; ISM band; PA; transmitter; WSN

1. Introduction
At present, wireless communication systems are experiencing a rapid growth because of
the advancement of complementary metal–oxide semiconductor (CMOS) technology [1,2] which
provides more advantages over Gallium Arsenide (GaAs) and Gallium Nitride (GaN) technologies.
CMOS technology enables operation at a lower power supply, resulting in a reduced power dissipation
in the circuit [3,4] and a minimized fabrication cost because of the compact chip size. CMOS offers
the prospect of integrating radiofrequency (RF)/digital/analog functions on a single chip in a low-cost
manner [5–7]. The CMOS power amplifier (PA) is a promising solution for modern wireless devices
to satisfy the demand of a low-power and low-cost design. Over the years, CMOS PA has been
widely used in various wireless communication applications, including home automation, Radio
Frequency Identification (RFID), industrial consumer electronics, TV transmissions, phones, and
medical instruments [8–10]. It has been integrated in high-frequency medical ultrasonic applications to
amplify high-voltage excitation signals to activate ultrasonic transducers, because ultrasonic imaging
requires a higher contrast resolution, which can be produced by a highly linear PA [4].

Electronics 2019, 8, 477; doi:10.3390/electronics8050477 www.mdpi.com/journal/electronics

Electronics 2019, 8, x FOR PEER REVIEW 2 of 21

transducers, because ultrasonic imaging requires a higher contrast resolution, which can be produced
Electronics
by a highly 2019,linear
8, x FOR
PAPEER
[4].REVIEW 2 of 21
The2019,
Electronics PA is the key component of RF transmitters. An RF transmitter is composed of functional
8, 477 2 of 21
transducers,
blocks, such because ultrasonic imaging
as a digital-to-analog requires
converter (DAC),a higher contrast resolution,
an up-conversion mixer, which can be produced
an oscillator, a PA, and
by a highly
a band passlinear PA [4].[11–13], as shown in Figure 1. Among all of these modules, the PA is the most
filter (BPF),
vital The
The
blockPA is the key
PAbecause component ofsignificantly
its performance RF transmitters. An
Anthe
affects RF transmitter
RFoverall
transmitter is
is composed
performance composed
of theof functional
oftransmitter
functional
blocks,
blocks, such
such asasa digital-to-analog
a digital-to-analog converter
converter (DAC),
(DAC),an up-conversion
an up-conversion
[14–16]. The PA can be defined as an electronic amplifier that converts a low-power RF signal mixer, an
mixer, oscillator,
an a PA,into
oscillator, aand
PA,a
ahigh-power
band pass
and a band RF filter (BPF),
passsignal [11–13],
filter [1].
(BPF), as shown
[11–13], as in Figure
shown in1. Among
Figure 1.all of
Amongthese modules,
all of these
The PA receives the RF signal from the mixer and then sends it to the the PA
modules,is the most
the PA
vital
is theblock
antenna most because
vital
after its performance
block
amplifying because significantly
its performance
and passing affects
it throughsignificantlythe pass
the band overall
affects performance
the[17–19].
filter overallIn ofaddition,
the transmitter
performance theof PA
the
[14–16]. The PA can be defined as an electronic amplifier that converts a
reduces the voltage swing to obtain a higher output power according to the system’s requirement.RF
transmitter [14–16]. The PA can be defined as an electronic amplifier thatlow-power
converts RF
a signal
low-power into a
high-power
signal into a RF signal [1].RFThe
high-power PA[1].
signal receives
The PA the RF signal
receives the RFfrom the from
signal mixerthe and thenand
mixer sends
thenitsends
to theit
antenna after amplifying
to the antenna after amplifyingand passing it through
and passing the the
it through band pass
band filter
pass [17–19].
filter [17–19]. InInaddition,
addition,the thePA PA
reduces the voltage swing to obtain
reduces the voltage swing to obtain a higher a higher output power according to the system’s requirement.

Figure 1. Basic block diagram of radio frequency (RF) transmitter.

Figure 2 describes the 1.

Figure basic block
Basic blockdiagram
diagram of radio
the CMOS PA.(RF)
frequency Thetransmitter.
block diagram consists of two
main stages, namely, Figure
the 1. Basic block
driver diagramstages.
and power of radioBoth
frequency (RF)
stages transmitter.
are biased with individual bias
Figure 2 describes the basic block diagram of the CMOS PA.
voltages. Different configurations are applied to the driver and power stages The block diagram consiststhe
to operate of two
PA
main Figure
stages,2 describes
namely, the
the basic
driver block
and diagram
power of
stages. the
Both CMOS
stages PA.
are The
biased block
with
properly [20–23]. Input and output matching networks are used to minimize the return losses diagram consists
individual bias of two
voltages.
to
main
obtainstages,
Different
a high namely,
gain andthe
configurations aredriver
applied
output and
power. power
to the stages.
driver
However, and Both stages
power
inter-stage are
to
matching biased
operate with
is alsothe individual
PA properly
required between bias
[20–23].
the
voltages.
andDifferent
Input and
driver output configurations
power matching
stages. networks areare
applied
used totominimize
the drivertheand power
return lossesstages to operate
to obtain the and
a high gain PA
properly [20–23].
output power. Input and
However, output matching isnetworks
inter-stage are used
also required to minimize
between the driverthe return
and power losses to
stages.
obtain a high gain and output power. However, inter-stage matching is also required between the
driver and power stages.

Figure 2. Block diagram of complementary metal–oxide semiconductor (CMOS) power amplifier

(PA) [20].
Figure 2. Block diagram of complementary metal–oxide semiconductor (CMOS) power amplifier
(PA) [20].
In the past decade, different PA design architectures have been proposed to achieve the desired
performances. These architectures suffer from high power consumption, nonlinearity, circuit complexity,
InFigure 2. Block
the past diagram
decade, of complementary
different metal–oxide semiconductor
PA design architectures (CMOS)to
have been proposed power amplifier
achieve the desired
low output power, low gain, and low efficiency. Thus, a high-performance PA must urgently be
performances. These architectures suffer from (PA) [20].
high power consumption, nonlinearity, circuit
designed to satisfy the rising demands for ISM band applications. This article is aimed to evaluate the
complexity, low output power, low gain, and low efficiency. Thus, a high-performance PA must
various aspects
In the of the designs andPA performances of PA forhave
2.4 GHz ISM band applications anddesired
review
urgently bepast decade,
designed to different
satisfy the design
rising architectures
demands for ISM band been proposed
applications. to achieve
This articlethe
is aimed to
their recent
performances.advances in terms
These architecturesof key performance parameters. This comparative study is expected to
evaluate the various aspects of thesuffer from
designs andhigh power consumption,
performances of PA for nonlinearity,
2.4 GHz ISMcircuitband
guide future works
complexity, on 2.4 GHz RF devices.
applications low
andoutput
reviewpower,
their low gain,
recent and lowinefficiency.
advances terms of Thus, a high-performance
key performance parameters.PA must
This
urgently be
comparative designed
study to satisfy the rising demands for ISM band applications.
is expected to guide future works on 2.4 GHz RF devices. This article is aimed to
2. Performance Parameters
evaluate the various aspects of the designs and performances of PA for 2.4 GHz ISM band
The performance
applications
2. PerformanceandParameters
reviewof CMOS
their PA was advances
recent evaluated in
in terms
termsofofseveral parameters. The
key performance most important
parameters. This
aspects of a study
comparative PA design are output
is expected power,
to guide power
future works consumption,
on 2.4 GHz RF power gain, linearity, and power
devices.
added efficiency (PAE). Inevitable trade-offs exist among these factors, and these trade-offs make PA
design
2. challenging
Performance at CMOS downscaling. The key factors for assessing transmitter performance were
Parameters
determined as follows:
Electronics 2019, 8, 477 3 of 21

2.1. Output Power

Output power (Pout ) refers to the amount of power that must be delivered to the load (antenna) [24]
and is considered the most important aspect of a PA design [25]. Power gain and efficiency have a
trade-off with output power. To generate output power, the energy supply in the device should exceed
the required output power because some power dissipates as heat [25]. When the supply voltage has
a constant value, the amount of current is critical in obtaining the output power. The output power
is proportional to the efficiency of the PA and therefore, determines the performance of the PA. It is
expressed in dBm by Equation (1) as follows:

Vout 2
Pout = (1)
2RL

where Vout is the output voltage, and RL is the resistance load.

2.2. Power Consumption

Power consumption is another important performance parameter of a PA. The increasing demand
for portable operation must be addressed without consuming excessive power to ensure the maximum
run time of the device. The total power consumption (PTotal ) of a PA is the sum of the dynamic and
static power consumption, as shown in Equation (2). Static power consumption (PS ) results from the
leakage current (ICC), whereas dynamic power consumption (PD ) occurs when switching at high
frequency [26]. Equations (3) and (4) show the derivation of the static and dynamic power consumption,
respectively. Static power significantly affects the overall power consumption. A reduction in power
consumption generates less heat in the device. Consequently, the temperature stress on the device will
decrease, and the reliability of the system will be increased. High power consumption reduces the
lifetime of PAs. Thus, PAs should be designed such that power consumption is minimized for a longer
battery life.
PTotal = PS + PD (2)

PS = VDD × ICC (3)

h  X i
PD = Cpd × fI × NSW + (CLn × fOn ) × VDD 2 (4)

where Cpd is the capacitance of the power consumption (F), fI is the input frequency (Hz), fOn is the
sum of different output frequencies at each output (Hz), NSW is the total number of outputs switching,
VDD is the supply voltage (V), and CLn is the sum of different load capacitances at each output.

2.3. Power Gain

Power gain (G) is the ratio of the output and input power, as expressed in Equation (5).
This parameter describes how well the power amplifier can deliver a significantly higher power signal
to the load compared to the input power [24]. The gain indicates the extent of the increase in the
amplitude of a signal. A power amplifier enhances the output power to provide improved efficiency
and sensitivity [25].
G = 10 log10 (Pout /Pin ) [dB] (5)

where Pout is the output power, and Pin is the input power.

2.4. Efficiency
The efficiency of the PA can be classified into two categories, namely drain efficiency (DE) and
power-added efficiency (PAE). DE is the ratio of the RF output power to the DC power dissipation, as
described in Equation (6) [27]. PAE is defined as the output power gained subtracted by the input power
and then divided by the DC power dissipation, as shown in Equation (7) [24]. PAE evaluates how
Electronics 2019, 8, 477 4 of 21

efficiently the PA converts the DC power into AC power signal when the input power is considered [12].
High output power leads to high PAE.

DE= Pout /P(DC,drain) (6)

PAE= (Pout − Pin )/P(DC,drain) (7)

2.5. Linearity
Linearity is defined as the scenario in which the output of the device varies linearly with
respect to the variations of the input [28]. Linearity has become increasingly important in current RF
communication structures. In general, the value of the third-order intercept point (IP3) determines the
linearity. The intercept point is obtained by plotting the graph of the output power with respect to the
input power on a logarithmic scale [28]. A high linearity means that the output power gained is linear
to the input power [25].
Therefore, to satisfy the current demand, PAs should be designed to have low power consumption,
high output power, high power gain, high PAE, and high linearity. The output power delivered by a
PA and PAE play important roles in the design of an efficient power amplifier.

3. PA Design Classes
PA can be classified based on the power classes of A, B, C, D, E, F, AB, and so on [29]. Power classes
are classified based on the types of bias applied to the RF transistors. Classes A, B, and AB are labeled as
linear amplifiers, whereas classes C, D, E, and F are categorized as non-linear amplifiers [12]. For linear
amplifiers, a class-A amplifier is biased such that the output device of the amplifier conducts 360◦
throughout the full cycle and as a consequence, the power loss is also increased which in turn leads to
have less efficiency [14]. By contrast, the class-B amplifier is operated similarly to the class-A amplifier,
but its output device conducts only a half (i.e., 180◦ ) of the sinusoidal cycle (either a positive or a
negative cycle [15]. Therefore, the power loss is decreased, and the efficiency is improved compared
with its class-A counterpart. On the other hand, the class-AB amplifier is the combination of class-A
and class-B amplifiers, in which both amplifiers can be on at the same time for a very short time [12]
and thus improves the efficiency further.
For non-linear amplifiers, the class-C amplifier, conducts less than a half cycle, and experiences
higher distortion and noise effects [30]. Although the efficiency of class-C PA is good, it suffers from
poor dynamic range. The class-D amplifier, which is also known as the switching amplifier, has a low
power loss because the active devices are kept either fully on or fully off [31]. The class-E amplifier is
preferred for the design of RF PAs because class E has a higher theoretical efficiency than classes D and
F [12]. The class-F amplifier operates in a unique manner by implementing the output network such
that the drain voltage and current do not overlap with each other [32]. Aside from the classes in PA, an
accurate architecture of PA must be selected to design an application-specific CMOS PA.

4. Advancement of 2.4 GHz CMOS PA

The PA design has emerged rapidly and has become more advanced. The rapid growth of
2.4 GHz ISM band devices demands a low-cost and low-power consumption solution. Although
considerable achievements have been attained in CMOS, realizing this goal remains challenging for
system-on-chip designers. The literature review shows that few design architectures are available for
PAs, such as general cascode, self-biased cascode, differential cascode, and power-combining technique.
The advancement of CMOS PAs operating at 2.4 GHz frequency are described in this study in terms of
circuit architecture and performance point of view.
Electronics 2019, 8, x FOR PEER REVIEW 5 of 21

technique. The advancement of CMOS PAs operating at 2.4 GHz frequency are described in this
study in terms of circuit architecture and performance point of view.
Electronics 2019, 8, 477 5 of 21
4.1. General Cascode Architecture
4.1. General Cascode
In the PA Architecture
design in CMOS technology, two main issues must be addressed: Oxide breakdown
and the hot carrier effect [16]. The gate-oxide breakdown is caused by a high voltage drop across the
In the PA design in CMOS technology, two main issues must be addressed: Oxide breakdown and
gate oxide, which results in an irreversible shortage of gate-to-channel capacitance. The oxide
the hot carrier effect [16]. The gate-oxide breakdown is caused by a high voltage drop across the gate
breakdown degrades the performance and the efficiency of the PA. Hot carrier effect refers to the
oxide, which results in an irreversible shortage of gate-to-channel capacitance. The oxide breakdown
acceleration of an electron by a high electric field in the MOS device, which generates a high kinetic
degrades the performance and the efficiency of the PA. Hot carrier effect refers to the acceleration
energy [4]. This effect increases the threshold voltage and degrades the performance of the device.
of an electron by a high electric field in the MOS device, which generates a high kinetic energy [4].
To overcome these problems, the general cascode circuit configuration was introduced in the PA
This effect increases the threshold voltage and degrades the performance of the device. To overcome
design [17].
these problems, the general cascode circuit configuration was introduced in the PA design [17].
Ding and Harjani (2005) proposed a general cascode parallel class-AB CMOS PA by integrating
Ding and Harjani (2005) proposed a general cascode parallel class-AB CMOS PA by integrating a
a linear power control technique, as shown in Figure 3 [33]. In this design, two amplifiers operate in
linear power control technique, as shown in Figure 3 [33]. In this design, two amplifiers operate in
parallel to improve the dynamic range and power efficiency. The input transistor M1 was biased with
parallel to improve the dynamic range and power efficiency. The input transistor M1 was biased with
a fixed voltage of 1.2 V. The cascode configuration was formed by the CS transistors M1, M2, M3, and
a fixed voltage of 1.2 V. The cascode configuration was formed by the CS transistors M1, M2, M3, and
M4, and the CG transistors M5 and M6. The CS transistors form the transconductance of the class-A
M4, and the CG transistors M5 and M6. The CS transistors form the transconductance of the class-A
and the class-B PAs in order to provide more linear transconductance, which led to high power gain
and the class-B PAs in order to provide more linear transconductance, which led to high power gain of
of 12 dB. At low input levels, the class-A amplifier contributed the majority of the gain, and the class
12 dB. At low input levels, the class-A amplifier contributed the majority of the gain, and the class B
B amplifier had a very low gain. As the input level increased, the gain of the class- B amplifier
amplifier had a very low gain. As the input level increased, the gain of the class- B amplifier increased,
increased, and its contribution to the overall gain increased proportionately. The outputs from both
and its contribution to the overall gain increased proportionately. The outputs from both amplifiers
amplifiers were combined in the current domain with a slight overhead, thereby producing an
were combined in the current domain with a slight overhead, thereby producing an improved isolation
improved isolation property and high power efficiency of 44%. AC coupling capacitors and the
property and high power efficiency of 44%. AC coupling capacitors and the matching network were
matching network were used for the output impedance matching [33].
used for the output impedance matching [33].

Figure 3. Circuit
Figure 3. Circuit schematic
schematic for
for the
the CMOS
CMOS parallel
parallel class-AB
class-AB amplifier
amplifier [33].
[33].

Saari et al. (2005) proposed an integrated cascode class-E PA (Figure 4) [34]. A cascode transistor
Saari et al. (2005) proposed an integrated cascode class-E PA (Figure 4) [34]. A cascode transistor
M2 was inserted at the drive stage to increase the output power (21.3 dB) and stability. The switch
M2 was inserted at the drive stage to increase the output power (21.3 dB) and stability. The switch
on-resistance was minimized by integrating the transistor M3 as a switch. Both the driver and power
on-resistance was minimized by integrating the transistor M3 as a switch. Both the driver and power
stages were biased with NMOS current mirrors to prevent bias oscillations. The proposed design
stages were biased with NMOS current mirrors to prevent bias oscillations. The proposed design
achieved a gain of up to 14.3 dB and a 40% PAE with a 3.3 V supply voltage. The input high-pass LC
achieved a gain of up to 14.3 dB and a 40% PAE with a 3.3 V supply voltage. The input high-pass LC
network degraded the gain performance. The source inductance LB4 reduced the gain by inducing
network degraded the gain performance. The source inductance LB4 reduced the gain by inducing
the negative feedback. Although the gain was reduced, the overall stability of the proposed design
was improved.
Electronics 2019,
Electronics 2019,8,
8,xxFOR
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REVIEW 66 of
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the negative
the negative feedback.
feedback. Although
Although the
the gain
gain was
was reduced,
reduced, the
the overall
overall stability
stability of
of the
the proposed
proposed design
design
Electronics 2019, 8, 477 6 of 21
was improved.
was improved.

Figure 4.
Figure
Figure 4. Schematic
4. Schematic of
of aa two-stage
two-stage class-E PA [34].
class-E PA
PA [34].

Sira et
Sira et
Sira al.
et al.
al. (2011) presented aa cascode
(2011) presented cascode modulated
modulated class-E class-E PA PA that used
PA that used 0.13
0.13 µm CMOS technology
µm CMOS technology
(Figure 5)
(Figure 5)
(Figure [35].
5) [35]. In
[35]. In this
In this design,
this design,
design, thethe transistor
the transistor
transistor M3 M3 was
M3 was cascoded
was cascoded
cascoded with with the
with the transistor
the transistor
transistor M2, M2, and
M2, and the
and the power
the power
power
control
control signal
signal was
was utilized
utilized at
at the
the gate
gate of
of the
the transistor
transistor M3.
M3. The
The
control signal was utilized at the gate of the transistor M3. The Vcasc dictated whether the cascodeVcasc
Vcasc dictated
dictated whether
whether the
the cascode
cascode
transistor
transistor M3
transistor M3 operated
M3 operated
operated in in the
in the saturation
the saturation
saturation or or linear
or linear region.
linear region.
region. If If the
the Vcasc
Vcasc value
value increased
increased from
from zero,
from zero, then
zero, then
then
M3 operated
M3 operated
M3 operated in in the
in the saturation
the saturation region.
saturation region.
region. If If the
the Vcasc
Vcasc was was further
further increased
increased to to 1.3
1.3 V,
V, then
V, then M3
then M3 entered
M3 entered
entered the the
the
linear
linear region.
region. The advantages
advantages of this proposed
proposed cascode
cascode modulated
modulated
linear region. The advantages of this proposed cascode modulated design are the 35-dB output power design
design are
are the
the 35-dB
35-dB output
output power
power
dynamic range.
dynamic range.
dynamic range. The The power
power dynamic
dynamic range range refers
refers to to the
the maximum
maximum range range over
over which
which thethe PA
PA average
PA average
average
output
output power
power can
can be
be controlled.
controlled. This design obtained approximately
output power can be controlled. This design obtained approximately 35% PAE and a 14.8 dB 35% PAE and a
a 14.8
14.8 dB
dB gain
gain
gain
with
with aa supply
supply voltage
voltage of
of 1.6
1.6 V
V and
and aachip
chip area
area of
of only
only 1.2
1.2 mm
mm ×× 1.0
1.0
with a supply voltage of 1.6 V and a chip area of only 1.2 mm × 1.0 mm. This design had a low output mm.
mm. This design had
had a low output
output
power
powerof
power of18
of 18dBm,
18 dBm,which
dBm, whichwas
which waslimited
was limitedby
limited by
by the the
the input
input
input power
power
power feed-through
feed-through
feed-through to to
the PAPA
to the
the output
PA because
output
output of the
because
because of
of
Miller
the capacitance
Miller capacitance between
betweenthe gate
the and
gate drain
and of
drain theofswitching
the switching transistor.
the Miller capacitance between the gate and drain of the switching transistor. The feed-through effect The
transistor. feed-through
The feed-througheffect was
effect
significant
was at low
was significant
significant atVcasc
at low levels,levels,
low Vcasc
Vcasc at which
levels, at the cascode
at which
which transistor
the cascode
the cascode was inwas
transistor
transistor saturation.
was At high
in saturation.
in saturation. AtVcasc
At high levels,
high Vcasc
Vcasc
M3 wasM3
levels,
levels, in was
M3 the
waslinear
in theregion,
in the but it did
linear region,
linear region, butnot
but affect
itit did
did notthe
not dynamic
affect
affect range. range.
the dynamic
the dynamic range.

Figure 5. Cascode-modulated CMOS PA [35].

 Electronics 2019, 8, x FOR PEER REVIEW 7 of 21
Electronics 2019, 8, 477 7 of 21
Figure 5. Cascode-modulated CMOS PA [35].

Bameri
Bamerietetal. al. (2011)
(2011) proposed
proposedanother
anothergeneral
generalcascode
cascodeclass-E
class-EPA
PAthat
thatutilized
utilizedananadvanced
advancedlinear
linear
power control technique, as shown in Figure 6 [16]. The gate voltage of the
power control technique, as shown in Figure 6 [16]. The gate voltage of the transistor M4 transistor M4was
was used
used to
to control
control thethe voltage
voltage of of
thethe output
output power.
power. TheThe significant
significant improvement
improvement offered
offered by by
thisthis design
design waswasthe
the wide
wide powerpower control
control rangerange of 155
of 155 dB from −136−136
dB from dBmdBmto +19 +19 dBm.
to dBm. However,
However, this design
this design suffered
suffered from
from a low output power because the output power was reduced as the control
a low output power because the output power was reduced as the control voltage was decreased. voltage was decreased.
The
The reduced
reducedoutputoutput power
power operates the PA
operates thefrom
PA afrom
switching mode tomode
a switching a linear
tomode, thereby
a linear producing
mode, thereby
aproducing
higher slope a higher slope of AM-AM characteristic for the cascode power control technique. control
of AM-AM characteristic for the cascode power control technique. At high At high
voltage
controllevels,
voltage the driver
levels, output
the driverpower
output also increased.
power An increase
also increased. An in the driver
increase output
in the driverpower reduced
output power
the Ron, thereby increasing its PAE and gain.
reduced the Ron, thereby increasing its PAE and gain.

Figure6.6. Linear
Figure Linear power
powercontrol
controlcascode
cascodePA
PAcircuit
circuit[16].
[16].

Sahu
Sahuand
andDeshmukh
Deshmukh (2013)(2013) introduced
introduced another
another PAPA that
that was
was operated
operated with
with aa 2.5
2.5 VV supply,
supply,asas
depicted
depictedininFigure
Figure7 [20].
7 [20].InIn
this PA,PA,
this thethe
driver stage
driver usedused
stage the cascode topology,
the cascode whereas
topology, the power
whereas stage
the power
utilized the basic
stage utilized thepower topology.
basic power Two types
topology. Twooftypes
bias circuits were tested
of bias circuits wereintested
this circuit.
in this Both theBoth
circuit. driver
the
stage
driverand the power
stage and the stage used stage
power the Metal
usedOxide Semiconductor
the Metal Field Effect Transistor
Oxide Semiconductor (MOSFET)-only
Field Effect Transistor
bias in order to reduce
(MOSFET)-only bias intotal
orderDCtocurrent
reduceup to 0.0901
total A. Theup
DC current input and output
to 0.0901 A. The matching
input and networks
output
reduced the input and output return losses, resulting in a low power consumption
matching networks reduced the input and output return losses, resulting in a low power of 0.2253 W and a
high PAE of 44.67%
consumption for aW1 and
of 0.2253 dB compression
a high PAE of point.
44.67% for a 1 dB compression point.
Cai et al. (2016) reported a class-D PA for medical applications in 0.18 µm CMOS technology [31].
The PA was designed with two active switches. The switches are alternatively turned on and off
depending on the driver stage output signal. A LC band pass filter was also utilized to control the
frequency of operation which exhibits the advantage of no power dissipation for out of band signal.
At 2.4 GHz, the PA reported less than −10 dB S11 to transmit a maximum of 15 dBm output power to a
50 Ω load with 50% PAE.
However, the cascode configuration experienced additional power losses. In practical cases, two
cascode devices cannot be switched on or off simultaneously. Thus, a greater power loss is always
present between them, which diminishes the efficiency performance of the PA [27].
Electronics 2019,8,8,477
Electronics2019, x FOR PEER REVIEW 88 of
of 21
21

Figure7.7. Schematic
Figure Schematic of
oftwo-stage
two-stageCMOS
CMOSPA
PA[20].
[20].

4.2. Self-Biased
Cai et al. Cascode Architecture
(2016) reported a class-D PA for medical applications in 0.18 µm CMOS technology
[31].For
Thethe
PAgeneral
was designed with two active
cascode topology, the switches.
breakdown The switches
voltage are alternatively
of the common gateturned on and off
(CG) transistor
depending
limits on the
the supply driverofstage
voltage output
a design. signal.
Thus, A LC band
a self-biased pass filter
technique wasan
allows also
RF utilized
signal totoswing
control the
at the
frequency
CG of operation
to increase the biasingwhich exhibits
voltage abovethe
VDDadvantage of no power
. The maximum drain dissipation for out is
to the gate voltage ofthe
bandsamesignal.
for
At 2.4
both GHz, the
cascode PA reported
transistors. lesssignal
A larger than −10 dB S
swing 11 to
can betransmit
delivereda maximum
at the outputof 15 dBmoxide
before output power to
breakdown
a 50 Ω load
occurs. with 50%this
By applying PAE.technique, the gate of the NMOS was boosted above VDD , and the power
However, the cascode
consumption was minimized configuration
[36]. experienced additional power losses. In practical cases, two
cascode devices cannot be switched on
The design presented in Figure 8 proposed or off simultaneously.
by Sowlati and Thus, a greater(2003)
Leenaerts powerisloss
theisfirst
always
PA
present
that can between
operate at them,
2.4 Vwhich
withoutdiminishes the efficiency
oxide breakdown performance
or hot of the PA [27].
carrier degradation [17]. The self-biased
cascode topology was applied at both driver and power stages to swing the RF signal at gate of
4.2. Self-Biased
M2. Cascode
An additional Architecture
bond pad was not required to connect through gate of M2, as the bias at this
point For
wasthe
provided by Rb–Cb network. Both
general cascode topology, gate and drain
the breakdown of M2
voltage of operated
the common at the same
gate DCtransistor
(CG) voltage.
Bias
limitsvoltages of 0.55
the supply and 0.8
voltage ofVa were
design.used for the
Thus, gates of thetechnique
a self-biased driver and power
allows anstages. The to
RF signal simulation
swing at
results
the CG to increase the biasing voltage above VDD. The maximum drain to the gate voltage is the31same
revealed that the proposed design provided a 24.5 dBm output power for a gain of dB
by
forutilizing the sliding
both cascode bias technique.
transistors. A largerThis technique
signal swing can is a de-biasing
be delivered technique appliedbefore
at the output at lowoxide
and
intermediate power levels to obtain the same gain as that at maximum power.
breakdown occurs. By applying this technique, the gate of the NMOS was boosted above VDD, and The gain variation was
reduced
the power by consumption
applying the sliding bias technique.
was minimized [36].
Murad et al. presented
The design (2009) designed a 0.18
in Figure 8 µm single-ended
proposed by Sowlaticlass-E
andPALeenaerts
for WLAN applications,
(2003) asPA
is the first shown
that
in Figure 9 [37]. In this design, the bias for CS gate is provided by R3 and C3,
can operate at 2.4 V without oxide breakdown or hot carrier degradation [17]. The self-biased cascode for which no extra
bond pad is
topology wasrequired.
appliedThe dc voltage
at both driverapplied
and powerto the CS gate
stages is the same
to swing the RFas signal
that applied
at gatetoofCSM2.drain.
An
As shown in
additional bondFigure
pad9,wasall inductors
not requiredweretoreplaced with bond
connect through wire
gate of inductors
M2, as thetobiasincrease
at thisthe quality
point was
factor (Q) and
provided by to minimize
Rb–Cb losses.Both
network. The high
gate Qandcontributed
drain of to M2obtaining
operateda higher
at the PAE.
sameThe DCdesign used
voltage. 2-
Bias
and 5-mmof
voltages bond
0.55wires,
and 0.8which wereused
V were equivalent
for thetogates
2.0 and 4.1 nH,
of the respectively.
driver and power This PA design
stages. achieved
The simulation
aresults
44.5% revealed
PAE and that
a 23 the
dBm output power
proposed designdelivered
provided with
a 24.5a dBm
supply voltage
output of 3.3
power forVa[37].
gainAlthough
of 31 dB byit
had a high PAE, a significantly high supply voltage was needed to operate
utilizing the sliding bias technique. This technique is a de-biasing technique applied at low andit. However, this work
adopted a class-E
intermediate powerPA levels
with atocascode topology,
obtain the which
same gain as reduced the stresspower.
that at maximum on the device
The gain due to the high
variation was
supply voltage.
reduced by applying the sliding bias technique.
Electronics 2019, 8, 477 9 of 21
Electronics 2019, 8, x FOR PEER REVIEW 9 of 21

Figure 8. Two-stage self-biased cascode PA [17].

Murad et al. (2009) designed a 0.18 µm single-ended class-E PA for WLAN applications, as
shown in Figure 9 [37]. In this design, the bias for CS gate is provided by R3 and C3, for which no
extra bond pad is required. The dc voltage applied to the CS gate is the same as that applied to CS
drain. As shown in Figure 9, all inductors were replaced with bond wire inductors to increase the
quality factor (Q) and to minimize losses. The high Q contributed to obtaining a higher PAE. The
design used 2- and 5-mm bond wires, which were equivalent to 2.0 and 4.1 nH, respectively. This PA
design achieved a 44.5% PAE and a 23 dBm output power delivered with a supply voltage of 3.3 V
[37]. Although it had a high PAE, a significantly high supply voltage was needed to operate it.
However, this work adopted a class-ETwo-stage
PA with a cascode topology, [17].
which reduced the stress on the
Figure 8. Two-stage self-biased cascode PA
PA [17].
device due to the high supply voltage.
Murad et al. (2009) designed a 0.18 µm single-ended class-E PA for WLAN applications, as
shown in Figure 9 [37]. In this design, the bias for CS gate is provided by R3 and C3, for which no
extra bond pad is required. The dc voltage applied to the CS gate is the same as that applied to CS
drain. As shown in Figure 9, all inductors were replaced with bond wire inductors to increase the
quality factor (Q) and to minimize losses. The high Q contributed to obtaining a higher PAE. The
design used 2- and 5-mm bond wires, which were equivalent to 2.0 and 4.1 nH, respectively. This PA
design achieved a 44.5% PAE and a 23 dBm output power delivered with a supply voltage of 3.3 V
[37]. Although it had a high PAE, a significantly high supply voltage was needed to operate it.
However, this work adopted a class-E PA with a cascode topology, which reduced the stress on the
device due to the high supply voltage.

Figure
Figure 9.
9. Schematic of class-E self-biased cascode PA [37].

Hong et etal.
al.(2010)
(2010)introduced
introduced a new self-biased
a new cascode
self-biased PA design
cascode with a capacitive
PA design cross-coupling
with a capacitive cross-
technique,technique,
coupling as shown as in Figure
shown 10
in [38]. The
Figure 10first
[38].amplifier
The firststage employed
amplifier stage aemployed
general cascode class-A
a general PA,
cascode
class-A PA,
whereas whereasstage
the second the implemented
second stage aimplemented a self-biased
self-biased cascode class-ABcascode class-AB
PA. Given PA. Given
that thick that
gate-oxide
transistors were used, the large size of the transistors resulted in a large gate-drain capacitance.
Capacitive cross-coupling was implemented to decrease the gate-drain capacitance and the layout
area of the bypass capacitance. Thus, the PA covered a small chip area of 1.0 mm × 1.6 mm and
improved the reverse isolation. A transformer was integrated at the output to improve the output
power. The transformer had a turn ratio of 2:1, which reduced the output impedance from 50 Ω to
12.5 Ω. At a supply voltage of 3.3 V, the PA achieved a 34.3% maximum PAE, a 25.2 dBm output
Figure 9. Schematic of class-E self-biased cascode PA [37].
power, and a 26.5 dB power gain [38].
Hong et al. (2010) introduced a new self-biased cascode PA design with a capacitive cross-
coupling technique, as shown in Figure 10 [38]. The first amplifier stage employed a general cascode
class-A PA, whereas the second stage implemented a self-biased cascode class-AB PA. Given that
capacitance. Capacitive cross-coupling was implemented to decrease the gate-drain capacitance and
the layout area of the bypass capacitance. Thus, the PA covered a small chip area of 1.0 mm × 1.6 mm
and improved the reverse isolation. A transformer was integrated at the output to improve the output
power. The transformer had a turn ratio of 2:1, which reduced the output impedance from 50 Ω to
12.5 Ω. At
Electronics a 8,supply
2019, 477 voltage of 3.3 V, the PA achieved a 34.3% maximum PAE, a 25.2 dBm output
10 of 21
power, and a 26.5 dB power gain [38].

Figure 10. Schematic of proposed

Figure 10. proposed capacitive-cross-coupled
capacitive-cross-coupled CMOS
CMOS PA
PA[38].
[38].

The
The objective
objective of
of the
the self-biased
self-biased cascode
cascode architecture
architecture was
was to
to provide
provide aa circuit
circuit that
that did
did not
not require
require
external
external bias supplies to minimize the use of resistor networks. Operational flexibility can be achieved
bias supplies to minimize the use of resistor networks. Operational flexibility can be achieved
by
by not
not providing
providing aa bias
bias voltage
voltage directly
directly from
from the
the power
power supply.
supply. Consequently,
Consequently, aa simple,
simple, compact,
compact,
efficient, and economical circuit was formed [39]. This design eliminated the requirement
efficient, and economical circuit was formed [39]. This design eliminated the requirement of of additional
bond pads and
additional bondovercame
pads andthe device stress.
overcame the device stress.

4.3.
4.3. Differential
Differential Cascode
Cascode Architecture
Architecture
Differential
Differentialcascode
cascodetopology
topologyisismainly
mainlycomposed
composedof ofCG
CGand andCS
CSamplifiers
amplifiers[40].
[40]. The
The differential
differential
configuration
configuration minimizes the common mode noise and the substrate coupling. Compared with
minimizes the common mode noise and the substrate coupling. Compared with other
other
designs,
designs, this architecture presents less impedance matching losses. In addition, the problem of
this architecture presents less impedance matching losses. In addition, the problem of low
low
breakdown voltage can easily be overcome by implementing this
breakdown voltage can easily be overcome by implementing this architecture. architecture.
Ho
Ho and
and Luong (2003) introduced
Luong (2003) introducedaadifferential
differentialclass-E
class-EPA PAwith
witha alow
low supply
supply voltage
voltage of of 1 V,
1 V, as
as shown in Figure 11 [41]. This architecture displayed a large capacitive
shown in Figure 11 [41]. This architecture displayed a large capacitive loading when it used loading when it used
millimeter-size transistors because
millimeter-size transistors becauseofofthethelow
lowsupply
supply voltage.
voltage. ThisThis issue
issue waswassolvedsolved by utilizing
by utilizing bond
bond
wire inductor and a cross-coupled pair. By doing so, a positive feedback was formed for
wire inductor and a cross-coupled pair. By doing so, a positive feedback was formed for the
the
preamplifier.
preamplifier. TheThe positive
positive feedback
feedback provided
provided an an optimum
optimum driving
driving signal
signal toto the
the output
output to
to maintain
maintain
high
high efficiency
efficiency and
and output
output power.
power. TheThe bond
bond wire
wire inductors
inductors generated
generated aa high-quality
high-quality factor,
factor, which
which
resulted in a 33% PAE and an 18 dBm output power. However, the bond
resulted in a 33% PAE and an 18 dBm output power. However, the bond wire inductor wire inductor was challenging
was
to predetermine
challenging in this design,
to predetermine inthereby reducing
this design, the reducing
thereby accuracy thewithin 5% to within
accuracy 10%. 5% to 10%.
Lee and Park (2014) proposed a modified mode-locking differential cascode PA to minimize the
time delay, as shown in Figure 12 [42]. This design was focused on improving the high power gain. The
input of the cross-coupled transistor was connected to the drain voltage of the CS transistor. This design
overcame the low breakdown voltage problems of CMOS devices. The time delay between the CS and
the cross-coupled transistors was reduced by this method, thereby maximizing the advantage of the
mode-locking technique and reducing the harmonics. An excessive time delay produces harmonics,
which distorts the signal. Although the parameters for this design are moderate, the power gain is
considerably high. The measured power-added efficiency for the proposed design was 34.9%, whereas
the saturated output power was 23.32 dBm.
Electronics 2019, 8, 477 11 of 21
Electronics 2019, 8, x FOR PEER REVIEW 11 of 21

Figure 11. Schematic of proposed differential PA [41].

Lee and Park (2014) proposed a modified mode-locking differential cascode PA to minimize the
time delay, as shown in Figure 12 [42]. This design was focused on improving the high power gain.
The input of the cross-coupled transistor was connected to the drain voltage of the CS transistor. This
design overcame the low breakdown voltage problems of CMOS devices. The time delay between
the CS and the cross-coupled transistors was reduced by this method, thereby maximizing the
advantage of the mode-locking technique and reducing the harmonics. An excessive time delay
produces harmonics, which distorts the signal. Although the parameters for this design are moderate,
the power gain is considerably
Figurehigh.
Figure 11. The measured
11. Schematic power-added
proposed
of proposed efficiency
differential PA
differential [41]. for the proposed design
PA[41].
was 34.9%, whereas the saturated output power was 23.32 dBm.
Lee and Park (2014) proposed a modified mode-locking differential cascode PA to minimize the
time delay, as shown in Figure 12 [42]. This design was focused on improving the high power gain.
The input of the cross-coupled transistor was connected to the drain voltage of the CS transistor. This
design overcame the low breakdown voltage problems of CMOS devices. The time delay between
the CS and the cross-coupled transistors was reduced by this method, thereby maximizing the
advantage of the mode-locking technique and reducing the harmonics. An excessive time delay
produces harmonics, which distorts the signal. Although the parameters for this design are moderate,
the power gain is considerably high. The measured power-added efficiency for the proposed design
was 34.9%, whereas the saturated output power was 23.32 dBm.

.
Figure 12. Schematic of mode-locking technique PA [42].
Figure 12. Schematic of mode-locking technique PA [42].
Ghorbani and Ghoushchi (2016) proposed a class-E differential PA by implementing capacitive
Ghorbani neutralization,
cross-coupling and Ghoushchi as (2016) proposed
shown a class-E
in Figure differential
13 [43]. PA by
This design implementing
applied capacitive
a complementary
cross-coupling neutralization, as shown in Figure 13 [43]. This design applied a complementary
CMOS cross-coupled pair with transistors M1–M4 to decrease the transistor size and, in turn, reduce
CMOS
the cross-coupled
inductor loss. The pair with transistors M1–M4
transconductance to decreasewas
of the transistors the transistor
increased size and,cross-coupling
by the in turn, reduce
the inductor loss. The transconductance of the transistors was increased by the
capacitor technique [44,45]. Consequently, the power gain increased because it was proportional cross-coupling
to the
capacitor technique
transconductance [44,45].
value. SuchConsequently, the power
capacitor cross coupling gain increased
improved because
the stability it was
of the proportional
PA. The simulationto
results indicate that a high gain of 35.6 dB was obtained with a supply voltage 1.8 V. .This design
produced a very high power gain and a high output power (28.5 dBm). However, the PAE performance
was moderate because itFigure 12. Schematic
was optimized byofthe
mode-locking technique
changing the PA [42]. capacitance with the
cross-coupling
input power.
Ghorbani and Ghoushchi (2016) proposed a class-E differential PA by implementing capacitive
cross-coupling neutralization, as shown in Figure 13 [43]. This design applied a complementary
CMOS cross-coupled pair with transistors M1–M4 to decrease the transistor size and, in turn, reduce
the inductor loss. The transconductance of the transistors was increased by the cross-coupling
capacitor technique [44,45]. Consequently, the power gain increased because it was proportional to
the transconductance value. Such capacitor cross coupling improved the stability of the PA. The
simulation results indicate that a high gain of 35.6 dB was obtained with a supply voltage 1.8 V. This
design produced a very high power gain and a high output power (28.5 dBm). However, the PAE
performance
Electronics was
2019, 8, 477 moderate because it was optimized by the changing the cross-coupling capacitance
12 of 21
with the input power.

Figure 13. Class-E

Class-E differential
differential PA with cross-coupling
cross-coupling pair
pair [43].
[43].

4.4. Power Combining

4.4. Power Combining Architecture
Architecture
If
If the
the output
output power
power requirement
requirement forfor aa transmitter
transmitter isis very
very high and aa single
high and single stage
stage PAPA cannot
cannot fulfil
fulfil
the
the demand, power combining methods are very useful where multiple stages of PA are added
demand, power combining methods are very useful where multiple stages of PA are added to to
achieve
achieve the the desired
desired overall
overall output
output power.
power. Transformers
Transformers are are the
the commonly
commonly utilized
utilized components
components for for
implementing
implementing aa fully fully integrated
integrated high-power
high-power powerpower amplifier
amplifier (PA)
(PA) asas aa power
power combiner
combiner whichwhich also
also
serve the purpose of impedance transformation in order to maximize
serve the purpose of impedance transformation in order to maximize the efficiency. the efficiency.
An
An etet al. (2009) proposed
al. (2009) proposed aa different
different architecture
architecture ofof the
the class-AB
class-AB PA PA design
design that
that consisted
consisted of of an
an
input balun and a parallel combining transformer (PCT), as depicted in Figure
input balun and a parallel combining transformer (PCT), as depicted in Figure 14 [46]. Cascode 14 [46]. Cascode topology
was applied
topology wasatapplied
the driver
at theand power
driver andstages
powerto prevent
stages excessive
to prevent voltage
excessive stress stress
voltage on theondevice, as it
the device,
undergoes
as it undergoesbreakdown at high
breakdown voltages
at high under
voltages an excessive
under voltage
an excessive stressstress
voltage [46]. [46].
The PCT concept
The PCT was
concept
applied by combining the three identical PAs in parallel for the layout of the transformers,
was applied by combining the three identical PAs in parallel for the layout of the transformers, which which was
more compact but displayed an average chip size of 2 mm 2 [47]. LC baluns were applied because they
was more compact but displayed an average chip size of 2 mm2 [47]. LC baluns were applied because
can
theybecan effectively exploited
be effectively for matching
exploited and power
for matching and combining
power combining[25]. With this
[25]. design,
With this the authors
design, the
achieved
authors achieved a maximum output power of 31 dBm, a power gain of 35 dB, and a PAE ofcurrent
a maximum output power of 31 dBm, a power gain of 35 dB, and a PAE of 27% at a 27% at
consumption
a current2019, of 650 mA with
consumption 650amA
power supply of 3.3 V [46].ofThis design generated
designa generated
very high output
Electronics 8, x FOR PEERofREVIEW with a power supply 3.3 V [46]. This a very
13 of 21
power with less PAE. However, this design was bulky and had a complex
high output power with less PAE. However, this design was bulky and had a complex circuitry. circuitry.

Figure 14. Proposed differential class-AB PA with parallel combining transformer (PCT) [46].
Figure 14. Proposed differential class-AB PA with parallel combining transformer (PCT) [46].

Ren et al. (2015) designed another 2.4 GHz PA using PCT technique, as shown in Figure 15 [48].
The driver stage uses class-A biasing, whereas the power stage follows class-AB biasing. Three
identical PAs were combined in parallel to form the PCT design. The self-biased cascode technique
was implemented inside the PA. This PA design delivered an output power of 30.7 dBm and a high
Electronics 2019, 8, 477 13 of 21
Figure 14. Proposed differential class-AB PA with parallel combining transformer (PCT) [46].

Ren et al. (2015) designed another 2.4 GHz PA using PCT technique, as shown in Figure 15 [48].
The driver
The driverstage
stageuses
uses class-A
class-A biasing,
biasing, whereas
whereas the power
the power stage follows
stage follows class-ABclass-AB biasing.
biasing. Three Three
identical
identical PAs were combined in parallel to form the PCT design. The self-biased cascode
PAs were combined in parallel to form the PCT design. The self-biased cascode technique was technique
was implemented
implemented insideinside theThis
the PA. PA.PAThis PA design
design delivered
delivered an output
an output power power of 30.7
of 30.7 dBm dBm
and andgain
a high a high
of
gaindB
33.2 of 33.2
[48], dB
but[48], but its
its PAE wasPAE
29%.was 29%.

Figure 15. Schematic of 2.4 GHz PCT PA [48].

Figure 15. Schematic of 2.4 GHz PCT PA [48].

PSCT is another method that performs parallel and series combining simultaneously inside a
PSCT is another method that performs parallel and series combining simultaneously inside a
single structure [49]. Ezzulddin and Jasim (2015) introduced another class-AB PA for wireless local
single structure [49]. Ezzulddin and Jasim (2015) introduced another class-AB PA for wireless local
area network (WLAN) applications by integrating the hybrid-type parallel-series power-combining
area network (WLAN) applications by integrating the hybrid-type parallel-series power-combining
transformer (PSCT) method, as shown in Figure 16 [50]. The design consisted of a single-ended
transformer (PSCT) method, as shown in Figure 16 [50]. The design consisted of a single-ended class-
class-AB PA connected in series to the PSCT with three other identical PAs combined in parallel to the
AB PA connected in series to the PSCT with three other identical PAs combined in parallel to the
PSCT. In class AB, the DC bias voltage of the gate-to-source slightly exceeded the threshold voltage,
PSCT. In class AB, the DC bias voltage of the gate-to-source slightly exceeded the threshold voltage,
and the transistor was biased at a small drain current. The LC tank circuit was designed to block higher
and the transistor was biased at a small drain current. The LC tank circuit was designed to block
harmonics from reaching the load. This PA simulated a very high output power of 30 dBm, a gain of
higher harmonics from reaching the load. This PA simulated a very high output power of 30 dBm, a
30 dB, and moderate PAE of 40% at 2.5 V supply voltage.
gain of 30 dB, and moderate PAE of 40% at 2.5 V supply voltage.
Electronics 2019, 8, 477 14 of 21
Electronics 2019, 8, x FOR PEER REVIEW 14 of 21

Figure Schematic
16.16.
Figure class-AB
Schematic PAPA
class-AB based on on
based parallel-series power-combining
parallel-series transformer
power-combining (PSCT)
transformer [50].
(PSCT)
5. Discussion [50].

In modern wireless communication systems, different classes of CMOS PAs have been implemented
5. Discussion
successfully. The CMOS process has become much more popular because of its simple integration, low
In modern wireless communication systems, different classes of CMOS PAs have been
power consumption, and low cost of design. However, these PAs are hindered by oxide breakdown
implemented successfully. The CMOS process has become much more popular because of its simple
and hot electron effect. The reason is that the CMOS technology is mostly optimized for low voltage,
integration, low power consumption, and low cost of design. However, these PAs are hindered by
whereas power amplifiers operate at high voltage. The low breakdown voltages of CMOS transistors
oxide breakdown and hot electron effect. The reason is that the CMOS technology is mostly
lead to the reliability problem in PAs. Thus, further investigations are needed to overcome the
optimized for low voltage, whereas power amplifiers operate at high voltage. The low breakdown
limitations of the PA design in CMOS technology.
voltages of CMOS transistors lead to the reliability problem in PAs. Thus, further investigations are
Different architectures have been proposed to satisfy the desired performance of the PA. The pie
needed to overcome the limitations of the PA design in CMOS technology.
chart and bar graph in Figures 17 and 18, which have been generated from the literature considered for
Different architectures have been proposed to satisfy the desired performance of the PA. The pie
this study, present the outcomes of the PA design architectures and classes in state-of-the-art works
chart and bar graph in Figures 17 and 18, which have been generated from the literature considered
in the past 18 years (2000 to 2018). The plotted graph shows that the dominant choice is the general
for this study, present the outcomes of the PA design architectures and classes in state-of-the-art
cascode architecture, which accounts for 33.33% of the overall PA design architectures. Compared with
works in the past 18 years (2000 to 2018). The plotted graph shows that the dominant choice is the
the rest, this type of architecture produces a higher power-added efficiency and a higher power gain at
general cascode architecture, which accounts for 33.33% of the overall PA design architectures.
a lower power consumption. The second most dominant choice is the power combining architecture,
Compared with the rest, this type of architecture produces a higher power-added efficiency and a
which accounts for 26.67% of the overall design architectures. This architecture is characterized by
higher power gain at a lower power consumption. The second most dominant choice is the power
a high output power and balanced parameter values. Both the self-biased and differential cascode
combining architecture, which accounts for 26.67% of the overall design architectures. This
architectures have the lowest percentage coverage of 20%. Among all classes of PA, class-E biasing has
architecture is characterized by a high output power and balanced parameter values. Both the self-
the highest percentage coverage of 53.33%. The high PAE allows the extensive integration of that class
biased and differential cascode architectures have the lowest percentage coverage of 20%. Among all
in the PA design. Class-D biasing has the second highest coverage of 25.34%, whereas class-AB biasing
classes of PA, class-E biasing has the highest percentage coverage of 53.33%. The high PAE allows
has the lowest coverage of 21.33%.
the extensive integration of that class in the PA design. Class-D biasing has the second highest
coverage of 25.34%, whereas class-AB biasing has the lowest coverage of 21.33%.
Electronics 2019, 8, 477 15 of 21
Electronics 2019, 8, x FOR PEER REVIEW 15 of 21
Electronics 2019, 8, x FOR PEER REVIEW 15 of 21

Figure
Figure 17.
17. Pie
Pie chart
chart of
of PA
PA architectures in the
architectures in the past
past 18
18 years
years (2000 to
to 2018).
18 years (2000
(2000 to 2018).
2018).

Figure
Figure 18. Bar
Bar graph
graph of
of PA
PA architectures and classes in the past 18 years (2000 to 2018).
Figure 18. Bar graph of PA architectures and classes in the past 18 years (2000 to 2018).
Several PA
Several PA design
design architectures
architectures achieved
achieved highhigh parameter
parameter performance,
performance, whereas
whereas somesome did
did not.
not.
Several PA design architectures achieved high parameter performance, whereas some did not.
Table 1 summarizes the design techniques, advantages, and disadvantages of
Table 1 summarizes the design techniques, advantages, and disadvantages of each PA architecture. each PA architecture.
Table 1 summarizes the design techniques, advantages, and disadvantages of each PA architecture.
As shown
As showninin Table 1, the
Table 1, general cascode
the general configuration
cascode eliminated
configuration the problem
eliminated the ofproblem
oxide breakdown
of oxide
As shown in Table 1, the general cascode configuration eliminated the problem of oxide
breakdown and hot carrier effect. The drawbacks of this architecture were additional power by
and hot carrier effect. The drawbacks of this architecture were additional power losses caused the
losses
breakdown and hot carrier effect. The drawbacks of this architecture were additional power losses
parasitic
caused by inductance. Integrating
the parasitic an inductor
inductance. withan
Integrating a high-quality
inductor with factor can linearly decrease
a high-quality factor can thelinearly
power
caused by the parasitic inductance. Integrating an inductor with a high-quality factor can linearly
losses. However,
decrease the powerthelosses.
breakdown voltage
However, theofbreakdown
the CG transistor
voltagelimits theCG
of the supply voltage
transistor in cascode
limits PAs.
the supply
decrease the power losses. However, the breakdown voltage of the CG transistor limits the supply
Thus, a strategy for device staking in series was introduced to reduce the voltage
voltage in cascode PAs. Thus, a strategy for device staking in series was introduced to reduce the stress of each device
voltage in cascode PAs. Thus, a strategy for device staking in series was introduced to reduce the
without decreasing
voltage stress of eachthe supply
device voltage
without [51]. In comparison,
decreasing a self-biased
the supply voltage [51]. In cascode
comparison,doesanot require
self-biased
voltage stress of each device without decreasing the supply voltage [51]. In comparison, a self-biased
external bias, minimizes the use of resistor networks, and overcomes the device
cascode does not require external bias, minimizes the use of resistor networks, and overcomes stress. Given thatthe
no
cascode does not require external bias, minimizes the use of resistor networks, and overcomes the
additional bond pads were required, a simpler circuit was produced, which
device stress. Given that no additional bond pads were required, a simpler circuit was produced, reduced the fabrication
device stress. Given that no additional bond pads were required, a simpler circuit was produced,
cost. However,
which reduced the self-biased
fabricationcascode is hindered
cost. However, by its low slew
the self-biased rate is
cascode [52], which causes
hindered the slew
by its low amplifier
rate
which reduced the fabrication cost. However, the self-biased cascode is hindered by its low slew rate
to respond more slowly to the rapid changes at the input level.
[52], which causes the amplifier to respond more slowly to the rapid changes at the input level.
[52], which causes the amplifier to respond more slowly to the rapid changes at the input level.
Table 1. Performance analysis between different PA design techniques.
Table 1. Performance analysis between different PA design techniques.
Design Techniques of
Architectures Design Techniques of Advantages Disadvantages
Architectures Architectures Advantages Disadvantages
Architectures
Electronics 2019, 8, 477 16 of 21

Table 1. Performance analysis between different PA design techniques.

Architectures Design Techniques of Architectures Advantages Disadvantages
- Eliminates oxide breakdown and
- The source terminal of the transistor is
hot carrier effect
connected to cascode with the drain of - Additional power losses in
- Circuit simplicity
General Cascode another transistor CG transistor
- Low power consumption
- The gate of transistors is biased with - Moderate output power
- High power gain and PAE
DC voltages.
- Small chip size
- A resistor and a capacitor produce bias
- No external bias supplies needed - Required high supply voltage
for the transistor to reduce the extra DC
- Can overcome the device stress - Low slew rate with slow react time of
voltage supply needed
Self-Biased Cascode - Simpler circuit and low-cost circuit PA to the input level
- Allow RF signal swing at the common
- High power gain - The supply voltage is limited by the
gate of two cascaded transistors to
- Reduced power consumption breakdown voltage of CG
improve the biasing voltage.
- Cross-coupling capacitors are used to
decrease the power dissipation of PA - Minimized common mode noise
- Considerably less PAE
with increasing transconductance. and substrate coupling
Differential Cascode - More complex circuitry
- The cross-coupling transistors form a - Minimized impedance matching losses
- Average output power
positive feedback on driver stage is - No low breakdown voltage problem
used to obtain a high efficiency
- Three identical PAs are combined in - Reduction of secondary inductor - Large chip size and high cost
Power Combining parallel to form a transformer losses - Complex circuitry
Architecture - LC balun is used as the input balun for - Generate high output power - High power consumption
an effective input matching. - High power gain - Poor PAE performance

In a differential configuration, the current is discharged to the ground twice per cycle, thereby
reducing the common mode noise and the substrate coupling. Removing the substrate noise component
twice in the circuit diminishes the interference problem [53]. In addition, the output power was doubled
from that under a single-ended configuration, and the optimum load was reduced. Consequently,
the matching losses were reduced [41]. The size of the transistors and the current flowing can be
reduced by using a differential configuration. The drain output voltage can be spread over both
transistors; thus, nearly twice of the supply voltage can be handled, which resolves the low breakdown
voltage. Moreover, the power combining architecture reduces the secondary inductor losses, thereby
minimizing the current flowing through it [50]. The power combiner generates a higher output power
by combining several units of power cells [49]. However, this kind of structure is more complex and
bulkier, and it consumes larger chip area, leading to a high manufacturing cost.
Table 2 shows a chronological summary of empirical results for PAs, which were extracted from
studies on differential topologies involving CMOS process, supply voltage, architectures, classes,
power consumption, power gain, PAE, and output power.
As shown in Table 2, the highest output power performances of the PA design were 31, 30.7,
and 30 dBm obtained from References [46,48,50], respectively, and all of these works used powers
combining method, suggesting that this method provides a higher output power compared with that
in other architectures. Although Reference [46] has a high output power of 31 dBm and a high-power
gain of 35 dB, its PAE performance was poor at 27%.
The highest PAE of 57% was achieved in Reference [16], which implemented a general cascade
architecture. The reason is that dissipation of the charge and discharge of parasitic capacitance was
reduced. Although its efficiency was high, the output power was only 19 dBm. It used a supply
voltage of 2.0 V, which was considerably low and resulted in a low power consumption. The design
proposed by Sahu and Deshmukh [20] achieved the highest power gain of 42.73 dB and the second
highest PAE of 44.7%. It attained a moderate output power of 20 dBm.
The PA based on the differential cascode designed by Ghorbani and Ghaznavi [38] achieved the
lowest power consumption of 0.225 W by implementing cross coupling capacitor technique, whereas
the method in Reference [46] consumed a large amount of power (2.1450 W) because of the vast
parasitic capacitances at the gates of the PCT. In addition, it had the lowest power gain. A significant
power gain of 35.6 dB was obtained in Reference [43]. It had a low supply voltage and a considerably
high output power. The PAE of this design was also quite high (43%). However, its other parameters
were low, displaying an output power of 18 dBm and a PAE of 33%. Thus, this design exhibited an
Electronics 2019, 8, 477 17 of 21

average performance for all parameters. Hence, this design would be ideal for a moderate performance
with a low power consumption.

Table 2. Performance comparison of 2.4 GHz CMOS PA.

CMOS Supply Power Power Output

Reference PAE
Technology Voltage Architectures Classes Consumed Gain Power
(Year) (%)
(µm) (V) (W) (dB) (dBm)
[34] General
0.18 3.3 Class-E - 14.3 40 21.3
(2005) cascode
[35] General
0.18 1.6 Class-E - 14.8 35 18
(2011) cascode
[16] General
0.13 2.0 Class-E - 17 57 19
(2011) cascode
[20] General
0.13 2.5 - 0.2283 42.73 44.7 20
(2013) cascode
[14] General
0.18 2.4 Class-F - 25.8 34.6 27.6
(2018) cascode
[17] Self-biased
0.18 2.4 - 0.5208 31 49 24.5
(2003) cascode
[37] Self-biased
0.18 3.3 Class-E - 13 44.5 23
(2009) cascode
[38] Self-biased
0.18 3.3 Class-A - 26.5 34.3 25.2
(2010) cascode
[41] Differential
0.35 1.0 Class-E - - 33 18
(2003) cascode
[42] Differential
0.18 3.3 - - 13.2 34.9 23.3
(2014) cascode
[43] Differential
0.18 1.8 Class-E 0.2250 35.6 43 28
(2016) cascade
[46] Power
0.18 3.3 Class-AB 2.1450 35 27 31
(2009) combining
[48] Power
0.18 3.3 Class-AB 0.8382 33.2 29 30.7
(2015) combining
[50] Power
0.13 2.5 Class-AB - 30 40 30
(2015) combining
[54] Power
0.065 3.3 - - 26.5 40.3 26.9
(2016) combining
Spiral-type
[55]
0.18 3.3 output - - 26.6 23.5 21.28
(2017)
transformer
Proportional
[12] series
0.18 2.5 Class-AB - 28 31 26.8
(2018) combining
transformer
[31] Switched
0.18 1.8 Class-D 0.9040 - 50 15
(2016) mode

Among the classes of PA architectures, the class-E PA was generally selected as the most. For the
general cascode architecture, References [16,34,35] were designed with a class-E PA. In self-biased
cascade cases, Reference [33] applied class-E biasing, whereas Referencs [41,42] adopted a differential
cascode topology. Their PAE values were very high, with one reaching up to 57%. Class-AB PAs
in power combining architecture has high output power of more than 30 dBm and a high power
gain of more than 30 dB in References [46,49,50]. However, the PAE performances of these designs
were unsatisfactory. Thus, the class-E PA had a higher PAE, whereas the class-AB PA had a higher
Electronics 2019, 8, 477 18 of 21

output power and power gain. The class-E PA achieved a high efficiency, and a lower supply voltage
was needed.
Comparison of Tables 1 and 2 indicate that in the case of the output power, the power combining
architecture was the ideal selection. It combined several power cell units, which can endure more
force and in turn can produce a higher output power. In terms of gain, the general cascode and the
self-biased cascode were considered the most suitable architectures because they can achieve a high
gain of 42.73 and 35.6 dB, respectively [20,43]. In terms of circuit complexity, the general cascode was
the best architecture with the simplest circuitry, whereas the power combining architecture had the
highest circuit complexity. Both the general and differential cascode architectures can operate at a
lower supply voltage compared that for the self-biased and power combining architectures.
Overall, the key advantage of the general cascode architecture is its high efficiency and gain while
maintaining the performance of the other parameters under the standard requirements. For low-power
and highly efficient applications, this architecture is considered the best. Among all types of PA
architectures, the general cascode was identified as the most suitable for full system integration. Besides,
class-E PA provided the best performance, and it can be easily integrated with the general cascode
architecture. Therefore, studies in this field will continue to be extremely active and vigorous for the
development of RF devices operating in a high-frequency range, such as 2.4 GHz with optimum power.

6. Conclusions
This article comprehensively discussed the different architectures of the CMOS PA design.
These architectures are for Industrial, Scientific and Medical (ISM) band applications with design
concerns and performance analysis. Several techniques have been implemented by different researchers
to improve the performance of 2.4 GHz RF PAs in CMOS technology. Several researchers have attempted
to maximize the transmitter output power, and several others have worked to reduce the leakage
of current and power consumption to obtain ultra-low power. A few studies have improved the
power gain. In designing a CMOS PA, the required performance of the specific parameters must be
identified and concentrated on. Output power, power efficiency, and power consumption are the
main performance parameters of PA that must be considered. Comparison showed that the general
cascode architecture is highly suitable for designing a 2.4 GHz CMOS PA and can address the demand
for high power gain, PAE, output power, and low-cost solutions by modern wireless communication
systems. The class biasing for the PA would be class-E if high efficiency is highly demanded for the
desired PA. The procedures of PA designing, and the relevant discussions presented in this study,
are expected to aid researchers in designing CMOS PAs and contribute to realizing small, low-cost,
wireless communication terminals at the 2.4 GHz ISM band.

Author Contributions: All authors have contributed equally in this review article.
Funding: This research was financially supported by the Xiamen University Malaysia (Project code:
[XMUMRF/2018-C2/IECE/0002]) and the Universiti Kebangsaan Malaysia (Project code: [DIP-2018-017]).
Conflicts of Interest: The authors declare no conflict of interest.

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