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Sri Venkateshwara College of Engineering: Usn: 1 V E IA Test-I

1) This document is an internal assessment test question paper for the 6th semester Electronics and Communication Engineering students for the course VLSI Design. 2) It contains 4 questions divided into 2 parts carrying a total of 30 marks. Students have to answer 3 full questions, choosing one from each part. 3) The questions assess students' understanding of MOS transistor theory, CMOS fabrication process, DC characteristics of CMOS inverter, and design of basic CMOS logic gates.

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jaya sree
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74 views1 page

Sri Venkateshwara College of Engineering: Usn: 1 V E IA Test-I

1) This document is an internal assessment test question paper for the 6th semester Electronics and Communication Engineering students for the course VLSI Design. 2) It contains 4 questions divided into 2 parts carrying a total of 30 marks. Students have to answer 3 full questions, choosing one from each part. 3) The questions assess students' understanding of MOS transistor theory, CMOS fabrication process, DC characteristics of CMOS inverter, and design of basic CMOS logic gates.

Uploaded by

jaya sree
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Format No ACD50

Date 01/08/2016
Sri Venkateshwara College of Engineering
INTERNAL ASSESSMENT TEST QUESTION PAPER Rev No. 01
Page 1 of 1

USN: 1 V E
CBCS SCHEME 2017
IA Test- I
Term: April-2021 to August-2021
Programme: Electronics & Communication Engineering Semester& Section: 6 - ‘A’ & ‘B’
Course Title : VLSI Design Date: 25/05/2021
Course Code: 17EC63 Time: 9.15 AM to 10.45 AM
Duration: 90 Minutes Maximum Marks: 30
Instructions: Answer THREE full questions, choosing ONE full question from each part. Use A4
sheets only.
Kx,
SL.NO Question Marks
COx
PART – I (20 Marks)
K2, Explain with a neat diagram enhancement mode transistor action of nMOS
a) CO363.1 transistor. 10
1 K2,
b) CO363.1
Describe the fabrication steps for nMOS transistor using a neat diagram 10
OR
K3, Derive the expression for drain to source current of nMOSFET
a) CO363.1 10
2 K3, With a neat circuit and sketch explain CMOS inverter DC characteristics by
b) CO363.1 mentioning all the operating regions 10

PART – II (10 Marks)


Using CMOS logic draw schematic and stick diagram for
K3, 10
3 a) (i) Y=
CO363.2
(ii) F =
OR
K3, Draw the design rule for pMOS, nMOS and CMOS 5
a) CO363.2
4
K3, Draw the schematic diagram and layout diagram for two input CMOS NOR 5
b) CO363.2 gate
COx- course outcome (1to5) Kx- blooms knowledge Level (K1, K2, K3, K4, K5, K6)
K1 – Remember K2 – Understand K3 – Apply K4 – Analyze K5 – Evaluate K6 – Create

CO No. Knowledge Max


COURSE OUTCOMES
XYZ.I Level Marks
C363.1 Understand the MOS transistor theory analyse the CMOS fabrication flow and
K2 40
technology scaling.
C363.2 Understand the stick and layout diagrams with the knowledge of physical design
aspects. K2 20

TOTAL 60

CXYZ.I : C – Course; X – YEAR; Y – SEMESTER; Z – Course Order; I- Order of CO

Scrutinizer Signature

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