MICROPROCESSOR AND

INTERFACING
CSE2006

Dr. Arvind Kumar

| School of Electronics Engineering, VIT Vellore |
Microprocessors and Interfaces: 2021-22
Lecture I/O Interfacing
IO-Mapped & Memory-Mapped
IO-Mapped & Memory-Mapped
 Modes of I/O Instructions

• Direct I/O
• Indirect I/O
• String
 8086 I/O Instructions
IN and OUT transfer data between an I/O device and the
microprocessor's accumulator (AL, AX or EAX).
The I/O address is stored in:
Register DX as a 16-bit I/O address (variable addressing/Indirect).
The byte, p8, immediately following the opcode (fixed address/Direct).
IN AL,19H; 8-bits data are saved to AL from I/O port 19H
IN AL, DX; 8-bits data are saved to AL from I/O port [DX]
IN AX, DX; 16-bits are saved to AX.
IN AX, 20H 16-bits data are saved to AX from I/O port 20H
OUT DX, AX; 16-bits are written to port DX from AX
OUT 19H, AL; 8-bits are written to I/O port 0019H.
Only 16-bits (A0 to A15) are decoded.
Address connections above A15 are undefined for I/O instructions.
OUTS
80x86 I/O Instructions

DX
 Modes of I/O Instructions
• Direct I/O – the port address is one of the operands.
– Address must be 00-FFh.
• IN AL, 27h

– Data flows through the accumulator

• MOV AX, BX ; move 16-bit data from AX to port
• OUT 26h, AX ; 26h (AL to 26h and AH to 27h)
 Modes of I/O Instructions
• Indirect I/O – the port address is preloaded into DX
– Address can be 0000-FFFFh

• String I/O – allows data to pass directly through the accumulator

(from I/O device to memory)
 I/O Interface
• I/O devices connect to processor through PORTS

• Ports are:
➢ registers (part of the I/O interface)
➢ 8, 16, or 32 bits wide
➢Addressed in the range 0000-FFFFh
➢Accessed with 2 instructions – IN, OUT
 Why Buffers

4/3/2021 13
 I/O Design in 8086
Any μP-based system when data is sent out by μP, the data on the data-bus must be
latched by the receiver/output device

Memories have internal latches–store data Latching System must

be designed for ports

Data provided by the μP is available only for short period of time (50-1000ns) data must
be latched else it will be lost

When data comes in from a port/memory, data must be input through a tri-state
buffer
 I/O Design in 8086

➢ Interfacing input devices like switches require buffers.

➢ Interfacing output devices like LEDs require latches.

➢ Programmable Peripheral Interface (PPI) device provides these features

Microprocessors and Interfaces:
8255 Programmable Peripheral
Interface
8255- PPI
Why do we need 8255?
• Intel 8255 is a peripheral interface (PPI) chip which is programmable.
• It is used for the connection of peripheral devices and interfacing.
• We call Peripheral device also as Input Output device.
• We use Input Output ports for the connection of Input Output
devices.
PPI 8255
• PPI 8255 is a general purpose programmable I/O device designed to
interface the CPU with its outside world such as ADC, DAC, keyboard
etc.
• We can program it according to the given condition. It can be used
with almost any microprocessor.

• It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT B

and PORT C.
• We can assign different ports as input or output functions.
 8255- PPI
Intel has developed several peripheral control chips for 80x86
family
–provide complete I/O interface to x86 chip

8255 PPI
PPI provides 3, 8-bit I/O ports (A, B and C) in one package Chip can be directly
interfaced to the data bus of 8086.

Other Peripheral Devices

8253/8254 –Programmable Interval Timer (PIT) 8259 –Programmable
Interrupt Controller (PIC) 8237 –Direct memory Access Controller
(DMAC)
 8255- PPI
• 82C55 programmable peripheral interface (PPI) is a
popular, low-cost interface component

• The PPI has 24 pins for I/O, programmable in groups of 8/12 pins
(Group A ,B,C)

• The groups operate in three distinct modes of operation (Mode 0, Mode

1 and Mode 2)

• The 82C55 (CMOS version) requires wait states if operated with a processor
using higher than an 8 MHz clock.
Pin Diagram of 8255
•PA0 – PA7 – Pins of port A
•PB0 – PB7 – Pins of port B
•PC0 – PC7 – Pins of port C
•D0 – D7 – Data pins for the transfer of data
•RESET – Reset input
•RD’ – Read input
•WR’ – Write input
•CS’ – Chip select
•A1 and A0 – Address pins
 Selection of ports

Chip Select.
A LOW on this input selects the chip and enables the communication between the 8255A and the CPU. It is
connected to the decoded address, and A0 & A1 are connected to the microprocessor address lines.
Operating Modes
8255A has three different operating modes
• Mode 0 − In this mode, Port A and B is used as two 8-bit ports and Port C as
two 4-bit ports. Each port can be programmed in either input mode or
output mode where outputs are latched and inputs are not latched. Ports
do not have interrupt capability.
• Mode 1 − In this mode, Port A and B is used as 8-bit I/O ports. They can be
configured as either input or output ports. Each port uses three lines from
port C as handshake signals. Inputs and outputs are latched.
• Mode 2 − In this mode, Port A can be configured as the bidirectional port
and Port B either in Mode 0 or Mode 1. Port A uses five signals from Port C
as handshake signals for data transfer. The remaining three signals from
Port C can be used either as simple I/O or as handshake for port B.
Data Bus Buffer
• It is a tri-state 8-bit buffer, which is used to interface the
microprocessor to the system data bus.
• Data is transmitted or received by the buffer as per the instructions
by the CPU.
• Control words and status information is also transferred using this
bus.
What is tri-state buffer?
A tri-state buffer is similar to a buffer, but it adds an additional
"enable" input that controls whether the primary input is
passed to its output or not. If the "enable" inputs signal is true,
the tri-state buffer behaves like a normal buffer.
Read/Write Control Logic
• This block is responsible for controlling the internal/external transfer
of data/control/status word.
• It accepts the input from the CPU address and control buses, and in
turn issues command to both the control groups.
Internal block diagram of 8255

214 = 16K
8255 can be connected
• It consists of 40 pins and operates in +5V regulated power supply.
• Port C is further divided into two 4-bit ports i.e. port C lower and port
C upper and port C can work in either BSR (bit set rest) mode or in
mode 0 of input-output mode of 8255.
• Port B can work in either mode or in mode 1 of input-output mode.
Port A can work either in mode 0, mode 1 or mode 2 of input-output
mode.
• It has two control groups, control group A and control group B.
Control group A consist of port A and port C upper. Control group B
consists of port C lower and port B.
• Depending upon the value if CS’, A1 and A0 we can select different
ports in different modes as input-output function or BSR. This is done
by writing a suitable word in control register (control word D0-D7).
• Mode 0 –In this mode all the three ports (port A, B, C) can work as
simple input function or simple output function. In this mode there is
no interrupt handling capacity.
• Mode 1 – Handshake I/O mode or strobbed I/O mode. In this mode
either port A or port B can work as simple input port or simple output
port, and port C bits are used for handshake signals before actual
data transmission. It has interrupt handling capacity and input and
output are latched.
• Example: A CPU wants to transfer data to a printer. In this case since
speed of processor is very fast as compared to relatively slow printer,
so before actual data transfer it will send handshake signals to the
printer for synchronization of the speed of the CPU and the
peripherals.
• Mode 2 – Bi-directional data bus mode. In this mode only port A
works, and port B can work either in mode 0 or mode 1. 6 bits port C
are used as handshake signals. It also has interrupt handling capacity.
WR: It stands for write. This control signal enables the write operation.
When this signal goes low, the microprocessor writes into a selected
I/O port or control register.

RESET: This is an active high signal. It clears the control register and
sets all ports in the input mode.

RD: It stands for Read. This control signal enables the Read operation.
When the signal is low, the microprocessor reads the data from the
selected I/O port of the 8255
Interfacing with 8086
Programming 8255
MOV DX 0FFF6h;
MOV AL 80h;
OUT DX AL;

Port A
MOV DX 0FFF0h;
OUT DX AL;

Port B
MOV DX 0FFF2h;
OUT DX AL;

Port C
MOV DX 0FFF4h;
OUT DX AL;
Control word Format
Control word Format
Example
Modes of operation of 8255
Example
Example
Handshaking signal
Handshaking signal
Output Write
 MODE 1 (Strobed I/O mode)

• Two groups – Group A and group B are available for strobe data transfer.
• Each group contains one 8 bit data I/O port and one four bit control /
data port.
• Both the input and outputs are latched.
• Out of 8-bit port C , PC0- PC2 are used to generate control signals for
port B and PC3- PC5 are used to generate control signals for port A.
• The lines PC6- PC7 may be used as independent data lines.
 MODE 2 (Strobed Bidirectional I/O mode)

• A single 8-bit port in Group A is available.

• The 8 bit port is bidirectional and additionally a 5-
bit control port is available..
• Both the input and outputs are latched.
• The 5-bit control port C , PC3- PC7 are used to generate/
• accept handshake signals for port A.
• Three I/O lines are available at port C, PC2- PC0.
BIT Set Reset (BSR) mode
Example
Example
Example
 Example
CR EQU 06H
REPEAT: MOV AL, 00H MOV AL, 01H
OUT CR, AL OUT CR, AL
MOV AL, 03H MOV AL, 03H
OUT CR, AL OUT CR, AL
MOV AL, 05H MOV AL, 04H
OUT CR, AL OUT CR, AL
CALL delay_1ms CALL delay_1ms
MOV AL, 01H JUMP REPEAT
OUT CR, AL
MOV AL, 02H
OUT CR, AL
MOV AL, 05H
OUT CR, AL
CALL delay_1ms
Display Interfacing
Display Interfacing
Microprocessors and Interfaces
8253/8254 Timer
 Features of 8253/8254

• The 8254 consists of three independent

16-bit programmable counters (timers).
• Each counter is capable of counting in binary or binary-
coded decimal (BCD).
• Maximum allowable input frequency to any
counter is 10 MHz
• Useful where the microprocessor must
control real-time events. Ex: real-time clocks, event
counters, and motor speed/direction control.
8253 8254
Its operating frequency is 0 - 2.6 MHz Its operating frequency is 0 - 10 MHz
It uses N-MOS technology It uses H-MOS technology
Read-Back command is not available Read-Back command is available
Pin diagram of 8253/8254
 Features of 8253/8254
• Each timer contains:

– a CLK input which provides the basic operating

frequency to the timer

– a Gate input pin which controls the timer in some

modes.

– an output (OUT) connection to obtain the output

of the timer.
Memory mapping
Control word Format
Programming the Counters
Control word Format
 Control word Format
Counter-1 Mode 0, Binary, N= 3A98H

0 1 1 1 0 0 0 0

Only 98H in LSB of Counter-1

Mov AL, 50H;
OUT 46H, AL
MOV AL, 98H
OUT 42H, AL

Only 3AH in MSB of Counter-1

Mov AL, 60H;
OUT 46H, AL
MOV AL, 3AH
OUT 42H, AL
 Reading the Counters
Simple Read Operation

Counter selected with the A1, A0 inputs, the CLK input of the selected Counter must be inhibited by
using either the GATE input or external logic. Otherwise, the count may be in the process of changing
when it is read, giving an undefined result. Two I/O read operation are performed by the MPU
1. The first I/O operation reads the low order byte.
2. The second I/O operation reads high order byte.

Counter Latch Command

This allows reading the contents of the Counters “on the fly'' without affecting counting in
progress.
The selected Counter's output latch (OL) latches the count at the time the Counter Latch Command
is received. This count is held in the latch until it is read by the CPU (or until the Counter is
reprogrammed). The count is then unlatched automatically and the OL returns to “following'' the
counting element (CE).
 Reading the Counters
Counter Latch Command

Latching counter0
MOV DX, C_REG
MOV AL, 00000000B ;
OUT DX, AL

Reading counter0
MOV DX, CNTR0
IN AL, DX
 Read-Back Command
• This command is used to read several counters at a time. It eliminates the need of writing
separate counter-latch commands for different counters.
• It allows the user to check the count value, programmed Mode, and current states of
• the OUT pin and Null Count flag of the selected counter/ counters. The read back
command is written to the Control Word Register.
• is reprogrammed). The counter is automatically unlatched when read, but other counters
remain latched until they are read.
 Read-Back Command
The read-back command may also be used to latch status information of selected
counter(s) by setting STATUS bit D4 = 0. Status must be latched to be read; status
of a counter is accessed by a read from that counter.
 Read-Back Command
Example:

Count and Status latched for counter 0 MOV DX,

C_REG
MOV AL, 11000010B ; count latched for counter 0 OUT DX, AL

Reading the latched status for count 0 MOV DX,

TRM0
IN AL, DX ; Reading Status MOV AH, AL
Reading the latched count for counter 0 IN AL, DX ;
Reading LSB of counter 0 MOV BL, AL
IN AL, DX ; Reading MSB of counter 0 MOV BH, AL
Control word Format
 Programming of 8253/8254

• Each counter is programmed by writing a control word, followed by the

initial count.
➢ The control word allows the programmer to select
• the counter,
• mode of operation, and
• type of operation (read/write).
• also selects either a binary or BCD count
 Mode of Operation

• –Six modes (Mode 0–Mode 5) of operation are available to each of

the 8254 counters

• –each mode functions with the CLK input, the gate (G) control
signal, and OUT signal.
Modes of counting
Mode 0 –Interrupt on Terminal count
Mode 0 –Interrupt on Terminal count
Mod 0 : Case 1
Mod 0 : Case 2
Mod 0 : Case 3
Mode 1 –Hardware retriggerable one-shot
Mod 1: Case 1
Mod 1: Case 2
Mod 1: Case 3
Modes of counting : Mode 1
Mode 2 Rate Generator (Divide by N counter)
Case 1
Case 2
Case 3
Mode 3 -Square Wave Generator
Case1 :Even count
Case2 :Odd count
Mode 4 – Software triggered strobe
Case1
Case 2
Case 3
Mode 5 – Hardware triggered strobe
Case 1
Case 2
Case 3
Reading the counter values
8254 Read Back control word
Status Register( 8254 only)
 Example :1

• Draw the interface diagram and write a program for 8253 interface
starting at 50H,
• Counter 0 used in mode 1, MSB+LSB, binary, to be loaded with 3080H
• Counter1 used in mode 0, LSB only, BCD to be loaded with 99.
Example:1
 Example:1
Counter 0 used in mode 1, MSB+LSB, binary, to be loaded with 3080H
Counter1 used in mode 0, LSB only, BCD to be loaded with 99.

Control word1=00110010 – 32H

Control word2=01010001-51H

CNT0 EQU 50H

CNT1 EQU 52H
CR EQU 56H
MOVAL, 32H
OUT 56H, AL
MOVAL, 51H
OUT 56H, AL
MOVAL, 80H
OUT 50H, AL
MOVAL, 30H
OUT 50H, AL
MOVAL, 99
29
OUT 52H, AL
Example :2
Example :2
Example :2
Example :2

10
2
Timer 8253
 What is 8253/8254?
❖ It is not possible to create a time delay using delay routines
❖ Intel’s programmable timer 8253/8254 will generate an accurate time
delay
❖ While 8253/8254 are capable of taking care of the time delays and
timing of the process, the microprocessor can be free from these tasks
and perform other tasks
❖ This reduces the software overhead on the microprocessor
Characteristic features of 8253
❖ Has three counters each with maximum count rate of 2.6 MHz.
❖ Thus, it is possible to maintain 3 separate delays or maintain 3
independent counters simultaneously
❖ 8253 communicates with the microprocessor’s bus using D0 to D7
bidirectional data buffer
Block and pin diagrams
 Cont’d
❖ The three counters are independent of each other but are similar in
organization
❖ They are 16 bit counters that can operate either in BCD or Hexadecimal
mode
❖ The mode control word register contains the information that is used for
writing or reading count value into or from the respective count registers
using OUT and IN instructions.
❖ The control word can only be written and cannot be read
❖ When CS’ is low, it enables the Timer 8253
Various control inputs
Control word register
❖ A control word must be written in the respective control register by
the microprocessor to initialize the 8253.
❖ Depending upon the control word decided by the user, the counter
works independently.
❖ Only after the data is put on the data bus and a falling edge appears in
the clock signal of the peripheral device, the count can be written to the
counter
Cont’d
Cont’d
Modes of counting
Mode 0 – interrupt or terminal count
▪ Output is initially low after the mode is set.
▪ Output remains low even if the count value is loaded in the counter
▪ The counter starts decrementing the count after the falling edge of the
clock, if the GATE input is high.
▪ At each falling edge, the counter decrements till the count becomes 0.
▪ Once count becomes 0, the output goes high and remains high until the
selected control word register or the count register is loaded with a new
mode or count respectively.
▪ The high output can be used to interrupt the processor whenever
required by setting a suitable count.
Cont’d
▪ When the count register is filled with a new count value while the
previous count is executing, then the following sequence of operations
occur.
▪ The first byte of the new count stops the previous count.
▪ The second byte, when written, starts the new count by terminating the
previous count
▪ For normal counting, the GATE signal should be active high.
▪ When GATE goes low, the counting is terminated and the current count
is latched until the GATE goes high again.
Cont’d
Mode 1 – programmable one shot mode
▪ In this mode, 8253 can be used as a monostable multivibrator
▪ The duration of the quasistable state of the multivibrator is defined by the
count value in the count register.
▪ The GATE input is used a a trigger input in Mode 1.
▪ The output remains high till a suitable count is loaded in the count register
and a trigger is applied
▪ After the trigger is applied, the output goes low and remains low till the
count becomes 0.
▪ When a new count value is filled in the count register when a previous count
is going on, it does not affect the count until there is a trigger given by the
GATE
▪ The new count starts after the new trigger pulse
Cont’d
Mode 2 – rate generator or divide-by-n counter
▪ If N is loaded as the count value, then after N-1 cycles, the output
becomes low only for one cycle
▪ The count N is reloaded and again the output becomes high and
remains for another N-1 cycles
▪ The output is normally high after initialization
▪ A low on the GATE signal can also force the output to be high
▪ If the GATE goes high, the counter starts counting from the initial
value
Cont’d
• The count down starts and whenever the count becomes zero,
another active low pulse is generated at the output.
• They last for one clock cycle
• The number of input clock pulses between the two active low pulses
is equal to the count value
Cont’d
Mode 3 – square wave generator
• When the count N is even then for half of the count the count is high
and for the rest half the count is low.
• If the count is odd, the first clock pulse decrements it by 1, making it
even
• Then the output goes high for the first half of the count and goes low for
the remaining half, thus generating a square wave.
• In case of odd count the output is high for a longer duration and low for
a shorter duration
• If the loaded count value N is odd, then the output is high for (N+1)/2
cycles and low for (N-1)/2 cycles.
continued
Mode 4 – Software triggered strobe
• Once the mode is set, the output goes high
• When count is loaded, the count starts.
• When count becomes 0, the output goes low for one cycle and then
becomes high again
• This low pulse can be used as a strobe, while interfacing the
microprocessor with other peripheral devices.
• When the GATE goes low, the count is latched
• If a new count is loaded in the count register when the previous
count is in progress, then the new count is accepted after one clock
cycle.
Mode 4
Mode 5 – to generate a delayed strobe
❖ When there is a rising edge at the trigger input, a strobe is created
❖ Once the mode is set and the count is given, the output goes high
❖ The counter starts counter after the rising edge of the trigger input
❖ When the count becomes 0, then the output becomes low for one
clock cycle.
Mode 5
weblinks
• https://nptel.ac.in/courses/108/107/108107029/
• https://nptel.ac.in/content/storage2/courses/108105057/Pdf/Lesson-
14.pdf
Input & Output Interface
Bi-Directional Buffer

Latch

64K I/P & 64K O/P

Input & Output Interface
Programmable interrupt controller
microprocessor - 8259
 Why 8259
❖ Consider that the CPU is connected with a number of I/O devices
that would prefer to transfer data using interrupt driven data
transfer mode.
❖ In such cases, more number of interrupt pins are required than
that are available in the microprocessor.
❖ The processor will be subjected to take care of the priorities of
the interrupts occurring at each pin.
❖ To overcome these disadvantages, the programmable interrupt
controller that is capable of handling number of interrupts is used.
continued
❖ 8259 can take care of all the interrupts simultaneously along with
their priorities and types.
❖ Intel’s 8259 was compatible with only 8-bit microprocessors but the
advanced version of it, 8259A is compatible with 8 as well as 16-bit
microprocessors.
Architecture of 8259
 Functional descriptions
❖ Interrupt Request Register (IRR) – The interrupts at IRQ input lines are
handled. Stores all the interrupt requests in order to address them one
by one as per the priority.
❖ Interrupt Service Register (ISR) – Keeps track of the requests being
served
❖ Priority resolver – Determines the priorities of the interrupt requests
appearing simultaneously. Highest priority interrupt is selected and
stored in the corresponding bit of ISR.
In fixed priority mode, IR0 has highest priority while IR7 has lowest
priority.
Priorities can be altered by programming 8259 in rotating priority mode
 continued
❖ Interrupt mask register (IMR) – Stores the bits required to mask
the interrupt inputs. It operates on IRR at the direction of priority
resolver.
❖ Interrupt control logic – Manages the interrupt and interrupt
acknowledgement signals to be sent to the CPU. It also accepts
INTA signals from the CPU.
❖ Data Bus Buffer – Interfaces 8259A to the microprocessor system
data bus. Control words, status, other information pass through
data buffer during Read, Write operations.
continued
❖ Read/write control logic – Accepts and decodes commands from CPU.
Allows status of 8259A to be transferred via the bus
❖ Cascade buffer/comparator – Stores and compares the IDs of all the
8259As used in the system.
The three pins CAS0-2 are output pins when 8259 acts as master
The same pins are input pins when 8259 acts as slave.
8259A Block Diagram
Cascaded 8259A

Max 64
Pin diagram
 continued
❖ CS – active low chip select signal for enabling 𝑅𝐷 and 𝑊𝑅 operations.
❖ 𝑅𝐷 - Active low read enable input.
❖ 𝑊𝑅 - This pin is an active low write enable input pin to 8259
❖ 𝐷7 − 𝐷0 - bidirectional data bus that carries 8-bit data either to a
control word or from a status word register. This can also carry interrupt
vector information.
❖ 𝐶𝐴𝑆0 − 𝐶𝐴𝑆2 Cascade lines – If more interrupts are required, the 8259A
is used in a cascade mode in which one 8259A is the master and 8 other
8259As as slaves, thus forming 64 vectored interrupt. These three lines
act as select lines for addressing the slaves.
 continued
❖ 𝑆𝑃/ 𝐸𝑁 - When the chip is used in buffered mode, it can be used as a
buffer enable. Else, this pin is used as an input to designate whether
the chip is used as a master (𝑆𝑃 = 1) or a slave (𝐸𝑁 =0)
❖ INT - This pin goes high whenever a valid interrupt is received.
❖ 𝐼𝑅0 - 𝐼𝑅7 - Act as inputs to accept interrupts requests to CPU.
❖ 𝐼𝑁𝑇𝐴 - Interrupt acknowledgement
 Interrupt sequence
❖ When one or more IR lines go high, the corresponding bits are set in
the IRR
❖ It finds the highest priority signal and sends an INT signal to the CPU
❖ CPU acknowledges with 𝐼𝑁𝑇𝐴 pulse.
❖ Upon reception of 𝐼𝑁𝑇𝐴 pulse, the highest priority bit of ISR and the
corresponding bit of IRR are set.
❖ The 8086 will initiate another 𝐼𝑁𝑇𝐴 pulse.
❖ Now, 8259A releases an 8-bit pointer on the data bus from where it is
read by the CPU.
❖ If automatic end of interrupt (AEOI) mode is programmed, the ISR bit
is reset by the end of the second 𝐼𝑁𝑇𝐴 pulse.
❖ Otherwise, ISR bit remains set until an EOI signal is issued.
Command words

Command words

Initialization CWs Operation CWs

Interface with 8259A
8259A Block Diagram
Cascaded 8259A

Max 64
 Addressing 8259A
➢Only Two Addresses per 8259A.

▪ INITIALIZATION COMMAND WORDS (ICWS)

ICW 1, ICW 2, ICW 3, & IC4

▪ Operation Command Words (OCWs):

OCW 1, OCW 2 & ICW 3
 8259A ICWs

ICW1 : Mandatory
8259A ICWs
 8259A ICWs

ICW2 : Mandatory
 8259A ICWs

ICW3 : Dependant on ICW 1 ( Mandatory if Cascade selected in ICW1)

 8259A ICWs

ICW3 : Dependant on ICW 1 ( Mandatory if Cascade selected in ICW1)

 8259 ICWs

ICW3 : Dependant on ICW 1 ( Mandatory if Cascade selected in ICW1)

 8259 ICWs
ICW4 : Dependant on ICW 1 ( Mandatory if 8086 used)

D0-0 for 8085

SFNM :1 for
D0-1 for 8086
Fully nested Normal EOI- D1-0
Cascade: 0/1 ISR has EOI
SFNM :0 for Auto EOI : D1-1
Single
After sending vector ISR
register set 0
 8259 OCWs

OCW1 : Non-Mandatory

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 Problem

4/20/2021 24
Problem
 Problem

4/20/2021 26
8255A PPI/8254 Timer
& 8259A PIC
 Problem-1

Write a control word to configure port A as input port in mode 0 and

port B in mode 1 as output port for 8255A.
 Problem-1
Write a control word to configure port A as input port in mode 0 and
port B in mode 1 as output port for 8255A.
Solution:

D7=1; I/O Mode.

D6=0 and D5=0; Port A is in Mode 0.
D4=1; Port A is input port
D3=0; Port C (Upper).
D2=1; Port B is in Mode 1.
D1=0; Port B is output Port.
D0=0; Port C (Lower)
The control word is 94H.
D0 and D3 are low if port C is used as output or if unused.
 Problem-2

A control word is given CDH. Explain the conditions of ports of

8255A.
 Problem-2
A control word is given CDH. Explain the conditions of ports of
8255A.

D7=1; I/O Mode.

D6=1 and D5=0; Port A is in Mode 2.
D4=0; Port A is output port
D3=1; Port C (Upper) is input port.
D2=1; Port B is in Mode 1.
D1=0; Port B is output Port.
D0=1; Port C (Lower) is input port.
 Problem-3

Write an 8086 assembly language procedure to read an ASCII

character from a keyboard via PORTA of an 8255 PPI when PORT C
bit PC4 is strobed low. Assume a base address of 20H.
 Problem-3
Write an 8086 assembly language procedure to read an ASCII
character from a keyboard via PORTA of an 8255 PPI when PORT C
bit PC4 is strobed low. Assume a base address of 20H.
Solution:
PORTA EQU 20H
PORTC EQU 24H
CONTROL EQU 26H
READ PROC NEAR
MOV AL, 98H ; 1001 1000
OUT CONTROL, AL ; Initialize PORTS
READ1:
IN AL, PORTC ; Is Strobe PC4 Low?
TEST AL, 10H ; 0001 0000
JNZ READ1
IN AL, PORTA ; Read ASCII Character
RET
READ ENDP 7
 Problem-4
(a) Identify the port address of the control register and counter 2 in figure.
(b)Write a subroutine to initialize counter 2 in mode 0 with a count of 50,000.
The subroutine should also include reading counts on the fly; when count
reaches zero, it should return to the main program.
(c)Write a main program to display seconds by calling the subroutine as
many times as necessary.
 Problem-4

4/28/2021 18
8
Problem-4
Problem-4
Problem-4
 Problem-5

Write instructions to generate a pulse in every 50 us later from counter 0.

Consider the figure of problem 4.
 Problem-5
Write instructions to generate a pulse in every 50 us later from counter 0.
Consider the figure of problem 4.
 Problem-6
Show 8259A interfacing connections with 8086 at the address 074x. Write an ALP
to initialize the 8259A in single level triggered mode non buffered on special fully
nested mode. Then set the 8259A to operate with IR6 masked and specific EOI
mode.

19
4
 Problem-6
Show 8259A interfacing connections with 8086 at the address 074x. Write an ALP
to initialize the 8259A in single level triggered mode non buffered on special fully
nested mode. Then set the 8259A to operate with IR6 masked and specific EOI
mode.

19
5
 Problem-6
Show 8259A interfacing connections with 8086 at the address 074x. Write an ALP
to initialize the 8259A in single level triggered mode non buffered on special fully
nested mode. Then set the 8259A to operate with IR6 masked and specific EOI
mode. Vector address of IR1is 81H.
 Problem-6
Show 8259A interfacing connections with 8086 at the address 074x. Write an ALP
to initialize the 8259A in single level triggered mode non buffered on special fully
nested mode. Then set the 8259A to operate with IR6 masked and specific EOI
mode. Vector address of IR1is 81H.

19
7
 Problem-6
Show 8259A interfacing connections with 8086 at the address 074x. Write an ALP
to initialize the 8259A in single level triggered mode non buffered on special fully
nested mode. Then set the 8259A to operate with IR6 masked and specific EOI
mode. Vector address of IR1is 81H.
 Problem-6
INTERRUPT PROC NEAR
MOV AL, AFH ; Loading ICW1 to AL
MOV DX, 0740H ; Loading Address of ICW1 to DX (Variable port addressing)
OUT DX, AL ; Sending ICW1 to port (address: 0740H ) of 8259A

MOV DX, 0742H ; address of ICW2

MOV AL, 80H ; Loading ICW2 to AL which select the vector address
MOV DX, AL ; Sending ICW2 to port (address: 0742H ) of 8259A
MOV AL, 11H ; Loading ICW4 to AL

OUT DX, AL ; Sends ICW4 to 0742H

MOV AL, 40H ; Loading OCW1 to AL
OUT DX, AL ; Sends OCW1 to 0742H

19
9
THANK YOU !
[email protected]

HTTPS://SITES.GOOGLE.COM/VIEW/ARVINDK
MICROPROCESSOR AND
INTERFACING
CSE2006

Dr. Arvind Kumar

| School of Electronics Engineering, VIT Vellore |
 • ANALOG-TO-DIGITAL (ADC)
• DIGITAL-TO-ANALOG (DAC) CONVERTERS
 ADC (Analog-to Digital Converter)
Interface with 8086

SOC: Start of Conversion

EOC : End of Conversion
 ADC 0808 / 0809
Block Diagram

Low-cost ADC, Power 15 mW,

Compatible with a wide range of microprocessors. Power Supply 5 V
Moderate speed 100 µs
Moderate accuracy Error + LSB
 ADC 0808 / 0809
Pin Diagram
Successive Approximation ADC
Successive Approximation ADC
Successive Approximation ADC
 ADC 0808 / 0809
Timing Diagram
ADC 0808 / 0809
ADC 0808 / 0809

D7=1; I/O Mode.

D6=0 and D5=0; Port A Mode
.
D4=1; Port A is input port
D3=1; Port C (Upper) is input
D2=0; Port B Mode 0.
D1=0; Port B is output
D0=0; Port C (Lower) is output
 ADC 0804

SOC: Start of Conversion WR’ and CS’

EOC : End of Conversion INTR
 ADC 0804

Permissible range of clock frequencies is 100 KHz - 1460 KHz.

desirable to use a frequency as close as possible to 1460 KHz so
conversion time is minimized
4/27/2021 12
 ADC 0804
Timing Diagram
 DAC0830

• A fairly common and low-cost digital-to-analog converter is the DAC0830.

• An 8-bit converter that transforms an 8-bit binary number into an analog

voltage.

• Other converters are available that convert from 10-, 12-, or 16-bit binary
numbers into analog voltages.
 DAC0830

• The number of voltage steps generated by the converter is equal to the number of binary
input combinations.

– an 8-bit converter generates 256 voltage levels

– a 10-bit converter generates 1024 levels

• The DAC0830 is a medium-speed converter that transforms a

digital input to an analog output in approximately 1.0 µs.
DAC0830
R-2R Ladder DAC
R-2R Ladder DAC
 DAC0830

Because this is an 8-bit converter, its output step voltage is defined as –VREF
(reference voltage), divided by 255. The step voltage is often called the resolution of the
converter
 interfacing Adc with 8086
❖ In most cases, PPI 8255 is used to interface the ADC to the microprocessor
❖ ADC is considered as input device to the microprocessor that sends an
initializing signal to the ADC to start the analog signal conversion
❖ There is a pulse which is called the start of conversion (SOC) signal
❖ A2D conversion is a slow process and the microprocessor has to wait until
the conversion is over.
❖ Once the conversion is over, the end of signal (EOS) is sent to inform the
microprocessor about the same and the result is ready at the output buffer
of ADC
Continued
❖ Issuing SOC, reading EOC, getting the results are all done by PPI 8255
❖ The time taken by the ADC for the conversion of the analog signal to
digital signal is called conversion delay
❖ It can range from a few microseconds to a few hundred milli seconds
❖ Selection of appropriate ADC – speed, resolution and cost factor.
 General algorithm for interfacing
❖ Ensure the stability of the analog input given to the ADC
❖ Issue SOC of ADC
❖ Read EOC to mark the end of conversion
❖ Read the digital output from the output buffer of ADC
❖ The analog input must be a constant value from the start to end of
conversion process
❖ This is done using a sampling and hold circuit
❖ The 8086 gives the hold signal to the sample and hold circuit
ADC 0808/0809
❖ Successive optimization converters – one of the fastest techniques
❖ Conversion delay is 100 microsecs for 640kHz
❖ Do not need an external zero or full scale adjustments
❖ 8 input analog signals can be provided
❖ Out of these 8 inputs, only 1 input can be selected for conversion by
using address lines ADD A, ADD B and ADD C
Address lines for conversion
Analog I/P Address lines
selected C B A
I/P 0 0 0 0
I/P 1 0 0 1
I/P 2 0 1 0
I/P 3 0 1 1
I/P 4 1 0 0
I/P 5 1 0 1
I/P 6 1 1 0
I/P 7 1 1 1
Pin diagram
Example problem for interfacing
continued
Interfacing 8086 with 0808
Interfacing digital to analog converters
❖ DACs convert binary numbers into their analog equivalent voltages
❖ Applications of DAC
❖Digitally controlled gains
❖Motor speed controls
❖Programmable gain amplifiers
 AD 7523 8-bit multiplying dac
❖ Intersil’s AD 7523 is a 16 pin, multiplying DAC containing R-2R ladder with
R=10 K for digital to analog conversion along with single pole double throw
NMOS switches to connect the digital inputs to the ladder.
 continued
❖ The supply range extends from +5V to +15V
❖ The maximum analog output value is +10V, when all the digital input
values are at logic high state
❖ To save the DAC from negative transients, a Zener diode is connected
between OUT1 and OUT2.
❖ An OPAMP is used as a current-to-voltage converter at the output of
AD 7523 in order to generate an equivalent output voltage for the
current produced.
Example problem to interface dac with 8086
Sawtooth wave
❖ Port A is designed to send the digital data as inputs
to the converter
❖ The ramp starts from 0V and hence AL is moved
with 00H.
❖ To increment the ramp, the value of AL must be
incremented till it reaches FFH
❖ After that the sawtooth again starts from 00H and
this procedure repeats
Dac 0800 8-bit digital to analog converter
❖ DAC 0800 is a monolithic 8-bit DAC manufactured by National
Semiconductor.
❖ It can work at various voltages from 4.8V to 18V, usually, 5V or 12 V
Pin diagram
example
Triangular wave
Interfacing 7-segment display with 8086
Types of 7-segment displays
 continued
7-segment
display

Common anode Common cathode

display display

❖ Basically LEDs have anode and cathode

❖ In Common anode display, anodes of all LEDs are connected to VCC,
cathodes are connected to the microprocessor port via 8255.
❖ In common cathode display, cathodes are connected to VCC and anodes
are connected to the microprocessor port via 8255.
continued

DISPLAY FORMAT
❖ Let us consider common anode display. The connection
table is as follows
❖ Logic 0 – turn on segment, logic 1 – turn off segment
7 – segment display interfacing
Equivalent hex values
Weblink for 7 segment display and 4x4
keyboard interfacing
• https://www.youtube.com/watch?v=Q1I4-8fVShA
• https://www.youtube.com/watch?v=7V69bSFBnVQ

https://nptel.ac.in/content/storage2/courses/106108100/pdf/T
eacher_Slides/mod3/M3L7.pdf
THANK YOU !
[email protected]

HTTPS://SITES.GOOGLE.COM/VIEW/ARVINDK
Peripheral Interfacing
 Data Communications
• Data communications refers to the ability of one computer to exchange
data with another computer or a peripheral
• Physically, the data comm. path may be a short, 5 to 10 feet ribbon cable
connecting a microcomputer and parallel printer; or it might be a high
speed telecommunications port connecting two computers thousands of
miles apart.
• Standard data communication interfaces and standards are needed
• Centronic’s parallel printer interface
• RS-232 defines a serial communications standard
• We focus on serial I/O this week
• 8251 USART (Universal Synchronous/Asynchronous
Receiver/Transmitter) is the key component for converting parallel data
to serial form and vice versa
• Two types of serial data communications are widely used
– Asynchronous communications
– Synchronous communications
Types of Transmission
 Asynchronous Communications

• Eliminates the need for a clock signal between

two microprocessor based systems
Transmit data

Receive data

System 1 Signal common System 2

 Asynchronous Communications

• Data to be transmitted is sent out one

character at a time and the receiver end of the
communication line synchronization is
performed by examining synchronization bits
that are included at the beginning and at the
end of each character
 8251
• The 8251A is a programmable serial
communication interface chip designed for
synchronous and asynchronous serial
data communication.
• It supports the serial transmission of data.
• It is packed in a 28 pin DIP.
Pin details
 Pin Description

D0
parallel data
- D7

C/D Control register or Data buffer select

RD Read Control

WR Write control

CS Chip Select

CLK clock pulse

RESET Reset

TxC Transmitter Clock

TxD transmitted data

RxC Receiver Clock

RxD Receiver Data

RxRDY Receiver Ready

TxRDY Transmitter Ready

DSR Data Set Ready

DTR Data Terminal Ready

SYNDET/ Synchronous Detect/

BRKDET DetectBreak

RTS Request to send Data

CTS Clear to send Data

TxEMPTY Transmitter Empty

Vcc Vcc (5V)

GND
Ground(0V)
 2 Signal Description of 8251

D0 – D7: This is an 8-bit data bus used to read or write status, command
word or data from or to the 8251A.

C / D: (Control Word/Data): This input pin, together with RD and WR

inputs, informs the 8251A that the word on the data bus is either a data or
control word/status information. If this pin is 1, control / status is on the bus,
otherwise data is on the bus.

RD: This active-low input to 8251A is used to inform it that the CPU is
reading either data or status information from its internal registers. This
active-low input to 8251A is used to inform it that the CPU is writing data or
control word to 8251A.

WR: This is an active-low chip select input of 825lA. If it is high, no read or

write operation can be carried out on 8251. The data bus is tristated if this
pin is high.
CLK: This input is used to generate internal device timings and is normally
connected to clock generator output. This input frequency should be at least
30 times greater than the receiver or transmitter data bit transfer rate.
RESET: A high on this input forces the 8251A into an idle state. The device will
remain idle till this input signal again goes low and a new set of control word is
written into it. The minimum required reset pulse width is 6 clock states, for the
proper reset operation.

TXC (Transmitter Clock Input): This transmitter clock input controls the rate
at which the character is to be transmitted. The serial data is shifted out on the
successive negative edge of the TXC.

TXD (Transmitted Data Output): This output pin carries serial stream of the
transmitted data bits along with other information like start bit, stop bits and
parity bit, etc.

RXC (Receiver Clock Input): This receiver clock input pin controls the rate at
which the character is to be received.

RXD (Receive Data Input): This input pin of 8251A receives a composite
stream of the data to be received by 8251 A.
RXD (Receive Data Input): This input pin of 8251A receives a
composite stream of the data to be received by 8251 A.

RXRDY (Receiver Ready Output): This output indicates that the 8251A
contains a character to be read by the CPU.

TXRDY - Transmitter Ready: This output signal indicates to the CPU

that the internal circuit of the transmitter is ready to accept a new
character for transmission from the CPU.
DSR - Data Set Ready: This is normally used to check if data set is ready
when communicating with a modem.
DTR - Data Terminal Ready: This is used to indicate that the device is
ready to accept data when the 8251 is communicating with a modem.

RTS - Request to Send Data: This signal is used to communicate with a

modem.
TXE- Transmitter Empty: The TXE signal can be used to indicate the
end of a transmission mode.
Architecture
 Arch - details
• The functional block diagram of 825 1A
consists five sections.
They are:
• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control.
 Read/Write control logic
• The Read/Write Control logic interfaces the
8251A with CPU, determines the functions of the
8251A according to the control word written into
its control register.
• It monitors the data flow.
• This section has three registers and they are
control register, status register and data buffer.
• The active low signals RD, WR, CS and
C/D(Low) are used for read/write operations with
these three registers.
 Read/Write control logic
• When C/D(low) is high, the control register is
selected for writing control word or reading
status word.
• When C/D(low) is low, the data buffer is selected
for read/write operation.
• When the reset is high, it forces 8251A into the
idle mode.
• The clock input is necessary for 8251A for
communication with CPU and this clock does not
control either the serial transmission or the
reception rate.
 Transmitter
• The transmitter section accepts parallel data
from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it
has a buffer register to hold an 8-bit parallel data
and another register called output register to
convert the parallel data into serial bits.
• When output register is empty, the data is
transferred from buffer to output register. Now
the processor can again load another data in
buffer register.
 Transmitter
• If buffer register is empty, then TxRDY is goes to
high.
• If output register is empty then TxEMPTY goes to
high.
• The clock signal, TxC (low) controls the rate at
which the bits are transmitted by the USART.
• The clock frequency can be 1,16 or 64 times the
baud rate.
 Receiver
• The receiver section accepts serial data and
convert them into parallel data
• The receiver section is double buffered, i.e., it
has an input register to receive serial data and
convert to parallel, and a buffer register to hold
the parallel data.
• When the RxD line goes low, the control logic
assumes it as a START bit, waits for half a bit
time and samples the line again.
• If the line is still low, then the input register
accepts the following bits, forms a character and
loads it into the buffer register.
 Receiver
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits
are received by the USART.
• During asynchronous mode, the signal
SYNDET/BRKDET will indicate the break in the data
transmission.
• During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
 Modem control
• The MODEM control unit allows to interface a MODEM to 8251A
and to establish data communication through MODEM over
telephone lines.
• This unit takes care of handshake signals for MODEM interface.
• The 825 1A can be either memory mapped or I/O mapped in the
system.
• 8251A in I/O mapped in the system is shown in the figure.
• Using a 3-to-8 decoder generates the chip select signals for I/O
mapped devices.
• The address lines A4, A5 and A6 are decoded to generate eight chip
select signals (IOCS-0 to IOCS-7) and in this, the chip select signal
IOCS-2 is used to select 8251A.
• The address line A7 and the control signal IO / M(low) are used as
enable for decoder.
• The address line A0 of 8085 is connected to C/D(low) of 8251A to
provide the internal addresses.
8251 interfaced with 8085
 Modem control
• The data lines D0 - D7 are connected to D0 - D7 of the
processor to achieve parallel data transfer.
• The RESET and clock signals are supplied by the
processor. Here the processor clock is directly
connected to 8251A. This clock controls the parallel data
transfer between the processor and 8251A.
• The output clock signal of 8085 is divided by suitable
clock dividers like programmable timer 8254 and then
used as clock for serial transmission and reception.
 Modem control
• The TTL logic levels of the serial data lines and the
control signals necessary for serial transmission and
reception are converted to RS232 logic levels using
MAX232 and then terminated on a standard 9-pin D-
.type connector.
• In 8251A the transmission and reception baud rates can
be different or same.
• The device which requires serial communication with
processor can be connected to this 9-pin D-type
connector using 9-core cable
• The signals TxEMPTY, TxRDY and RxRDY can be used
as interrupt signals to initiate interrupt driven data
transfer scheme between processor and 8251
 Modem control
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits
are received by the USART.
• During asynchronous mode, the signal
SYNDET/BRKDET will indicate the break in the data
transmission.
• During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
A0 RD WR Task Port Address

0 0 1 Read Data Word 90H

0 1 0 Write Data Word 90H

1 0 1 Read Status Word 91H

1 1 0 Write Control Word 91H

 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
8251 command register

EH IR RTS ER SBRK RxE DTR TxE

TxE: transmit enable

DTR: data terminal ready
RxE: receiver enable
SBPRK: send break character
ER: error reset
RTS: request to send
IR: internal reset
EH: enter hunt mode
 8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
8251 interfaced with 8085
 8251
• The 8251A is a programmable serial
communication interface chip designed for
synchronous and asynchronous serial
data communication.
• It supports the serial transmission of data.
• It is packed in a 28 pin DIP.
Pin details
Architecture
 Arch - details
• The functional block diagram of 825 1A
consists five sections.
They are:
• Read/Write control logic
• Transmitter
• Receiver
• Data bus buffer
• Modem control.
 Read/Write control logic
• The Read/Write Control logic interfaces the
8251A with CPU, determines the functions of the
8251A according to the control word written into
its control register.
• It monitors the data flow.
• This section has three registers and they are
control register, status register and data buffer.
• The active low signals RD, WR, CS and
C/D(Low) are used for read/write operations with
these three registers.
 Read/Write control logic
• When C/D(low) is high, the control register is
selected for writing control word or reading
status word.
• When C/D(low) is low, the data buffer is selected
for read/write operation.
• When the reset is high, it forces 8251A into the
idle mode.
• The clock input is necessary for 8251A for
communication with CPU and this clock does not
control either the serial transmission or the
reception rate.
 Transmitter
• The transmitter section accepts parallel data
from CPU and converts them into serial data.
• The transmitter section is double buffered, i.e., it
has a buffer register to hold an 8-bit parallel data
and another register called output register to
convert the parallel data into serial bits.
• When output register is empty, the data is
transferred from buffer to output register. Now
the processor can again load another data in
buffer register.
 Transmitter
• If buffer register is empty, then TxRDY is goes to
high.
• If output register is empty then TxEMPTY goes to
high.
• The clock signal, TxC (low) controls the rate at
which the bits are transmitted by the USART.
• The clock frequency can be 1,16 or 64 times the
baud rate.
 Receiver
• The receiver section accepts serial data and
convert them into parallel data
• The receiver section is double buffered, i.e., it
has an input register to receive serial data and
convert to parallel, and a buffer register to hold
the parallel data.
• When the RxD line goes low, the control logic
assumes it as a START bit, waits for half a bit
time and samples the line again.
• If the line is still low, then the input register
accepts the following bits, forms a character and
loads it into the buffer register.
 Receiver
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits
are received by the USART.
• During asynchronous mode, the signal
SYNDET/BRKDET will indicate the break in the data
transmission.
• During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
 Modem control
• The MODEM control unit allows to interface a MODEM to 8251A
and to establish data communication through MODEM over
telephone lines.
• This unit takes care of handshake signals for MODEM interface.
• The 825 1A can be either memory mapped or I/O mapped in the
system.
• 8251A in I/O mapped in the system is shown in the figure.
• Using a 3-to-8 decoder generates the chip select signals for I/O
mapped devices.
• The address lines A4, A5 and A6 are decoded to generate eight chip
select signals (IOCS-0 to IOCS-7) and in this, the chip select signal
IOCS-2 is used to select 8251A.
• The address line A7 and the control signal IO / M(low) are used as
enable for decoder.
• The address line A0 of 8085 is connected to C/D(low) of 8251A to
provide the internal addresses.
 Modem control
• The data lines D0 - D7 are connected to D0 - D7 of the
processor to achieve parallel data transfer.
• The RESET and clock signals are supplied by the
processor. Here the processor clock is directly
connected to 8251A. This clock controls the parallel data
transfer between the processor and 8251A.
• The output clock signal of 8085 is divided by suitable
clock dividers like programmable timer 8254 and then
used as clock for serial transmission and reception.
 Modem control
• The TTL logic levels of the serial data lines and the
control signals necessary for serial transmission and
reception are converted to RS232 logic levels using
MAX232 and then terminated on a standard 9-pin D-
.type connector.
• In 8251A the transmission and reception baud rates can
be different or same.
• The device which requires serial communication with
processor can be connected to this 9-pin D-type
connector using 9-core cable
• The signals TxEMPTY, TxRDY and RxRDY can be used
as interrupt signals to initiate interrupt driven data
transfer scheme between processor and 8251
 Modem control
• The CPU reads the parallel data from the buffer register.
• When the input register loads a parallel data to buffer
register, the RxRDY line goes high.
• The clock signal RxC (low) controls the rate at which bits
are received by the USART.
• During asynchronous mode, the signal
SYNDET/BRKDET will indicate the break in the data
transmission.
• During synchronous mode, the signal SYNDET/BRKDET
will indicate the reception of synchronous character.
 8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Baud Rate

Stop bits Parity enable
0: disable 00: Syn. Mode
00: invalid 1: enable 01: x1 clock
01: 1 bit 10: x16 clock
10: 1.5 bits Character length 11: x64 clock
11: 2 bits
00: 5 bits
01: 6 bits
Parity 10: 7 bits
0: odd 11: 8 bits
1: even
8251 command register

EH IR RTS ER SBRK RxE DTR TxE

TxE: transmit enable

DTR: data terminal ready
RxE: receiver enable
SBPRK: send break character
ER: error reset
RTS: request to send
IR: internal reset
EH: enter hunt mode
 8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY

TxRDY: transmit ready

RxRDY: receiver ready
TxEMPTY: transmitter empty
PE: parity error
OE: overrun error
FE: framing error
SYNDET: sync. character detected
DSR: data set ready
8251 interfaced with 8085
 8255 PPI

• PPI
Programmable Peripheral
Interface

20
 Intel 8255 PPI
PPI – Programmable Peripheral Interface
It is an I/O port chip used for interfacing I/O
devices with microprocessor
Very commonly used peripheral chip
Knowledge of 8255 essential for students in the
Microprocessors lab for Interfacing experiments

21
 About 82C55
• The 82C55 is a popular interfacing component, that
can interface any TTL-compatible I/O device to a
microprocessor.
• It is used to interface to the keyboard and a parallel
printer port in PCs (usually as part of an integrated
chipset).
• Requires insertion of wait states if used with a
microprocessor using higher that an 8 MHz clock.
• PPI has 24 pins for I/O that are programmable in
groups of 12 pins and has three distinct modes of
operation.
82C55 : Pin Layout
8255 Control Word
Basic Mode Definitions and Bus
Int

• Mode 0
– Basic I/O
• Mode 1
– Strobe I/O
• Mode 2
– Bi-Dir Bus
 Programming 8255
 8255 has three operation modes: mode 0, mode 1, and mode 2

11-26
27
8255 PPI contd.
3 ports in 8255 from user’s point of view
- Port A, Port B and Port C.
Port C composed of two independent 4-bit ports
- PC7-4 (PC Upper) and PC3-0 (PC Lower)
A1 A0 Selected port
0 0 Port A
0 1 Port B
1 0 Port C
1 1 Control port
28
 8255 40 pin DIP

Intel 8255 PPI Vcc (+5V)

PA7-0
GND Port A
Chip Select Circuit RD
U2A
WR PC7-4
1 2 1 U1
2
3 CS Port C PC3-0
7404 4
A7 8
5 D7-0 Control Port
U3A 6 PB7-0
11
1 2 12
7430 A1 Port B

7404 A0
M/IO*
Reset

A7=0, A6=1, A5=1, A4=1, A3=1, A2=1, & M/IO*= 0

29
8255 PPI Contd.
There is also a Control port from the Processor point
of view. Its contents decides the working of 8255.
When CS (Chip select) is 0, 8255 is selected for
communication by the processor. The chip select
circuit connected to the CS pin assigns addresses to
the ports of 8255.
For the chip select circuit shown, the chip is selected
when A7=0, A6=1, A5=1, A4=1, A3=1, A2=1, & M/IO*= 0
Port A, Port B, Port C and Control port will have the
addresses as 7CH, 7DH, 7EH, and 7FH respectively.
30
 8255 PPI Contd.
Mode 0: Simple Input or Output

In this mode, ports A, B are used as two simple 8-bit I/O ports
port C as two 4-bit ports.
Each port can be programmed to function as simply an input port or
an output port. The input/output features in Mode 0 are as follows.

1. Outputs are latched.

2. Inputs are not latched.

3. Ports don’t have handshake or interrupt capability.

31
 8255 PPI Contd.
Mode 1: Input or Output with Handshake

In this mode, handshake signals are exchanged between

the MPU and peripherals prior to data transfer.
The features of the mode include the following:

1. Two ports (A and B) function as 8-bit I/O ports.

They can be configured as either as input or output ports.

2. Each port uses three lines from ort C as handshake signals.

The remaining two lines of Port C can be used for simple I/O operations.

3. Input and Output data are latched.

4. Interrupt logic is supported.

32
 8255 PPI Contd.
Mode 2: Bidirectional Data Transfer

This mode is used primarily in applications such as data transfer

between two computers.

In this mode, Port A can be configured as the bidirectional port

Port B either in Mode 0 or Mode 1.

Port A uses five signals from Port C

as handshake signals for data transfer.

The remaining three signals from port C can be used either

as simple I/O or as handshake for port B.

33
 8255 Handshake signals

Where are the Handshake signals?

Port C pins act as handshake signals, when Port A
and Port B are configured for other than Mode 0.
Port A in Mode 2 and Port B in Mode 1 is possible,
as it needs only 5+3 = 8 handshake signals
After Reset of 8255, Port A , Port B , and Port C are
configured for Mode 0 operation as input ports.

34
8255 Handshake signals Contd.

PC2-0 are used as handshake signals by Port B

when configured in Mode 1. This is immaterial
whether Port B is configured as i/p or o/p port.
PC5-3 are used as handshake signals by Port A
when configured as i/p port in Mode 1.
PC7,6,3 are used as handshake signals by Port A
when configured as o/p port in Mode 1.
PC7-3 are used as handshake signals by Port A
when configured in Mode 2.
35
8255 PPI Contd.
Port A can work in Mode 0, Mode 1, or Mode 2
Port B can work in Mode 0, or Mode 1
Port C can work in Mode 0 only, if at all

Port A, Port B and Port C can work in Mode 0

Port A and Port B can work in Mode 1
Only Port A can work in Mode 2

36
8255 MD Control word
Control port having Mode Definition (MD) control word
1 M2A M1A I/P A I/P CU M1B I/P B I/P CL
Means Mode
1 - PCU as input 1 -PCL as input
Definition
control word 0 - PCU as output 0 -PCL as output
1 - PA as input 1 - PB as input
M2A M1A 0 - PA as output 0 - PB as output
0 0 Port A in Mode 0 1 – Port B in Mode 1
0 1 Port A in Mode 1 0 – Port B in Mode 0
1 0/1 Port A in Mode 2
37
8255 MD Control word Contd.
Ex. 1: Configure Port A as i/p in Mode 0, Port B as o/p in
mode 0, Port C (Lower) as o/p and Port C (Upper) as i/p
ports.
Required MD control word:
1 0 0 1 1 0 0 0 = 98H
MD control PC Lower as o/p
PA in Mode 0 PB as o/p Reqd. instrns.
PA as i/p PB in Mode 0 MOV AL, 98H
PC Upper as i/p OUT 7FH, AL
38
8255 MD Control word Contd.
Ex. 2: Configure Port A as i/p in Mode 1, Port B as o/p in
mode 1, Port C7-8 as i/p ports. (PC5-0 are handshake lines,
some i/p lines and others o/p. So they are shown as X)
Required MD control word:
1 0 1 1 1 1 0 X = BCH or BDH
MD control PC3-0 as don’t care
PA in Mode 1 PB as o/p Reqd. Instrns.
PA as i/p PB in Mode 1 MOV AL,BCH
PC Upper(C7-8) as i/p OUT 7FH, AL
39
8255 Contd.
There are 2 control words in 8255
Mode Definition (MD) Control word and
Port C Bit Set / Reset (PCBSR) Control Word

MD control word configures the ports of 8255

- as i/p or o/p in Mode 0, 1, or 2

PCBSR control word is used to set to 1 or reset to 0

any one selected bit of Port C

40
8255 MD Control word Contd.
Ex. 3:Configure Port A in Mode 2, Port B as o/p in mode 1.
(PC5-0 are handshake lines for Port A and PC2-0 are
handshake signals for port B)
Required MD control word:
1 1 0 X X 1 0 X = C4H / C5H..
MD control PC3-0 as handshake
PA in Mode 2 PB as o/p Reqd. instrns.
PA bidirectional PB in Mode 1 MOV AL, C4H
PC7-0 as handshake OUT 7FH, AL
41
8255 PCBSR Control word
Control port having Port C Bit Set / Reset control word
0 X X X SB2 SB1 SB0 S/R*
Select bit of PC 1 - Set to 1
PC bit set
Don’t to be set / reset 0 - Reset to 0
/ reset
cares 0 0 0 Bit 0 of Port C
control
word 0 0 1 Bit 1 of Port C
:
:
1 1 1 Bit 7 of Port C
42
 8253 / 8254 Timer
• To program a given counter to divide the
CLK input frequency, one must send the
divisor to that specific counter’s register.
• Although all three counters share the same
control register, the divisor registers are
separate for each counter
• Example: given the port addresses for
8253/54: Counter 0: 94H Counter 1:
95H
Counter 2: 96H Engr 4862 Microprocessors
Control Reg: 97H
 8253 / 8254 Timer
• Task1: program counter 0 for binary counter
for mode 3 to divide CLK0 by number 4282
(BCD)
MOV AL, 0011 0111B
OUT 97H, AL
MOV AX, 4282H (BCD needs H)
OUT 94H, AL (Low Byte)
MOV AL, AH
OUT 94H, AL (High Byte)
• OUT0 = CLK0 /Engr
42824862 Microprocessors
 Shape of the 8253/54 Output
• Given CLK = 1.193 MHz, the clock period of
input frequency is 838 ns
• If the number N loaded into the counter is
even, both high and low pulse are the same
length, which is N/2 * 838 ns
• If the number N loaded into the counter is
odd, the high pulse is (N+1)/2 * 838 ns and
the low pulse is (N–1)/2 * 838 ns
•  If N is odd, the high portion of the output
square wave is slightly wider than the low
portion Engr 4862 Microprocessors
 8253/54 Operation Modes
• Mode 0: Interrupt on terminal count
– The output is initially low, and remain low for the
duration of the count if GATE=1. When the
terminal count is reached, the output will go
high and remain high until a new control word
or new count number is loaded
• Width of low pulse = N * T, where T is clock period
– Example: GATE=1 and CLK = 1 MHz
Clock count N = 1000

Engr 4862 Microprocessors

 8253/54 Operation Modes
• Mode 0: Interrupt on terminal count
– If GATE becomes low at the middle of the count,
the count will stop and the output will be low. The
count resumes when the GATE becomes high
again  This in effect adds to the total time the
output is low.
• Mode 1: HW triggered / programmable one
shot
– The triggering must be done through the GATE
input by sending a 0-to-1 pulse to it.
– Steps: 1) Load the count register
2) A 0-to-1 pulse
Engr 4862 must be sent to the
Microprocessors

GATE input to trigger the count

 8253/54 Operation Modes
• Mode 1: HW triggered / programmable one
shot
– In Mode 1, after sending the 0-to-1 pulse to
GATE, OUT becomes low and stays low for a
duration of N*T, then becomes high and stays
high until the GATE is triggered again
– If during the activation, a retriggered happened,
then restart the down counting
• Mode 2: Rate Generator (Divide-by-N
counter)
– In Mode2, if GATE=1, OUT will be high for N*T,
goes low only for one clock pulse,
Engr 4862 Microprocessors
then counter is
reloaded automatically, and the process
 8253/54 Operation Modes
• Mode 3: Square wave rate generator
– Most commonly used
• Mode 4: Software triggered strobe
– Similar to Mode2, except that the counter is not
reloaded automatically
– In Mode4, if GATE=1, the output will go high
when loading the count, it will stay high for
duration N*T. After the count reaches zero, it
becomes low for one clock pulse, then goes high
again and stays high until a new command word
or new count is loaded
– To repeat the strobe, the count must be reloaded
Engr 4862 Microprocessors
 8253/54 Operation Modes
• Mode 5: Hardware triggered strobe
– Similar to Mode4, except that the triggering must
be done with the GATE input
– The count starts only when a 0-to-1 pulse is sent
to the GATE input
– If GATE retriggered during the counting, it will
restart the down counting

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

8253 / 8254 Timer

Engr 4862 Microprocessors

 8259
• 8259 is Programmable Interrupt Controller (PIC)
• It is a tool for managing the interrupt requests.
• 8259 is a very flexible peripheral controller
chip:PIC can deal with up to 64 interrupt
inputs
– interrupts can be masked
– various priority schemes can also programmed.
• originally (in PC XT) it is available as a
separate IC
• Later the functionality of (two PICs) is in the
motherboards chipset.
 Pin description
• 8-bit bi-directional data bus, one address line is
needed,the direction of data flow is controlled by RD
and WR.
• CS is as usual connected to the output of the address
decoder.
• Interrupt requests are output on INT which is
connected to the INTR of the processor. Int.
acknowledgment is received by INTA.
• IR0-IR7 allow 8 separate interrupt requests to be
inputted to the PIC.
• sp/en=1 for master , sp/en=0 for slave.
• CAS0-3 inputs/outputs are used when more than one
PIC to cascaded.
FIGURE 9-4 Block diagram and pin definitions for the 8259A Programmable Interrupt Controller (PIC). (Courtesy of Intel
Corporation.)
FIGURE 9-5 Interfacing the PIC to the 386 and 486 processors. Two I/O ports are required.
FIGURE 9-7 All interrupt requests must pass through the PIC’s interrupt request register (IRR) and interrupt mask register
(IMR). If put in service, the appropriate bit of the in-service (IS) register is set.
Example of two cascaded
PICs
 OPERATION
• PIC is to be initialized and programmed to
control its operation.
• The operation in simple words:
When an interrupt occurs , the PIC determines the highest
priority, activates the processor via its INTR input, and
sends the type number onto the data bus when the
processor acknowledges the interrupt.
• Priority:
What is used in PC is fully nested mode. That is the
lowest numbered IRQ input has highest priority.
Lower priority interrupts will not be forwarded to the
processor until the higher priority interrupts have
been serviced.
FIGURE 9-8 (a) Simultaneous interrupt requests arrive on IR4 and IR6. IR4 has highest priority and its IS bit is set as the IR4
service routine is put in service. (b) The IR4 service routine issues a rotate-on-nonspecific-EOI command, resetting IS4 and
assigning it lowest priority. IR6 is now placed in service. (c) The IR6 service routine issues a rotate-on-nonspecific-EOI
command, resetting IS6 and assigning it lowest priority.

John Uffenbeck
The 80x86 Family: Design, Copyright ©2002 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Programming, and Interfacing, 3e All rights reserved.
FIGURE 9-9 Example illustrating the difference between the rotate-on-nonspecific-EOI command and the rotate-on-specific-
EOI command.
 Modes
• Fully Nested mode
• Special Fully Nested mode
• Nonspecific Rotating
• Specific Rotating
• Special Mask
• Polling
FIGURE 9-11 8259A initialization control word format. (Courtesy of Intel Corporation.)

John Uffenbeck
The 80x86 Family: Design, Copyright ©2002 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
Programming, and Interfacing, 3e All rights reserved.
 Features of 8279
The important features of 8279 are,
• Simultaneous keyboard and display operations.
• Scanned keyboard mode.
• Scanned sensor mode.
• 8-character keyboard FIFO.
• 1 6-character display.
• Right or left entry 1 6-byte display RAM.
• Programmable scan timing.
 Pin details

• A0: Selects data (0) or control/status (1) for

reads and writes between micro and 8279.

Output that blanks the displays.

• CLK: Used internally for timing. Max is 3 MHz.

• CN/ST: Control/strobe, connected to the control

key on the keyboard.

• Chip select that enables programming,

reading the keyboard, etc.

• DB7-DB0: Consists of bi-directional pins that

connect to data bus on micro.
 Pin details
• IRQ: Interrupt request, becomes 1 when a key
is pressed, data is available.
• OUT A3-A0/B3-B0: Outputs that sends data to
the most significant/least significant nibble of
display.

• : Connects to micro's IORC or RD

signal, reads data/status registers.
• RESET: Connects to system RESET.
• RL7-RL0: Return lines are inputs used to sense
key depression in the keyboard matrix.
•Shift: Shift connects to Shift key on keyboard.
• SL3-SL0: Scan line outputs scan both the
keyboard and displays.
Block diagram of 8279
 Sections
• Keyboard
• Display
• Scan
• CPU interface
 Keyboard section
• The keyboard section consists of eight return lines RL0 - RL7
that can be used to form the columns of a keyboard matrix.
• It has two additional input : shift and control/strobe. The keys
are automatically debounced.
• The two operating modes of keyboard section are 2-key
lockout and N-key rollover.
• In the 2-key lockout mode, if two keys are pressed
simultaneously, only the first key is recognized.
• In the N-key rollover mode simultaneous keys are recognized
and their codes are stored in FIFO.
• The keyboard section also have an 8 x 8 FIFO (First In First
Out) RAM.
• The FIFO can store eight key codes in the scan keyboard
mode. The status of the shift key and control key are also
stored along with key code.
• The 8279 generate an interrupt signal when there is an entry
in FIFO.
 Display section
• The display section has eight output lines divided into
two groups A0-A3 and B0-B3.
• The output lines can be used either as a single group of
eight lines or as two groups of four lines, in conjunction
with the scan lines for a multiplexed display.
• The output lines are connected to the anodes through
driver transistor in case of common cathode 7-segment
LEDs.
• The cathodes are connected to scan lines through driver
transistors.
• The display can be blanked by BD (low) line.
• The display section consists of 16 x 8 display RAM. The
CPU can read from or write into any location of the
display RAM.
 Scan section
• The scan section has a scan counter and four
scan lines, SL0 to SL3.
• In decoded scan mode, the output of scan lines
will be similar to a 2-to-4 decoder.
• In encoded scan mode, the output of scan lines
will be binary count, and so an external decoder
should be used to convert the binary count to
decoded output.
• The scan lines are common for keyboard and
display.
• The scan lines are used to form the rows of a
matrix keyboard and also connected to digit
drivers of a multiplexed display, to turn ON/OFF.
 CPU interface section
• The CPU interface section takes care of data transfer
between 8279 and the processor.
• This section has eight bidirectional data lines DB0 to
DB7 for data transfer between 8279 and CPU.
• It requires two internal address A =0 for selecting data
buffer and A = 1 for selecting control register of8279.
• The control signals WR (low), RD (low), CS (low) and A0
are used for read/write to 8279.
• It has an interrupt request line IRQ, for interrupt driven
data transfer with processor.
• The 8279 require an internal clock frequency of 100 kHz.
This can be obtained by dividing the input clock by an
internal prescaler.
• The RESET signal sets the 8279 in 16-character display
with two -key lockout keyboard modes.
Control Word Description:

First three bits given below select one of 8 control registers

(opcode).

 000DDMMM
Mode set: Opcode 000.
DD sets displays mode.
MMM sets keyboard mode.

DD field selects either:

• 8- or 16-digit display
• Whether new data are entered
to the rightmost or leftmost
display position.
Control Word Description:
MMM field:

MMM

• Encoded Mode: SL outputs are active-high, follow binary

bit pattern 0-7 or 0-15 depending on 8 or 16 digit display.
• Decoded Mode: SL outputs are active-low (only one of
the four outputs will be low at any time).Pattern output:
1110, 1101, 1011, 0111.
 I/O Interface
Control Word Description:

• Strobe : An active high pulse on the CN/ST input pin strobes

data from the RL pins into an internal FIFO for reading by micro
later.
• 2-key lockout/N-key rollover: Prevents 2 keys from being
recognized if pressed simultaneously/Accepts all keys pressed
from 1st to last.
 Write display format

 100ZAAAA

write display Selects address – to write address of one of the

Display. Z selects auto-increment so subsequent writes go to
subsequent display positions.
 Clear Display format
• 1100CCFA
• The clear control word clears the
display, FIFO or both
• Bit F clears FIFO and the display RAM
status, and sets address pointer to 000.
• If CC are 00 or 01, all display RAM
locations become 00000000.
• If CC is 10, --> 00100000,
• if CC is 11, --> 11111111.
 Basic DMA concept
Direct memory access (DMA) is a feature of
modern computer systems that allows certain
hardware subsystems to read/write data to/from
memory without microprocessor intervention,
allowing the processor to do other work.
Used in disk controllers, video/sound cards etc,
or between memory locations.
Typically, the CPU initiates DMA transfer, does
other operations while the transfer is in progress,
and receives an interrupt from the DMA controller
once the operation is complete.
Can create cache coherency problems (the data
in the cache may be different from the data in the
external memory after DMA)
86
 The 8237 DMA controller
 Supplies memory and I/O with control signals and addresses
during DMA transfer
 4-channels (expandable)
 0: DRAM refresh
 1: Free
 2: Floppy disk controller
 3: Free
 1.6MByte/sec transfer rate
 64 KByte section of memory address capability with single
programming
 “fly-by” controller (data does not pass through the DMA-only
memory to I/O transfer capability)
 Initialization involves writing into each channel:
i) The address of the first byte of the block of data that must be
transferred (called the base address).
ii) The number of bytes to be transferred (called the word count).

87
 8237 pins
 CLK: System clock
 CS΄: Chip select (decoder output)
 RESET: Clears registers, sets mask register
 READY: 0 for inserting wait states
 HLDA: Signals that the μp has relinquished buses
 DREQ3 – DREQ0: DMA request input for each channel
 DB7-DB0: Data bus pins
 IOR΄: Bidirectional pin used during programming
and during a DMA write cycle
 IOW΄: Bidirectional pin used during programming
and during a DMA read cycle
 EOP΄: End of process is a bidirectional signal used as input to terminate
a
DMA process or as output to signal the end of the DMA transfer
 A3-A0: Address pins for selecting internal registers
 A7-A4: Outputs that provide part of the DMA transfer address
 HRQ: DMA request output
 DACK3-DACK0: DMA acknowledge for each channel.
 AEN: Address enable signal
 ADSTB: Address strobe
 MEMR΄: Memory read output used in DMA read cycle
 MEMW΄: Memory write output used in DMA write cycle

88
8237 pin
Diagram

89
A 8237 DMA application

DMA ARCHITECTURE
90
 8237 registers
• CAR (Current Address Register): holds the 16-bit
memory address used for the DMA transfer (one
for each channel), either incremented or
decremented during the operation
• CWCR (Current Word Count Register): Programs a
channel for the number of bytes (up to 64K)
transferred during a DMA operation
• BA (Base Address) and WC (Word Count): Used
when auto-initialization is selected for a channel, to
reload the CAR and CWCR when DMA is
complete.
• CR (Command Register): Programs the operation
of the controller 91
• MR (Mode Register):

• Programs the mode of

operation for a channel (one
for each channel).

92
• MR (Mask
Register):

• SR (Status
Register): Shows
the status of each
DMA channel
93
8237 Software commands

94
 8237 Software commands
 Clear First/Last Flip-Flop - This command is executed prior to writing or reading
new address or word count information to the 82C37. This command initializes the
flipflop to a known state (low byte first) so that subsequent accesses to register
contents by the microprocessor will address upper and lower bytes in the correct
sequence.
 Set First/Last Flip-Flop - This command will set the flip-flop to select the high byte
first on read and write operations to address and word count registers.
 Master Clear - This software instruction has the same effect as the hardware
Reset. The Command, Status, Request, and Temporary registers, and Internal
First/Last Flip-Flop and mode register counter are cleared and the Mask register is
set. The 82C37A will enter the idle cycle.
 Clear Mask Register - This command clears the mask bits of all four channels,
enabling them to accept DMA requests.
 Clear Mode Register Counter - Since only one address location is available for
reading the Mode registers, an internal two-bit counter has been included to select
Mode registers during read operation. To read the Mode registers, first execute the
Clear Mode Register Counter command, then do consecutive reads until the
desired channel is read. Read order is channel 0 first, channel 3 last. The lower
two bits on all Mode registers will read as ones.

95
8237 block diagram

96
 Initiating a DMA transaction
 Save the current interrupt status and disable
interrupts by executing the CLI instruction
 Disable the channel that will be used for the
transaction
 Reset the flip-flop by writing a value of 0X to the
register
 Set the Mode Register
 Set the Page Register
 Set the Offset Register
 Set the Block Size Register
 Enable the channel that will be used for the
transaction
 Restore the interrupt status
97
 A/D Interfacing

• After the conversion is over, the ADC sends end

of conversion EOC signal to inform the
microprocessor that the conversion is over and
the result is ready at the output buffer of the
ADC.

• These tasks of issuing an SOC pulse to ADC,

reading EOC signal from the ADC and reading
the digital output of the ADC are carried out by
the CPU using 8255 I/O ports.
 A/D Interfacing
• The time taken by the ADC from the active
edge of SOC pulse till the active edge of
EOC signal is called as the conversion
delay of the ADC.
• Successive approximation techniques and
dual slope integration techniques are the
most popular techniques used in the
integrated ADC chip.
• The analog to digital converter chips 0808
and 0809 are 8-bit CMOS, successive
approximation converters.
ADC 0804
 ADC Interfacing
• CS :Active low input used to activate the ADC0804
chip.

RD (data enable) : Active low input used to get

converted data out of the ADC0804 chip. When CS = 0,
if a high-to-low pulse is applied to the RD pin, the 8-bit
digital output shows up at the D0-D7 data pins.
WR (start conversion): Active low input used to inform
the ADC0804 to start the conversion process. If CS = 0
when WR makes a low-to-high transition, the
ADC0804 starts converting the analog input value of
Vin to an 8-bit digital number. When the data
conversion is complete, the INTR pin is forced low by
the ADC0804.
 ADC Interfacing
• CLK IN and CLK R : Connect to external capacitor and
resistor for self-clocking, f = 1/(1.1RC). The clock affect
the conversion time and this time cannot be faster than
110 micros.

INTR (end of conversion) This is an active low output

pin. When the conversion is finished, it goes low to
signal the CPU that the converted data is ready to be
picked up. After INTR goes low, we make CS = 0 and
send a high-to-low pulse to the RD pin to get the data
out of the ADC0804 chip.
 ADC Interfacing
• Vin (+) and Vin (-) :These are the
differential analog inputs where Vin =
Vin (+) - Vin (-). Often the Vin (-) pin is
connected to ground and the Vin (+)
pin is used as the analog input to be
converted to digital.
• VCC : This is the +5V power supply. It
is also used as a reference voltage
when the Vref/2 (pin 9) input is open.
 ADC Interfacing
• Vref/2 :- Input voltage pin used for the
reference voltage. If this pin is open, the
analog input voltage for the the ADC is
ranged from 0 to 5 volts.This is optional
input pin. It is used only when the input
signal range is small. When pin 9 is at
2V, the range is 0-4V, i.e. Twice the
voltage at pin 9. Pin 6 (V+), Pin 7(V-):
The actual input is the difference in
voltages applied to these pins. The
analogue input can range from 0 to 5V.
ADC Interfacing
ADC Interfacing
A/D Interfacing [0808 ]
 A/D Interfacing
• The ADC 0808 is 8-channel 8-bit ADC chip.
It has 8 analog inputs i.e. IN0-IN7.
A/D Interfacing
A/D Interfacing
A/D Interfacing
 3/9/14

D/A INTERFACING

DEEPAK.P
 D/A Interfacing
• The digital to analog converters convert
binary number into their equivalent
voltages.
• The DAC find applications in areas like
digitally controlled gains, motors speed
controls, programmable gain amplifiers etc.
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing
 D/A Interfacing
• AD 7523 8-bit Multiplying DAC : This is a 16 pin
DIP, multiplying digital to analog converter,
containing R-2R ladder for D-A conversion along
with single pole double thrown NMOS switches to
connect the digital inputs to the ladder.

• supply range is from +5V to +15V, while

• Vref may be any where between -10V to +10V.
• The maximum analog output voltage will be any where between -
10V to +10V, when all the digital inputs are at logic high state.
D/A Interfacing
D/A Interfacing
D/A Interfacing
D/A Interfacing
 Reg. No.:
Name :

Final Assessment Test Key – May 2016

Programme : B.Tech-CSE Semester : Winter’15- 16
Class nbr : 1214 & 1511
Course : Microprocessor and Interfacing Code : CSE221
Faculty : Profs K.Khadar Nawas R.Maheswari Slot : F2
Time : Three Hours Max. Marks : 100

Answer all the Questions

Sub
Q.No. . Question Description Marks
Sec.

1. a) A hypothetical CPU has a parallel address bus, a parallel data bus, a RD and WR active [5]
LOW control signals. Two ROMs of size 4K words each and two RAMs of sizes 16K and
8K bytes, respectively, are to be connected to the CPU. The memories are to be so
connected that they fill the address space of the CPU as per the memory map shown in the
figure. Assume that chip select signals are active LOW.

i) What is the maximum number of lines that could be dedicated by the CPU for
the address lines?

32K= 32x 1024 = 32x 210= 25 x 210 = 215

ii)Determine the values of address X, Y, Z and W as decimal numbers.

4K (ROM)= (0-4095) ,
16RAM (4096- 20479),
4K ROM( 20480- 24577),
8K RAM (24578-32763).
Illustrate the memory organization in an 8086 based microsystem in detail.
Diagram (2.5)
b) [5]
Explanation (2.5)

2. In an 8086 based micro system, How will you make the micro system work as a single
processor system? With timing signals explain how it read and write in single processor
[10]
mode.

Page 1 of 4
 Min mode explanation with diagram (5)
Timing diagram (5)

Using appropriate assembler directives write an assembly language program to check

whether the given number “2622” is Nibble wise palindrome or not.

DATA SEGMENT
X DW 2662H
TEMP DW 0H
MES DB 10,13,'THE WORD IS NIBBLEWISE PALINDROME $'
MES1 DB 10,13,'THE WORD IS NOT NIBBLEWISE PALINDROME $'
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE,DS:DATA
START: MOV AX,DATA
MOV DS,AX
MOV AX,X
MOV BX,X
MOV CL,04
AND AX,0000FH
AND BX,0F000H
ROL BX,CL
CMP AX,BX
3. JNZ TER [10]
MOV AX,X
ROR AX,CL
MOV BX,AX
AND AX,000FH
ROR BX,CL
AND BX,000FH
CMP AX,BX
JNZ TER
MOV AH,09H
LEA DX,MES
INT 21H
JMP LAST
TER:MOV AH,09H
LEA DX,MES1
INT 21H
LAST:MOV AH,4CH
INT 21H
CODE ENDS
END START

4. Write an ALP in 8086 using procedural call to get your registration number from keyboard
and segregate the registration number to identify the year of admission, programme name
and four digit register number. Also compare and contrast procedural call and macro.
1. String segregation (3) [10]
2. INT 21 H to display the content the appropriate message (3)
3. Compare procedural call and macro (4)

Assume that address decoding is done such that when ICW1 is to be used, the port address [10]
5.
is C0H and for other ICWs the address is C2H.
Write an initialization instruction for setting up the system with the following
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 specifications:
i) The system has a single 8259, with edge triggered interrupt inputs and interrupt type
numbers from 90H,91H and 92H for IR0 to IR2.
ii) It should also operate in slave buffered mode with normal EOI.
1) Control word identification (4)
2) Initialization instructions (3)
3) Code for full configuration (3)

Interface an 8255 with 8086 at 0010H as an I/O address of port A. Interface four 7-segment [10]
6.
displays with 8255.Each display has a enable pin, connect those enable pins at port B to
select the digit positions and the display data is transferred to the 7-segment at port A.
Write a sequence of instruction to display ‘1’,’2’,’3’ and ‘4’ over the four displays
continuously as per their positions starting with ‘1’ at the least significant position and
show the circuit connections.
1) Control word identification (4)
2) Seven segment manipulations (3)
3) Code for full configuration (3)

Write an 8087 assembly language program that determine the volume of the given [10]
7.
container with diameter “d=5cm” and height “h=3.5cm”. Illustrate the outcome of result in
single precision format and write the expected output in Hex format.

1) Program for calculating Volume (7)

2) IEEE single precision format analysis with the output(3)

8. Write an 8087 program to verify the equation 12sin2 θ+cos θ = 6 and copy the control word [10]
in AX register and also analysis the impact of conditional codes.
8087 program to verify the equation [12sin2 θ+cos θ = 6] for given value of X.
(8)

data segment
oneighty dd 180
theta dd 30.156
x dd ?
y dd ?
h dd ?
result dd ?
data ends
code segment
assume cs:code,ds:data
Page 3 of 4
 start:mov ax,data
mov ds,ax
finit

fld oneighty
fld theta
fldpi
fmul
fdiv

fptan
fstp x
fst y
fmul st(0),st(0)
fld x
fmul st(0),st(0)
fadd
fsqrt

fld x
fdiv st(0), st(1)
fmul st(0), st(0)

fld y
fdiv st(0), st(2)
Conditional codes (2)
Compare the features of 8086, 80286 & 80386.
9. a) [5]
Minimum 5 points about comparison each carry one mark(5)
Illustrate and compare the register organisation in 8086 and 80386.
b) [5]
Diagram of 8086 and 80386 register organization (2)
Explanation with compare and contrast (3)
10. Draw the architecture of 80286. Explain the working of addressing unit in Protected and
Real mode.
1. Architecture (3)
[10]
2. Explanation of the architecture(2)
3. The working of addressing unit in Protected and Real mode with appropriate
diagram(5)


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