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fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2691012, IEEE
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1

Thermal Analysis and Balancing for Modular

Multilevel Converters in HVDC Applications
Frederik Hahn, Student Member, IEEE, Markus Andresen, Student Member, IEEE,
Giampaolo Buticchi, Senior Member, IEEE, and Marco Liserre, Fellow, IEEE

Abstract—The modular multilevel converter (MMC) has be- maritime converter stations, where the access is limited. With
come a very attractive solution for interfacing high voltages in respect to reliability, in power converters the power semicon-
hybrid networks. The MMC enables scalability to different power ductors have been found to be among the most sensitive com-
levels, full controllability provided by IGBTs and can achieve very
high efficiencies by using a low switching frequency method as the ponents and are prone to fail because of applied thermal stress.
nearest level modulation. However, the nearest level modulation Their expected lifetime is evaluated based on thermal cycle’s
requires a capacitor voltage balancing algorithm, which can magnitude and the related average junction temperatures [11].
result in unbalanced loading for the power semiconductors in the For increasing the lifetime, active thermal control can regulate
different submodules. Particularly at low power factor operation, the junction temperature profile by adjusting the power losses
which could occur in case of low-voltage ride through and
of reactive power injection, the conventional algorithm is not [12], [13]. For application in the MMC, it was proposed to
effective anymore. This article provides thermal stress analysis circulate reactive power for reducing the thermal fluctuations
of the MMC in operation and proposes a thermal balancing [14]. However, this thermal control approach is not addressed
approach, which is embedded in the capacitor voltage balancing to the thermal imbalances among the different submodules
algorithm. The purpose of the thermal balancing is to achieve (SMs) which can occur at low switching frequencies or due to
similar stress distribution among the different submodules to
enhance the lifetime. The junction temperatures in the different parameter variations, as it has been done instead in [15] and
submodules are studied for HVDC applications and the article [16], respectively.
proves experimentally, that the thermal balance within the As a problem resulting from the very low switching fre-
submodules is significantly improved. quency with NLM, the turn on times are not similar for the
different power semiconductors in the different SMs and can
result in uneven thermal stress distribution [15]. This uneven
I. I NTRODUCTION stress affects the lifetime and can result in failures of power
The modular multilevel converter (MMC) was firstly pro- semiconductors.
posed by Marquardt and Lesnicar in 2003 [1] and has be- In this article an MMC converter for HVDC applications
come a very popular solution in HVDC transmission systems. with 150 SMs per arms is considered with NLM and the
Projects up to 1000 MW are realized or planned to be built effect of unequal stress for the different power semiconductors
[2]. The HVDC systems have to be designed and controlled in the SMs is demonstrated. It is shown, that the NLM can
to provide high efficiency, availability and reliability during result in highly different lifetime expectations for the different
steady state operation as well as during fault conditions being power semiconductors in the SMs. To overcome this problem,
very challenging at DC side [3], [4], [5], [6]. In general, the a thermal balancing algorithm is introduced and validated
MMC particularly profits from its scalability to different power experimentally by emulating the behavior of different SMs
and voltage levels by using standard components (IGBTs) [1], and by measuring the junction temperature with a high speed
[7]. Since a very high number of IGBTs is required to block infrared camera.
high voltages, even low switching frequency methods can The article is organized as follows. Section II introduces
achieve a suitable output waveforms [8], [9]. The minimization the MMC including the used mathematical model, control
of the switching frequency and consequently a maximization and capacitor voltage balancing. A thermal analysis with
of the efficiency is achieved with the nearest level modulation experimental validation is done in Section III showing the
(NLM) [8], [10]. The NLM, which approximates the voltage limitations in steady-state MMC operation. In Section IV the
reference to the closest available voltage level, can be easily basic principle and the potential of active thermal balancing is
adopted even for multilevel converters [8]. presented and validated for different operation points. Finally,
In addition to the efficiency, the reliability is a very impor- the conclusion is given in Section V.
tant design criterion for high power converters, especially for
II. MMC D ESCRIPTION
This work was supported by the European Research Council under the
European Union’s Seventh Framework Programme (FP/2007- 2013) / ERC A. Topology
Grant Agreement 616344 HEART - the Highly Efficient And Reliable smart
Transformer. The circuit of a three-phase MMC in double-star connection
F. Hahn, M. Andresen, G. Buticchi and M. Liserre are with the Chair is shown in Fig. 1 [17]. In each arm, there are N series-
of Power Electronics, Faculty of Engineering, Christian-Albrechts University
of Kiel, Kaiserstrasse 2, 24143 Kiel, Germany, e-mail: {frha, ma, gibu, connected SMs designed as chopper-cells. Both switching
ml}@tf.uni-kiel.de states and the paths of the arm current are illustrated in Fig. 2

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idc T1 Inserted (S=1) Bypassed (S=0)

D1
SM SM SM C vc
v1p vsm T1 T1
T2 D2 D1 D1
SM SM SM On +v Off +v
Vdc Rarm vgrid T2
c
T2
c

Rgrid Lgrid D2 D2
Larm
2 ~ Off On
i1p iac,1
~
vdiff,1
i1n
Vdc ~ T1 T1
Larm D1 D1
2 Rarm On +v Off +v
c c
SM SM SM T2 T2
v1n D2 D2
Off On
SM SM SM

Fig. 1: Three-phase circuit of a modular multilevel converter Fig. 2: Current paths in a submodule (SM) during normal
(MMC) in double-star connection. MMC operation.

[18]. The three-phase grid is represented as 120◦ phase-shifted C. Control and Modulation
grid voltages vgrid and resistive-inductive grid impedances,
The power transmission and the average capacitor voltages
divided in Rgrid and Lgrid .
are separately controlled by the AC current and the differential
B. Mathematical Model current, respectively [15]. The energy stored in the upper and
the lower arm are equalized [21]. The current controllers are
The overall voltage across the SMs in the upper and the
designed following the technical optimum principle [22]. The
lower arm are given in (1) and (2). S(x) describes the switching
average capacitor voltage control is tuned to minimize the
state of the xth SM. During normal MMC operation only two
differential current ripple to relieve the semiconductors. The
switching states are used.
number of inserted SMs (non ) is calculated in order to follow
N
the reference voltages v∗conv and v∗diff . Assuming that the DC
voltage and the capacitor voltages are ideally regulated, the
vp = ∑ Sp (x) · vc,p (x) (1)
equations (8) and (9) are obtained [23]. Since the number of
x=1
N SMs is an integer, the results have to be rounded.
vn = ∑ Sn (x) · vc,n (x) (2)
x=1
N v∗conv v∗diff
 
Each phase voltage is described in (3). The AC current can non,p = round − − (8)
be controlled by the difference between vn and vp . Half of the 2 Vco 2Vco
N v∗conv v∗diff
 
voltage difference can be defined as the converter voltage in non,n = round + − (9)
(4) [19]. 2 Vco 2Vco

diac D. Capacitor Voltage Balancing

vac = Rgrid · iac + Lgrid · + vgrid (3)
dt
The balancing of the capacitor voltages is one important
vn − vp challenge in the MMC as addressed in [1], [20], [24]–[31].
vconv = (4)
2 The goal is to achieve an equal power distribution among the
The arm currents can be separated into two parts: the SMs. In general, it is possible to separate voltage balancing
differential current idiff and the contribution to the phase methods in distributed and centralized methods [26].
current iac . Considering an equal contribution, the arm currents Distributed methods are controlling the voltage of each
can be described in (5) and (6). The differential current idiff capacitor in a closed-loop and are usually adopted with carrier
is contained both in the upper and in the lower arm current phase-shifted pulse-width modulation [20], [24], [25]. The
without being measurable directly [20]. balancing control causes a modification in the modulating
signals and requires a sufficiently high switching frequency
iac [26]. However, the hardware and software costs for controllers
ip = idiff + (5)
2 would become excessive in an HVDC application due to the
iac huge number of SMs.
in = idiff − (6)
2 Centralized methods are directly combined with the mod-
The differential voltage vdiff is described in (7). The differ- ulator and can be applied to NLM in HVDC applications
ential current is controlled by the sum of vp and vn . [32]. The modulator provides the number of inserted SMs
which are selected depending on the capacitor voltages and
didiff
vdiff = 2Larm · + 2Rarm · idiff (7) the arm current direction [1], [27], [28]. However, additional
dt
switching actions can be required [29]. One big challenge is

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the sufficiently fast sorting of the capacitor voltages for a high TABLE I: MMC simulation parameters.
number of SMs [30], [31]. Description Parameter Value Unit
SMs per arm N 150
III. T HERMAL A NALYSIS OF MMC DC voltage Vdc 300 kV
Arm inductance Larm 72 mH
A. Thermal Principles and Lifetime Expectation Arm resistance Rarm 200 mΩ
The junction temperature of power semiconductors is of SM’s capacity C 10 mF
Capacitor voltage limit Vc,lim 2500 V
major importance because it is influencing the efficiency of
Grid voltage Vgrid,ll 120 kV
the converter and the lifetime of the system. For IGBTs an
Grid inductance Lgrid 25 mH
increase in the junction temperature Tj affects a reduction in
Grid resistance Rgrid 1 Ω
the efficiency, while the design for a low maximum junc- K
Cooling resistance (IGBT) Rth,CH,T 5.2
tion temperature counteracts the goal of a compact and cost kW
K
Cooling resistance (Diode) Rth,CH,D 11.7
effective systems. The influence of the chip temperature on kW
Sampling time Ts 20 µs
the lifetime is given with several failure mechanisms, which
are dependent on the junction temperature [33]. The number
of power cycles to failure Nf can be approximated by (10)
whereas the constants a1 , a2 and a3 have to be fitted by cycling B. Analysis of MMC Operation
tests [34]. The used simulation model is based on the mathematical
model derived in Section II and discretized in MATLAB by
a3
using a sampling time of 20 µs. In Table I the simulation
Nf = a1 · (∆Tj )−a2 · exp T j (10) parameters for an HVDC application are summarized, whereby
the DC voltage is assumed to be constant. The MMC consists
This mathematical lifetime model only considers a single
of 150 SMs per arm and is rated for a nominal power of
magnitude of thermal cycles ∆Tj , which is not sufficient to
300 MW. A high-voltage grid and the corresponding grid
estimate the lifetime based on a real mission profile. In this
transformer are emulated.
case, the Miner rule is commonly applied with linear damage
The control was described in Section II and in [15] and
accumulation as shown in (11).
NLM is applied to achieve high efficiency. (1.3) A centralized
∞
ni method is applied for capacitor voltage balancing due to the
Cm = ∑ ≤1 (11) huge number of SMs. Not only the modulation but also the
i=0 Ni balancing algorithm is selected to provide a very low switching
In this equation, Ni is the number of cycles to failure in frequency. This is achieved by only inserting SMs which
the stress range i and ni the number of detected cycles in the are currently switched off and vice versa [29]. Additional
ith stress range. As soon as the accumulated damage Cm = switching operations can be required because the capacitor
1, the device is expected to fail. Based on this equation, the voltages are limited to 2500 V for protection.
lifetime is obtained as the inverse of the damage divided by the As semiconductors the IGBT module CM1200HC-90R from
time period in which this damage was affected. The approach Mitsubishi is considered, the power losses are calculated by the
is developed for IGBTs and diodes, as well. However, the datasheet characteristics according to [37]. The thermal model
interpretation of the diodes’ lifetimes should be done carefully is based on the Foster Network as illustrated in Fig. 3, and
since the theoretical model is primary applied to IGBTs. the thermal impedances of the semiconductors from junction
Despite the high importance of the junction temperature, to case are obtained from the datasheet. Furthermore, the
there is still no suitable low cost method for accessing the thermal resistances between case and heatsink Rth,CH are
junction temperature of the power semiconductors: Direct given in Table I. Since the time constants of the cooling
measurement is only practical in laboratory environments, elements would be relatively high, a constant temperature
Thermo Sensitive Electrical Parameters (TSEP) affect addi- difference between cooling and case is assumed for steady
tional components and sensor costs and observers or estimators state operation. The semiconductors are cooled by a water
deal with parameter uncertainties and high complexity for temperature of Ta = 40 ◦ C.
high precision [35]. Particularly, in modular power converters,
there is the additional challenge of a high number of power Ptot,T Tj,T TC,T
semiconductors, resulting in many junction temperatures to
Rth_1,T Rth_2,T Rth_3,T Rth_4,T Rth_5,T
be taken into account. A cheaper solution can be realized WT Ta
by model based approaches only requiring low bandwidth
case temperature measurement and the thermal characteristics Rth_6,T
Ptot,D Tj,D TC,D
provided in the datasheet [36]. The computation effort can
Rth_1,D Rth_2,D Rth_3,D Rth_4,D Rth_5,D
be reduced by transforming the fourth order Foster model WD
to second order [36]. A disadvantage of the model based
approaches are model uncertainties and often the neglected
thermal coupling between different power semiconductors. Fig. 3: Foster model for IGBT module and cooling system.

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Tj,T1 [°C]
vconv [kV]
100 60
Phase 1
Phase 2 55
0
Phase 3
50
−100 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
85

Tj,T2 [°C]
1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2
80
vgrid,Y [kV]

100 75
70
0 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89

Tj,D1 [°C]
70
−100
60
1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2
50
2000 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
iac [A]

Tj,D2 [°C]
0 60
55
−2000
50
1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
time [s] time [s]

(a) (a)
[A] vdiff,1 [kV]

10 70

Tj,T1 [°C]
0
60
−10
1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2 50
400 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89

Tj,T2 [°C]
diff,1

200
0 60
vcx,1n [V] vcx,1p [V] Vc_av,1 [V] i

1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2
2100 50
2000 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
Tj,D1 [°C]

1900 70
1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2
2500 60
2000
50
1500 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2
Tj,D2 [°C]

70
2500
60
2000
1500 50
1.8 1.82 1.84 1.86 1.88 1.9 1.92 1.94 1.96 1.98 2 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
time [s] time [s]

(b) (b)
Fig. 4: Electrical behavior of the MMC in OP1 (steady state: Fig. 5: Thermal behavior of the semiconductors in the first
Pgrid = 300 MW, cos ϕ = 0.95): a) Converter phase voltages, 21 SMs in the upper arm (phase 1): a) OP1 (steady state:
grid voltages and phase currents (3 phases), b) Differential Pgrid = 300 MW, cos ϕ = 0.95), b) OP2 (steady state: Qgrid =
voltage, differential current and capacitor voltages of the first 300 Mvar, cos ϕ = 0). [15]
21 SMs (phase 1). [15]

The MMC is considered in steady state operation and the is active when the corresponding SM is inserted and when the
rated power is transmitted from DC to AC side. The three- arm current is positive. The cyclic behavior of power losses
phase converter voltages, the grid voltages and phase currents also causes thermal cycles with the fundamental frequency of
are depicted in Fig. 4a for a power transmission of 300 MW, the grid (50 Hz). As it can be seen, the temperatures are already
defined as operation point 1 (OP1). A power factor of cos ϕ = regulated by the capacitor voltage balancing up to a certain
0.95 corresponds to a reactive power of 98.6 Mvar. The phase degree. However, the loading of the SMs can be quite different.
currents reach an amplitude of around 2150 A. The differential Especially at low power factors, the spread in the temperatures
voltage and the differential current (phase 1) are depicted in becomes very significant. This is illustrated in Fig. 5b where
Fig. 4b. The peak-to-peak ripple of the differential current the temperatures are depicted for a maximum reactive power
is around 120 A, by obtaining an average capacitor voltage (OP2: Qgrid = 300 Mvar, cos ϕ = 0). The individual capacitors
oscillating of about 70 V. The individual capacitor voltages are not charged as fast as before since the arm currents are
are balanced and limited to 2500 V. oscillating around zero. Therefore, the semiconductors can
The thermal behavior of the semiconductors is considered conduct the current for a longer time without being changed by
in the upper arm (phase 1) and is depicted for the first 21 SMs the capacitor voltage balancing. An active thermal balancing
in Fig. 5a. The highest junction temperatures occur in IGBT can solve this problem and will be demonstrated in Section
T2 and is caused by the considered power flow direction. T2 IV.

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SOFTWARE
Switching Arm current
profile profile
iarm,ref
-+
iarm
PI

PWM

Vdc1 Vdc2
Fig. 7: Setup of the experimental bench.
2 iarm Lfilter 2
S
Vdc1 Vdc2
vsm
2 2

device under device for

test current control

HARDWARE

Fig. 6: Experimental bench for electrical and thermal evalua-

Fig. 8: Experimental validation of arm current and voltage at
tion of one MMC SM.
one SM (no. 61).

C. Experimental Validation
rating of the semiconductors is not a critical issue since the
For the validation of the theoretical results, an experimental conduction losses are dominant at low switching frequencies.
bench has been developed and puts the focus on one single The conduction losses are directly related to the switching
SM. Both the electrical behavior of each SM and the thermal sequence and the arm current. Thus, the relative temperatures
behavior of its semiconductors can be validated on this bench. between the full system in simulation and the temperatures in
The emulation of each SM with and without the proposed the downscaled system are highly correlated. The reduction of
method can show qualitatively the impact on the semiconduc- thermal spread by thermal balancing will be verified by means
tor’s junction temperature. of the changing switching sequences. The temperatures of the
The experimental bench for the emulation of one SM is module are measured and recorded by the infrared camera
depicted in Fig. 6. The prototype consists of one half-bridge ImageIR 8300.
as device-under test and an additional half-bridge to emulate Fig. 7 shows a photo of the setup. The electrical waveforms
the reference arm current. The submodule’s capacitor voltage for one SM (no. 61) are depicted in Fig. 8 for OP1 (Pgrid =
Vdc1 is generated by a DC source. Voltage oscillations can 300 MW, cos ϕ = 0.95). The SM voltage is obtained according
be neglected for thermal evaluation since they are only small, to its switching profile. The reference arm current is properly
just relevant for the switching losses and would be mostly controlled, independent from the SM’s switching state. The
filtered due to higher thermal time constants. The device- temperature distribution in the IGBT module is illustrated
under test is fed by a DSPACE system with the switching in Fig. 9. The junction temperatures of IGBTs T1 , T2 and
pattern of one SM from the simulation. The reference arm diodes D1 , D2 are recorded and shown with the simulated
current is controlled by a PI controller whereas Vdc2 > Vdc1 temperature behavior in Fig. 10. Just the temperature ranges
has to be fulfilled. In this way, both simulated operation points are downscaled by the experimental results due to the reduced
are investigated experimentally. The system parameters are power level and the usage of different power semiconductors.
summarized in Table II. Beyond that, both thermal profiles match together proving the
One half-bridge of the open 1200 V IGBT module validity of the experimental results.
DP25F1200T101666 from Danfoss was selected as device
under test. The SM capacitor voltage is downscaled to 100 V
for protection since the absence of the filling gel makes 66
D2 64
high-voltage operation riskier. The reference arm current is 62
limited by a downscaling factor of 50. The changed power 60
58
56
54
52
TABLE II: System parameters. 50
T2 48
46
Vdc1 100 V T1 D1 44
42
Vdc2 200 V
Lfilter 3.6 mH Fig. 9: Temperature distribution in the IGBT module recorded
fsw 10 kHz by infrared camera for one SM (no. 61).

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58 85
Tj,T1 [° C] simulation simulation

Tj,T2 [° C]
56
80
54
75
52

50 70
0.6 0.8 1 1.2 1.4 1.6 1.8 0.6 0.8 1 1.2 1.4 1.6 1.8

54
65
IR camera IR camera
Tj,T1 [° C]

Tj,T2 [° C]
53
52 60
51
50 55
0.6 0.8 1 1.2 1.4 1.6 1.8 0.6 0.8 1 1.2 1.4 1.6 1.8

75
65
70 simulation simulation
Tj,D1 [° C]

Tj,D2 [° C]
65
60 60

55
50 55
0.6 0.8 1 1.2 1.4 1.6 1.8 0.6 0.8 1 1.2 1.4 1.6 1.8

65 58
IR camera IR camera
Tj,D1 [° C]

Tj,D2 [° C]
56
60
54
55
52

50 50
0.6 0.8 1 1.2 1.4 1.6 1.8 0.6 0.8 1 1.2 1.4 1.6 1.8
time [s] time [s]

Fig. 10: Junction temperature profile for one SM (no. 61) from simulation and from test bench from infrared camera for OP1
(steady state: Pgrid = 300 MW, cos ϕ = 0.95).

IV. ACTIVE T HERMAL BALANCING TABLE III: Active thermal balancing principle.

A. Active Thermal Balancing Approach nkon − nk−1

on iarm Action
positive >0 insert SM(s) with lowest temperature in D1
Active thermal balancing algorithms are presented in [15]
positive <0 insert SM(s) with lowest temperature in T2
and [16] with the purpose of an equalized heat and stress
negative >0 bypass SM(s) with lowest temperature in T1
distribution among all SMs. Unbalanced stress distribution, negative <0 bypass SM(s) with lowest temperature in D2
affecting the semiconductors’ lifetimes, can occur at very low
switching frequencies in HVDC applications [15] or due to pa-
rameter variations as demonstrated for fast switching medium-
In (12)-(15) cost functions are defined to include both: the
voltage applications [16]. Active thermal balancing relieves
SM capacitor voltage and the junction temperature of the most
the conducting semiconductor by changing the corresponding
stressed power semiconductor. The weighting factor α is used
SM’s switching state as soon as the temperature becomes rela-
to adjust the strength of active thermal balancing whereas
tively high. The algorithm can be applied to all semiconductors
it is disabled for α = 0. A simplified flowchart of active
[15] or to the most stressed semiconductor [16] and can be
thermal balancing embedded in a capacitor voltage balancing
always activated [15] or in predefined scenarios [16]. The
is depicted in Fig. 11. The cost function is selected for each
thermal balancing methods are software based and integrated
sampling time by taking into account the arm current direction
in the capacitor voltage balancing algorithm, limiting the costs.
and whether SMs have to be switched on or off. The SMs
Usually, the capacitor voltage balancing algorithm takes to be inserted or bypassed are selected by minimizing the
decision of switching on or off SMs only based on the applied cost function so that the current will be redirected to
capacitor voltages and on the arm current direction. However, the less stressed anti-parallel semiconductor. In addition to the
in this manner the temperatures of the semiconductors can thermal balancing, a maximum temperature should be defined
be different. An active thermal balancing takes the junction as thermal protection.
temperatures into account with the purpose to select the
SMs by minimizing the temperatures of the semiconductors
carrying the current after one switching operation. A possible c1 = (vc − vc,min ) + α1 (Tj,D1 − Tj,D1,min ) (12)
principle for a thermal balancing is summarized in Table III, c2 = (vc,max − vc ) + α2 (Tj,T2 − Tj,T2,min ) (13)
whereas nkon and nk−1on describe the actual and the previous c3 = (vc,max − vc ) + α3 (Tj,T1 − Tj,T1,min ) (14)
number of SMs which have to be inserted according to the
modulator. c4 = (vc − vc,min ) + α4 (Tj,D2 − Tj,D2,min ) (15)

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for k=1:p

Modulator: non k

• bypass concerned SMs

• replace them optimally
z =|non k-non k-1|=0?

No
No
• calculate and sort: • calculate and sort:
c3=(vcma x-vc)+α·(Tj,T1-Tj,T1,min) Yes z>0? No iarm >0? Yes z>0? Yes c1=vc-vcmin +α·(Tj,D1-Tj,D1,min)
• insert z SMs with lowest c3 • insert z SMs with lowest c1

No No
Yes

• calculate and sort: • calculate and sort:

c4=vc-vcmin +α·(Tj,D2-Tj,D2,min) c2=(vcma x-vc)+α·(Tj,T2-Tj,T2,min)
• bypass |z| SMs with lowest c4 • bypass |z| SMs with lowest c2

Yes
vCn>Vcma x

Fig. 11: Simplified flowchart of active thermal balancing embedded in capacitor voltage balancing related to one arm (p:
number of iterations, z: auxiliary variable).

The junction temperatures can be directly obtained by mal balancing without deteriorating the performance of the
one of the methods discussed in Section III-A. The junction operation.
temperatures are provided for the thermal balancing algorithm This effect becomes even stronger in OP2 (Qgrid =
by a feedback loop to balance the temperatures. 300 Mvar, cos ϕ = 0) as shown in Fig. 14b. The thermal
The active thermal balancing is activated to reduce the spread in the temperatures is clearly reduced by the active
spread in the temperatures for both operation points from thermal balancing as shown in Fig. 13 with almost constant
Section III. The weighting factor α is selected to achieve semiconductor power losses. The spread of the capacitor
a similar weighting between capacitor voltage and thermal voltages is slightly increased due to changed commutation
balancing. The capacitor voltage oscillations are expected times without negatively affecting the switching frequency.
within a range of around 750 V referring to Fig. 4b (OP1). The averaged difference between highest and lowest junc-
The factor α is set constant to 50 for the different cost tion temperature is decreased by between 12.4 K (T2 ) and
functions: α = α1 = α2 = α3 = α4 . This corresponds to a 21.6 K (D1 ). This corresponds to a reduction between 71.4
realistic temperature range of 15 K. and 79.7 %. The reduction of the thermal spread and of the
The maximum, the minimum and the average temperatures maximum temperatures can be exploited for a more economic
for IGBTs T1 and T2 and for the capacitor voltages of the rating, especially for the diodes and the related cooling system.
150 SMs are depicted in Fig. 12 for OP1 (Pgrid = 300 MW,
cos ϕ = 0.95). The average temperature is approximately con-
stant independent from the weighting factor due to almost TABLE IV: Comparison of power losses in semiconductors,
efficiency and switching frequency with and without thermal
constant semiconductor losses according to Table IV. The
spread of the capacitor voltages is not significantly changed balancing for OP1 and OP2.
and the switching frequency is kept almost constant. However, OP1 power losses (upper arm) switching frequency
the spread in the temperatures is reduced by the active thermal α =0 395.3 kW 53 Hz
balancing (α = 50) in comparison to the usual capacitor α = 50 392.4 kW 49 Hz
voltage balancing (α = 0). The averaged difference between
OP2 power losses (upper arm) switching frequency
highest and lowest junction temperature are summarized in
α =0 297.5 kW 51 Hz
Fig. 14a for both weighting factors. A reduction between
α = 50 297.9 kW 49 Hz
19.5 % (T2 ) and 35.1 % (D1 ) is achieved by the active ther-

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2691012, IEEE
Transactions on Power Electronics
8

Tj,max Tj,max
α α
α α
Tj,av Tj,av
Tj,min
Tj,min

α α
α α

(a) (a)
Tj,max α α
α Tj,max Tj,av α
Tj,min Tj,av
Tj,min

α α
α α

(b) (b)
Tj,max Tj,max
α α
Tj,av α α
Tj,av
Tj,min
Tj,min

α α
α α

(c) (c)
Tj,max
α α
Tj,av Tj,max
α Tj,av α

Tj,min Tj,min

α α
α α

(d) (d)
2500 2500
[V]

vc,1p [V]

α=0 α=0
2000 α=50 2000 α=50
c,1p
v

1500 1500
1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
vc,1p,max− vc,1p,min [V]

[V]

800 800
c,1p,min

600 α=0 600 α=0

400 α=50 400 α=50
−v
c,1p,max

200 200
0 0
1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89 1.8 1.81 1.82 1.83 1.84 1.85 1.86 1.87 1.88 1.89
v

time [s] time [s]

(e) (e)
Fig. 12: Maximum, minimum, averaged junction temperatures Fig. 13: Maximum, minimum, averaged junction temperatures
and capacitor voltages in the upper arm (ph. 1) in OP1 (steady and capacitor voltages in the upper arm (ph. 1) in OP2 (steady
state: Pgrid = 300 MW, cos ϕ = 0.95): a) IGBTs T1 , b) IGBTs state: Qgrid = 300 Mvar, cos ϕ = 0): a) IGBTs T1 , b) IGBTs
T2 , c) Diodes D1 , d) Diodes D2 , e) Capacitor voltages. T2 , c) Diodes D1 , d) Diodes D2 , e) Capacitor voltages.

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2691012, IEEE
Transactions on Power Electronics
9

α α
α α

α
α
α
α

T1 T2 D1 D2 T1 T2 D1 D2
α
(a) (b)
α
α
Fig. 14: Maximum temperature difference (averaged) among α
all 150 SMs in the upper arm (phase 1): a) OP1 (steady state:
Pgrid = 300 MW, cos ϕ = 0.95), b) OP2 (steady state: Qgrid = 1

300 Mvar, cos ϕ = 0).

The impact of active thermal balancing is particularly strong

in OP2. The corresponding lifetime expectations under this α
α
profile are calculated based on (10), (11) and illustrated in Fig.
α
15 for all semiconductors whereas unrealistic long lifetimes α
have been set to 100 years. Without active thermal balancing,
1
failures can occur very early in many SMs. Compared to
this, the thermal stress is much better balanced by active
thermal balancing. The lifetime of each semiconductor has
been increased by minimum 50 % for at least the 20 SMs
with the lowest expected lifetime. Additionally, the mean
α
lifetime has been increased for all power semiconductors. The α
enhanced reliability can be exploited for longer maintenance α
intervals or for the usage of less SMs in the system. α

B. Experimental Validation of Active Thermal Balancing of

MMC Fig. 15: Lifetime expectation for the power semiconductors of
Three different SMs are selected from simulation for each all submodules in the upper arm (phase 1) in OP2.
operation point to further demonstrate the effect of active
thermal balancing. The corresponding switching profiles and
junction temperatures are depicted in Fig. 16 for OP1. The The active thermal balancing reduces the spread and the
SM no. 122 can be seen as a kind of reference for a cycles in the temperatures by providing a more homogenous
balanced loading. In comparison, the switching profile and the switching profile. The remaining thermal cycles are linked to
temperatures of SMs no. 61 and 94 are not always homogenous the extremely low switching frequency since not each SM will
without active thermal balancing. As a consequence, the be automatically changed in each period. Nevertheless, the
temperature spread among the three SMs is relatively high. By thermal stress is strongly reduced by active thermal balancing
means of active thermal balancing, the inhomogeneity and the by maintaining the very high efficiency. Thus, an active
temperature spread among the SMs has been strongly reduced. thermal balancing has the potential to significantly enhance
Remarkably, not only the spread among the SMs is reduced the semiconductors’ lifetime of the system by preventing
but also the number of fast and high temperature changes in imbalanced loading of the SMs.
single power semiconductors. For medium-voltage applications the thermal spread is
These thermal cycles can be particularly evident at low highly damped by the capacitor voltage balancing due to lower
power factors as illustrated in Fig. 17 for OP2. The switching number of SMs and due to increased switching frequencies
profile of one SM can be quite inhomogeneous without thermal as it has been demonstrated in [28]. This is the reason why
balancing as seen in SM no. 146. The SM is switched off for the presented thermal balancing algorithm is mainly relevant
a long time whereas only the semiconductors T2 and D2 are for HVDC applications. The experimental validation can be
loaded. During this time the submodule’s capacitor voltage provided by the emulation of the thermal behavior of single
does not change so that the sole capacitor voltage balancing SMs with the switching pattern from the HVDC-MMC as
is not effective anymore to achieve a thermal balance. demonstrated in this article.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2691012, IEEE
Transactions on Power Electronics
10

p 1 1

p
0.5 SM 61 0.5 SM 61
S

S
0 0
0.5 1 1.5 2 0.5 1 1.5 2
1 1
p

p
0.5 SM 94 0.5 SM 94
S

S
0 0
0.5 1 1.5 2 0.5 1 1.5 2
1 1
p

p
0.5 SM 122 0.5 SM 122
S

S
0 0
0.5 1 1.5 2 0.5 1 1.5 2
Tj,D2 [° C] Tj,D1 [° C] Tj,T2 [° C] Tj,T1 [° C]

[° C]
55 SM 61 55 SM 61

j,T1
SM 94 SM 94
50 50

[° C] T
SM 122 SM 122
0.5 1 1.5 2 0.5 1 1.5 2
70 70
65 SM 61 65 SM 61

j,T2
60 SM 94 60 SM 94
55 55

[° C] T
SM 122 SM 122
0.5 1 1.5 2 0.5 1 1.5 2
65 65
60 SM 61 60 SM 61

j,D1
55 SM 94 55 SM 94
50 50

[° C] T
SM 122 SM 122
0.5 1 1.5 2 0.5 1 1.5 2
60 60
55 SM 61 55 SM 61

j,D2
50 SM 94 50 SM 94
45 SM 122 T 45 SM 122
0.5 1 1.5 2 0.5 1 1.5 2
time [s] time [s]
(a) (b)
Fig. 16: Switching states and junction temperatures in three MMC SMs (no. 61, 94, 122) recorded by infrared camera in OP1:
a) Disabled active thermal balancing (α = 0), b) Enabled active thermal balancing (α = 50).

1 1
p

0.5 SM 67 0.5 SM 67
S

0 0
0.5 1 1.5 2 0.5 1 1.5 2
1 1
p

0.5 SM 141 0.5 SM 141

S

0 0
0.5 1 1.5 2 0.5 1 1.5 2
1 1
p

0.5 SM 146 0.5 SM 146

S

0 0
0.5 1 1.5 2 0.5 1 1.5 2
Tj,D2 [° C] Tj,D1 [° C] Tj,T2 [° C] Tj,T1 [° C]

[° C]

55 55
SM 67 SM 67
50 50
j,T1

SM 141 SM 141
45 45
[° C] T

SM 146 SM 146
0.5 1 1.5 2 0.5 1 1.5 2
60 60
55 SM 67 55 SM 67
j,T2

50 SM 141 50 SM 141
45 45
[° C] T

SM 146 SM 146
0.5 1 1.5 2 0.5 1 1.5 2
60 60
SM 67 SM 67
j,D1

50 SM 141 50 SM 141
[° C] T

SM 146 SM 146
0.5 1 1.5 2 0.5 1 1.5 2
60 60
SM 67 SM 67
j,D2

50 SM 141 50 SM 141
T

SM 146 SM 146
0.5 1 1.5 2 0.5 1 1.5 2
time [s] time [s]
(a) (b)
Fig. 17: Switching states and junction temperatures in three MMC SMs (no. 67, 141, 146) recorded by infrared camera in
OP2: a) Disabled active thermal balancing (α = 0), b) Enabled active thermal balancing (α = 50).

0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2691012, IEEE
Transactions on Power Electronics
11

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0885-8993 (c) 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2017.2691012, IEEE
Transactions on Power Electronics
12

modular multilevel converter,” IEEE Transactions on Power Electronics, Marco Liserre (S’00-M’02-SM’07-F’13) is Full
vol. 31, no. 6, pp. 3977–3984, June 2016. Professor and Head of the Chair of Power Elec-
[33] M. Ciappa, “Selected failure mechanisms of modern power modules,” tronics at the University of Kiel (Germany). He
Microelectronics Reliability, vol. 42, no. 4-5, pp. 653–667, 2002. has published over 200 technical papers (1/3 in
[34] R. Bayerer, T. Herrmann, T. Licht, J. Lutz, and M. Feller, “Model for international peer-reviewed journals) and a book at
power cycling lifetime of igbt modules - various factors influencing second reprint and also translated in Chinese. These
lifetime,” in Integrated Power Systems (CIPS), 2008 5th International works have received more than 15000 citations,
Conference on, March 2008, pp. 1–6. for this reason he is listed in ISI Thomson report
[35] N. Baker, M. Liserre, L. Dupont, and Y. Avenas, “Improved reliability of "The world’s most influential scientific minds" from
power modules: A review of online junction temperature measurement 2014. He has been awarded with an European ERC
methods,” IEEE Industrial Electronics Magazine, vol. 8, no. 3, pp. 17– Consolidator Grant, one of the most prestigious in
27, Sept 2014. Europe. He is member of IAS, PELS, PES and IES. He did serve all
[36] M. Andresen, M. Schloh, G. Buticchi, and M. Liserre, “Computational these societies in various capacities such as reviewer, associate editor, editor,
light junction temperature estimator for active thermal control,” in IEEE conference chairman or track chairman. He has been founding Editor-in-
Energy Conversion Congress and Exposition (ECCE), 2016. Chief of the IEEE Industrial Electronics Magazine, founding Chairman of the
[37] F. Ertürk and A. M. Hava, “A detailed power loss analysis of modular Technical Committee on Renewable Energy Systems, and IES Vice-President
multilevel converter,” in 2015 IEEE Applied Power Electronics Confer- responsible of the publications. He has received several IEEE Awards.
ence and Exposition (APEC), March 2015, pp. 1658–1665.

Frederik Hahn (S’16) was born in Verden, Ger-

many, in 1988. He received his bachelor’s and
master’s degrees in electrical engineering from
Christian-Albrechts-Universität zu Kiel, Kiel, Ger-
many. Since 2015 he is working towards his Ph.D.
degree at the Chair of Power Electronics. His current
research interests include modular power converters
for renewable high power applications and reliability
in power electronics.

Markus Andresen (S’15) received his B.Sc and

M.Sc in electrical engineering and business adminis-
tration from Christian-Albrechts-University of Kiel,
Kiel, Germany. Since 2013 he is working towards
his Ph.D degree from the chair of power electronics
at Christian-Albrechts-Unversity of Kiel, Germany.
In 2010, he was an intern in the Delta Shanghai
Design Center at Delta Electronics (Shanghai) Co.,
Ltd., China and in 2017 he was a visiting scholar
at the University of Wisconsin-Madison, USA. His
current research interests include control of power
converters and reliability in power electronics.

Giampaolo Buticchi (S’10-M’13-SM’17) was born

in Parma, Italy, in 1985. He received the Masters
degree in Electronic Engineering in 2009 and the
Ph.D degree in Information Technologies in 2013
from the University of Parma, Italy. In 2012 he was
visiting researcher at The University of Nottingham,
UK. He is now working as a postdoctoral research
associate at the University of Kiel, Germany. His
research area is focused on power electronics for
renewable energy systems, smart transformer fed
micro-grids and reliability in power electronics.

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