Energy Metering IC With SPI Interface and Active Power Pulse Output

MCP3909
Energy Metering IC with SPI Interface and Active Power Pulse Output
Features Description
• Supports IEC 62053 International Energy The MCP3909 device is an energy-metering IC
Metering Specification and legacy IEC 1036/ designed to support the IEC 62053 international
61036/687 Specifications metering standard specification. It supplies a frequency
• Digital waveform data access through SPI output proportional to the average active real power,
interface with simultaneous serial access to ADC channels and
multiplier output data. This output waveform data is
- 16-bit Dual ADC output data words
available at up to 14 kHz with 16-bit ADC output and
- 20-bit Multiplier output data word 20-bit multiplier output words. The 16-bit, delta-sigma
• Dual functionality pins support serial interface ADCs allow for a wide range of IB and IMAX currents
access and simultaneous Active Power Pulse and/or small shunt (<200 µOhms) meter designs.
Output A no-load threshold block prevents any current creep
• Two 16-bit second order delta-sigma measurements for the active power pulse outputs.
Analog-to-Digital Converters (ADCs) with multi-bit The integrated on-chip voltage reference has an
DAC ultra-low temperature drift of 15 ppm per degree C.
- 81 dB SINAD (typ.) both channels This accurate energy metering IC with high field
reliability is available in the industry standard 24-lead
• 0.1% typical active energy measurement error
SSOP pinout.
over 1000:1 dynamic range
• PGA for small signal inputs supports low value Package Type
shunt current sensor 24-Lead DVDD 1 24 FOUT0
• Ultra-low drift on-chip reference: SSOP HPF 2 23 FOUT1
15 ppm/°C (typical) AVDD 3 22 HFOUT
NC 4 21 DGND
• Direct drive for electromagnetic mechanical
CH0+ 5 20 NEG / SDO
counter and two-phase stepper motors
CHO- 6 19 NC
• Low IDD of 4 mA (maximum) CH1- 7 18 CLKOUT
• Tamper output pin for negative power indication CH1+ 8 17 CLKIN
MCLR 9 16 G0
• Industrial Temperature Range: -40°C to +85°C
REFIN / OUT 10 15 G1
AGND 11 14 F0 / CS
F2 / SCK 12 13 F1 / SDI
Functional Block Diagram

G0 G1 HPF
F2/SCK F1/SDI F0/CS NEG/SDO
CH0+ + 16-bit 16
PGA Multi-level HPF1
CH0- –
DS ADC MCLR
16
4 kΩ Dual Functionality Pin
Control
REFIN/ Serial Control
OUT And Output SPI
2.4V Buffers Interface
Reference 16
CH1+ + 16-bit 16
Multi-level HPF1
CH1- – HFOUT FOUT0 FOUT1
DS ADC
20
Clock
Sub-system Stepper
Active Power Motor
LPF1 DTF Output Drive
X conversion for
Active Power
OSC1 OSC2
© 2009 Microchip Technology Inc. DS22025B-page 1

MCP3909
NOTES:
DS22025B-page 2 © 2009 Microchip Technology Inc.

MCP3909
1.0 ELECTRICAL † Notice: Stresses above those listed under "Maximum
Ratings" may cause permanent damage to the device. This is
CHARACTERISTICS a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
Absolute Maximum Ratings † operation listings of this specification is not implied. Exposure
to maximum rating conditions for extended periods may affect
VDD...................................................................................7.0V device reliability.
Digital inputs and outputs w.r.t. AGND ....... -0.6V to VDD +0.6V
Analog input w.r.t. AGND ..................................... ....-6V to +6V
VREF input w.r.t. AGND .............................. -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) .................5.0 kV, 500V
ESD on all other pins (HBM,MM) ........................5.0 kV, 500V
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V to 5.5V,
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter Sym Min Typ. Max Units Comment
Active Power Measurement Accuracy
Active Energy Measurement E — 0.1 — % FOUT Channel 0 swings 1000:1 range,
Error FOUT0, FOUT1 Frequency outputs
only, does not apply to serial
interface data. (Note 1, Note 4)
No-Load Threshold/ NLT — 0.0015 — % FOUT Frequency outputs only, does not
Minimum Load Max apply to serial interface data.
Disabled when F2, F1, F0 = 0, 1, 1
(Note 5, Note 6)
System Gain Error — 1 5 % FOUT (Note 2, Note 5)
AC Power Supply Rejection AC PSRR — 0.01 — % FOUT F2, F1, F0 = 0, 1, 1 (Note 3)
(output frequency variation)
DC Power Supply Rejection DC PSRR — 0.01 — % FOUT HPF = 1, Gain = 1 (Note 3)
(output frequency
variation)
Waveform Sampling
A/D Converter Signal-to- SINAD — 81 — dB Applies to both channels,
Noise and Distortion Ratio VIN = 0 dBFS at 50 Hz
(VIN = Full Scale)
Bandwidth — 14 — kHz Applies to both channels,
(Notch Frequency) MCLK/256
Phase Delay Between — — 1/MCLK s HPF = 0 and 1, < 1 MCLK period
Channels (Note 4, Note 6, Note 7)
Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 75 Hz.
See typical performance curves for higher frequencies and increased dynamic range. This parameter is
not 100% production tested.
2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between
measured output frequency and expected transfer function.
3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz,
CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1 Vpp @ 100 Hz. DC PSRR: 5V ±500 mV
4: Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).
5: Refer to Section 4.0 “Device Overview” for complete description.
6: Specified by characterization, not production tested.
7: 1 MCLK period at 3.58 MHz is equivalent to less than < 0.005 degrees at 50 or 60 Hz.

MCP3909
ELECTRICAL CHARACTERISTICS (CONTINUED)
Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter Sym Min Typ. Max Units Comment
ADC/PGA Specifications
Offset Error VOS — 2 5 mV Referred to Input, applies to both
channels
Gain Error Match — 0.5 — % FOUT (Note 5)
Internal Voltage Reference
Voltage — 2.4 — V
Tolerance — ±2 — %
Tempco — 15 — ppm/°C
Reference Input
Input Range 2.2 — 2.6 V
Input Impedance 3.2 — — kΩ
Input Capacitance — — 10 pF
Analog Inputs
Maximum Signal Level — — ±1 V CH0+,CH0-,CH1+,CH1- to AGND
Differential Input Voltage — — ±470/G mV G = PGA Gain on Channel 0
Range Channel 0
Differential Input Voltage — — ±660 mV
Range Channel 1
Input Impedance 390 — — kΩ Proportional to 1/MCLK
Oscillator Input
Frequency Range MCLK 1 — 4 MHz
Power Specifications
Operating Voltage 4.5 — 5.5 V AVDD, DVDD
IDD,A IDD,A — 2.3 2.8 mA AVDD pin only
IDD,D IDD,D — 0.8 1.2 mA DVDD pin only
Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is
measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 75 Hz.
See typical performance curves for higher frequencies and increased dynamic range. This parameter is
not 100% production tested.
2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between
measured output frequency and expected transfer function.
3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz,
CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1 Vpp @ 100 Hz. DC PSRR: 5V ±500 mV
4: Error applies down to 60 degree lead (PF = 0.5 capacitive) and 60 degree lag (PF = 0.5 inductive).
5: Refer to Section 4.0 “Device Overview” for complete description.
7: 1 MCLK period at 3.58 MHz is equivalent to less than < 0.005 degrees at 50 or 60 Hz.

MCP3909
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 4.5V to 5.5V, AGND, DGND = 0V.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA -40 — +85 °C
Operating Temperature Range TA -40 — +125 °C Note
Storage Temperature Range TA -65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 24L-SSOP θJA — 73 — °C/W
Note: The MCP3909 operates over this extended temperature range, but with reduced performance. In any case,
the Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.

MCP3909
TIMING CHARACTERISTICS
AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter Sym Min Typ Max Units Comment
Frequency Outputs
FOUT0 and FOUT1 Pulse Width tFW — 275 — ms 984376 MCLK periods
(Logic Low) (Note 1)
HFOUT Pulse Width tHW — 90 — ms 322160 MCLK periods
(Note 2)
FOUT0 and FOUT1 Pulse Period tFP Refer to Equation 4-1 s
HFOUT Pulse Period tHP Refer to Equation 4-2 s
FOUT0 to FOUT1 Falling-Edge tFS2 — 0.5 tFP —
Time
FOUT0 to FOUT1 Minimum Sepa- tFS — 4/MCLK —
ration
Digital I/O
FOUT0 and FOUT1 Output High VOH 4.5 — — V IOH = 10 mA, DVDD = 5.0V
Voltage
FOUT0 and FOUT1 Output Low VOL — — 0.5 V IOL = 10 mA, DVDD = 5.0V
Voltage
HFOUT and NEG Output High VOH 4.0 — — V IOH = 5 mA, DVDD = 5.0V
Voltage
HFOUT and NEG Output Low VOL — — 0.5 V IOL = 5 mA, DVDD = 5.0V
Voltage
High-Level Input Voltage VIH 2.4 — — V DVDD = 5.0V
(All Digital Input Pins)
Low Level Input Voltage VIL — — 0.85 V DVDD = 5.0V
(All Digital Input Pins)
Input Leakage Current — 0.1 ±1 µA VIN = 0, VIN = DVDD
Pin Capacitance — — 10 pF (Note 3)
Serial Interface Timings (Note 4)
Data Ready Pulse Width tDR 4/MCLK
Reset Time tRST 100 — — ns
Output Data Rate fADC — MCLK/256 —
Serial Clock Frequency fCLK — 20 MHz VDD = 5V
Window for serial mode entry tWINDOW — — 32/ — Last bit must be clocked in
codes MCLK before this time.
Window start time for serial tWINSET 1/MCLK — — — First bit must be clocked in
mode entry codes after this time.
Serial Clock High Time tHI — — 25 ns fCLK= 20 MHz
Serial Clock Low Time tLO — — 25 ns fCLK= 20 MHz
CS Fall to First Rising CLK Edge tSUCS 15 — — ns
Data Input Setup Time tSU 10 — — ns
Data Input Hold Time tHD — — 10 ns
Note 1: If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.
2: If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. When F2, F1, F0
equals 0,1,1, the HFOUT pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz
4: Serial timings specified and production tested with 180 pF load.

MCP3909
TIMING CHARACTERISTICS (CONTINUED)
AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C.
Parameter Sym Min Typ Max Units Comment
CS Rise to Output Disable tDIS — — 150 ns
CLK Rise to Output Data Valid tDO — — 30 ns
SDO Rise Time tR — 2 — ns
SDO Fall Time tF — 2 — ns
Note 1: If output pulse period (tFP) falls below 984376*2 MCLK periods, then tFW = 1/2 tFP.
2: If output pulse period (tHP) falls below 322160*2 MCLK periods, then tHW = 1/2 tHP. When F2, F1, F0
equals 0,1,1, the HFOUT pulse time is fixed at 64 x MCLK periods or 18 µs for MCLK = 3.58 MHz
4: Serial timings specified and production tested with 180 pF load.
tFP
tFW
FOUT0
tFS
tFS2
FOUT1
tHW
HFOUT
tHP
NEG
FIGURE 1-1: Output Timings for Active Power Pulse Outputs and Negative Power Pin.
CS
tSUCS
tCLK tHI tLO
CLK
tSU tHD
SDI
tDO tDIS
tR tF
Hi-z
SDO
FIGURE 1-2: Serial Interface Timings showing Output, Rise, Hold, and CS Times.

MCP3909
VDD
( V DD – V OL )
R = ------------------------------------
I OL
SPI Data
Output
Pin ( V OH )
180 pF
R = ------------------
I OH
FIGURE 1-3: SPI Output Pin Loading Circuit During SPI Testing.

MCP3909
2.0 TYPICAL PERFORMANCE CURVES
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise specified, DVDD, AVDD = 5V; AGND, DGND = 0V; VREF = Internal, HPF = 1 (AC mode),
MCLK = 3.58 MHz, CH1 input = 660 mVP-P at 50 Hz, CH0 amplitude sweeps at 50 Hz.
1 1
0.8 0.8
Measurement Error (%)

0.6 0.6
0.4 +85°C
0.4 +85°C
0.2 +25°C 0.2 +25°C
0 0
-0.2 -40°C `
-0.2 -40°C
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0.0000 0.0001 0.0010 0.0100 0.1000 0.0000 0.0001 0.0010 0.0100 0.1000
CH0 Vp-p Amplitude (V) CH0 Vp-p Amplitude (V)
FIGURE 2-1: Active Power Measurement FIGURE 2-4: Active Power Measurement
Error (Gain = 8 PF = 1). Error (Gain = 8, PF = 0.5).
1 1
0.8 0.8
0.6 0.6 +85°C

+85°C
0.4 0.4
+25°C 0.2 +25°C
0.2
0 0 -40°C
- 40°C
-0.2 -0.2
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0.0000 0.0001 0.0010 0.0100 0.1000 0.0000 0.0001 0.0010 0.0100 0.1000
Error (Gain = 16, PF = 1). Error (Gain = 16, PF = 0.5).
1 1
0.8 0.8
0.6 0.6
0.4 +85°C 0.4 +85°C
0.2 0.2
0 +25°C 0 +25°C
-0.2 - 40°C -0.2 -40°C
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0.0001 0.0010 0.0100 0.1000 1.0000 0.0001 0.0010 0.0100 0.1000 1.0000
Error (Gain = 2, PF = 1). Error (Gain =2, PF = 0.5).

MCP3909
1 3000
0.8 16384 Samples
2500 Mean = -1.20 mV

0.6
Std. Dev. = 25.1 µV
0.4 +85°C 2000
Occurance
0.2
0 +25°C
1500
-0.2 - 40°C
1000
-0.4
-0.6 500
-0.8
-1 0
-1.30
-1.27
-1.25
-1.22
-1.20
-1.18
-1.16
-1.13
-1.11
0.0001 0.0010 0.0100 0.1000 1.0000
CH0 Vp-p Amplitude (V) Bin (mV)
FIGURE 2-7: Active Power Measurement FIGURE 2-10: Channel 0 Offset Error
Error (Gain = 1, PF = 1). (DC Mode, HPF off, G = 2, PF = 1).
L
1 1200
0.8 16384 Samples
1000 Mean = -1.65 mV

0.6
Std. Dev = 16.99 µV
0.4 800
+85°C Occurance
0.2
600
0 +25°C
-0.2 -40°C 400
-0.4
200
-0.6
-0.8 0
-1
-1.72
-1.70
-1.69
-1.68
-1.67
-1.66
-1.65
-1.64
-1.62
-1.61
-1.60
-1.59
0.0001 0.0010 0.0100 0.1000 1.0000
CH0 Vp-p Amplitude (V) Bin (mV)
FIGURE 2-8: Active Power Measurement FIGURE 2-11: Channel 0 Offset Error
Error (Gain = 1, PF = 0.5). (DC Mode, HPF off, G = 8, PF = 1).
3000 600
16,384 Samples 16384 Samples
2500 Mean = -1.62 mV 500 Mean = - 17.91 mV
Std. Dev = 54.6 µV Std. Dev = - 1.22 µV
Occurance
2000 400
Occurance
1500 300
1000 200
500 100
0
0
-1.30 -1.25 -1.23 -1.20 -1.17
-1.77 -1.68 -1.59 -1.50
Bin (mV) Bin (mV)
FIGURE 2-9: Channel 0 Offset Error FIGURE 2-12: Channel 0 Offset Error
(DC Mode, HPF off, G = 1, PF = 1). (DC Mode, HPF Off, G = 16, PF = 1).

MCP3909
0.3 0.3
0.25

0.2
0.2
VDD=5.0V
0.15 0.1
+85°C
0.1
VDD=4.5V 0 +25°C
0.05 VDD=4.75V
VDD=5.25V - 40°C
0 -0.1
-0.05
VDD=5.5V -0.2
-0.1
-0.15 -0.3
0.0001 0.0010 0.0100 0.1000 1.0000 0.0001 0.0010 0.0100 0.1000 1.0000
Error over VDD , Internal VREF (G = 16, PF = 1). Error with External VREF (G = 1, PF = 1).
0.2 1
0.8

0.15 0.6
VDD=4.5V 0.4
0.1
VDD=4.75V 0.2 +85°C
+25°C
0.05 0
VDD=5.0V -0.2 -40°C
0 -0.4
VDD=5.25V
-0.05 -0.6
VDD=5.5V -0.8
-0.1 -1
0.0001 0.0010 0.0100 0.1000 1.0000 0.0001 0.0010 0.0100 0.1000 1.0000
Error over VDD, External VREF (G = 1, PF = 1). Error with External VREF (G = 1, PF = 0.5).
0.5 0.5
0.4 PF = 0.5 0.4
0.3 0.3
0.2 0.2
0.1 +85°C
% Error
0.1
0 0 +25°C
-0.1 -0.1 - 40°C
-0.2 -0.2
-0.3 PF = 1 -0.3
-0.4 -0.4
-0.5 -0.5
45 50 55 60 65 70 75 0.0001 0.0010 0.0100 0.1000 1.0000
Frequency (Hz) CH0 Vp-p Amplitude (V)
Error vs. Input Frequency (G = 16). Error with External VREF (G = 2, PF = 1).

MCP3909
1 1
0.8 0.8

0.6 0.6
0.4 0.4
+85°C
0.2 +85°C 0.2
0 0 +25°C
-0.2 -40°C -0.2 - 40°C
+25°C
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0.0001 0.0010 0.0100 0.1000 1.0000 0.0000 0.0001 0.0010 0.0100 0.1000
Error with External VREF (G = 2, PF = 0.5). Error with External VREF (G = 16, PF = 1).
1 1
0.8 0.8

0.6 0.6
0.4 0.4
0.2 +85°C 0.2 +25°C -40°C
+25°C
0 0
-0.2 +85°C
-0.2 -40°C
-0.4 -0.4
-0.6 -0.6
-0.8 -0.8
-1 -1
0.0000 0.0001 0.0010 0.0100 0.1000 0.0000 0.0001 0.0010 0.0100 0.1000
Error with External VREF (G = 8, PF = 1). Error with External VREF (G =16, PF = 0.5).
1 100 100
0.8 90 SINAD (dBFS) 90
0.6 80 80
70
SINAD (dBFS)
0.4 70
0.2 +25°C +85°C 60 60 SINAD (dB)
0 50 SINAD(dB) 50
-0.2 -40°C 40 40
-0.4 30 30
-0.6 20 20
-0.8 10 10
-1 0 0
0.0000 0.0001 0.0010 0.0100 0.1000 0.0001 0.0010 0.0100 0.1000 1.0000
FIGURE 2-21: Active Power Measurement FIGURE 2-24: Signal-to-Noise and

Error with External VREF (G = 8, PF = 0.5). Distortion Ratio vs. Input Signal Amplitude
(G = 1).

MCP3909
100 100 100 100

90 SINAD (dBFS) 90 90 90
80 80 80 80
70 70 70 SINAD (dBFS) 70
SINAD (dBFS)
SINAD (dBFS)
SINAD (dB)
SINAD (dB)
60 60 60 60
50 50 50 50
SINAD (dB)
40 40 40 40
30 30 30 30
SINAD (dB)
20 20 20 20
10 10 10 10
0 0 0 0
0.000100 0.001000 0.010000 0.100000 1.000000 0.000010 0.000100 0.001000 0.010000 0.100000
FIGURE 2-25: Signal-to-Noise and FIGURE 2-27: Signal-to-Noise and

Distortion Ratio vs. Input Signal Amplitude Distortion Ratio vs. Input Signal Amplitude
(G = 2). (G = 16).
100 100 0
90 90 -20
80 SINAD (dBFS) 80
-40
Amplitude (dB)
70 70
SINAD (dBFS)
SINAD (dB)
60 60 -60
50 50 -80
40 40
SINAD (dB) -100
30 30
20 20 -120
10 10 -140
0 0
-160
0.00001 0.0001 0.001 0.01 0.1
0 2000 4000 6000
CH0 Vp-p Amplitude (V) Frequency (Hz)
FIGURE 2-26: Signal-to-Noise and FIGURE 2-28: Frequency Spectrum,

Distortion Ratio vs. Input Signal Amplitude 50 Hz Input Signal.
(G = 8).

MCP3909
NOTES:

MCP3909
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1: PIN FUNCTION TABLE
MCP3909
Symbol Description
SSOP
1 DVDD Digital Power Supply Pin
2 HPF High-Pass Filters Control Logic Pin
3 AVDD Analog Power Supply Pin
4 NC No Connect
5 CH0+ Non-Inverting Analog Input Pin for Channel 0 (Current Channel)
6 CH0- Inverting Analog Input Pin for Channel 0 (Current Channel)
7 CH1- Inverting Analog Input Pin for Channel 1 (Voltage Channel)
8 CH1+ Non-Inverting Analog Input Pin for Channel 1 (Voltage Channel)
9 MCLR Master Clear Logic Input Pin
10 REFIN/OUT Voltage Reference Input/Output Pin
11 AGND Analog Ground Pin, Return Path for internal analog circuitry
12 SCK / F2 Serial Clock or Frequency Control for HFOUT Logic Input Pin
13 SDI / F1 Serial Data Input or Frequency Control for FOUT0/1 Logic Input Pin
14 CS / F0 Chip Select or Frequency Control for FOUT0/1 Logic Input Pin
15 G1 Gain Control Logic Input Pin
16 G0 Gain Control Logic Input Pin
17 OSC1 Oscillator Crystal Connection Pin or Clock Input Pin
18 OSC2 Oscillator Crystal Connection Pin or Clock Output Pin
19 NC No Connect
20 SDO / NEG Serial Data Out or Negative Power Logic Output Pin
21 DGND Digital Ground Pin, Return Path for Internal Digital Circuitry
22 HFOUT High-Frequency Logic Output Pin (Intended for Calibration)
23 FOUT1 Differential Mechanical Counter Logic Output Pin
24 FOUT0 Differential Mechanical Counter Logic Output Pin
3.1 Digital VDD (DVDD) 3.3 Analog VDD (AVDD)

DVDD is the power supply pin for the digital circuitry AVDD is the power supply pin for the analog circuitry
within the MCP3909. within the MCP3909.
This pin requires appropriate bypass capacitors and This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified should be maintained to 5V ±10% for specified
operation. Refer to Section 6.0 “Applications operation. Refer to Section 6.0 “Applications
Information”. Information”.
3.2 High-Pass Filter Input Logic Pin

(HPF)
HPF controls the state of the high-pass filter in both
input channels. A logic ‘1’ enables both filters,
removing any DC offset coming from the system or the
device. A logic ‘0’ disables both filters allowing DC
voltages to be measured.

MCP3909
3.4 Current Channel (CH0-, CH0+) 3.9 Serial Clock Input or F2 Frequency
CH0- and CH0+ are the fully differential analog voltage Control Pin
input channels for the current measurement, containing This dual function pin can act as either the serial clock
a PGA for small-signal input, such as shunt current
input for SPI communication or the F2 selection for the
sensing. The linear and specified region of this channel
high-frequency output and low-frequency output pin
is dependant on the PGA gain. This corresponds to a
ranges, changing the value of the constants FC and
maximum differential voltage of ±470 mV/G and
maximum absolute voltage, with respect to AGND, of HFC used in the device transfer function. FC and HFC
±1V. Up to ±6V can be applied to these pins without the are the frequency constants that define the period of
risk of permanent damage. the output pulses for the device.
Refer to Section 1.0 “Electrical Characteristics”.
3.10 Serial Data Input or F1 Frequency
3.5 Voltage Channel (CH1-,CH1+) Control Pin
This dual function pin can act as either the serial data
CH1- and CH1+ are the fully differential analog voltage
input for SPI communication or the F1 selection for the
input channels for the voltage measurement. The linear
high-frequency output and low-frequency output pin
and specified region of these channels have a
ranges, changing the value of the constants FC and
maximum differential voltage of ±660 mV and a
HFC used in the device transfer function. FC and HFC
maximum absolute voltage of ±1V, with respect to
are the frequency constants that define the period of
AGND. Up to ±6V can be applied to these pins without
the output pulses for the device.
the risk of permanent damage.
Refer to Section 1.0 “Electrical Characteristics”.
3.11 Chip Select (CS) or F0 Frequency
Control Pin
3.6 Master Clear (MCLR)
This dual function pin can act as either the chip select
MCLR controls the reset for both delta-sigma ADCs, all
for SPI communication or the F0 selection for the high-
digital registers, the SINC filters for each channel and frequency output and low-frequency output pin ranges
all accumulators post multiplier. The MCLR pin is also by changing the value of the constants FC and HFC
used to change pin functionality and enter the serial used in the device transfer function. FC and HFC are
interface mode. A logic ‘0’ resets all registers and holds the frequency constants that define the period of the
both ADCs in a Reset condition. The charge stored in output pulses for the device.
both ADCs is flushed and their output is maintained to
0x0000h. The only block consuming power on the
digital power supply during Reset is the oscillator 3.12 Gain Control Logic Pins (G1, G0)
circuit. G1 and G0 select the PGA gain (G) on Channel 0 from
four different values: 1, 2, 8 and 16.
3.7 Reference (REFIN/OUT)
REFIN/OUT is the output for the internal 2.4V 3.13 Oscillator (OSC1, OSC2)
reference. This reference has a typical temperature OSC1 and OSC2 provide the master clock for the
coefficient of 15 ppm/°C and a tolerance of ±2%. In device. A resonant crystal or clock source with a similar
addition, an external reference can also be used by sinusoidal waveform must be placed across these pins
applying voltage to this pin within the specified range. to ensure proper operation. The typical clock frequency
This pin requires appropriate bypass capacitors to specified is 3.579545 MHz. However, the clock
AGND, even when using the internal reference only. frequency can be within the range of 1 MHz to 4 MHz
Refer to Section 6.0 “Applications Information”. without disturbing measurement error. Appropriate
load capacitance should be connected to these pins for
3.8 Analog Ground (AGND) proper operation.
A full-swing, single-ended clock source may be
AGND is the ground connection to internal analog
connected to OSC1 with proper resistors in series to
circuitry (ADCs, PGA, band gap reference, POR). To
ensure no ringing of the clock source due to fast
ensure accuracy and noise cancellation, this pin must
transient edges.
be connected to the same ground as DGND, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this device be tied to
this plane of the PCB. This plane should also reference
all other analog circuitry in the system.

MCP3909
3.14 Serial Data Output or Negative 3.16 High-Frequency Output (HFOUT)
Power Output Logic Pin (NEG) HFOUT is the high-frequency output of the device and
This dual function pin can act as either the serial data supplies the instantaneous real-power information. The
output for SPI communication or NEG. NEG detects the output is a periodic pulse output, with its period propor-
phase difference between the two channels and will go tional to the measured real power, and to the HFC
to a logic ‘1’ state when the phase difference is greater constant defined by F0, F1 and F2 pin logic states. This
than 90° (i.e., when the measured real power is output is the preferred output for calibration due to
negative). The output state is synchronous with the faster output frequencies, giving smaller calibration
rising-edge of HFOUT and maintains the logic ‘1’ until times. Since this output gives instantaneous real
the real power becomes positive again and HFOUT power, the 2ω ripple on the output should be noted.
shows a pulse. However, the average period will show minimal drift.
3.15 Ground Connection (DGND) 3.17 Frequency Output (FOUT0, FOUT1)

DGND is the ground connection to internal digital FOUT0 and FOUT1 are the frequency outputs of the
circuitry (SINC filters, multiplier, HPF, LPF, device that supply the average real-power information.
digital-to-frequency converter and oscillator). To The outputs are periodic pulse outputs, with its period
ensure accuracy and noise cancellation, DGND must be proportional to the measured real power, and to the FC
connected to the same ground as AGND, preferably constant, defined by F0 and F1 pin logic states. These
with a star connection. If a digital ground plane is pins include high-output drive capability for direct use
available, it is recommended that this device be tied to of electromechanical counters and 2-phase stepper
this plane of the Printed Circuit Board (PCB). This motors. Since this output supplies average real power,
plane should also reference all other digital circuitry in any 2ω ripple on the output pulse period is minimal.
the system.

MCP3909
NOTES:

MCP3909
4.0 DEVICE OVERVIEW 4.1 Active Power
The MCP3909 is an energy metering IC that serves two The instantaneous power signal contains the active-
distinct functions that can operate simultaneously: power information; it is the DC component of the
instantaneous power. The averaging technique can be
- Active Power Pulse Output
used with both sinusoidal and non-sinusoidal
- Waveform Output via SPI Interface waveforms, as well as for all power factors. The
For the active power output, the device supplies a instantaneous power is thus low-pass filtered in order
frequency output proportional to active (real) power, to produce the instantaneous real-power signal.
and higher frequency output proportional to the A digital-to-frequency converter accumulates the
instantaneous power for meter calibration. instantaneous active real power information to produce
For the waveform output, it can be used serially to output pulses with a frequency proportional to the
gather 16-bit voltage channel and current channel A/D average real power. The low-frequency pulses present
data, or 20-bit wide multiplier output data. Both at the FOUT0 and FOUT1 outputs are designed to drive
channels use 16-bit, second-order, delta-sigma ADCs electromechanical counters and two-phase stepper
that oversample the input at a frequency equal to motors displaying the real-power energy consumed.
MCLK/4, allowing for wide dynamic range input signals. Each pulse corresponds to a fixed quantity of real
A Programmable Gain Amplifier (PGA) increases the energy, selected by the F2, F1 and F0 logic settings. The
usable range on the current input channel (Channel 0). HFOUT output has a higher frequency setting and less
Figure 4-1 represents the simplified block diagram of integration period such that it can represent the
the MCP3909, detailing its main signal processing instantaneous real-power signal. Due to the shorter
blocks. accumulation time, it enables the user to proceed to
faster calibration under steady load conditions (see
Two digital high-pass filters cancel the system offset on Section 4.8 “Active Power FOUT0/1 and HFOUT
both channels such that the real-power calculation Output Frequencies”).
does not include any circuit or system offset. After
being high-pass filtered, the voltage and current signals
are multiplied to give the instantaneous power signal.
This signal does not contain the DC offset components,
such that the averaging technique can be efficiently
used to give the desired active-power output.
CH0+
MCP3909
+
CH0- -
PGA ADC HPF
FOUT0
ANALOG DIGITAL
X ..0101... FOUT1
HFOUT
LPF DTF
CH1+ +
CH1- -
ADC HPF
Frequency
Content
0 0 0 0 0
Input Signal with ADC Output code

System offset and contains System DC Offset INSTANTANEOUS INSTANTANEOUS
line frequency and ADC offset removed by HPF POWER REAL POWER
FIGURE 4-1: Active Power Signal Flow with Frequency Contents.

MCP3909
4.2 Analog Inputs reached. The DC saturation point is around 700 mV for
Channel 0 and 1V for Channel 1, using internal voltage
The MCP3909 analog inputs can be connected directly reference. The output code will be locked past the
to the current and voltage transducers (such as shunts saturation point to the maximum output code.
or current transformers). Each input pin is protected by
specialized ESD structures that are certified to pass The clocking signals for the ADCs are equally
5 kV HBM and 500V MM contact charge. These distributed between the two channels in order to
structures also allow up to ±6V continuous voltage to minimize phase delays to less than 1 MCLK period
be present at their inputs without the risk of permanent (see Section 3.2 “High-Pass Filter Input Logic Pin
damage. (HPF)”). The SINC filters main notch is positioned at
MCLK/256 (14 kHz with MCLK = 3.58 MHz), allowing
Both channels have fully differential voltage inputs for the user to be able to measure wide harmonic content
better noise performance. The absolute voltage at each on either channel. The data ready signals used for
pin relative to AGND should be maintained in the ±1V synchronization of the part with a MCU will come at a
range during operation in order to ensure the measure- rate of MCLK/256 and a pipeline delay of 3 data readys
ment error performance. The common-mode signals is required to settle the SINC 3rd order digital filter. The
should be adapted to respect both the previous magnitude response of the SINC filter is shown in
conditions and the differential input voltage range. For Figure 4-2.
best performance, the common-mode signals should
be referenced to AGND.
0
The current channel comprises a PGA on the front-end
Normal Mode Rejection (dB)

to allow for smaller signals to be measured without -20
additional signal conditioning. The maximum
-40
differential voltage specified on Channel 0 is equal to
±470 mV/Gain (see Table 4-1). The maximum peak -60
voltage specified on Channel 1 is equal to ±660 mV. -80
TABLE 4-1: GAIN SELECTIONS -100
Maximum -120
G1 G0 CH0 Gain
CH0 Voltage 0 5 10 15 20 25 30
0 0 1 ±470 mV Frequency (kHz)
0 1 2 ±235 mV
FIGURE 4-2: SINC Filter Magnitude
1 0 8 ±60 mV
Response (MCLK = 3.58 MHz).
1 1 16 ±30 mV
4.4 Ultra-Low Drift VREF
4.3 16-Bit Delta-Sigma A/D Converters
The MCP3909 contains an internal voltage reference
The ADCs used in the MCP3909 for both current and source specially designed to minimize drift over
voltage channel measurements are delta-sigma ADCs. temperature. This internal VREF supplies reference
They comprise a second-order, delta-sigma modulator voltage to both current and voltage channels ADCs.
using a multi-bit DAC and a third-order SINC filter. The The typical value of this voltage reference is 2.4V
delta-sigma architecture is very appropriate for the ±100 mV. The internal reference has a very low typical
applications targeted by the MCP3909 because it is a temperature coefficient of ±15 ppm/°C, allowing the
waveform-oriented converter architecture that can offer output frequencies to have minimal variation with
both high linearity and low distortion performance respect to temperature since they are proportional to
throughout a wide input dynamic range. It also creates (1/VREF)².
minimal requirements for the anti-aliasing filter design.
The multi-bit architecture used in the ADC minimizes The output pin for the voltage reference is REFIN/OUT.
quantization noise at the output of the converters Appropriate bypass capacitors must be connected to
without disturbing the linearity. the REFIN/OUT pin for proper operation
(see Section 6.0 “Applications Information”). The
Both ADCs have a 16-bit resolution, allowing wide input voltage reference source impedance is typically 4 kΩ,
dynamic range sensing. The oversampling ratio of both which enables this voltage reference to be overdriven
converters is 64. Both converters are continuously by an external voltage reference source.
converting during normal operation. When the MCLR
pin is low, both converters will be in Reset and output
code 0x0000h. If the voltage at the inputs of the ADC is
larger than the specified range, the linearity is no longer
specified. However, the converters will continue to
produce output codes until their saturation point is

MCP3909
If an external voltage reference source is connected to 4.6 High-Pass Filters and Multiplier
the REFIN/OUT pin, the external voltage will be used
as the reference for both current and voltage channel The active real-power value is extracted from the DC
ADCs. The voltage across the source resistor will then instantaneous power. Therefore, any DC offset
be the difference between the internal and external component present on Channel 0 and Channel 1
voltage. The allowed input range for the external affects the DC component of the instantaneous power
voltage source goes from 2.2V to 2.6V for accurate and will cause the real-power calculation to be
measurement error. A VREF value outside of this range erroneous. In order to remove DC offset components
will cause additional heating and power consumption from the instantaneous power signal, a high-pass filter
due to the source resistor, which might affect has been introduced on each channel. Since the
measurement error. high-pass filtering introduces phase delay, identical
high-pass filters are implemented on both channels.
The filters are clocked by the same digital signal,
4.5 Power-On Reset (POR)
ensuring a phase difference between the two channels
The MCP3909 contains an internal POR circuit that of less than one MCLK period. Under typical conditions
monitors analog supply voltage AVDD during operation. (MCLK = 3.58 MHz), this phase difference is less than
This circuit ensures correct device startup at system 0.005°, with a line frequency of 50 Hz. The cut-off
power-up and system power-down events. The POR frequency of the filter (4.45 Hz) has been chosen to
circuit has built-in hysteresis and a timer to give a high induce minimal gain error at typical line frequencies,
degree of immunity to potential ripple and noise on the allowing sufficient settling time for the desired
power supplies, allowing proper settling of the power applications. The two high-pass filters can be disabled
supply during power-up. A 0.1 µF decoupling capacitor by applying logic ‘0’ to the HPF pin.
should be mounted as close as possible to the
AVDD pin, providing additional transient immunity 0

(see Section 6.0 “Applications Information”). -5
The threshold voltage is typically set at 4V, with a -10
tolerance of about ±5%. If the supply voltage falls below -15
this threshold, the MCP3909 will be held in a Reset -20
condition (equivalent to applying logic ‘0’ on the MCLR -25
pin). The typical hysteresis value is approximately
-30
200 mV in order to prevent glitches on the power sup-
-35
ply.
-40
Once a power-up event has occurred, an internal timer 0.1 1 10 100 1000
prevents the part from outputting any pulse for
Frequency (Hz)
approximately 1s (with MCLK = 3.58 MHz), thereby
preventing potential metastability due to intermittent FIGURE 4-4: HPF Magnitude Response
resets caused by an unsettled regulated power supply.
(MCLK = 3.58 MHz).
Figure 4-3 illustrates the different conditions for a
power-up and a power-down event in the typical The multiplier output gives the product of the two
conditions. high-pass filtered channels, corresponding to
instantaneous real power. Multiplying two sine wave
signals by the same ω frequency gives a DC
AVDD component and a 2ω component. The instantaneous
power signal contains the real power of its DC
component, while also containing 2ω components
5V coming from the line frequency multiplication. These
4.2V
4V
2ω components come for the line frequency (and its
harmonics) and must be removed in order to extract the
1s real-power information. This is accomplished using the
low-pass filter and DTF converter.
0V Time
NO
PROPER
DEVICE RESET PULSE RESET
OPERATION
MODE OUT
FIGURE 4-3: Power-on Reset Operation.

MCP3909
4.7 Active Power Low-Pass Filter and application will then remove the small sinusoidal
DTF Converter content of the output frequency and filter out the
remaining 2ω ripple.
For the active power signal calculation, the MCP3909
HFOUT is intended to be used for calibration purposes
uses a digital low-pass filter. This low-pass filter is a
due to its instantaneous power content. The shorter
first-order IIR filter, which is used to extract the active
integration period of HFOUT demands that the 2ω
real-power information (DC component) from the
component be given more attention. Since a sinusoidal
instantaneous power signal. The magnitude response
signal average is zero, averaging the HFOUT signal in
of this filter is detailed in Figure 4-5. Due to the fact that
steady-state conditions will give the proper real energy
the instantaneous power signal has harmonic content
value.
(coming from the 2ω components of the inputs), and
since the filter is not ideal, there will be some ripple at
the output of the low-pass filter at the harmonics of the 4.8 Active Power FOUT0/1 and HFOUT
line frequency. Output Frequencies
The cut-off frequency of the filter (8.9 Hz) has been The thresholds for the accumulated energy are
chosen to have sufficient rejection for commonly-used different for FOUT0/1 and HFOUT (i.e., they have
line frequencies (50 Hz and 60 Hz). With a standard different transfer functions). The FOUT0/1 allowed
input clock (MCLK = 3.58 MHz) and a 50 Hz line output frequencies are quite low in order to allow
frequency, the rejection of the 2ω component (100 Hz) superior integration time (see Section 4.7 “Active
will be more than 20 dB. This equates to a 2ω Power Low-Pass Filter and DTF Converter”). The
component containing 10 times less power than the FOUT0/1 output frequency can be calculated with the
main DC component (i.e., the average active real following equation:
power).
EQUATION 4-1: FOUT FREQUENCY
0 OUTPUT EQUATION
-5 8.06 × V 0 × V 1 × G × F C
-10 F OUT ( Hz ) = ----------------------------------------------------------
-
2
-15
( V REF )
Where:
-20
-25 V0 = the RMS differential voltage on
-30 Channel 0
-35 V1 = the RMS differential voltage on
-40 Channel 1
0.1 1 10 100 1000 G = the PGA gain on Channel 0 (current
Frequency (Hz) channel)
FIGURE 4-5: LPF1 Magnitude Response FC = the frequency constant selected

(MCLK = 3.58 MHz). VREF = the voltage reference
The output of the low-pass filter is accumulated in the

digital-to-frequency converter. This accumulation is For a given DC input V, the DC and RMS values are
compared to a different digital threshold for FOUT0/1 equivalent. For a given AC input signal with amplitude
and HFOUT, representing a quantity of real energy of V, the equivalent RMS value is V/ sqrt(2), assuming
measured by the part. Every time the digital threshold purely sinusoidal signals. Note that since the real
on FOUT0/1 or HFOUT is crossed, the part will output a power is the product of two RMS inputs, the output
pulse (See Section 4.8 “Active Power FOUT0/1 and frequencies of AC signals are half of the DC inputs
HFOUT Output Frequencies”). ones, again assuming purely sinusoidal AC signals.
The constant FC depends on the FOUT0 and FOUT1
The equivalent quantity of real energy required to digital settings. Table 4-2 shows FOUT0/1 output
output a pulse is much larger for the FOUT0/1 outputs frequencies for the different logic settings.
than the HFOUT. This is such that the integration period
for the FOUT0/1 outputs is much larger. This larger
integration period acts as another low-pass filter so that
the output ripple due to the 2ω components is minimal.
However, these components are not totally removed,
since realized low-pass filters are never ideal. This will
create a small jitter in the output frequency. Averaging
the output pulses with a counter or a MCU in the

MCP3909
TABLE 4-2: ACTIVE POWER OUTPUT FREQUENCY CONSTANT FC FOR FOUT0/1 (VREF = 2.4V)
FOUT Frequency (Hz) FOUT Frequency (Hz)
FC (Hz)
F1 F0 FC (Hz) with Full-Scale with Full-Scale
(MCLK = 3.58 MHz)
DC Inputs AC Inputs
0 0 MCLK/221 1.71 0.74 0.37
20
0 1 MCLK/2 3.41 1.48 0.74
1 0 MCLK/219 6.83 2.96 1.48
18
1 1 MCLK/2 13.66 5.93 2.96
The high-frequency output HFOUT has lower 4.8.1 MINIMAL OUTPUT FREQUENCY
integration times and, thus, higher frequencies. The FOR NO-LOAD THRESHOLD
output frequency value can be calculated with the
The MCP3909 also includes, on each output
following equation:
frequency, a no-load threshold circuit that will eliminate
any creep effects in the meter. The outputs will not
EQUATION 4-2: ACTIVE POWER HFOUT show any pulse if the output frequency falls below the
FREQUENCY OUTPUT no-load threshold. This threshold only applies to the
EQUATION pulse outputs and does not gate any serial data coming
8.06 × V 0 × V 1 × G × HF C from either the A/D output or the multiplier output. The
HF OUT ( Hz ) = ---------------------------------------------------------------
- minimum output frequency on FOUT0/1 and HFOUT is
2
( V REF ) equal to 0.0015% of the maximum output frequency
Where: (respectively FC and HFC) for each of the F2, F1 and F0
selections (see Table 4-2 and Table 4-3); except when
V0 = the RMS differential voltage on F2, F1, F0 = 011. In this last configuration, the no-load
Channel 0 threshold feature is disabled. The selection of FC will
V1 = the RMS differential voltage on determine the start-up current load. In order to respect
Channel 1 the IEC standards requirements, the meter will have to
G = the PGA gain on Channel 0 be designed to allow start-up currents compatible with
(current channel) the standards by choosing the FC value matching
these requirements. For additional applications
HFC = the frequency constant selected
information on no-load threshold, startup current and
VREF = the voltage reference other meter design points, refer to AN994,
"IEC Compliant Active Energy Meter Design Using The
The constant HFC depends on the FOUT0 and FOUT1 MCP3905/6”, (DS00994).
digital settings with the Table 4-3.
The detailed timings of the output pulses are described
in the Timing Characteristics table (see Section 1.0
“Electrical Characteristics” and Figure 1-1).
TABLE 4-3: OUTPUT FREQUENCY CONSTANT HFC FOR HFOUT (VREF = 2.4V)
HFC (Hz) HFOUT Frequency (Hz) with
F2 F1 F0 HFC HFC (Hz)
(MCLK = 3.58 MHz) full scale AC Inputs
0 0 0 64 x FC MCLK/215 109.25 27.21
0 0 1 32 x FC MCLK/215 109.25 27.21
0 1 0 16 x FC MCLK/215 109.25 27.21
0 1 1 2048 x FC MCLK/27 27968.75 6070.12
1 0 0 128 x FC MCLK/216 219.51 47.42
1 0 1 64 x FC MCLK/216 219.51 47.42
1 1 0 32 x FC MCLK/216 219.51 47.42
1 1 1 16 x FC MCLK/216 219.51 47.42

MCP3909
NOTES:

MCP3909
5.0 SERIAL INTERFACE After a serial mode has been entered, all blocks of the
MCP3909 device are still operational. The PGA, A/D
DESCRIPTION
converters, HPF, multiplier, LPF, and other digital
sections are still functional, allowing the device to have
5.1 Dual Functionality Pin And Serial true dual functionality in energy metering systems.
Interface Overview
The MCP3909 device contains three serial modes that DVDD 1 24 FOUT0
are accessible by changing the pin functionality of the HPF 2 23 FOUT1
NEG, F2, F1, and F0 pins to SDO, SCK, SDI and CS, AVDD 3 22 HFOUT
NC 4 21 DGND
respectively.
CH0+ 5 20 NEG / SDO
These modes are entered by giving the MCP3909 CHO- 6 19 NC
device a serial command on these pins during a time CH1- 7 18 CLKOUT
window after device reset or POR. During this window CH1+ 8 17 CLKIN
of time, F2 acts as SCK, F1 acts as SDI and F0 acts MCLR 9 16 G0
REFIN / OUT 10 15 G1
as CS. Once a serial mode has been entered, the
AGND 11 14 F0 / CS
device must be reset to disable mode functionality, or
F2 / SCK 12 13 F1 / SDI
change to another serial mode. This is done by using
MCLR pin or power on reset event.
FIGURE 5-1: Dual Functionality Pins for
During serial mode entry and the three serial modes, the MCP3909.
data is clocked into the device on the rising edge of
SCK and out of the device on the falling edge of SCK.
The SPI data can be access at up to 20 MHz. This
speed enables quick data retrieval in between
conversion times. For 3-phase metering applications
with multiple ADCs, this fast communication is essen-
tial to allow for power calculation windows between
conversions, as shown in Figure 5-3.
IRQ
tSAMPLE
tLINE_CYC
IRQ Phase A,B,C I & V Data
SDO DR 16 bits
x 6 ADCs DR
tSAMPLE
FIGURE 5-2: Data Access between Data Ready Pulses using SPI Interface for a 3-phase System.

MCP3909
MCLR tWINDOW
tWINSET
1
2 3 4 5 6 7 8
F2 / SCK
F0 / CS
F1 / SDI D7 D6 D5 D4 D3 D2 D1 D0
FIGURE 5-3: Dual Functionality Pin Serial Mode Entry Protocol.
5.2 Serial Mode Entry Codes After entering any of these modes the active power
calculation block is still functional and presents output
The MCP3909 devices contains three different serial pulses on FOUT0, FOUT1, and HFOUT. For this reason,
modes with data presented in 2's complement coding. the F2, F1, F0 output frequency selection constant can
• Multiplier Output be changed with multiple command bytes for serial
• Dual Channel Output mode entry.
• Filter Input The command bytes to enter these modes are
described in Table 5-1.
TABLE 5-1: ENTRY CODES

Internal State of F2, F1, F0 Constants Frequency
Command Selection During Serial Mode (1)
Serial Mode
D7......D0
F2 F1 F0
1 0 1 0 0 0 0 1 Multiplier Output 0 F1 pin 1
1 0 1 0 1 0 0 1 Multiplier Output 1 F1 pin 1
1 0 1 0 0 1 0 0 Dual Channel Output Pre HPF1 0 F1 pin 1
1 0 1 0 1 1 0 0 Dual Channel Output Post HPF1 1 F1 pin 1
1 0 1 0 1 0 1 0 Filter Input 1 0 F0 pin
Note 1: The active power frequency outputs FOUT0, FOUT1, and HFOUT remain active after serial mode entry.
Leaving the SDI (F1) and CS (F0) pins at a known state after serial communication will control the
frequency selection. The HPF pin controls the state of the HPF for the multiplier mode output and the
output pulses from the active power D to F block.

MCP3909
5.3 Multiplier Output Mode clock cycles and a new multiplier output value is ready.
If the multiplier value is not clocked out of the device it
Multiplier mode allows the user to retrieve the output will be over-written. Data is clocked out on the rising
of the multiplier on the MCP3909 device. Data is edge of SCK.
presented in a 20 bit (19 bit + sign) protocol, MSB first.
A data ready flag (DR) is output for every MCLK/256
+ – + –
( CH0 – CH0 ) ( CH1 – CH1 )
Multiplier Code = --------------------------------------------------------------------------------- • 524288 • 8.06 • G
V REF 2
TABLE 5-2: MULTIPLIER OUTPUT MODE CODING

Binary Decimal
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 +524287
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 +524286
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -1
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 -524287
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 -524288
F0 / CS
X 20
1 2 3 4 17 18 19 20
F2 / SCK
X 20
Hi-z Hi-z
NEG / SDO DR D19 D18 D17 D16 D3 D2 D1 D0 0
SIGN MSB LSB

Hi-z
F1 / SDI
FIGURE 5-4: Multiplier Output Mode.

MCP3909
5.4 Dual Channel Output Mode A data ready flag (DR) is output for every MCLK / 256
clock cycles and a new filter output value is ready. If the
This mode allows the user to retrieve the individual dual channel output values are not clocked, and is not
channel information from the ADC outputs. The ADC clocked out of the device, they will be over-written.
outputs of both channels are synchronized together
and their data ready is represented by the data ready The following formulas relate the channel input
pulse on SDO. If the ADC output values are not clocked voltages to their respective output code. The code
out of the device, they will be over-written. A 32-bit data locks to +32767 on the positive side, and to -32768 on
word is given, each channel is 16 bits (15 bits + sign), the negative side.
presented in 2's complement coding. Channel 1 comes
first then channel 0.
⎛ ( V IN+ – V IN- )⎞ 0.66

Channel 0 Code = ⎜ ------------------------------------⎟ × 32768 × ⎛ 8.06 × -----------⎞ × PGA
⎝ V REF ⎠ ⎝ 0.47⎠
( V IN+ – V IN- ) 0.47

Channel 1 Code = ------------------------------------ × 32768 × ⎛ 8.06 × -----------⎞
V REF ⎝ 0.66⎠
TABLE 5-3: CHANNEL OUTPUT MODE

CODING 5.5 High-Pass Filter Control
Binary Decimal There are two options for the channel output data. The
0 111 1111 1111 1111 + 32,767 first options collects the channel data pre-high pass
0 111 1111 1111 1110 + 32,766 filter, or the output of the SINC filter of the delta sigma
modulator. The second option collects the channel data
0 000 0000 0000 0000 0
post high pass filter. It is important to note that the
1 111 1111 1111 1111 -1 HPF pin controls the state of the high pass filter for this
1 000 0000 0000 0001 - 32,767 second option. If the HPF pin is low, the post high pass
1 000 0000 0000 0000 - 32,768 filter mode will output all zero's. This HPF pin must be
high to access the post HPF data in the channel output
mode.
F0 / CS
X 16 X 32 X 16
1 2 15 16 17 18 31 32
F2 / SCK
X 16 X 32 X 16
Hi-z Hi-z
NEG / SDO DR D31 D30 D17 D16 D15 D14 D1 D0
Channel 1 Channel 0
Hi-z
F1 / SDI
FIGURE 5-5: Dual Channel Output Mode.

MCP3909
5.6 Filter Input Mode When using filter input mode, the user must wait for
the data ready flag (DR) to appear on SDO before
The filter input mode allows the user to feed the attempting to clock in data to the device. The user can
MCP3909 device an input to the LPF1. Data is not access either the multiplier output or the dual
received MSB first. The MCP3909 will treat this data channel output while in this mode.
as if it were the output of the multiplier and will LPF
and D-F the result as normal, giving the resulting
output frequency on HFOUT, FOUT0 and FOUT1. See
Tables 4-2 and 4-3 for transfer functions of the output
frequencies.
F0 / CS
X 20
1 2 3 4 17 18 19 20
F2 / SCK
X 20
F1 / SDI Hi-z
D19 D18 D17 D16 D3 D2 D1 D0
Hi-z
NEG / SDO DR
FIGURE 5-6: Filter Input Mode.

MCP3909
5.7 Using the MCP3909 with 5.7.1 SPI MODE DEFINITIONS
Microcontroller (MCU) SPI Ports The following table represents the standard SPI mode
With microcontroller SPI ports, it is required to send terminology, the respective PIC bit settings, and a
groups of eight bits. It is also required that the description of compatibility for the MCP3909 device.
microcontroller SPI port be configured to clock out data The MCP3909 works in SPI mode 0,1 mode, that is the
on the falling edge of clock and latch data in on the data is clocked out of the part on the rising edge and
rising edge, or vice versa depending on the mode. clocked in on the falling edge of SCK.
TABLE 5-4: SPI MODE COMPATIBILITY
Standard SPI PIC Control Bits

State MCP3909
Mode Description
Compatibility
Terminology CKP CKE
0,0 0 1 — Idle state for clock is low level, transmit (from PIC)
occurs from active to idle clock state
0,1 0 0 Idle state for clock is low level, transmit (from PIC)
√ occurs from idle to active clock state
1,0 1 1 — Idle state for clock is high level, transmit (from PIC)
occurs from active to idle clock state
1,1 1 0 — Idle state for clock is high level, transmit (from PIC)
occurs from idle to active clock state

MCP3909
F0 / CS
MCU latches data from
Device on falling edges of SCK
F2 / SCK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Data is clocked out

on rising edges of SCK
F1 / SDI Don’t Care
NEG / SDO
D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4
MCU Transmit Buffer X X X X X X X X X X X X X X X X
D11 D10 D9 D8 D4
MCU Receive Buffer D19 D18 D17 D16 D15 D14 D13 D12 D7 D6 D5
Data stored into MCU receive register Data stored into MCU receive register
after transmission of first 8 bits after transmission of second 8 bits
F0 / CS
F2 / SCK 17 18 19 20 21 22 23 24
D3 D2 D1 D0
NEG / SDO
MCU Transmit Buffer X X X X X X X X
MCU Receive Buffer D3 D2 D1 D0 0 0 0 0
X = Don’t Care Bits

Data stored into MCU receive register
after transmission of third 8 bits
N = Null Bits
FIGURE 5-7: Multiplier Output Mode 1 SPI Communication using 8-bit segments (Mode 0,1:
SCK idles low).

MCP3909
F0 / CS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
F2 / SCK
Data is clocked out
on rising edges
CHANNEL 0
NEG / SDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MCU Receive Buffer D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CH0 Data stored into MCU receive regis- CH0 Data stored into MCU receive register
ter after transmission of first 8 bits after transmission of second 8 bits
F0 / CS
F2 / SCK 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Data is clocked out

on rising edges
CHANNEL 1
NEG / SDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
MCU Receive Buffer D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CH1 Data stored into MCU receive regis- CH1 Data stored into MCU receive register
ter after transmission of third 8 bits after transmission of fourth 8 bits
FIGURE 5-8: Dual Channel Output Mode SPI Communication using 8-bit segments
(Mode 0,1: SCK idles low).

MCP3909
6.0 APPLICATIONS INFORMATION 6.1 Performing RMS, Apparent Power,
and Active Power using MCP3909
The following application figures represent meter
designs using the MCP3909 device. Some of these Waveform data
applications ideas are available as fully function meter Figure 6-1 represents power calculations from
reference designs and demo boards. For complete waveform data based on a PIC MCU and MCP3909
schematic and for fully function meter designs, visit device. The PIC MCU accomplishes the following
Microchip’s web page for demo board and reference energy meter calculation outputs per phase, per line
design availability. cycle:
- RMS Current
- RMS Voltage
- Active Power
- Apparent Power
Output registers for the power quantities and
calibration registers for phase, offset, gain, and LSB
adjustment are available through a serial interface to
the PIC microcontroller. See Microchip’s web page for
firmware solution and demo board.
The example signal flow here shows 4 output power
quantities and 6 calibration registers. For a 60 Hz
design that is using 128 samples per line cycle for the
power calculation the MCP3909 would have a new
data ready pulse every 130 µs. The SPI
communication to gather 16-bits x 2 channels at
10 MHz is approximately 3.2 µs, leaving ~125 µs for
the power calculations before the next sample is ready.
MCP3909 PIC Microcontroller
RMS Current
ADC X2 S X X Apparent Power

CURRENT
PHA_I_RMS_OFF:16 PHA_VA_GAIN:16
X S X Active Power
VOLTAGE
ADC F PHA_DELAY:8 PHA_W_GAIN:16
PHA_W_OFF:32
PHA_V_RMS_OFF:16
X2 S RMS Voltage
FIGURE 6-1: Power Calculations from Waveform sampling using PIC MCU. Register names shown
are used on MCP3909 Energy Meter Reference Design.

MCP3909
6.2 Achieving Line Cycle Sampling A simpler lower cost option would be to choose a
with Zero Blind Cycles frequency that would give an integer number of line
cycles for exactly 50 Hz (or 60 Hz). This is possible
In most energy meter applications, it will be necessary using a 39.3216 MHz crystal for the PIC18F device.
to have 2N samples for each 50 or 60 Hz line cycle,
Figure 6-2 shows example clock frequencies to
where N is typically 64, 128 or 256. Controlling the
achieve 128 samples for each line cycle, 1.63 MHz for
MCLK of the MCP3909 allows you to control the
a 50 Hz line, or 1.96 MHz for a 60 Hz line. The
sample rate and ultimately the data ready (DR) pulses
MCP3909 clock can operate from 1 MHz to 4 MHz.
for coherent waveform sampling. The following
scheme shows how the TIMER and COMPARATOR Using this approach, the PIC MCU can gather the
modules of the PIC MCU can be used to generate the waveform data immediately after the data ready pulse,
clock for the MCP3909 from either a PLL internal at up to 10 MHz. The remainder of the time can be used
MCLK. For class 0.2 or class 0.1 meter designs that to calculate the power measurements to achieve true
require harmonic analysis using a PLL is line cycle sampling with zero blind cycles.
recommended to shift sample rate with line cycle drift, For more information and firmware, see the Microchip’s
e.g. line cycle changes from 60 Hz to 59.1 Hz. This is web page for demo board information.
shown as option 1 in Figure 6-2.
128 samples/line cycle

X1
Phase A || B || C 39.3216 MHz
50 (or 60 Hz) (50 or 60 Hz)
1.63 MHz (50)
PLL Circuit 1.96 MHz (60) 3.579 MHz PIC MCU
x 32768 CCP2 / 32768
Option 1 Option 2
MCLK input
MCP3909 To PIC MCU

MCP3909 MCP3909
IRQ IRQ
SDO
SDO
SDO
DR Pulse
tSAMPLE
tLINE_CYC
IRQ Phase A,B,C I & V Data
SDO DR 16 bits
x 6 ADCs DR
tSAMPLE
FIGURE 6-2: Using the PIC device to control the MCP3909 MCLK to achieve 2N samples per line
cycle, 3-phase sampling shown with 6 ADCs

MCP3909
N L PHA_W:16 kW
ENERGY_W:64 kWhr
ENERGY_VA_GLSB:16 kVAhr
PHA_I_RMS:16 A
PHA_V_RMS:16 V
LCD
...
RB0
RB7
AVDD,DVDD CLKIN RC1/CCP2
CH0+
CH0- RC3/SCK
MCP3909 SCK
Resistor Divider CH1+ SDI RC5/SDO
CH1- SDO RC4/SDI
AGND,DGND CS RA0/ANO
OSC1
40 MHZ
PIC MCU
OSC2
Power Supply
Circuitry
RX/RC6
RS-232
TX/RC7
To PC or
Calibration
GND Equipment
FIGURE 6-3: Simplified MCU Based Energy Meter.
6.3 Meter Calibration 6.4 Analog Meter Design Tips

To achieve meter calibration the MCP3909 waveform For analog design tips and PCB layout recommenda-
samples are adjusted during the power calculations on tions, refer to AN994, "IEC Compliant Active Energy
the PIC MCU. In Figure 6-3, this interface is shown via Meter Design Using The MCP390X” (DS00994). This
RS-232 on the PIC microcontroller. This process is application note includes all required energy meter
streamlined using calibration software available from design information, including the following:
Microchip’s web site. • Meter rating and current sense choices
• Shunt design
• PGA selection
• F2, F1, F0 selection
• Meter calibration
• Anti-aliasing filter design
• Compensation for parasitic shunt inductance
• EMC design
• Power supply design
• No-Load threshold
• Start-up current
• Accuracy Testing Results from MCP390X-based
meter
• EMC Testing Results from MCP390X-based
meter

MCP3909
NOTES:

MCP3909
7.0 PACKAGING INFORMATION
7.1 Package Marking Information
24-Lead SSOP Examples:
XXXXXXXXXXXX MCP3909
XXXXXXXXXXXX I/SS^^
e3
YYWWNNN 0951256
Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
e3 Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

MCP3909

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MCP3909
APPENDIX A: REVISION HISTORY
Revision B (April 2009)

The following is the list of modifications:
1. Updated EDS information and Timing
Characteristics in Section 1.0 “Electrical
Characteristics”.
Revision A (December 2006)

• Original Release of this Document.

MCP3909
NOTES:

MCP3909
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. -X /XX Examples:

a) MCP3909-I/SS: Energy Metering IC
Device Temperature Package Industrial Temperature,
Range 24LD SSOP.
b) MCP3909T-I/SS: Tape and Reel,
Device: MCP3909: Energy Metering IC Energy Metering IC
MCP3909T: Energy Metering IC Industrial Temperature,
(Tape and Reel) 24LD SSOP.
Temperature Range: I = -40°C to +85°C
Package: SS = Plastic Shrink Small Outline (209 mil Body),

24-lead

MCP3909
NOTES:

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Accuron,
and may be superseded by updates. It is your responsibility to
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
ensure that your application meets with your specifications.
PICSTART, rfPIC, SmartShunt and UNI/O are registered
MICROCHIP MAKES NO REPRESENTATIONS OR trademarks of Microchip Technology Incorporated in the
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
U.S.A. and other countries.
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION, FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SEEVAL, SmartSensor and The Embedded Control Solutions
QUALITY, PERFORMANCE, MERCHANTABILITY OR Company are registered trademarks of Microchip Technology
FITNESS FOR PURPOSE. Microchip disclaims all liability Incorporated in the U.S.A.
arising from this information and its use. Use of Microchip Analog-for-the-Digital Age, Application Maestro, CodeGuard,
devices in life support and/or safety applications is entirely at dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
the buyer’s risk, and the buyer agrees to defend, indemnify and ECONOMONITOR, FanSense, In-Circuit Serial
hold harmless Microchip from any and all damages, claims, Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
suits, or expenses resulting from such use. No licenses are Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
conveyed, implicitly or otherwise, under any Microchip PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
intellectual property rights. PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.

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03/26/09

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MCP3909

Functional Block Diagram

F2/SCK F1/SDI F0/CS NEG/SDO

© 2009 Microchip Technology Inc. DS22025B-page 1

DS22025B-page 2 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS22025B-page 3

DS22025B-page 4 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS22025B-page 5

DS22025B-page 6 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS22025B-page 7

DS22025B-page 8 © 2009 Microchip Technology Inc.

Measurement Error (%)

0.6 0.6 +85°C

CH0 Vp-p Amplitude (V) CH0 Vp-p Amplitude (V)

© 2009 Microchip Technology Inc. DS22025B-page 9

2500 Mean = -1.20 mV

1000 Mean = -1.65 mV

DS22025B-page 10 © 2009 Microchip Technology Inc.

Measurement Error (%)

Measurement Error (%)

© 2009 Microchip Technology Inc. DS22025B-page 11

Measurement Error (%)

Measurement Error (%)

FIGURE 2-21: Active Power Measurement FIGURE 2-24: Signal-to-Noise and

DS22025B-page 12 © 2009 Microchip Technology Inc.

100 100 100 100

FIGURE 2-25: Signal-to-Noise and FIGURE 2-27: Signal-to-Noise and

FIGURE 2-26: Signal-to-Noise and FIGURE 2-28: Frequency Spectrum,

© 2009 Microchip Technology Inc. DS22025B-page 13

DS22025B-page 14 © 2009 Microchip Technology Inc.

3.1 Digital VDD (DVDD) 3.3 Analog VDD (AVDD)

3.2 High-Pass Filter Input Logic Pin

© 2009 Microchip Technology Inc. DS22025B-page 15

DS22025B-page 16 © 2009 Microchip Technology Inc.

3.15 Ground Connection (DGND) 3.17 Frequency Output (FOUT0, FOUT1)

© 2009 Microchip Technology Inc. DS22025B-page 17

DS22025B-page 18 © 2009 Microchip Technology Inc.

Input Signal with ADC Output code

FIGURE 4-1: Active Power Signal Flow with Frequency Contents.

© 2009 Microchip Technology Inc. DS22025B-page 19

Normal Mode Rejection (dB)

TABLE 4-1: GAIN SELECTIONS -100

0 0 1 ±470 mV Frequency (kHz)

DS22025B-page 20 © 2009 Microchip Technology Inc.

Normal Mode Rejection (dB)

FIGURE 4-3: Power-on Reset Operation.

© 2009 Microchip Technology Inc. DS22025B-page 21

FIGURE 4-5: LPF1 Magnitude Response FC = the frequency constant selected

The output of the low-pass filter is accumulated in the

DS22025B-page 22 © 2009 Microchip Technology Inc.

© 2009 Microchip Technology Inc. DS22025B-page 23

DS22025B-page 24 © 2009 Microchip Technology Inc.

IRQ Phase A,B,C I & V Data

© 2009 Microchip Technology Inc. DS22025B-page 25

FIGURE 5-3: Dual Functionality Pin Serial Mode Entry Protocol.

TABLE 5-1: ENTRY CODES

DS22025B-page 26 © 2009 Microchip Technology Inc.

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