This configuration is called Complementary MOS (CMOS).

The circuit topology is 173

complementary push-pull in the sense that for high input, the nMOS transistor drives
(pulls down) the output node while the pMOS transistor acts as the load, and for low input MOS Inverters:
the pMOS transistor drives (pulls up) the output node while the nMOS transistor acts as Static
the load. Consequently, both devices contribute equally to the circuit operation charac- Characteristics
teristics.

VDD VDO

T...
Vin = VDSn

(a) (b)

Figure5.16. (a) CMOS inverter circuit. (b)Simplified view of the CMOS inverter, consisting
of two complementary nonideal switches.

The CMOS inverter has two important advantages over the other inverter configu-
rations. The first and perhaps the most important advantage is that the steady-state power
dissipation of the CMOS inverter circuit is virtually negligible, except for small power
dissipation due to leakage currents. In all other inverter structures examined so far, a
nonzero steady-state current is drawn from the power source when the driver transistor
is turned on, which results in a significant DC power consumption. The other advantages
of the CMOS configuration are that the voltage transfer characteristic (VTC) exhibits a
full output voltage swing between 0 V and VDD, and that the VTC transition is usually very
sharp. Thus, the VTC of the CMOS inverter resembles that of an ideal inverter.
Since nMOS and pMOS transistors must be fabricated on the same chip side- by-side,
the CMOS process is more complex than the standard nMOS-only process. In particular,
the CMOS process must provide an n-type substrate for the pMOS transistors and a p-type
substrate for the nMOS transistors. This can be achieved by building either n-type tubs
(wells) on a p-type wafer, or by building p-type tubs on an n-type wafer (cf. Chapter 2).
In addition, the close proximity of an nMOS and a pMOS transistor may lead to the
formation of two parasitic bipolar transistors, causing a latch-up condition. In order to
prevent this undesirable effect, additional guardringsmust be built around the nMOS and
the pMOS transistors as well (cf. Chapter 13). The increased process complexity of
CMOS fabrication may be considered as the price being paid for the improvements
achieved in power consumption and noise margins.
174

CHAPTER 5
Circuit Operation

In Fig. 5.16, note that the input voltage is connected to the gate terminals of both the
I
nMOS and the pMOS transistors. Thus, both transistors are driven directly by the input
signal, Vin. The substrate of the nMOS transistor is connected to the ground, while the
substrate of the pMOS transistor is connected to the power supply voltage, VDD, in order
to reverse-bias the source and drain junctions. Since VSB = 0 for both devices, there will
be no substrate-bias effect for either device. It can be seen from the circuit diagram in Fig.
5.16 that

VGS,,n = Vif
(5.51)
VDS,. = Vo.t
and also,
VGS, P =-(VDD- Vif)
(5.52)
VDS P =-(VDD - Vut)

We will start our analysis by considering two simple cases. When the input voltage
is smaller than the nMOS threshold voltage, i.e., when Vi, < V.,, the nMOS transistor
is cut-off. At the same time, the pMOS transistor is on, operating in the linear region.
Since the drain currents of both transistors are approximately equal to zero (except for
small leakage currents),, i.e.,

D,n = IDp = (5.53)

the drain-to-source voltage of the pMOS transistor is also equal to zero, and the output
voltage VOH is equal to the power supply voltage.

VOUt = VOH = VDD (5.54)

On the other hand, when the input voltage exceeds (VDD + VT )' the pMOS transistor is
turned off. In this case, the nMOS transistor is operating in the linear region, but its drain-
to-source voltage is equal to zero because condition (5.53) is satisfied. Consequently, the
output voltage of the circuit is
I
V..t =VOL = ° (5.55) I

Next, we examine the operating modes of the nMOS and the pMOS transistors as
functions of the input and output voltages. The nMOS transistor operates in saturation i
if Vin > VMOn and if the following condition is satisfied.

VDSnVGSn -VTO,n X Vo >Vin -VTo,n (5.56)

The pMOS transistor operates in saturation if V11 < (VDD + V7ThP), and if: 17

VDSP < VGSp VTOP ¢_* out < Vn-VTO, p (5.57) MOS Inverter,
Stati
Characteristic

OmL pMOS in saturation

E both in saturation

VTOp VTOn VIL VIH VDD + VTOP VDD

Input Voltage (V)

Figqre 5.17. Operating regions of the nMOS and the pMOS transistors.

Both of these conditions for device saturation are illustrated graphically as shaded areas
on the Vu - V plane in Fig. 5.17. A typical CMOS inverter voltage transfer characteristic
is also superimposed for easy reference. Here, we identify five distinct regions, labeled
A through E, each corresponding to a different set of operating conditions. The table
below lists these regions and the corresponding critical input and output voltage levels.

Region V V° nMOS pMOS

A < VTOl VOH cut-off linear
B VIL high = VOH saturation linear
C V ^Vth Vth saturation saturation
D VIH low VOL linear saturation
E >(VDD + VTO, p) VOL linear cut-off
176 In Region A, where Vin< V.,, the nMOS transistor is cut-off and the output voltage
is equal to VOH = VDD. As the input voltage is increased beyond Vm,, (into Region B), the
CHAPIER 5 nMOS transistor starts conducting in saturation mode and the output voltage begins to
decrease. Also note that the critical voltage VIL which corresponds to (dV.., /dVin) = -1
is located within Region B. As the output voltage further decreases, the pMOS transistor
enters saturation at the boundary of Region C. It is seen from Fig. 5.17 that the inverter
threshold voltage, where VI, = VOU, is located in Region C. When the output voltage V.",
falls below (Vin - V7,n), the nMOS transistor starts to operate in linear mode. This
corresponds to Region D in Fig. 5.17, where the critical voltage point VIH with (dV0 ,,,
dVjn) = -1 is also located. Finally, in Region E, with the input voltage Vi > (VLD + Vp),
the pMOS transistor is cut-off, and the output voltage is VOL = 0.
In a simplistic analogy, the nMOS and the pMOS transistors can be seen as nearly
ideal switches- controlled by the input voltage- that connect the output node to the power
supply voltage or to the ground potential, depending on the input voltage level. The
qualitative overview of circuit operation, illustrated in Fig. 5.17 and discussed above,
also highlights the complementary nature of the CMOS inverter. The most significant
feature of this circuit is that the current drawn from the power supply in both of these
steady-state operating points, i.e., in Region A and in Region E, is nearly equal to zero.
The only current that flows in either case is the very small leakage current of the reverse-
biased source and drain junctions. The CMOS inverter can drive any load, such as
interconnect capacitance or fanout logic gates which are connected to its output node,
either by supplying current to the load, or by sinking current from the load.
The steady-state input-output voltage characteristics of the CMOS inverter can be
better visualized by considering the interaction of individual nMOS and pMOS transistor
characteristics in the current-voltage space. We already know that the drain current IDn
of the nMOS transistor is a function of the voltages VGSf and VDS,n. Hence, the nMOS
drain current is also a function of the inverter input and output voltages V,. and VO,,,
according to (5.51).

I D'n = f (in VOWt)

This two-variable function, which is essentially described by the current equations (3.54)
through (3.56), can be represented as a surface in the three-dimensional current-voltage
space. Figure 5.18 shows this IDn(Vin V0 ,t) surface for the nMOS transistor.

Similarly, the drain current ID p of the pMOS transistor is also a function of the
inverter input and output voltages Vin and Vot, according to (5.52).

ID,p = f (Vin V.,H)

This two-variable function, described by the current equations (3.57) through (3.59), can
be represented as another surface in the three-dimensional current-voltage space. Figure:
5.19 shows the corresponding IDP(Vin Vut) surface for the pMOS transistor.
 A

17

MOS Inverters
Static
4_-
I - Characteristic
E
3-

0 2-

C 1-
0 5

0-
0 3
1
2
3
4
! UV 0,I
#'Put Voltage (V)

Figure 5.18. Current-voltage surface representing the nMOS transistor characteristics.

E
.- 3
C;
x

. 2
0
1
U
5
4
0
0 3
N

-
inPut Voltage (V) 5 0 OJIR_

Figure 5.19. Current-voltage surface representing the pMOS transistor characteristics.

178

CHAPTER 5 J

4-

0
2~
0
.C 1'
0 5

0
0

- -w~e ()

Figure 5.20. Intersection of the current-voltage surfaces shown in Figures 5.18 and 5.19.

<E 4- 5
6 3- 0S
x

2 2-
I D

oa

-t 5
Input Voltage (V)

angle.
Figure 5.21. The intersecting current-voltage surfaces shown from a different viewing
Notice that projection of the intersection curve on the voltage plane gives the VTC.
 Remember that in a CMOS inverter operating in steady-state, the drain current of the 179
nMOS transistor is always equal to the drain current of the pMOS transistor, according
to KCL. MOS Inverters:
D,n = ID,p Static
Characteristics
Thus, the intersection of the two current-voltage surfaces shown in Figs. 5.18 and 5.19
will give the operating curve of the CMOS inverter circuit in the three-dimensional
current-voltage space. The intersection of the two characteristic surfaces is shown in Fig.
5.20. The intersecting surfaces are shown from a different viewing angle in Fig. 5.21, with
the intersection curve highlighted in bold.
It is clear that the vertical projection of the intersection curve on the Vi - VOt plane
produces the typical CMOS inverter voltage transfer characteristic already shown in Fig.
5.17. Similarly, the horizontal projection of the intersection curve on the ID - Vin plane
gives the steady-state current drawn by the inverter from the power supply voltage as a
function of the input voltage. In the following, we will present an in-depth analysis of the
CMOS inverter static characteristics, by calculating the critical voltage points on the
VTC. It has already been established that VOn = VDD and VOL = 0 for this inverter; thus,
we will devote our attention to VILE VIH and the inverter switching threshold, Vth.

Calculation of VIL

By definition, the slope of the VTC is equal to (-1), i.e., dV0,, dVin = -1 when the input
voltage is V = VIL. Note that in this case, the nMOS transistor operates in saturation while
the pMOS transistor operates in the linear region. From IDn= ID p we obtain the following
current equation:

-(VGSfn-VTOn) = 2 2(VCSp-VTOP).VDSp VDsP (5.58)

Using equations (5.51) and (5.52), this expression can be rewritten as

- (- in-VTO, n ) = 2 *[2 (-Vn VDD - VTO,,,)

.( l- VDD )(Vl D

To satisfy the derivative condition at VILE we differentiate both sides of (5.59) with respect
to Vn.

k(VinkVTOn) =P[(V in DD TOp)(dV (V.,in

LP dV(
180 Substituting V, = VIL and (dVoutldVin) = -1 in (5.60), we obtain

CHAPTER 5 k.f(VIL -VTO,f) =kP (2VOUt- VIL +VTO,P -VDD) (5.61)

The critical voltage V1L can now be found as a function of the output voltage V,, as
follows:

2 V01 t +VTOIP VDD +kR VTO,(

IL VIL= 1 k
lI+kR (5.62)

where kR is defined as

R k

This equation must be solved together with the KCL equation (5.59) to obtain the
numerical value of VIL and the corresponding output voltage, V01, . Note that the solution
is fairly straightforward and does not require numerical iterations as in the previous cases,
since none of the transistors is subject to substrate-bias effects.

Calculation of V1H

When the input voltage is equal to VIH, the nMOS transistor operates in the linear region,
and the pMOS transistor operates in saturation. Applying KCL to the output node, we
obtain

2 [ (VGS,n VTO,n) DSnDSn 2 GSPTOP (563)

Using equations (5.51) and (5.52), this expression can be rewritten as

[n V')V V 2]kP _V V~
2 (Vin TOn out uti 2 (Vin DD TO,P) (5.64)

Now, differentiate both sides of (5.64) with respect to V,,.

kn (ViV TOn) d(.Yoiui' +vKut - vut ( dV0,,ut

*[(Vin- VrO~n)
in)+V°Ut OUT( d~in
( d-V)] (5.65)
= P ( n VDD VTO,P)

Substituting, Vin = VIH and (dV0ut dVin) = -1 in (5.65), we obtain

 I I I I 1
nk .(-VIH +VTOfl+2Vt)=kP (VIH VDD VTO,p) (5.66)

The critical voltage VIH can now be found as a function of VO, as follows: MOS Inverte
Ut~~~~~~~~~~~Sa
Characteristi
VI = VDD +VTOP +kR (2 V0 u, + VTofn) (5.67)
VIH= l+kR

Again, this equation must be solved simultaneously with the KCL equation (5.64) to
obtain the numerical values of VIH and VO,.

Calculationof Vth
Vth

The inverter threshold

threshold voltage
voltage is
is defined
defined as
as V,,
V = = Vi,
V = = V,,.t.
V0,u.Since
Since the
the CMOS
CMOS inverter
inverter
exhibits large noise
exhibits large noise margins
margins and
and aa very
very sharp
sharp VTC
VTC transition,
transition, the
the inverter
inverter threshold
voltage emerges as an important parameter characterizing the DC performance of the
inverter. For Vin
V, = VUV
VU, both transistors are
are expected to be in saturation mode; hence, we
can write the following KCL equation.

In
2 ((V.,,.
VGS,- VI.,n)' = 'P2
VTO,n) (VS,P
(VGIp - VTO, P)
VI.,p)' (5.68)
2 2

Replacing
Replacing VGSn and
VGSn and VGS'P
VSp inin (5.68) according to
5.68) according to (5.5
(5.51) and (5.52),
1) and we obtain
5.52), we obtain
'n )2=kp.(V _V _V

'(Vi. VTOn i 22 -'Vi"(Vi

i" V VTnVTOP)2
T.")2 (5.69)
(5.69)

The correct
The correct solution
solution for
for Vinfor
Vin for this
this equation
equation isis

MKin
Vin 1+
1+ L
LP
rk,
kP
VTOn++
= VTOn
rkn
_.(VDD+VTOP)
'(VDD VTO P) (5.70)
(530)

Finally, the
Finally, the inverter
inverter threshold
threshold (switching
(switching threshold)
threshold) voltage
voltage V,,
V, isis found
found as
as

VTO +
VTOn (VDD + VTOP)
'(VDD
FiR
Vth =
1+ 0+4
FR k
i(57
(5.71)
(5.71)
182 Note that the inverter threshold voltage is defined as Vth = Vln = VOt. When the input
voltage is equal to V, however, we find that the output voltage can actually attain any
CHAPTER 5 value between (Vth - V. n) and (Vth - V70 p), without violating the voltage conditions used
in this analysis. This is due to the fact that the VTC segment corresponding to Region C
in Fig. 5.17 becomes completely vertical if the channel-length modulation effect is
neglected, i.e., if A = 0. In more realistic cases with A > 0, the VTC segment in Region
C exhibits a finite, but very large, slope. Figure 5.22 shows the variation of the inversion
(switching) threshold voltage Vth as a function of the transconductance ratio kR, and for
fixed values of VDD, VM . and VP

2.0

1.9

1.8
2
1.7
0
M
Co
1.6
0)

a0) 1.5
IC
0
(I
1.4

1.3

1.2
0 0.5 1 1.5 2 2.5 3 3.5 4

Transconductance Ratio kR = (kn / kP)

Figure 5.22. Variation of the inversion threshold voltage as a function of kR.

It has already been established that the CMOS inverter does not draw any significant
current from the power source, except for small leakage and subthreshold currents, when
the input voltage is either smaller than V, or larger than (VDD+V7T ). The nMOS and
the pMOS transistors conduct a nonzero current, on the other hand, uring low-to-high
and high-to-low transitions, i.e., in Regions B, C, and D. It can be shown that the current
being drawn from the power source during transition reaches its peak value when V =
Vth. In other words, the maximum current is drawn when both transistors are operating
in saturation mode. Figure 5.23 shows the voltage transfer characteristic of a typical
CMOS inverter circuit and the power supply current, as a function of the input voltage.

Design of CMOS Inverters

The inverter threshold voltage Vth was identified as one of the most important parameters
that characterize the steady-state input-output behavior of the CMOS inverter circuit. The
CMOS inverter can, by virtue of its complementary push-pull operating mode, provide 183
a full output voltage swing between 0 and VDD, and therefore, the noise margins are
relatively wide. Thus, the problem of designing a CMOS inverter can be reduced to MOS Inverters:
setting the inverter threshold to a desired voltage value. Static
Characteristics
6 8.0

5
6.0
4 a
a) io
0) 0

0 3 4.0 c
a

0 2
2.0

0 0.0
0 1 2 3 4 5 6
InputVoltage (V)

Figure 5.23. Typical VTC and the power supply current of a CMOS inverter circuit.

Given the power supply voltage VDD, the nMOS and the pMOS transistor threshold
voltages, and the desired inverter threshold voltage Vth, the corresponding ratio kR can be
found as follows. Reorganizing (5.71) yields

1 Vth-VTO,n
(5.72)
VkR VDD + VTO p-Vth

Now solve for kR that is required to achieve the given Vh.

k, ( VDD +VTO, p - V)
(5.73)
kPT V1h VTO,n )

Recall that the switching threshold voltage of an ideal inverter is defined as

Vh, ideal - VDD (5.74)

2
184 Substituting (5.74) in (5.73) gives

CHAPTER 5 2kIiID~~lI(.5

cows ! ~~~~~~~~~~kP
ideal- (. a VrD VTO,, ) (5.75)

for a near-ideal CMOS VTC that satisfies the condition (5.74). Since the operations of
the nMOS and the pMOS transistors of the CMOS inverter are fully complementary, we
can achieve completely symmetric input-output characteristics by setting the threshold
voltages as V = V70 = IVM'PI. This reduces (5.75) to:

kp) metric (5.76)

Note that the ratio kR is defined as

k ju C. ( u W)

- u p C. - 'U .( ) (5 7 7 )

assuming that the gate oxide thickness tox, and hence, the gate oxide capacitance C0 xhave
the same value for both nMOS and pMOS transistors. The unity-ratio condition (5.76) for
the ideal symmetric inverter requires that

XL )n _Up 230 cm 2 /V-s

( W) An 580 cm 2 /V s (5.78)

Hence,

(WL) =2.(WL)n (5.79)

It should be noted that the numerical values used in (5.78)

5.78) for electron and hole mobilities
are typical values, and that exact yn An and /jP/up values will vary with surface doping
concentration of the substrate and the tub. The VTCs of three CMOS inverter circuits wit with
different kR ratios are shown in Fig. 5.24. It can be seen clearly that the inverter threshold
voltage Vth shifts to lower values with increasing kR kR ratio.
 185

6 MOS Inverters:
Static
Characteristics
5

> 3

02

0
0 1 2 3 4 5 6
Input Voltage (V)

Figure5.24. Voltage
Figure Volt, transfer characteristics of three CMOS inverters, with differentt nMOS-to-
nMOS -to-
pMOS ratios.

For a symmetric
symmel CMOS inverter with V7,, = IVPI and kR = 1, the critical
al voltage
VIL can be found, using (5.62), as follows:

VIL = 8 (3 VDD +2 VTOn) (5.80)

(5.80)
8

Also, the critical voltage VIH is found as

VIH = (5 VDD- 2 VTOf) (5.81)

(5.81)
8

Note that the sum of VIL and VIH is always equal to VDD in a symmetric inverter.

VIL + VIH = VDD (5.82)

The noise margins NML and NMH for this symmetric CMOS inverter are now calculated
using (5.3) and (5.4).
186 NML = IL-VOL = VIL

CHAPTER NMH = VOH-VIH = VDD VIH (5.83)

which are equal to each other, and also to V.

NML = NMH = VIL (5.84)

Example 5.4

Consider a CMOS inverter circuit with the following parameters:

VDD = 3 . 3 V
V =,n0.6 V
VTOP= -0.7 V
k== 200 pA/V 2
kp = 80 gA/V2

Calculate the noise margins of the circuit. Notice that the CMOS inverter being
considered here has kR = 2.5 and V.,, X IVTPI; hence, it is not a symmetric inverter.

First, the output low voltage VOL and the output high voltage VOH are found, using (5,54)
and (5.55), as VOL =0 and VOH = 5 V. To calculate VIL in terms of the output voltage, we
use (5.62).

2 V, + VTO P-VDD +kR VTOf

VIL= 1+kR

=V0, 0. 7-3.3 +15 =0.57V, -0. 71

1+2.5ou

Now substitute this expression into the KCL equation (5.59).

2.5(0.57V,-0.71-0.6) =2(0.57Vnt-0.71-3.3+0.7)(V,ut-3.3)-(Vou,-3.3)

This expression yields a second-order polynomial in V,, as follows:

.. 2 ~~~~
0. 66 VO.t 2 +0. 05 V - 6.65 = 0

Only one root of this quadratic equation corresponds to a physically correct solution for
Vet (i-e., V,t > 0).
 Kw = Vo",3.14
V f187

From this value, we can calculate the critical voltage VIL as: MOS Inverters:
Static
VL = 0. 57.3.14 - 0.71 = 1.08 V Characteristics

To calculate VIH in terms of the output voltage, use (5.67):

VI=VDD + VTO~p +kR .(2 Vout, +VTof.)

1+kR
3.3-0.7+2.5(2Vu, +0.6) +117
1+2.5 O+1

Next, substitute this expression into the KCL equation (5.64) to obtain a second-order
polynomial in Vut.

f ~2.5
[2 (1.43 V ~+9706)otvu2](.43 Vout - 1.43)'

2.61 + 6.94 V,-24

Again, only one root of this quadratic equation corresponds to the physically correct
solution for V, at this operating point, i.e., when V,. = VIH.

Vout =0.27 V

From this value, we can calculate the critical voltage VIH as:

VIH =1.43 0.37+1.17=1.55 V

Finally, we find the noise margins for low voltage levels and for high voltage levels using
(5.3) and (5.4).

NML = VIL -VOL = 1.08 V

NMH = VOH - VIH = 1. 75 V

Supply Voltage Scaling in CMOS Inverters

In the following, we will briefly examine the effects of supply voltage scaling, i.e.,
reduction of VDD, upon the static voltage transfer characteristics of CMOS inverters. The
188 overall power dissipation of any digital circuit is a strong function of the supply voltage
VDD. With the growing trend for reducing the power dissipation in large-scale integrated
CHAPTER 5 systems and especially in portable applications, reduction (or scaling) of the power
supply voltage emerges as one of the most widely practiced measures for low-power
design. While such reduction is usually very effective, several important issues must also
be addessed so that the system performance is not sacrificed. In this context, it is quite
relevant to explore the influence of supply voltage scaling upon the VTC of simple
CMOS inverter circuits.
The expressions we have developed in this section for VIL' V IH' and Vth indeed show
that the static characteristics of the CMOS inverter allow significant variation of the
supply voltage without affecting the functionality of the basic inverter. Neglecting
second-order effects such as subthreshold conduction, it can be seen that the CMOS
inverter will continue to operate correctly with a supply voltage which is as low as the
following limit value.

VDD -VTOn +VTO p (5.85)

This means that correct inverter operation will be sustained if at least one of the transistors
remains in conduction, for any given input voltage. Figure 5.25 shows the voltage transfer
characteristics of a CMOS inverter, obtained with different supply voltage levels. The
exact shape of the VtC near the limit value is essentially determined by subthreshold
conduction properties of the nMOS and pMOS transistors, yet it is clear that the circuit
operates as an inverter over a large range of supply voltages levels.

a) 3
co

I0 2

0
0 1 2 3 4 5 6
InputVoltage (V)

Figure 5.25. Voltage transfer characteristics of a CMOS inverter, obtained with different power
supply voltage levels.