Cpe - Eee241-Dld Lab Manual
Cpe - Eee241-Dld Lab Manual
Sarmad Hassan
Umair Safdar
Ahmad Mudassir
Supervised By
Dr. Abbas Javed
Acknowledgement
Contribution of the following faculty members is highly appreciated:
✓ Engr. Syed Junaid Akhtar
✓ Engr. Wajeeha Khan
✓ Engr. Sara Sajid
✓ Engr. Abdul Moeed
✓ Engr. Hasnain Kashif
✓ Engr. Arslan Khalid
✓ Engr. Nesruminallah
Books
Text Books
Reference Books
Theory CLOs:
1. CLO1: Comprehend the working with different number systems, Boolean algebra and mapping methods
using standard mathematical rules. (PLO1-C2)
2. CLO2: Analyze the working of combinational and sequential logic circuits using digital logic principles
and Boolean algebra. (PLO2-C4)
3. CLO3: Plan and design the combinational and sequential logic circuits using digital logic principles,
Boolean algebra and mapping methods. (PLO3-C5)
Lab CLOs:
4. CLO4: To analyze and design the combinational and sequential logic circuits using software and
hardware platforms. (PLO3-C5)
5. CLO5: Follow the software and hardware tools to reproduce the response of the digital logic circuits
using software and hardware platforms. (PLO5-P3)
6. CLO6: To explain and write effective lab reports of experiments performed during lab (PLO10-A3)
7. CLO7: To demonstrate the working of a digital logic circuit designed individually and by the teamwork
using software and hardware platforms. (PLO9-A3)
Grading Policy
The final marks for lab would comprise of Lab Assessment (25%), Lab S1 (10%), Lab S2 (15 %) and Lab
Terminal (50%).
S-I 0.5*(S-I Exam result) + 0.5* (average of lab evaluation of Lab 1-4)
S-II 0.5*(S-II Exam result) + 0.5*[ (average of lab evaluation of Lab 5-8) * 1.5]
Terminal 0.1*[(OEP marks out of 25)*2] +0.4*(Terminal Exam result out of 50) +0.25*[(average
of lab evaluation of Lab 9-12) *5] + 0.10*[(average of lab evaluation of Lab 5-8) *5] + 0.15*[(average
of lab evaluation of Lab 1-4) *5]
The minimum pass marks for both lab and theory shall be 50%. Students obtaining less than 50% marks
(in either theory or lab, or both) shall be deemed to have failed in the course. The final marks would be
computed with 75% weight to theory and 25% to lab final marks.
List of Equipment
IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7404 (NOT Gate), IC 7408 (AND Gate), IC 7432 (OR Gate),
IC 7447 (BCD to 7seg), IC 7486 (X-OR Gate), IC 74138 (De-multiplexer), IC 74148 (Encoder), IC 7420 (4
Input NAND GATE), IC 7474 (D Flip Flop), IC 7476 (J-K Flip Flop), IC 74147 (10 to 4 Line Encoder), IC
74139 (2 Line to 4 Decoder), IC 74153 (Dual Multiplexer 1 of 4), IC 74157 (quadruple 1 of 2 Data selector),
IC 7485 (4-Bit Comparator), IC 7495 (4-Bit Shift Register), 7483 (4-Bit Adder), Trainer Board
Software Resources
Proteus Professional 6.9
Lab Instructions
• This lab activity comprises of three parts: Pre-lab, Lab Tasks, Post Lab Tasks, Lab Report and
Conclusion and Viva session.
• The students should perform and demonstrate each lab task separately for step-wise evaluation.
• Only those tasks that are completed during the allocated lab time will be credited to the students.
• Students are however encouraged to practice on their own in spare time for enhancing their skills.
8) Make sure that the last connection to be made in your circuit is the power supply and first thing to be
disconnected is also the power supply.
9) Equipment should not be removed, transferred to any location without permission from the laboratory
staff.
10) Students are not allowed to use any equipment without proper orientation and actual hands on equipment
operation.
11) Smoking and drinking in the laboratory are not permitted.
All these rules and regulations are necessary precaution in Electronic Laboratory to safeguard the students,
laboratory staff, the equipment and other laboratory users.
Preface ii
Acknowledgement ii
Books ii
Grading Policy iv
List of Equipment v
Software Resources v
Lab Instructions v
LAB # 1: To Identify the Responses of Different Logic Gates using Hardware and Software Platforms 11
Objectives 11
Pre Lab 11
In- Lab 12
Post LAB: 21
LAB # 2: To Explain the Universality of NAND and NOR GATES in Order to Design Other Logic Gates 23
Objectives 23
Pre-Lab: 23
In-Lab 23
Post-Lab: 28
LAB # 3: To Show the output of simplified Boolean Expression by following the k-map, using Hardware and
Software Platforms 30
Objectives 30
Pre-Lab 30
In-Lab 31
LAB # 4: To Show the Behaviour of Binary Adder/Subtractor and reproduce its circuit using Universal Gates 36
Objectives 36
Pre-Lab 36
Part 1 -Familiarize yourself with Half Adder & Full Adder 36
In-Lab 37
Post-Lab: 43
LAB # 5: To Follow the Steps of BCD to Excess 3 Code Conversion and Reproduce the Results using Dedicated IC
45
Objectives 45
Pre Lab 45
In Lab 45
Post Lab 45
LAB # 6: To Follow the Steps of Binary to Gray Code Conversion and Reproduce the Results using Logic Gates 49
Objectives 49
Pre Lab 49
In-Lab 49
Post Lab: 53
LAB # 8: To Show the response of Binary Comparator(s) using hardware and software tools and to Reproduce
the Comparator using dedicated IC 65
Objectives 65
Pre Lab 65
Post Lab: 68
LAB # 9: To Show the response of an Encoder/Decoder and to Reproduce the binary converters using basic logic
gates 70
Objectives 70
Pre Lab 70
Part 1 - To realize a decoder circuit using basic gates and to verify IC 74LS139 70
Part 2 - To set up and test a 7-segment static display system to display numbers 0 to 9 70
In Lab 70
Post Lab: 77
LAB # 10: To Identify the Response of Sequential Circuit(s) using Hardware and Software Platforms 79
Objectives 79
Pre Lab 79
In Lab 79
Post Lab: 83
LAB # 11: To show the Response of Shift Registers using 7495 IC and Reproduce the shift registers using D-Flip-
Flops 85
Objectives 86
Pre Lab 86
In Lab 86
Post Lab 87
LAB # 12: To Reproduce a Synchronous Sequence Detector using hardware and software tools 89
Objectives 89
Pre Lab 89
In Lab 89
Post Lab 89
LAB # 13: To Show the Response of Ring and Johnson Counter using 7495 IC 94
Objectives 94
Pre Lab 94
In Lab 94
Post Lab 95
LAB # 14: To Reproduce the Asynchronous Counters using hardware and software tools 97
Pre Lab 97
In Lab: 97
• To identify various ICs used in proteus software and to perform basic functionality of
logic gates
Pre Lab
These basic logic gates are implemented as small-scale integrated circuits (SSICs) or as part of
more complex medium scale (MSI) or very large-scale (VLSI) integrated circuits. Digital IC
gates are classified not only by their logic operation, but also the specific logic-circuit family to
which they belong. Each logic family has its own basic electronic circuit upon which more
complex digital circuits and functions are developed. The following logic families are the most
frequently used.
TTL and ECL are based upon bipolar transistors. TTL has a well-established popularity among
logic families. ECL is used only in systems requiring high-speed operation. MOS and CMOS,
are based on field effect transistors. They are widely used in large scale integrated circuits
because of their high component density and relatively low power consumption. CMOS logic
consumes far less power than MOS logic. There are various commercial integrated circuit chips
available. TTL ICs are usually distinguished by numerical designation as the 5400 and 7400
series.
In- Lab
Lab Tasks-Part-A
Study and verify the truth table of logic gates
Lab Task 1:
0 0 1
0 1 1
Fig: 1.1
1 0 1
1 1 0
Table: 1.1
Lab Task 2:
Inputs Output
IC 7408 AND gate
A B
0 0 0
0 1 0
1 0 0
Fig: 1.2
1 1 1
Table: 1.2
Lab Task 3:
0 1
1 0
Fig: 1.3
Table: 1.3
Lab Task 4:
Inputs Output
IC 7402 NOR gate
A B
0 0
0 1
1 0
1 1
Fig: 1.4
Table: 1.4
IC 7432 OR gate
Output
A B
0 0 1
0 1 0
1 0 0
Fig: 1.5
1 1 0
Table: 1.5
Lab Task 6:
A B
Fig: 1.6 0 0 0
0 1 1
1 0 1
Table:
1.6 1 1 0
Proteus is a software for microprocessor simulation, schematic capture, and printed circuit board
(PCB) design. It is developed by Labcenter Electronics.
PROSPICE Mixed mode SPICE simulation - industry standard SPICE3F5 simulator combined
with a digital simulator.
ARES PCB Layout - PCB design system with automatic component placer, rip-up and retry
auto-router and interactive design rule checking.
VSM - Virtual System Modelling lets co-simulate embedded software for popular
microcontrollers alongside hardware design.
System Benefits
Integrated package with common user interface and fully context sensitive help. But we only use
the ISIS Schematic Capture
In Lab:
Lab Tasks-Part-B
Right click on the ISIS icon present on desktop and then open it.
Fig: 1.8
Lab Task 1:
Inputs Output
A B
0 0 0
0 1 0
1 0 0
1 1 1
Fig: 1.9
Table: 1.7
Search the Components by names and then click OK to adding them in Devices Panel
Fig: 1.11
Fig: 1.12
Fig: 1.13
Lab Task 2:
A B
0 0 0
0 1 1
Fig: 1.14
1 0 1
1 1 1
Table: 1.8
Lab Task 3:
0 1
Fig: 1.16
1 0
Table: 1.9
Fig: 1.17
Lab Task 4:
A B
Output
0 0 1
Fig: 1.18
0 1 1
Table: 1.10 1 0 1
1 1 0
Fig: 1.19
Lab Task 5:
Inputs
A B
Output
1 1 0
0 0 0
0 1 1
Fig: 1.21
Post Lab:
Fig: 1.22
A B C D F1 F2
0 0 0 0 0 0
0 0 0 1 1 1
0 0 1 0 1 0
0 0 1 1 1 1
0 1 0 0 1 1
0 1 0 1 0 1
0 1 1 0 1 1
0 1 1 1 0 1
1 0 0 0 1 0
1 0 1 0 1 0
1 0 1 1 1 1
1 1 0 0 1 0
1 1 0 1 1 1
1 1 1 0 1 0
1 1 1 1 1 1
Table: 1.12
Post LAB:
Design XOR and XNOR circuits using AND, NOT and OR gates.
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
Pre-Lab:
Background theory:
Digital circuits are more frequently constructed with NAND or NOR gates than with AND and
OR gates. NAND and NOR gates are easier to fabricate with electronic components and are the
basic gates used in all IC digital logic families. Because of the prominence of NAND and NOR
gates in the design of digital circuits, rules and procedures have been developed for conversion
from Boolean function given in terms of AND, OR, and NOT into equivalent NAND and NOR
logic diagram.
Read and understand the universal gates also list the truth tables of AND, OR, NOT, NAND,
NOR and XOR gates.
In-Lab
Procedure
✓ Use any one or more of the NAND gates of the IC for this experiment.
✓ Any one or more Logic Switches of the trainer (S1 to S9) can be used for input to the
NAND gate.
✓ For output indication, connect the output pin of the circuit to any one of the LEDs of the
trainer (L0 to L15).
Lab Tasks-Part-1
✓ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✓ By setting the switches to 1 and 0, verify that the output of the circuit conforms to that
of an AND gate. Record your observation in the table below
Fig: 2.1
Table: 2.1
U1:B U1:C
1 4 10
6 8
5 9 ?
1 74HC00 74HC00
Verification of OR function
✓ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✓ By setting the switches to 1 and 0, verify that the output of the circuit conforms to that
of an OR gate. Record your observation in the table below
Fig: 2.2
Table: 2.2
74HC00 U2:B
4
6
5 ?
U2:A 74HC00
1
3
0 2
74HC00
OR From NAND
Lab task 3
✓ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✓ By setting the switch to 1 and 0, verify that the output of the circuit conforms to that
of a NOT gate. Record your observation in the table below
Fig: 2.3
Table: 2.3
✓ Use any one or more of the NOR gates of the IC for this experiment.
✓ Any one or more Logic Switches of the trainer (S2 to S9) can be used for input to the
NOR gate.
✓ For output indication, connect the output pin of the circuit to any one of the LEDs of the
trainer (L0 to L15).
Lab Tasks-Part-2
Lab Task 1:
✓ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✓ By setting the switches to 1 and 0, verify that the output of the circuit conforms to that
of an AND gate. Record your observation in the table below
Fig: 2.4
74HC02 U6:D
11
13
12 ?
U6:C 74HC02
8
10
1 9
74HC02
Verification of OR function
✓ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✓ By setting the switches to 1 and 0, verify that the output of the circuit conforms to
that of an OR gate. Record your observation in the table below
Fig: 2.5
U7:A U7:B
1 2 5
1 4
3 6 ?
0 74HC02 74HC02
OR Form NOR
Lab task 3
✓ Connect +5V to pin 14 (Vcc) and Ground to pin 7 (GND) of the IC.
✓ By setting the switch to 1 and 0, verify that the output of the circuit conforms to that of
an NOT gate. Record your observation in the table below
Fig: 2.6
U6:A
2
1
0 3 ?
74HC02
U3:A U2:D
1 13
3 11
1 2 12
74HC00 74HC00
U2:C
10
8
9 ?
U3:B U3:C 74HC00
4 10
6 8
0 5 9
74HC00 74HC00
74HC00 74HC00
U4:A U4:C
1 10
3 8
1 2 9
74HC00 74HC00
74HC00
NOR From NAND
U10:B
5
4
1 6
U10:D U12:A
74HC02 11 2
13 1
12 3 ?
74HC02 74HC02
U10:C
8
10
0 9
74HC02
74HC02 74HC02
74HC02 74HC02
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
• To display the Boolean expression in its simplified form using Karnaugh map
• To display the results of simplified Boolean expression using hardware and software
platforms
Pre-Lab
A Boolean function can be represented by a Karnaugh map in which each cell corresponds to a
minterm. The cells are arranged in such a way that any two immediately adjacent cells correspond
to two minterms of distance 1. There is more than one way to construct a map with this property.
Karnaugh Maps
For a function of two variables, say, 𝑓 (𝑥, 𝑦),
Read and understand the methods for simplification of Boolean function. List a truth table, derive
its Boolean expression and use K-Map for simplification of the derived Boolean expression.
Lab Tasks-Part-1
Lab Task 1:
Realization of Boolean expression:
TRUTH TABLE
INPUTS OUTPUT
A B C D Y
0 0 0 0 0
0 0 0 1 0
0 0 1 0 1
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 1
0 1 1 1 0
1 0 0 0 1
1 0 0 1 1
1 0 1 0 1
1 0 1 1 1
1 1 0 0 0
1 1 0 1 0
1 1 1 0 1
1 1 1 1 0
Table: 3.1
1
1
1 1 1 1
𝑌 = 𝐴𝐵′ + 𝐶 𝐷'
Lab Task 2:
For the given truth table simplify the Boolean expression by using K-Map
Truth Table
Inputs Output
A B C D Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 0
0 0 1 1 0
0 1 0 0 1
0 1 0 1 1
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 0 1 1 0
1 1 0 1 1
1 1 1 0 0
1 1 1 1 1
Table: 3.2
Karnaugh Maps:
F = Aʹ Bʹ Cʹ Dʹ + Aʹ Bʹ Cʹ D + Aʹ B Cʹ Dʹ + Aʹ B Cʹ D + + A B Cʹ D
1 1 0 0
1 1 0 0
0 1 1 0
0 0 0 0
Aʹ Cʹ + ABD
9 8 74HC08
1 U14:A
1
74HC04
3
2 ?
U3:B 74HC32
1 3
4 6
1 5
1 4073
Orignal Circuit
Lab Tasks-Part-2
Lab Task 1:
Implement the following simplified function by using basic gates as mention in Task 1 Part 1
𝑌 = 𝐴𝐵′ + 𝐶 𝐷'
Fig: 3.1
Lab Task 2:
Post-Lab
Implement the Task 2 of Part 1 by using universal gates (NAND & NOR).
U16:B
0 5
4
6
1 74HC02
U16:D
11
13 U11:D U16:A
1 12 11 2
13 1
74HC02 12 3
74HC02 74HC02
U16:C U13:C D6
8 11 LED-GREEN
10 12 10
1 9 13
74HC02 4025
U17:A
2
1
1 3
74HC02
From NOR
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre-Lab
A combinational logic circuit that performs the addition of two data bits, A and B, is called a
half-adder. Addition will result in two output bits; one of which is the sum bit, S, and the other
is the carry bit, C. The Boolean functions describing the half-adder are:
S =A ⊕ B
C=AB
Full Adder
The half-adder does not take the carry bit from its previous stage into account. This carry bit
from its previous stage is called carry-in bit. A combinational logic circuit that adds two data
bits, A and B, and a carry-in bit, Cin, is called a full-adder. The Boolean functions describing
the full-adder are:
S = (x ⊕ y) ⊕ Cin
C = xy + Cin (x ⊕ y)
Half Subtractor
S =A ⊕ B
C = A’ B
Full Subtractor
Subtracting two single-bit binary values, B, Cin from a single-bit value A produces a difference
bit D and a borrow out Br bit. This is called full subtraction. The Boolean functions describing
the full-subtractor are:
D = (x y) Cin
In-Lab
Lab Tasks-Part-1
Lab Task 1
Implement half adder by using basic gates and verify the results
Fig: 4.1
Truth Table
OUTPUTS
INPUTS
Observed Values
A B S C
0 0 0 0
1 0 1 0
1 1 0 1
Table: 4.1
Lab Task 2:
Implement half adder by using NAND gates and verify the results
Fig: 4.2
Truth Table
OUTPUTS
INPUTS
Observed Values
A B S C
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
Table: 4.2
Implement full adder by using basic gates and verify the results
Fig: 4.3
Truth Table
C c
i
A B C n S
0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 1 1 1
1 1 0 0 1 1
1 1 1 1 1 1
Table: 4.3
A B C Cin S c
0 0 1 1 0 0
0 1 0 0 0 0
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 1 1 1
1 1 0 0 1 1
1 1 1 1 1 1
Lab Task 4
Implement full adder by using NAND gates and verify the results
Fig: 4.4
Truth Table
Table: 4.4
Lab Tasks-Part-2
Lab Task 1
Implement half subtractor by using basic gates and verify the results
Truth Table
OUTPUTS
INPUTS
Observed Values
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Table: 4.5
Lab Task 2:
Implement half subtractor by using NAND gates and verify the results
Fig: 4.6
Truth Table :
OUTPUTS
INPUTS
Input Observed Values
A B D Br
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
Lab Task 3:
Implement full subtractor by using basic gates and verify the results
Fig. 4.7
Truth Table:
Table: 4.7
A B C Cin S c
0 0 0 0 0 0
0 1 0 0 0 0
0 1 1 1 0 1
1 0 0 0 0 0
1 0 1 1 1 1
1 1 0 0 1 1
1 1 1 1 1 1
Lab Task 4
Implement full subtractor by using NAND gates and verify the results
Fig: 4.8
Truth Table
Table: 4.8
A B C Cin S c
0 0 0 0 0 0
0 0 1 1 0 0
0 1 0 0 0 0
1 0 0 0 0 0
1 0 1 1 1 1
1 1 0 0 1 1
1 1 1 1 1 1
Post-Lab:
Design half adder, full adder, half subtractor and full subtractor using NOR gates.
Half adder
Full Adder
Half Subrtarctor
Half Subtractor
Full Subtractor
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre Lab
In Lab
Lab Tasks-Part-1
Lab Task 1
Fig. 5.1
U3:D
12
11
13 0
74HC86 1
U3:C
9 1 U2 1
8 10 9
10 0 8
A1
A2
S1
S2
6 0
3 2
74HC86 1
A3
A4
S3
S4
15 0
U3:A
1 11
B1
1
3 7
B2
2 4
B3
16
B4
74HC86
U3:B 13 14
4
C0 C4 0
6 7483
5
74HC86
Truth Table
Table: 5.1
Lab Tasks-Part-2
Lab Task 2:
U11:D
12
11
13 1
74HC86 0
U11:C
9 1 U10 0
8 ? ?
10 1 ?
A1
A2
S1
S2
? 1
? ?
74HC86 ?
A3
A4
S3
S4
? 0
U11:A
1 ?
B1
1
3 ?
B2
2 ?
B3
?
B4
74HC86
U11:B ? ?
4
C0 C4 1
6 7483
5
74HC86
Truth Table
Table: 5.2
Post Lab
74HC00 74HC00
U6:A
1
X2 0 2
8
9
4023
U5:C
10 U5:D
8 13 U7:A
9 11 1
74HC00
12
2
3
1 B
74HC00
X3 1 U7:B 74HC00
4
6
5
U7:C
10 74HC00
8
9
74HC00
U7:D
13
11
12
U8:A
74HC00 1
3
U8:B 2
4
6 74HC00 U6:C
X4 0 5 11
74HC00
12
13
10
1 C
U8:D
U8:C 13 4023
10 11
8 12
9
74HC00
74HC00
U6:B
3
4 6
5
4023
U9:A
1
2
3
1 D
74HC00
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre Lab
Lab Tasks-Part-1
Binary Code to Gray Code Conversion
Boolean Expressions:
G3=B3; G2=B3 B2
G1=B1 B2; G0=B1 B0
Lab Tasks-Part-2
Gray Code to Binary Code Conversion
B3=G3; B2=G3 G2
B1=G3 G2 G1; B0=G3 G2 G1 G0
In Lab:
Lab Task 1:
Fig: 6.1
Truth Table
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Table: 6.1
Lab Task 2:
Fig: 6.2
Fig: 6.3
Truth Table
Gray Binary
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0
0 0 0 1
0 0 1 1
0 0 1 0
0 1 1 0
0 1 1 1
0 1 0 1
0 1 0 0
1 1 0 0
1 1 0 1
1 1 1 1
1 1 1 0
1 0 1 0
1 0 1 1
1 0 0 1
1 0 0 0
Table: 6.2
Lab Task 4:
Realization using NAND gates
Post Lab:
The student performance for the assigned task during the lab session was:
Pre Lab
In lab
4:1 Multiplexer
Truth Table
Enable
Select Inputs Input Inputs Outputs
X X 1 X X X X
0 0 0 0 X X X
0 0 0 1 X X X
0 1 0 X 0 X X
0 1 0 X 1 X X
1 0 0 X X 0 X
1 0 0 X X 1 X
1 1 0 X X X 0
1 1 0 X X X 1
Table: 7.1
Lab Task 3:
Tasks-Part-2 Lab
Task 1:
Truth Table
Enable Data
Select Inputs Outputs
Input Input
E D S1 S0 Y3 Y2 Y1 Y0
1 0 X X
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
Table: 7.3
Lab Task 3:
Inputs Outputs
Ea S1 S0 Y3 Y2 Y1 Y0
1 X X
0 0 0
0 0 1
0 1 0
0 1 1
Table: 7.4
Lab Tasks-Part-3
Lab Task 1: Half Adder using MUX:
Design:
SUM CARRY
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A
Table: 7.5
Design:
SUM
I0 I1 I2 I3
0 1 2 3
4 5 6 7
A A’ A’ A
CARRY
I0 I1 I2 I3
0 1 2 3
4 5 6 7
0 A A 1
Circuit Diagram:
Table: 7.6
Design:
DIFFERENCE BORROW
I0 I1 I0 I1
0 1 0 1
2 3 2 3
A A’ 0 A’
Circuit Diagram:
Table: 7.7
Design:
Circuit Diagram:
Table: 7.8
Post Lab:
Design Half Adder and full Adder using MUX without using IC74153 (using basic gates only).
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre Lab
Magnitude Comparator is a logical circuit, which compares two signals A and B and
generates three logical outputs, whether A > B, A = B, or A < B. IC 7485 is a high speed
4-bit magnitude comparator, which compares two 4-bit words. The A = B Input must be
held high for proper compare operation.
In Lab:
Lab Tasks-Part-1
Circuit Diagram:
Fig: 8.1
Table: 8.1
Circuit Diagram:
Fig: 8.2
Truth Table:
Lab Tasks-Part-2
Lab Task 1: 4-Bit Comparator
Circuit Diagram:
Fig: 8.3
Truth Table:
Post Lab:
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
• To explain the basic functionality and working of Encoder using logic gates
• To explain the basic functionality and working of decoder using logic gates
• To display the results of various applications of encoder using hardware and software
platforms
• To display the results of various applications of decoder using hardware and software
platforms
Pre Lab
Decoder
A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. Decoder is also called a min-term generator/max-term
generator. A min-term generator is constructed using AND and NOT gates. The appropriate
output is indicated by logic 1 (positive logic). Max-term generator is constructed using NAND
gates. The appropriate output is indicated by logic 0 (Negative logic).
The IC 74139 accepts two binary inputs and when enable provides 4 individual active low
outputs. The device has 2 enable inputs (Two active low).
The Light Emitting Diode (LED), finds its place in many applications in this modern electronic
fields. One of them is the Seven Segment Display. Seven-segment displays contain the
LED’s are basically of two types- Common Cathode (CC) -All the 8 anode legs uses only one
cathode, which is common. Common Anode (CA)-The common leg for the entire cathode is of
Anode type.
A decoder is a combinational circuit that connects the binary information from ‘n’ input lines to
a maximum of 2n unique output lines. The IC7447 is a BCD to 7-segment pattern converter. The
IC7447 takes the Binary Coded Decimal (BCD) as the input and outputs the relevant 7 segment
code.
An encoder performs a function that is the opposite of decoder. It receives one or more signals
in an encoded format and output a code that can be processed by another logic circuit. One of
the advantages of encoding data, or more often data addresses in computers, is that it reduces
the number of required bits to represent data or addresses. For example, if a memory has 16
different locations, in order to access these 16 different locations, 16 lines (bits) are required if
the addressing signals are in 1 out of n format. However, if we code the 16 different addresses
into a binary format, then only 4 lines (bits) are required. Such a reduction improves the speed
of information processing in digital systems.
In Lab:
Table: 9.1
Boolean Expressions:
Circuit Diagram:
Fig: 9.1
TRUTH TABLE:
Table: 9.2
Fig: 9.2
Lab Tasks-Part-2:
CIRCUIT DIAGRAM:
Fig: 9.3
TRUTH TABLE:
Decimal
Output Logic Levels from IC 7447 to
BCD Inputs 7segments number
display
D C B A a b c d e f g
0 0 0 0 0 0 0 0 0 0 1
0 0 0 1 1 0 0 1 1 1 1
0 0 1 0 0 0 1 0 0 1 0
0 0 1 1 0 0 0 0 1 1 0
Lab Tasks-Part-3:
TRUTH TABLE
Table: 9.4
CIRCUIT DIAGRAM:
Fig: 9.5
Table: 9.5
Fig: 9.6
TRUTH TABLE
Post Lab:
Design the encoders and decoders used in Lab task-1 and Lab task-3 using NAND and NOR
Gates.
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre Lab
SR LATCH
S-R latch consists of two cross-coupled NOR gates. An S-R flip-flop can also be design using
cross-coupled NAND gates as shown. The truth tables of the circuits are shown below. A
clocked S-R flip-flop has an additional clock input so that the S and R inputs are active only
when the clock is high. When the clock goes low, the state of flip-flop is latched and cannot
change until the clock goes high again. Therefore, the clocked S-R flip-flop is also called
“enabled” S-R flip-flop. A D latch combines the S and R inputs of an S-R latch into one input
by adding an inverter. When the clock is high, the output follows the D input, and when the
clock goes low, the state is latched.
In Lab
Lab Task 1:
S-R LATCH:
TRUTH TABLE
Table: 10.1
Lab Task 2:
SR FLIP FLOP:
Fig: 10.2
TRUTH TABLE
Table: 10.2
Lab Task 3:
CONVERSION OF SR-FLIP FLOP TO T-FLIP FLOP (Toggle)
SYMBOL
Fig: 10.3
Table: 10.3
Lab Task 4:
Fig:10.4
0 X
1 0
1 1
Table: 10.4
Lab Task 5:
Lab Task 6:
Fig: 10.6
Truth Table
Post Lab:
Differentiate between different types of FLIP FLOPS.
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Objectives
1. To explain the working of a shift register using 7495 IC
2. To differentiate between the different types of shift register
Pre Lab
In digital circuits, a shift register is a cascade of flip flops, sharing the same clock, in which the
output of each flip-flop is connected to the "data" input of the next flip-flop in the chain, resulting
in a circuit that shifts by one position the "bit array" stored in it, shifting in the data present at its
input and shifting out the last bit in the array, at each transition of the clock input.
More generally, a shift register may be multidimensional, such that it’s "data in" and stage outputs
are themselves bit arrays: this is implemented simply by running several shift registers of the
same bit-length in parallel.
Shift registers can have both parallel and serial inputs and outputs. These are often configured as
'serial-in, parallel-out' (SIPO) or as 'parallel-in, serial-out' (PISO). There are also types that have
both serial and parallel input and types with serial and parallel output. There are also
'bidirectional' shift registers which allow shifting in both directions: L→R or R→L. The serial
input and last output of a shift register can also be connected to create a 'circular shift register'.
In Lab
1. Check all the components for their working
2. Insert the appropriate IC into the IC base
3. Make connections as shown in the circuit diagram
4. Verify the Truth Table and observe the outputs
Fig: 11.1
Serial
i/p Shift QA QB QC QD
Data Pulses
- -
0 t1
1 t2
0 t3
1 t4
X t5
X t6
X t7
X t8
Table: 11.1
Lab Task 2:
SERIAL IN PARALLEL OUT (SIPO)
Serial Shift QA QB QC QD
i/p data Pulses
- -
0 t1
1 t2
0 t3
1 t4
Table: 11.2
Lab Task 3:
PARALLEL IN PARALLEL OUT (PIPO)
Clock
Input Shift QA QB QC QD
Terminal Pulses
- -
CLK2 t1
Table: 11.3
Clock
Input Shift QA QB QC QD
Terminal Pulses
- -
CLK2 t1
CLK2 t2
0 t3
1 t4
X t5
Table: 11.4
Post Lab:
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre Lab
A sequence detector is a sequential logic circuit that can be used to detect whether a given
sequence of bits has been received or not by a receiver. Consider, for example, a single-input
single-output sequence detector. Let the sequence to be detected be 101. Repetition is allowed in
this sequence. This means that, the circuit will give an output of I when it detects first the
sequence 101 in a series of incoming bits. Let the next two bits after the first 101 be 01. We find
that the circuit will read this as 101 and output another 1. This is because we have given
permission for repetition, and the circuit will consider the last 1 in the first 101 as a valid first 1
in the next sequence of 101.
In Lab
Procedure
1. Draw the state diagram of the state machine below and show it to the lab instructor.
5. Draw the circuit diagram using NAND GATES ONLY for the state machine
State Diagram
QA QB QC Y DA DB DC
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
1 0 1 0 10
1 0 1 1 11
1 1 0 0 12
1 1 0 1 13
1 1 1 0 14
1 1 1 1 15
Table: 12.1
For __________ For _____________
Q CY Q CY
Q AQ B 00 01 11 10 Q AQ B 00 01 11 10
00 00
01 01
11 11
10 10
For __________
Q AQ B 00 01 11 10
00
01
11
10
D Q
CLK
D Q
CLK
D Q
CLK
Fig: 12.1
Table: 12.3
Post Lab:
Design a sequence detector which to detect 110101.
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre Lab
In Lab
Lab Task-1
Circuit Diagram:
Fig: 13.1
Truth Table:
8
Table: 13.1
Lab Task-2:
Circuit Diagram :
Fig: 13.1
Truth Table :
Clock Q Q Q Q
Pulses A B C D
Table: 13.1
Post Lab:
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.
Pre Lab
In Lab:
Mod 8 up counter
Circuit Diagram
Fig: 14.1
Table: 14.1
Fig: 14.2
TRUTH TABLE
Table: 14.2
Fig: 14.3
TRUTH TABLE
Table: 14.3
Table: 14.4
PROCED
URE:
1) Check all the components for their working.
Mod_ 5 counter
Table: 14.6
Table: 14.7
Circuit Diagram:
Table: 14.8
Table: 14.8
Table: 14.9
Circuit Diagram:
The student performance for the assigned task during the lab session was:
The student completed assigned tasks without any help from the
Excellent 4
instructor and showed the results appropriately.
The student completed assigned tasks with minimal help from the
Good 3
instructor and showed the results appropriately.
The student could not complete all assigned tasks and showed
Average 2
partial results.