SAFETY PRECAUTIONS

(Always read these cautions before using the product)

Before using this product, please read this manual and the related manuals introduced in this manual, and
pay full attention to safety to handle the product correctly.

Please store this manual in a safe place and make it accessible when required. Always forward a copy of
the manual to the end user.

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 CONDITIONS OF USE FOR THE PRODUCT
(1) Mitsubishi programmable controller ("the PRODUCT") shall be used in conditions;
i) where any problem, fault or failure occurring in the PRODUCT, if any, shall not lead to any major
or serious accident; and
ii) where the backup and fail-safe function are systematically or automatically provided outside of
the PRODUCT for the case of any problem, fault or failure occurring in the PRODUCT.

(2) The PRODUCT has been designed and manufactured for the purpose of being used in general
industries.
MITSUBISHI SHALL HAVE NO RESPONSIBILITY OR LIABILITY (INCLUDING, BUT NOT
LIMITED TO ANY AND ALL RESPONSIBILITY OR LIABILITY BASED ON CONTRACT,
WARRANTY, TORT, PRODUCT LIABILITY) FOR ANY INJURY OR DEATH TO PERSONS OR
LOSS OR DAMAGE TO PROPERTY CAUSED BY the PRODUCT THAT ARE OPERATED OR
USED IN APPLICATION NOT INTENDED OR EXCLUDED BY INSTRUCTIONS, PRECAUTIONS,
OR WARNING CONTAINED IN MITSUBISHI'S USER, INSTRUCTION AND/OR SAFETY
MANUALS, TECHNICAL BULLETINS AND GUIDELINES FOR the PRODUCT.
("Prohibited Application")
Prohibited Applications include, but not limited to, the use of the PRODUCT in;
• Nuclear Power Plants and any other power plants operated by Power companies, and/or any
other cases in which the public could be affected if any problem or fault occurs in the PRODUCT.
• Railway companies or Public service purposes, and/or any other cases in which establishment of
a special quality assurance system is required by the Purchaser or End User.
• Aircraft or Aerospace, Medical applications, Train equipment, transport equipment such as
Elevator and Escalator, Incineration and Fuel devices, Vehicles, Manned transportation,
Equipment for Recreation and Amusement, and Safety devices, handling of Nuclear or
Hazardous Materials or Chemicals, Mining and Drilling, and/or other applications where there is a
significant risk of injury to the public or property.

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REVISIONS
*The manual number is given on the bottom left of the back cover.
Print Date *Manual Number Revision
Dec., 2008 SH (NA)-080809ENG-A First edition
Mar., 2009 SH (NA)-080809ENG-B Partial corrections
Section 3.3, 3.8, 5.1.3, 6.1.7, 6.2.14, 7.3.3, 7.11.18, 7.11.19, 7.12.1.5,12.7,
7.12.11, 7.12.25, 7.12.26, 7.13.4, 7.13.5, 7.15.7, 7.15.8
Jul., 2009 SH (NA)-080809ENG-C Revision because of function support by the Universal model QCPU having a
serial number "11043" or later
Partial corrections
Section 2.1, 2.5.6, 2.5.18, 2.5.20, 7.6.9, 7.12.7, 7.12.11, 12.1.3, 12.1.4,
APPENDIX 1.2, 1.3, 1.4.2, 3, 5.1
Additions
Section 2.5.16, 7.16, 7.18.10
Modification
Section 2.5.21 2.5.22, Section 2.5.22 2.5.21, Section 9.13 7.6.10,
Section 9.14 7.6.1, Section 9.15 7.16, Section 9.15.1 7.16.1,
Section 9.15.2 7.16.2, Section 9.15.3 7.16.3, Section 9.1 7.18.9,
Section 9.2 7.18.11, Section 9.3 7.18.12, Section 9.4 7.18.13,
Section 9.5 7.18.14, Section 9.6 7.18.15, Section 9.7 7.18.16,
Section 9.8 7.18.17, Section 9.9 7.18.18, Section 9.10 7.18.19,
Section 9.11 9.1, Section 9.11.1 9.1.1, Section 9.11.2 9.1.2,
Section 9.12 9.2, Section 9.12.1 9.2.1, Chapter 10 11, Chapter 11 10

Jan., 2010 SH (NA)-080809ENG-D Model Additions

L02CPU, L26CPU-BT
Partial corrections
SAFETY PRECAUTIONS, INTRODUCTION, MANUALS, Chapter 1, Section
2.3.2, 2.4.1, 2.4.2, 2.4.3, 2.4.4, 2.5.1, 2.5.6, 2.5.18, 3.2.4, 3.3, 3.4, 3.5.1, 3.5.2,
3.6, 3.8, 3.10, Chapter 4, 5, 6, 7, 8, 9, 10, 11, 12, APPENDIX 1.1, 2.1, 3, 4,
INDEX, Warranty
Additions
CONDITIONS OF USE FOR THE PRODUCT, Section 2.6.1, 2.6.2, 2.7.1, 2.7.2,
2.8.1, 2.9.1, 7.18.20, 7.18.21, APPENDIX 1.5
Modification
Section 2.5.19 2.6, Section 2.5.20 2.7, Section 2.5.21 2.8,
Section 2.5.22 2.9
Apr., 2010 SH (NA)-080809ENG-E Revision because of function support by the Universal model QCPU having a
serial number "12012" or later
Model Additions
Q50UDEHCPU, Q100UDEHCPU
Partial corrections
INTRODUCTION, MANUALS, Section 1.1, 1.2, 3.5.2, 7.6.10, 7.11.7, 7.14.3,
7.18.2, 7.18.3, 7.18.9, 9.1.1, 8.2.1, 9.1, 12.1.3, 12.1.4, APPENDIX 1.4.1, 1.4.2,
1.5.1, 1.5.2, 2, 3

3
 *The manual number is given on the bottom left of the back cover.
Print Date *Manual Number Revision
Aug., 2010 SH (NA)-080809ENG-F Revision because of function support by the Universal model QCPU having a
serial number "12052" or later
Partial corrections
Section 6.2.11, 6.2.12, 6.3.15, 7.3.3, 7.3.5, 7.11.7, APPENDIX 1.2, 1.3, 1.4.1,
1.4.2, 1.5.1, 1.5.2
Jan., 2011 SH (NA)-080809ENG-G Partial corrections
Section 2.1, 2.5.18, 3.6, 7.6.9, 7.6.10, 7.8.2, 7.10.2, 7.18.5, 8.1.1, 12.1.3, 12.1.4,
12.1.6, 12.1.11, Appendix 1.4.1, Appendix 1.4.2, Appendix 1.5.1, Appendix 1.5.2,
Appendix 3, Appendix 4
Apr., 2011 SH (NA)-080809ENG-H Full revision and revision because of function support by the LCPU having a serial
number "13012" or later
Jul., 2011 SH (NA)-080809ENG-I Model Additions
L02CPU-P, L26CPU-PBT
Partial corrections
INTRODUCTION, Section 1.2, 5.2.1, 5.2.4, 5.2.5, 7.18.9, 9.1, Appendix 1.5.1,
Appendix 1.5.2, Appendix 2.1.1
Oct., 2011 SH(NA)-080809ENG-J Partial corrections
INTRODUCTION, MANUALS, Section 1.2, 2.1, 2.4.3, 2.6.2, 3.3, 3.6, 6.4.4, 6.6.1,
6.8.1, 6.8.2, 6.8.7, 7.6.10, 7.6.13, 7.8.1, 7.8.2, 7.9.1, 7.9.2, 7.10.1, 7.14.1, 7.14.2,
7.18.4 to 7.18.14, 7.18.16, 7.18.18 to 7.18.20, 8.1.1, 8.2.1, 8.2.2, 9.1, 9.1.1, 9.2.1,
10.1 to 10.3, 11.1, Appendix 1.4.2
May, 2012 SH(NA)-080809ENG-K Partial corrections
Section 2.1, 2.5.3, 2.5.9, 3.2.4, 5.3.1, 5.3.4, 5.3.7, 6.1.3, 6.1.4, 6.2.9 to 6.2.12,
6.3.5, 6.3.6, 6.3.16, 6.3.17, 6.4.2, 6.4.3, 6.4.8, 7.9.1, 7.9.3, 7.11.7, 7.11.11,
7.11.20, 7.12.1 to 7.12.26, 7.18.9
Aug., 2012 SH(NA)-080809ENG-L Revision because of function support by the Universal model QCPU and LCPU
having a serial number "14072" or later
Partial corrections
MANUALS, Section 2.1, 3.10, 6.1.7, 6.2.14, 7.11.7, 7.18.16, 7.18.17, 7.18.18,
Appendix 1.2, 1.3, 1.4, 1.5
Additions
Section 2.6.3, 8.3, 8.3.1, 8.3.2, 8.3.3, 8.3.4
Feb., 2013 SH (NA)-080809ENG-M Revision because of function support by the Universal model QCPU and LCPU
having a serial number "14112" or later
Model Additions
Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, Q26UDVCPU,
L02SCPU, L06CPU, L26CPU

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 Print Date *Manual Number Revision
May, 2013 SH(NA)-080809ENG-N Model Additions
L02SCPU-P, L06CPU-P, L26CPU-P
Partial corrections
INTRODUCTION, MANUALS, Section 1.2, 5.1.3, 6.1.7, 6.2.14, 6.4.8, 7.3.3, 7.3.5,
7.5.15, 7.6.11, 7.11.8, 7.11.18, 7.11.9, 7.12.17, 7.12.18, 7.12.25, 7.12.26, 7.13.4,
7.13.5, 7.15.7, 7.15.8, 7.18.9, 7.18.12, 7.18.13,7.18.20, 8.2.2, 8.3.1, 8.3.2, 8.3.3,
8.3.4, 9.1, Appendix 1.5, Appendix 2.1
Sep., 2013 SH(NA)-080809ENG-O Partial corrections
Section 6.8.4, 7.7.2, 8.2.2
Jan., 2014 SH(NA)-080809ENG-P Revision because of function support by the High Performance model QCPU,
Process CPU, and Redundant CPU having a serial number "16021" or later.
Partial corrections
Section 7.9.2, Appendix 1.3, 1.4, 1.5, Appendix 2.1

Japanese Manual Version SH-080804-T

This manual confers no industrial property rights or any rights of any other kind, nor does it confer any patent licenses.
Mitsubishi Electric Corporation cannot be held responsible for any problems involving industrial property rights which may
occur as a result of using the contents noted in this manual.

 2008 MITSUBISHI ELECTRIC CORPORATION

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 INTRODUCTION

This document is the MELSEC-Q/L Programming Manual (Common Instructions). It describes the common instructions
required for programming of the QCPU and LCPU.

"Common instructions" are all instructions except for dedicated instructions for intelligent function modules; PID control
instructions; SFC instructions; ST instructions; instructions for socket communication features; trigger logging instructions;
and dedicated instructions for LCPU positioning/counter functionality.

Please read this manual and other relevant manuals carefully before using this product. Please familiarize yourself with the
functions and performance of the Q series and L series sequencers in order to handle this product correctly.
When applying the program examples introduced in this manual to the actual system, ensure the applicability and confirm that
it will not cause system control problems.

 Relevant CPU module

CPU module Model
Basic model QCPU Q00JCPU, Q00CPU, Q01CPU
High Performance model QCPU Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU
Process CPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU
Redundant CPU Q12PRHCPU, Q25PRHCPU
Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDVCPU,
Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU,
Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU,
Universal model QCPU
Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDHCPU,
Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU,
Q50UDEHCPU, Q100UDEHCPU
L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU,
LCPU
L26CPU-P, L26CPU-BT, L26CPU-PBT

6
Memo

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 CONTENTS
CONTENTS

SAFETY PRECAUTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
CONDITIONS OF USE FOR THE PRODUCT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
REVISIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
CONTENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
MANUALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

CHAPTER 1 GENERAL DESCRIPTION 22

1.1 Related Programming Manuals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.2 Abbreviations and Generic Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

CHAPTER 2 INSTRUCTION TABLES 29

2.1 Types of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
2.2 How to Read Instruction Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.3 Sequence Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
2.3.1 Contact instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
2.3.2 Association instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
2.3.3 Output instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.4 Shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
2.3.5 Master control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.3.6 Termination instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2.3.7 Other instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

2.4 Basic instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.4.1 Comparison operation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
2.4.2 Arithmetic operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
2.4.3 Data conversion instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
2.4.4 Data transfer instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
2.4.5 Program branch instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.4.6 Program execution control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.4.7 I/O refresh instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
2.4.8 Other convenient instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

2.5 Application Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2.5.1 Logical operation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
2.5.2 Rotation instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
2.5.3 Shift instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
2.5.4 Bit processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.5.5 Data processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
2.5.6 Structure creation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
2.5.7 Data table operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
2.5.8 Buffer memory access instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.5.9 Display instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
2.5.10 Debugging and failure diagnosis instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
2.5.11 Character string processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
2.5.12 Special function instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
2.5.13 Data control instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
2.5.14 Switching instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
2.5.15 Clock instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

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 2.5.16 Expansion clock instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79
2.5.17 Program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
2.5.18 Other instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

2.6 Instructions for Data Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

2.6.1 Instructions for Network refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.6.2 Instructions for Reading/Writing Routing Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
2.6.3 Refresh device write/read instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

2.7 Multiple CPU dedicated instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

2.7.1 Instructions for Writing to the CPU Shared Memory of Host CPU . . . . . . . . . . . . . . . . . . . . .85
2.7.2 Instructions for Reading from the CPU Shared Memory of Another CPU . . . . . . . . . . . . . . .85

2.8 Multiple CPU high-speed transmission dedicated instruction . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.8.1 Instructions for Multiple CPU high-speed transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

2.9 Redundant system instructions (For Redundant CPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

2.9.1 Instructions for Redundant system (For Redundant CPU). . . . . . . . . . . . . . . . . . . . . . . . . . .86

CHAPTER 3 CONFIGURATION OF INSTRUCTIONS 87

3.1 Configuration of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
3.2 Designating Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
3.2.1 Using bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
3.2.2 Using word (16 bits) data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
3.2.3 Using double word data (32 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
3.2.4 Using single/double-precision real number data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93
3.2.5 Using character string data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

3.3 Indexing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
3.4 Indirect Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
3.5 Reducing Instruction Processing Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.5.1 Subset Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109
3.5.2 Operation processing with standard device registers (Z)
(Universal model QCPU and LCPU only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

3.6 Cautions on Programming (Operation Errors) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

3.7 Conditions for Execution of Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
3.8 Counting Step Number. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
3.9 Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device. . . . . . . 123
3.10 Precautions for Use of File Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

CHAPTER 4 HOW TO READ INSTRUCTIONS 130

CHAPTER 5 SEQUENCE INSTRUCTIONS 132

5.1 Contact Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
5.1.1 LD, LDI Operation start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
AND, ANI Series connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
OR, ORI Parallel connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132
5.1.2 LDP, LDF Pulse operation start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
ANDP, ANDF Pulse series connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
ORP, ORF Pulse parallel connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134

9
 5.1.3 LDPI, LDFI Pulse NOT operation start . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
ANDPI, ANDFI Pulse NOT series connection . . . . . . . . . . . . . . . . . . . . . . . . . .136
ORPI, ORFI Pulse NOT parallel connection . . . . . . . . . . . . . . . . . . . . . . . . .136

5.2 Association Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

5.2.1 ANB Ladder block series connection . . . . . . . . . . . . . . . . . . . . . . . .139
ORB Ladder block parallel connection . . . . . . . . . . . . . . . . . . . . . . .139
5.2.2 MPS Operation results push . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
MRD Operation results read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
MPP Operation results pop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140
5.2.3 INV Operation results inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
5.2.4 MEP, MEF Operation results conversion . . . . . . . . . . . . . . . . . . . . . . . . . .144
5.2.5 EGP, EGF Pulse conversion of edge relay operation results . . . . . . . . . . .145

5.3 Output Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

5.3.1 OUT Out (excluding timers, counters, and annunciators) . . . . . . . . .147
5.3.2 OUT T Low-speed timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
OUTH T High-speed timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
OUT ST Low-speed retentive timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
OUTH ST High-speed retentive timer . . . . . . . . . . . . . . . . . . . . . . . . . . . .149
5.3.3 OUT C Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152
5.3.4 OUT F Annunciator output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154
5.3.5 SET Setting devices (excluding annunciators) . . . . . . . . . . . . . . . . .155
5.3.6 RST Resetting devices (excluding annunciators) . . . . . . . . . . . . . . .157
5.3.7 SET F Setting annunciators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
RST F Resetting annunciators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159
5.3.8 PLS Leading edge output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
PLF Trailing edge output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161
5.3.9 FF Bit device output inversion . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
5.3.10 DELTA, DELTAP Pulse conversion of direct output . . . . . . . . . . . . . . . . . . . . . . .164

5.4 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

5.4.1 SFT, SFTP Bit device shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166

5.5 Master Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168

5.5.1 MC Setting the master control . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168
MCR Resetting the master control . . . . . . . . . . . . . . . . . . . . . . . . . . .168

5.6 Termination Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172

5.6.1 FEND Main routine program end . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
5.6.2 END Sequence program end . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174

5.7 Other instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176

5.7.1 STOP Sequence program stop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .176
5.7.2 NOP, NOPLF, PAGE n No operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177

CHAPTER 6 BASIC INSTRUCTIONS 181

6.1 Comparison Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
6.1.1 =, <>, >, <=, <, >= BIN 16-bit data comparisons . . . . . . . . . . . . . . . . . . . . . . . . . .181
6.1.2 D=, D<>, D>, D<=, D<, BIN 32-bit data comparisons . . . . . . . . . . . . . . . . . . . . . . . . . .182
D>=

10
 6.1.3 E=, E<>, E>, E<=, E<, Floating-point data comparisons (Single precision) . . . . . . . . .184
E>=
6.1.4 ED=, ED<>, ED>, ED<=, Floating-point data comparisons (Double precision) . . . . . . . .186
ED<, ED>=
6.1.5 $=, $<>, $>, $<=, $<, Character string data comparisons . . . . . . . . . . . . . . . . . . . . . .188
$>=
6.1.6 BKCMP, BKCMPP BIN 16-bit block data comparisons . . . . . . . . . . . . . . . . . . . . . .191
6.1.7 DBKCMP, BIN 32-bit block data comparisons . . . . . . . . . . . . . . . . . . . . . .193
DBKCMPP

6.2 Arithmetic Operation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197

6.2.1 +, +P, -, -P BIN 16-bit addition and subtraction operations . . . . . . . . . . . . .197
6.2.2 D+, D+P, D-, D-P BIN 32-bit addition and subtraction operations . . . . . . . . . . . . .200
6.2.3 *, *P, /, /P BIN 16-bit multiplication and division operations . . . . . . . . . . .203
6.2.4 D*, D*P, D/, D/P BIN 32-bit multiplication and division operations . . . . . . . . . . .205
6.2.5 B+, B+P, B-, B-P BCD 4-digit addition and subtraction operations . . . . . . . . . . .207
6.2.6 DB+, DB+P, DB-, DB-P BCD 8-digit addition and subtraction operations . . . . . . . . . . .210
6.2.7 B*, B*P, B/, B/P BCD 4-digit multiplication and division operations . . . . . . . . . .213
6.2.8 DB*, DB*P, DB/, DB/P BCD 8-digit multiplication and division operations . . . . . . . . . .215
6.2.9 E+, E+P, E-, E-P Addition and subtraction of floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .217
6.2.10 ED+, ED+P, ED-, ED-P Addition and subtraction of floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221
6.2.11 E*, E*P, E/, E/P Multiplication and division of floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225
6.2.12 ED*, ED*P, ED/, ED/P Multiplication and division of floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227
6.2.13 BK+, BK+P, BK-, BK-P BIN 16-bit data block addition and subtraction operations . . . .229
6.2.14 DBK+, DBK+P, DBK-, BIN 32-bit data block addition and subtraction operations . . . .231
DBK-P
6.2.15 $+, $+P Linking character strings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234
6.2.16 INC, INCP 16-bit BIN data increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
DEC, DECP 16-bit BIN data decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
6.2.17 DINC, DINCP 32-bit BIN data increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238
DDEC, DDECP 32-bit BIN data decrement . . . . . . . . . . . . . . . . . . . . . . . . . . . .238

6.3 Data conversion instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240

6.3.1 BCD, BCDP Conversion from BIN data to BCD 4-digit data . . . . . . . . . . . . .240
DBCD, DBCDP Conversion from BIN data to BCD 8-digit data . . . . . . . . . . . . .240
6.3.2 BIN, BINP Conversion from BCD 4-digit data to BIN data . . . . . . . . . . . . .242
DBIN, DBINP Conversion from BCD 8-digit data to BIN data . . . . . . . . . . . . .242
6.3.3 FLT, FLTP Conversion from BIN 16-bit data to floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
DFLT, DFLTP Conversion from BIN 32-bit data to floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
6.3.4 FLTD, FLTDP Conversion from BIN 16-bit data to floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246
DFLTD, DFLTDP Conversion from BIN 32-bit data to floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246

11
 6.3.5 INT, INTP Conversion from floating-point data to BIN 16-bit data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
DINT, DINTP Conversion from floating-point data to BIN 32-bit data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
6.3.6 INTD, INTDP Conversion from floating-point data to BIN 16-bit data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
DINTD, DINTDP Conversion from floating-point data to BIN 32-bit data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249
6.3.7 DBL, DBLP Conversion from BIN 16-bit to BIN 32-bit data . . . . . . . . . . . . .251
6.3.8 WORD, WORDP Conversion from BIN 32-bit to BIN 16-bit data . . . . . . . . . . . . .252
6.3.9 GRY, GRYP Conversion from BIN 16-bit data to Gray code . . . . . . . . . . . . .253
DGRY, DGRYP Conversion from BIN 32-bit data to Gray code . . . . . . . . . . . . .253
6.3.10 GBIN, GBINP Conversion from Gray code to BIN 16-bit data . . . . . . . . . . . . .254
DGBIN, DGBINP Conversion from Gray code to BIN 32-bit data . . . . . . . . . . . . .254
6.3.11 NEG, NEGP Complement of 2 of BIN 16-bit data (sign inversion) . . . . . . . .256
DNEG, DNEGP Complement of 2 of BIN 32-bit data (sign inversion) . . . . . . . .256
6.3.12 ENEG, ENEGP Floating-point sign inversion (Single precision) . . . . . . . . . . . .257
6.3.13 EDNEG, EDNEGP Floating-point sign inversion (Double precision) . . . . . . . . . . . .258
6.3.14 BKBCD, BKBCDP Conversion from block BIN 16-bit data to BCD 4-digit data . . .259
6.3.15 BKBIN, BKBINP Conversion from block BCD 4-digit data to block BIN 16-bit
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261
6.3.16 ECON, ECONP Conversion from Single precision to Double precision . . . . . . .262
6.3.17 EDCON, EDCONP Conversion from Double precision to Single precision . . . . . . .263

6.4 Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265

6.4.1 MOV, MOVP 16-bit data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
DMOV, DMOVP 32-bit data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265
6.4.2 EMOV, EMOVP Floating-point data transfer (Single precision) . . . . . . . . . . . . .266
6.4.3 EDMOV, EDMOVP Floating-point data transfer (Double precision) . . . . . . . . . . . .268
6.4.4 $MOV, $MOVP Character string transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .269
6.4.5 CML, CMLP 16-bit data negation transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .271
DCML, DCMLP 32-bit data negation transfer . . . . . . . . . . . . . . . . . . . . . . . . . . .271
6.4.6 BMOV, BMOVP Block 16-bit data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274
6.4.7 FMOV, FMOVP Identical 16-bit data block transfer . . . . . . . . . . . . . . . . . . . . . .277
6.4.8 DFMOV, DFMOVP Identical 32-bit data block transfer . . . . . . . . . . . . . . . . . . . . . .279
6.4.9 XCH, XCHP 16-bit data exchanges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
DXCH, DXCHP 32-bit data exchanges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
6.4.10 BXCH, BXCHP Block 16-bit data exchanges . . . . . . . . . . . . . . . . . . . . . . . . . .282
6.4.11 SWAP, SWAPP Upper and lower byte exchanges . . . . . . . . . . . . . . . . . . . . . . .284

6.5 Program Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285

6.5.1 CJ, SCJ, JMP Pointer branch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
6.5.2 GOEND Jump to END . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288

6.6 Program Execution Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289

6.6.1 DI Interrupt disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
EI Interrupt enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
IMASK Interrupt program mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .289
6.6.2 IRET Recovery from interrupt programs . . . . . . . . . . . . . . . . . . . . . .295

12
 6.7 I/O Refresh Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296
6.7.1 RFS, RFSP I/O refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296

6.8 Other Convenient Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298

6.8.1 UDCNT1 Counter 1-phase input up or down . . . . . . . . . . . . . . . . . . . . . .298
6.8.2 UDCNT2 Counter 2-phase input up or down . . . . . . . . . . . . . . . . . . . . . .300
6.8.3 TTMR Teaching timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .302
6.8.4 STMR Special function timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
6.8.5 ROTC Rotary table shortest direction control . . . . . . . . . . . . . . . . . . .305
6.8.6 RAMP Ramp signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307
6.8.7 SPD Pulse density measurement . . . . . . . . . . . . . . . . . . . . . . . . . . .309
6.8.8 PLSY Fixed cycle pulse output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311
6.8.9 PWM Pulse width modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312
6.8.10 MTR Matrix input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .313

CHAPTER 7 APPLICATION INSTRUCTIONS 316

7.1 Logical operation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316
7.1.1 WAND, WANDP Logical products with 16-bit data . . . . . . . . . . . . . . . . . . . . . . .317
DAND, DANDP Logical products with 32-bit data . . . . . . . . . . . . . . . . . . . . . . .317
7.1.2 BKAND, BKANDP Block logical products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321
7.1.3 WOR, WORP Logical sums of 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
DOR, DORP Logical sums of 32-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . .323
7.1.4 BKOR, BKORP Block logical sum operations . . . . . . . . . . . . . . . . . . . . . . . . . .327
7.1.5 WXOR, WXORP 16-bit exclusive OR operations . . . . . . . . . . . . . . . . . . . . . . . . .329
DXOR, DXORP 32-bit exclusive OR operations . . . . . . . . . . . . . . . . . . . . . . . . .329
7.1.6 BKXOR, BKXORP Block exclusive OR operations . . . . . . . . . . . . . . . . . . . . . . . . .333
7.1.7 WXNR, WXNRP 16-bit data exclusive NOR operations . . . . . . . . . . . . . . . . . . .335
DXNR, DXNRP 32-bit data exclusive NOR operations . . . . . . . . . . . . . . . . . . .335
7.1.8 BKXNR, BKXNRP Block exclusive NOR operations . . . . . . . . . . . . . . . . . . . . . . .339

7.2 Rotation instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341

7.2.1 ROR, RORP, RCR, RCRPRight rotation of 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . .341
7.2.2 ROL, ROLP, RCL, RCLP Left rotation of 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .344
7.2.3 DROR, DRORP, DRCR, Right rotation of 32-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . .346
DRCRP
7.2.4 DROL, DROLP, DRCL, Left rotation of 32-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .348
DRCLP

7.3 Shift instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350

7.3.1 SFR, SFRP n-bit shift to right of 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . .350
SFL, SFLP n-bit shift to left of 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . . .350
7.3.2 BSFR, BSFRP 1-bit shift to right of n-bit data . . . . . . . . . . . . . . . . . . . . . . . . . .352
BSFL, BSFLP 1-bit shift to left of n-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . .352
7.3.3 SFTBR, SFTBRP n-bit shift to right of n-bit data . . . . . . . . . . . . . . . . . . . . . . . . . .354
SFTBL, SFTBLP n-bit shift to left of n-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . .354
7.3.4 DSFR, DSFRP 1-word shift to right of n-word data . . . . . . . . . . . . . . . . . . . . . .357
DSFL, DSFLP 1-word shift to left of n-word data . . . . . . . . . . . . . . . . . . . . . . .357
7.3.5 SFTWR, SFTWRP n-word shift to right of n-word data . . . . . . . . . . . . . . . . . . . . . .359
SFTWL, SFTWLP n-word shift to left of n-word data . . . . . . . . . . . . . . . . . . . . . . .359

13
 7.4 Bit processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362
7.4.1 BSET, BSETP Bit set for word devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
BRST, BRSTP Bit reset for word devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . .362
7.4.2 TEST, TESTP, DTEST, Bit tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363
DTESTP
7.4.3 BKRST, BKRSTP Batch reset of bit devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

7.5 Data processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367

7.5.1 SER, SERP 16-bit data search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
DSER, DSERP 32-bit data search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367
7.5.2 SUM, SUMP 16-bit data check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
DSUM, DSUMP 32-bit data check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .369
7.5.3 DECO, DECOP Decoding from 8 to 256 bits . . . . . . . . . . . . . . . . . . . . . . . . . . .371
7.5.4 ENCO, ENCOP Encoding from 256 to 8 bits . . . . . . . . . . . . . . . . . . . . . . . . . . .372
7.5.5 SEG, SEGP 7-segment decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .373
7.5.6 DIS, DISP 4-bit dissociation of 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . .375
7.5.7 UNI, UNIP 4-bit linking of 16-bit data . . . . . . . . . . . . . . . . . . . . . . . . . . . . .376
7.5.8 NDIS, NDISP Dissociation of random data . . . . . . . . . . . . . . . . . . . . . . . . . . .378
NUNI, NUNIP Linking of random data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378
7.5.9 WTOB, WTOBP Data dissociation in byte units . . . . . . . . . . . . . . . . . . . . . . . . .381
BTOW, BTOWP Data linking in byte units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .381
7.5.10 MAX, MAXP Maximum value search for 16-bit data . . . . . . . . . . . . . . . . . . .384
DMAX, DMAXP Maximum value search for 32-bit data . . . . . . . . . . . . . . . . . . .384
7.5.11 MIN, MINP Minimum value search for 16-bit data . . . . . . . . . . . . . . . . . . .386
DMIN, DMINP Minimum value search for 32-bit data . . . . . . . . . . . . . . . . . . .386
7.5.12 SORT BIN 16 bit-data sort operations . . . . . . . . . . . . . . . . . . . . . . . . .388
DSORT BIN 32 bit-data sort operations . . . . . . . . . . . . . . . . . . . . . . . . .388
7.5.13 WSUM, WSUMP Calculation of totals for 16-bit data . . . . . . . . . . . . . . . . . . . . . .391
7.5.14 DWSUM, DWSUMP Calculation of totals for 32-bit data . . . . . . . . . . . . . . . . . . . . . .392
7.5.15 MEAN, MEANP Calculation of averages for 16-bit data . . . . . . . . . . . . . . . . . . .393
DMEAN, DMEANP Calculation of averages for 32-bit data . . . . . . . . . . . . . . . . . . .393

7.6 Structure creation instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395

7.6.1 FOR, NEXT FOR to NEXT instruction loop . . . . . . . . . . . . . . . . . . . . . . . . .395
7.6.2 BREAK, BREAKP Forced end of FOR to NEXT instruction loop . . . . . . . . . . . . . .397
7.6.3 CALL, CALLP Subroutine program calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . .398
7.6.4 RET Return from subroutine programs . . . . . . . . . . . . . . . . . . . . . . .402
7.6.5 FCALL, FCALLP Subroutine program output OFF calls . . . . . . . . . . . . . . . . . . .403
7.6.6 ECALL, ECALLP Subroutine calls between program files . . . . . . . . . . . . . . . . . .407
7.6.7 EFCALL, EFCALLP Subroutine output OFF calls between program files . . . . . . . .411
7.6.8 XCALL Subroutine program calls . . . . . . . . . . . . . . . . . . . . . . . . . . . . .416
7.6.9 COM Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .419
7.6.10 COM Select refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .421
7.6.11 CCOM, CCOMP Select refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .424
7.6.12 IX, IXEND Index modification of entire ladder . . . . . . . . . . . . . . . . . . . . . .426
7.6.13 IXDEV, IXSET Designation of modification values in index modification
of entire ladders . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429

7.7 Data Table Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431

7.7.1 FIFW, FIFWP Writing data to the data table . . . . . . . . . . . . . . . . . . . . . . . . . .431

14
 7.7.2 FIFR, FIFRP Reading oldest data from tables . . . . . . . . . . . . . . . . . . . . . . . .432
7.7.3 FPOP, FPOPP Reading newest data from data tables . . . . . . . . . . . . . . . . . . .434
7.7.4 FDEL, FDELP Deletion of data from data tables . . . . . . . . . . . . . . . . . . . . . . .436
FINS, FINSP Insertion of data in data tables . . . . . . . . . . . . . . . . . . . . . . . . .436

7.8 Buffer memory access instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439

7.8.1 FROM, FROMP Reading 1-word data from the intelligent function module . . . .439
DFRO, DFROP Reading 2-word data from the intelligent function module . . . .439
7.8.2 TO, TOP Writing 1-word data to the intelligent function module . . . . . . .441
DTO, DTOP Writing 2-word data to the intelligent function module . . . . . . .441

7.9 Display instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445

7.9.1 PR Print ASCII code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .445
7.9.2 PRC Print comment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448
7.9.3 LEDR Error display and annunciator reset . . . . . . . . . . . . . . . . . . . . .451

7.10 Debugging and failure diagnosis instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453

7.10.1 CHKST, CHK Special format failure check . . . . . . . . . . . . . . . . . . . . . . . . . . .453
7.10.2 CHKCIR, CHKEND Changing check format of CHK . . . . . . . . . . . . . . . . . . . . . . . .457

7.11 Character string processing instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

7.11.1 BINDA, BINDAP Conversion from BIN 16-bit data to decimal ASCII . . . . . . . . .460
DBINDA, DBINDAP Conversion from BIN 32-bit data to decimal ASCII . . . . . . . . .460
7.11.2 BINHA, BINHAP Conversion from BIN 16-bit data to hexadecimal ASCII . . . . . .462
DBINHA, DBINHAP Conversion from BIN 32-bit data to hexadecimal ASCII . . . . . .462
7.11.3 BCDDA, BCDDAP Conversion from BCD 4-digit data to decimal ASCII data . . . .465
DBCDDA, DBCDDAP Conversion from BCD 8-digit data to decimal ASCII data . . . .465
7.11.4 DABIN, DABINP Conversion from decimal ASCII to BIN 16-bit data . . . . . . . . .468
DDABIN, DDABINP Conversion from decimal ASCII to BIN 32-bit data . . . . . . . . .468
7.11.5 HABIN, HABINP Conversion from hexadecimal ASCII to BIN 16-bit data . . . . . .470
DHABIN, DHABINP Conversion from hexadecimal ASCII to BIN 32-bit data . . . . . .470
7.11.6 DABCD, DABCDP Conversion from decimal ASCII to BCD 4-digit data . . . . . . . .472
DDABCD, DDABCDP Conversion from decimal ASCII to BCD 8-digit data . . . . . . . .472
7.11.7 COMRD, COMRDP Reading device comment data . . . . . . . . . . . . . . . . . . . . . . . . .474
7.11.8 LEN, LENP Character string length detection . . . . . . . . . . . . . . . . . . . . . . .476
7.11.9 STR, STRP Conversion from BIN 16-bit data to character string . . . . . . . .478
DSTR, DSTRP Conversion from BIN 32-bit data to character string . . . . . . . .478
7.11.10 VAL, VALP Conversion from character string to BIN 16-bit data . . . . . . . .482
DVAL, DVALP Conversion from character string to BIN 32-bit data . . . . . . . .482
7.11.11 ESTR, ESTRP Conversion from floating-point data to character string data . .485
7.11.12 EVAL, EVALP Conversion from character string to floating-point data . . . . . .490
7.11.13 ASC, ASCP Conversion from hexadecimal BIN to ASCII . . . . . . . . . . . . . . .494
7.11.14 HEX, HEXP Conversion from ASCII to hexadecimal BIN . . . . . . . . . . . . . . .496
7.11.15 RIGHT, RIGHTP Extracting character string data from the right . . . . . . . . . . . . .498
LEFT, LEFTP Extracting character string data from the left . . . . . . . . . . . . . .498
7.11.16 MIDR, MIDRP Random selection from character strings . . . . . . . . . . . . . . . . .500
MIDW, MIDWP Random replacement in character strings . . . . . . . . . . . . . . . .500
7.11.17 INSTR, INSTRP Character string search . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .504
7.11.18 STRINS, STRINSP Insertion of character string . . . . . . . . . . . . . . . . . . . . . . . . . . .506
7.11.19 STRDEL, STRDELP Deletion of character string . . . . . . . . . . . . . . . . . . . . . . . . . . . .508
7.11.20 EMOD, EMODP Floating-point data to BCD . . . . . . . . . . . . . . . . . . . . . . . . . . . .510

15
 7.11.21 EREXP, EREXPP From BCD format data to floating-point data . . . . . . . . . . . . . .512

7.12 Special function instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514

7.12.1 SIN, SINP SIN operation on floating-point data (Single precision) . . . . . .514
7.12.2 SIND, SINDP SIN operation on floating-point data (Double precision) . . . . . .515
7.12.3 COS, COSP COS operation on floating-point data (Single precision) . . . . .517
7.12.4 COSD, COSDP COS operation on floating-point data (Double precision) . . . . .518
7.12.5 TAN, TANP TAN operation on floating-point data (Single precision) . . . . . .520
7.12.6 TAND, TANDP TAN operation on floating-point data (Double precision) . . . . .522
7.12.7 ASIN, ASINP Arc sine operation on floating-point data (Single precision) . . .523
7.12.8 ASIND, ASINDP Arc sine operation on floating-point data (Double precision) . .525
7.12.9 ACOS, ACOSP Arc cosine operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .527
7.12.10 ACOSD, ACOSDP Arc cosine operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .528
7.12.11 ATAN, ATANP Arc tangent operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .530
7.12.12 ATAND, ATANDP Arc tangent operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .532
7.12.13 RAD, RADP Conversion from floating-point angle to radian
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533
7.12.14 RADD, RADDP Conversion from floating-point angle to radian
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535
7.12.15 DEG, DEGP Conversion from floating-point radian to angle
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .536
7.12.16 DEGD, DEGDP Conversion from floating-point radian to angle
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .537
7.12.17 POW, POWP Exponentiation operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539
7.12.18 POWD, POWDP Exponentiation operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .541
7.12.19 SQR, SQRP Square root operation for floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542
7.12.20 SQRD, SQRDP Square root operation for floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .544
7.12.21 EXP, EXPP Exponent operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .545
7.12.22 EXPD, EXPDP Exponent operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .547
7.12.23 LOG, LOGP Natural logarithm operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .549
7.12.24 LOGD, LOGDP Natural logarithm operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .550
7.12.25 LOG10, LOG10P Common logarithm operation on floating-point data
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .552
7.12.26 LOG10D, LOG10DP Common logarithm operation on floating-point data
(Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .553
7.12.27 RND, RNDP Random number generation . . . . . . . . . . . . . . . . . . . . . . . . . . .554
SRND, SRNDP Series updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .554

16
 7.12.28 BSQR, BSQRP BCD 4-digit square roots . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
BDSQR, BDSQRP BCD 8-digit square roots . . . . . . . . . . . . . . . . . . . . . . . . . . . . .555
7.12.29 BSIN, BSINP BCD type SIN operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .557
7.12.30 BCOS, BCOSP BCD type COS operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .559
7.12.31 BTAN, BTANP BCD type TAN operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .561
7.12.32 BASIN, BASINP BCD type arc sine operations . . . . . . . . . . . . . . . . . . . . . . . . . .562
7.12.33 BACOS, BACOSP BCD type arc cosine operation . . . . . . . . . . . . . . . . . . . . . . . . .564
7.12.34 BATAN, BATANP BCD type arc tangent operations . . . . . . . . . . . . . . . . . . . . . . .566

7.13 Data Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568

7.13.1 LIMIT, LIMITP Upper and lower limit controls for BIN 16-bit data . . . . . . . . . .568
DLIMIT, DLIMITP Upper and lower limit controls for BIN 32-bit data . . . . . . . . . .568
7.13.2 BAND, BANDP BIN 16-bit dead band controls . . . . . . . . . . . . . . . . . . . . . . . . .570
DBAND, DBANDP BIN 32-bit dead band controls . . . . . . . . . . . . . . . . . . . . . . . . .570
7.13.3 ZONE, ZONEP Zone control for BIN 16-bit data . . . . . . . . . . . . . . . . . . . . . . . .573
DZONE, DZONEP Zone control for BIN 32-bit data . . . . . . . . . . . . . . . . . . . . . . . .573
7.13.4 SCL, SCLP, DSCL, Scaling (Coordinate data by point) . . . . . . . . . . . . . . . . . . . . . .575
DSCLP
7.13.5 SCL2, SCL2P, DSCL2, Scaling (Coordinate data by X and Y) . . . . . . . . . . . . . . . . . . .578
DSCL2P

7.14 File register switching instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581

7.14.1 RSET, RSETP Switching file register block numbers . . . . . . . . . . . . . . . . . . . .581
7.14.2 QDRSET, QDRSETP File setting for file register . . . . . . . . . . . . . . . . . . . . . . . . . . . .582
7.14.3 QCDSET, QCDSETP File setting for comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . .584

7.15 Clock instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587

7.15.1 DATERD, DATERDP Reading clock data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .587
7.15.2 DATEWR, DATEWRP Writing clock data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .588
7.15.3 DATE+, DATE+P Clock data addition operation . . . . . . . . . . . . . . . . . . . . . . . . . .590
7.15.4 DATE-, DATE-P Clock data subtraction operation . . . . . . . . . . . . . . . . . . . . . . .592
7.15.5 SECOND, SECONDP Time data conversion (from Hour/Minute/Second to Second)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .594
7.15.6 HOUR, HOURP Time data conversion (from Second to Hour/Minute/Second)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .595
7.15.7 DT=, DT<>, DT>, DT<=, Date comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .596
DT<, DT>=
7.15.8 TM=, TM<>, TM>, TM<=, Time comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .601
TM<, TM>=

7.16 Expansion Clock Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605

7.16.1 S.DATERD, SP.DATERD Reading expansion clock data . . . . . . . . . . . . . . . . . . . . . . . . .605
7.16.2 S.DATE+, SP.DATE+ Expansion clock data addition operation . . . . . . . . . . . . . . . . .607
7.16.3 S.DATE-, SP.DATE- Expansion clock data subtraction operation . . . . . . . . . . . . . . .610

7.17 Program control instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613

7.17.1 PSTOP, PSTOPP Program standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614
7.17.2 POFF, POFFP Program output OFF standby . . . . . . . . . . . . . . . . . . . . . . . . . .615
7.17.3 PSCAN, PSCANP Program scan execution registration . . . . . . . . . . . . . . . . . . . .616
7.17.4 PLOW, PLOWP Program low speed execution registration . . . . . . . . . . . . . . . .617
7.17.5 PCHK Program execution status check . . . . . . . . . . . . . . . . . . . . . . .619

17
 7.18 Other instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
7.18.1 WDT, WDTP Watchdog timer reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .621
7.18.2 DUTY Timing pulse generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .622
7.18.3 TIMCHK Time check . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .623
7.18.4 ZRRDB, ZRRDBP Direct 1-byte read from file register . . . . . . . . . . . . . . . . . . . . .624
7.18.5 ZRWRB, ZRWRBP File register direct 1-byte write . . . . . . . . . . . . . . . . . . . . . . . . .625
7.18.6 ADRSET, ADRSETP Indirect address read operations . . . . . . . . . . . . . . . . . . . . . . .627
7.18.7 KEY Numerical key input using keyboard . . . . . . . . . . . . . . . . . . . . .628
7.18.8 ZPUSH, ZPUSHP Batch save of index register . . . . . . . . . . . . . . . . . . . . . . . . . . .632
ZPOP, ZPOPP Batch recovery of index register . . . . . . . . . . . . . . . . . . . . . . . .632
7.18.9 UNIRD, UNIRDP Reading module information . . . . . . . . . . . . . . . . . . . . . . . . . . .634
7.18.10 TYPERD,TYPERDP Reading module model name . . . . . . . . . . . . . . . . . . . . . . . . . .638
7.18.11 TRACE Trace set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643
TRACER Trace reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .643
7.18.12 SP.FWRITE Writing data to designated file . . . . . . . . . . . . . . . . . . . . . . . . .644
7.18.13 SP.FREAD Reading data from designated file . . . . . . . . . . . . . . . . . . . . . .654
7.18.14 SP.DEVST Writing data to standard ROM . . . . . . . . . . . . . . . . . . . . . . . . .665
7.18.15 S.DEVLD, SP.DEVLD Reading data from standard ROM . . . . . . . . . . . . . . . . . . . . . .667
7.18.16 PLOADP Loading program from memory card . . . . . . . . . . . . . . . . . . . .668
7.18.17 PUNLOADP Unloading program from program memory . . . . . . . . . . . . . . .671
7.18.18 PSWAPP Loading and unloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673
7.18.19 RBMOV, RBMOVP High-speed block transfer of file register . . . . . . . . . . . . . . . . .675
7.18.20 UMSG User Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680

CHAPTER 8 INSTRUCTIONS FOR DATA LINK 683

8.1 Network refresh instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683
8.1.1 S.ZCOM, SP.ZCOM Refresh for the designated module . . . . . . . . . . . . . . . . . . . . .683

8.2 Reading/Writing Routing Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687

8.2.1 S.RTREAD, SP.RTREAD Reading routing information . . . . . . . . . . . . . . . . . . . . . . . . . . .687
8.2.2 S.RTWRITE, Registering routing information . . . . . . . . . . . . . . . . . . . . . . . . .688
SP.RTWRITE

8.3 Refresh Device Write/Read Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690

8.3.1 S.REFDVWRB, Refresh device write (in 1-bit units) . . . . . . . . . . . . . . . . . . . . .690
SP.REFDVWRB
8.3.2 S.REFDVWRW, Refresh device write (in 16-bit units) . . . . . . . . . . . . . . . . . . . .694
SP.REFDVWRW
8.3.3 S.REFDVRDB, Refresh device read (in 1-bit units) . . . . . . . . . . . . . . . . . . . . . .698
SP.REFDVRDB
8.3.4 S.REFDVRDW, Refresh device read (in 16-bit units) . . . . . . . . . . . . . . . . . . . . .702
SP.REFDVRDW

CHAPTER 9 MULTIPLE CPU DEDICATED INSTRUCTION 706

9.1 Writing to the CPU Shared Memory of Host CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706
9.1.1 S.TO, SP.TO Writing to host CPU shared memory . . . . . . . . . . . . . . . . . . . .707
9.1.2 TO, TOP, DTO, DTOP Writing to host CPU shared memory . . . . . . . . . . . . . . . . . . . .710

18
 9.2 Reading from the CPU Shared Memory of another CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714
9.2.1 FROM, FROMP, DFRO, Reading from other CPU shared memory . . . . . . . . . . . . . . . .715
DFROP

CHAPTER 10 MULTIPLE CPU HIGH-SPEED TRANSMISSION DEDICATED

INSTRUCTIONS 720
10.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720
10.2 D.DDWR, DP.DDWR Writing Devices to Another CPU . . . . . . . . . . . . . . . . . . . . . . .730
10.3 D.DDRD, DP.DDRD Reading Devices from Another CPU . . . . . . . . . . . . . . . . . . . .733

CHAPTER 11 REDUNDANT SYSTEM INSTRUCTIONS (For REDUNDANT CPU) 737

11.1 SP.CONTSW System Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .737

APPENDICES 740
Appendix 1 OPERATION PROCESSING TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740
Appendix 1.1 Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .740
Appendix 1.2 Operation Processing Time of Basic Model QCPU . . . . . . . . . . . . . . . . . . . . . . . . .741
Appendix 1.3 Operation Processing Time of High Performance Model QCPU/Process CPU/
Redundant CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .757
Appendix 1.4 Operation Processing Time of Universal Model QCPU . . . . . . . . . . . . . . . . . . . . . .781
Appendix 1.4.1 Subset instruction processing time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .781
Appendix 1.4.2 Processing time of instructions other than subset instruction . . . . . . . . . . . . . .801
Appendix 1.5 Operation Processing Time of LCPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .867
Appendix 1.5.1 Subset instruction processing time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .867
Appendix 1.5.2 Processing time of instructions other than subset instruction . . . . . . . . . . . . . .874

Appendix 2 CPU PERFORMANCE COMPARISON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 897

Appendix 2.1 Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU . . . . . . . . . . . . . .897
Appendix 2.1.1 Usable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .897
Appendix 2.1.2 I/O control mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .898
Appendix 2.1.3 Data that can be used by instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .899
Appendix 2.1.4 Timer comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .900
Appendix 2.1.5 Comparison of counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .901
Appendix 2.1.6 Comparison of display instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .901
Appendix 2.1.7 Instructions whose designation format has been changed (Except dedicated
instructions for AnACPU and AnUCPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .902
Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions. . . . . . . . . . . . . . . . . . . . . . . . . .903

Appendix 3 APPLICATION PROGRAM EXAMPLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 904

Appendix 3.1 Concept of Programs which Perform Operations of a nth power of X, a nth root X
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .904

INDEX 906

INSTRUCTION INDEX 911

19
 MANUALS
To understand the main specifications, functions, and usage of the CPU module, refer to the basic manuals.
Read other manuals as well when using a different type of CPU module and its functions.
Order each manual as needed, referring to the following list.

The numbers in the "CPU module" and the respective modules are as follows.
Number CPU module
1) Basic model QCPU
2) High Performance model QCPU
3) Process CPU
4) Redundant CPU
5) Universal model QCPU
6) LCPU

: Basic manual, : Other CPU module manuals

Manual name CPU module
Description
< Manual number (model code) > 1) 2) 3) 4) 5) 6)
 User's manual
QCPU User's Manual Specifications of the hardware (CPU modules,
(Hardware design, Maintenance and Inspection) power supply modules, base units, extension
cables, memory cards, SD memory cards, extended
SRAM cassettes, and batteries), system
< SH-080483ENG (13JR73) > maintenance and inspection, and troubleshooting
QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080807ENG (13JZ27) >
Qn(H)/QnPH/QnPRHCPU User's Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080808ENG (13JZ28) >
QnUCPU User's Manual
Functions for the communication via built-in
(Communication via Built-in Ethernet Port)
Ethernet port of the CPU module
< SH-080811ENG (13JZ29) >
MELSEC-L CPU Module User's Manual Specifications of the hardware (CPU modules,
(Hardware design, Maintenance and Inspection) power supply modules, a branch module, an
extension module, and SD memory cards), system
maintenance and inspection, troubleshooting, and
< SH-080890ENG (13JRZ36) > error codes
MELSEC-L CPU Module User's Manual
(Function Explanation, Program Fundamentals) Functions, methods, and devices for programming
< SH-080889ENG (13JZ35) >
MELSEC-L CPU Module User's Manual
(Built-In I/O Function) Built-in I/O Functionality of the CPU
< SH-080892ENG (13JZ38) >
MELSEC-L CPU Module User's Manual
Functions for the communication via built-in
(Communication via Built-in Ethernet Port)
Ethernet port of the CPU module
< SH-080891ENG (13JZ37) >
QnUDVCPU/LCPU User's Manual
(Data Logging Function) Data Logging Functionality of the CPU Module
< SH-080893ENG (13JZ39) >

20
 : Basic manual, : Other CPU module manuals
Manual name CPU module
Description
< Manual number (model code) > 1) 2) 3) 4) 5) 6)
 Programming Manual
MELSEC-Q /L Programming Manual
How to use sequence instructions, basic
(Common Instructions)
instructions, and application instructions
< SH-080809ENG (13JW10) >
System configuration, performance specifications,
MELSEC-Q /L/QnA Programming Manual (SFC)
functions, programming, debugging, and error
< SH-080041 (13JF60) >
codes for SFC (MELSAP3) programs
MELSEC-Q /L Programming Manual (MELSAP-L) Programming methods, specifications, and
< SH-080072 (13JC03) > functions for SFC (MELSAP-L) programs
MELSEC-Q /L Programming Manual
(Structured Text) Programming methods using structured languages
< SH-080366E (13JF68) >
MELSEC-Q /L/QnA Programming Manual
(PID Control Instructions) Dedicated instructions for PID control
< SH-080040 (13JF59) >
MELSEC-Q Programming/Structured
Programming Manual (Process Control Describes the dedicated instructions for performing
Instructions) process control.
< SH-080316E (13JF59) >

Related Manuals

Manual name
Description
< Manual number (model code) >
CC-Link IE Controller Network Reference Manual Specifications, procedures and settings before system operation, parameter
settings, programming, and troubleshooting of the CC-Link IE Controller
< SH-080668ENG (13JV16) > Network module
MELSEC-Q CC-Link IE Field Network Master/Local Specifications, procedures and settings before system operation, parameter
Module User's Manual settings, programming, and troubleshooting of the CC-Link IE Field Network
< SH-080917ENG (13JZ47) > module
MELSEC-L CC-Link IE Field Network Master/Local Specifications, procedures and settings before system operation, parameter
Module User's Manual settings, programming, and troubleshooting of the CC-Link IE Field Network
< SH-080972ENG (13JZ54) > module
Q Corresponding MELSECNET/H Network System Specifications, procedures and settings before system operation, parameter
Reference Manual (PLC to PLC network) setting, programming, and troubleshooting of a MELSECNET/H network system
< SH-080049 (13JF92) > (PLC to PLC network)
Q Corresponding MELSECNET/H Network System Specifications, procedures and settings before system operation, parameter
Reference Manual (Remote I/O network) setting, programming, and troubleshooting of a MELSECNET/H network system
< SH-080124 (13JF96) > (remote I/O network)
Type MELSECNET, MELSECNET/B Data Link System
Describes the general concept, specifications, and part names and settings for
Reference Manual
MELSECNET (II) and MELSECNET/B.
< IB-66530 (13JF70) >
MELSEC-Q/L Ethernet Interface Module User's Manual E-mail function, programmable controller CPU status monitoring function,
(Application) communication via CC-Link IE Field Network, CC-Link IE Controller Network,
MELSECNET/H, or MELSECNET/10, communication using the data link
< SH-080010 (13JF70) > instructions, and file transfer function (FTP server) of the Ethernet module

21
CHAPTER 1 GENERAL DESCRIPTION

This manual describes the common instructions required for programming of the QCPU and LCPU.
"Common instructions" are all instructions except for dedicated instructions for intelligent function modules; PID control
instructions; SFC instructions; ST instructions; instructions for socket communication features; trigger logging instructions for
the LCPU; and dedicated instructions for LCPU positioning/counter functionality.

1.1 Related Programming Manuals

Before reading this manual, check the functions, programming methods, devices and others that are necessary to create
programs with the CPU in the manuals below:
• QnUCPU User's Manual (Function Explanation, Program Fundamentals)
• Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals)
• MELSEC-L CPU Module User's Manual (Function Explanation, Program Fundamentals)
(1) Basic model QCPU

Qn(H)/QnPH/
QnPRHCPU Describes the functions
User's Manual and devices of the CPU
(Function Explanation, module, and programming.
Program
Fundamentals)

This manual

MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L

Programming QnA Programming QnA Programming Programming Programming
Manual (Common Manual Manual (SFC) Manual Manual
Instructions) (PID Control (MELSAP-L) (Structured Text)
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST language.
other than those described to perform PID control.
in the manuals on the right.

22
(2) High Performance model QCPU

1
Qn(H)/QnPH/
QnPRHCPU
User's Manual Describes the functions
(Function Explanation, and devices of the CPU
module, and programming.
2
Program
Fundamentals)

3
This manual

4
MELSEC-Q/L MELSEC-Q/L/ MELSEC-Q/L/ MELSEC-Q/L MELSEC-Q/L
Programming QnA Programming QnA Programming Programming Programming
Manual (Common Manual Manual (SFC) Manual Manual 5
Instructions) (PID Control (MELSAP-L) (Structured Text)
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST language. 6
other than those described to perform PID control.
in the manuals on the right.

(3) Process CPU 7

8
Qn(H)/QnPH/ Describes the functions and
QnPRHCPU devices of the CPU module,
User's Manual and programming.
(Function Explanation,
Program

1.1
Fundamentals)

Related Programming Manuals

This manual

MELSEC-Q/L MELSEC-Q MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L

Programming Manual Programming/ Programming Manual Programming Manual Programming Manual
(Common Instruction) Structured (SFC) (MELSAP-L) (Structured Text)
Programming Manual
(Process Control
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST
other than those described to perform process control. language.
in the manuals on the right.

23
(4) Redundant CPU

Qn(H)/QnPH/ Describes the functions and

QnPRHCPU devices of the CPU module,
User's Manual and programming.
(Function Explanation,
Program
Fundamentals)

This manual

MELSEC-Q/L MELSEC-Q MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L

Programming Manual Programming/ Programming Manual Programming Manual Programming Manual
(Common Instruction) Structured (SFC) (MELSAP-L) (Structured Text)
Programming Manual
(Process Control
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST
other than those described to perform process control. language.
in the manuals on the right.

MELSEC-Q/L/QnA
Programming Manual
(PID Control
Instructions)

Describes the instructions

to perform PID control.

24
(5) Universal model QCPU

1
QnUCPU Describes the functions and

2
User's Manual devices of the CPU module,
and programming.
(Function Explanation,
Program
Fundamentals)
3

This manual
4

MELSEC-Q/L
Programming Manual
MELSEC-Q
Programming/
MELSEC-Q/L/QnA
Programming Manual
MELSEC-Q/L
Programming Manual
MELSEC-Q/L
Programming Manual
5
(Common Instruction) Structured (SFC) (MELSAP-L) (Structured Text)
Programming Manual
(Process Control
Instructions)
6
Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST
other than those described to perform process control. language.
in the manuals on the right.
7

8
MELSEC-Q/L/QnA
Programming Manual
(PID Control
Instructions)

1.1
Related Programming Manuals
Describes the instructions
to perform PID control.

25
(6) LCPU

MELSEC-L
Describes the functions and
CPU Module
devices of the CPU module,
User's Manual
and programming.
(Function Explanation,
Program
Fundamentals)

This manual

MELSEC-Q/L MELSEC-Q/L/QnA MELSEC-Q/L/QnA MELSEC-Q/L MELSEC-Q/L

Programming Manual Programming Manual Programming Manual Programming Manual Programming Manual
(Common Instruction) (PID Control (SFC) (MELSAP-L) (Structured Text)
Instructions)

Describes the instructions Describes the instructions Describes SFC. Describes MELSAP-L. Describes the ST
other than those described to perform process control. language.
in the manuals on the right.

26
1.2 Abbreviations and Generic Names
1
This manual uses the generic names and abbreviations shown below to refer to Q/L series CPU modules, unless otherwise
specified.
* indicates a part of the model or version. 2
Generic term/Abbreviation Description of Generic Name/Abbreviation
 Series
Q series The abbreviation for Mitsubishi MELSEC-Q series programmable controller
L series The abbreviation for Mitsubishi MELSEC-L series programmable controller 3
 CPU module type
A generic term for Basic model QCPU, High Performance model QCPU, Process CPU, Redundant
CPU module
CPU, Universal model QCPU and LCPU 4
Basic model QCPU A generic term for Q00JCPU, Q00CPU and Q01CPU
High Performance model QCPU A generic term for Q02CPU, Q02HCPU, Q06HCPU, Q12HCPU and Q25HCPU
Process CPU
Redundant CPU
A generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU
A generic term for Q12PRHCPU and Q25PRHCPU
5
A generic term for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDVCPU,
Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU, Q06UDVCPU,
Universal model QCPU Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU, 6
Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU and
Q100UDEHCPU

Built-in Ethernet port QCPU

A generic term for Q03UDVCPU, Q03UDECPU, Q04UDVCPU, Q04UDEHCPU, Q06UDVCPU,
Q06UDEHCPU, Q10UDEHCPU, Q13UDVCPU, Q13UDEHCPU, Q20UDEHCPU, Q26UDVCPU,
7
Q26UDEHCPU, Q50UDEHCPU and Q100UDEHCPU
High-speed Universal model
QCPU
A generic term for Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU and Q26UDVCPU
8
A generic term for the L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT,
Built-in Ethernet port LCPU
and L26CPU-PBT
 CPU module model
QnCPU A generic term for Q00JCPU, Q00CPU, Q01CPU and Q02CPU

1.2
QnHCPU A generic term for Q02HCPU, Q06HCPU, Q12HCPU and Q25HCPU
QnPHCPU A generic term for Q02PHCPU, Q06PHCPU, Q12PHCPU and Q25PHCPU

Abbreviations and Generic Names

QnPRHCPU A generic term for Q12PRHCPU and Q25PRHCPU
A generic term for Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU, Q03UDVCPU,
Q03UDECPU, Q04UDHCPU, Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU, Q06UDVCPU,
QnUCPU Q06UDEHCPU, Q10UDHCPU, Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU, Q13UDEHCPU,
Q20UDHCPU, Q20UDEHCPU, Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU, Q50UDEHCPU and
Q100UDEHCPU
A generic term for Q02UCPU, Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU,
QnU(D)(H)CPU
Q13UDHCPU, Q20UDHCPU and Q26UDHCPU
A generic term for Q03UDCPU, Q04UDHCPU, Q06UDHCPU, Q10UDHCPU, Q13UDHCPU,
QnUD(H)CPU
Q20UDHCPU and Q26UDHCPU
QnUDVCPU A generic term for Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU and Q26UDVCPU
A generic term for Q03UDECPU, Q04UDEHCPU, Q06UDEHCPU, Q10UDEHCPU, Q13UDEHCPU,
QnUDE(H)CPU
Q20UDEHCPU, Q26UDEHCPU, Q50UDEHCPU and Q100UDEHCPU
A generic term for L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU,
LCPU
L26CPU-P, L26CPU-BT and L26CPU-PBT
 Others
Programing Tool A generic term for GX Developer and GX Works2
The product name of Q/L series Corresponding SW D5C-GPPW-type GPP function software
package
GX Developer : Version of the software
Check the GX Developer versions that can be used for each CPU module in "System Configuration,"
User's Manual (Hardware Design, Maintenance and Inspection).

27
 Generic term/Abbreviation Description of Generic Name/Abbreviation
The product name of Q/L series Corresponding SW D5C-GXW2-type GPP function software
package
GX Works2 : Version of the software
Check the GX Works2 versions that can be used for each CPU module in "System Configuration,"
User's Manual (Hardware Design, Maintenance and Inspection).
CC-Link IE A generic term for the CC-Link IE Controller Network and the CC-Link IE Field Network
MELSECNET/H The abbreviation for MELSECNET/H network system
MELSECNET/10 The abbreviation for MELSECNET/10 network system
MELSECNET(II/,B) The abbreviation for MELSECNET and MELSECNET/B data link system
Intelligent function module device A generic term for intelligent function module devices and special function module devices
A generic term for Q33B, Q35B, Q38B and Q312B main base units on which CPU module (except
Q3 B Q00JCPU), Q series power supply module, Q series I/O module, and intelligent function module can
be mounted
A generic term for Q32SB, Q33SB and Q35SB slim type main base units on which Basic model QCPU
Q3 SB (except Q00JCPU), High Performance model QCPU, slim type power supply module, Q series I/O
module, and intelligent function module can be mounted
Other name for Q38RB redundant power supply main base unit on which CPU module (except
Q3 RB Q00JCPU), redundant power supply module, Q series I/O module, and intelligent function module can
be mounted.
A generic term for the Q35DB, Q38DB and Q312DB type Multiple CPU high speed main base unit on
Q3 DB which CPU module (except the Q00JCPU), Q series power supply module, Q series I/O module, and
intelligent function module can be mounted
A generic term for Q52B and Q55B extension base unit on which the Q Series I/O and intelligent
Q5 B
function module can be mounted
A generic term for Q63B, Q65B, Q68B and Q612B extension base unit on which Q Series power
Q6 B
supply module, I/O module, intelligent function module can be mounted
Other name for Q68RB redundant power supply extension base unit on which redundant power supply
Q6 RB
module, Q series I/O module, and intelligent function module can be mounted.
Another term for Q65WRB extension base unit for redundant system on which redundant power supply
Q6 WRB
module, Q series I/O module, and intelligent function module can be mounted.
A generic term for QA1S51B extension base unit on which AnS Series I/O module, special function
QA1S5 B
module can be mounted
A generic term for QA1S65B and QA1S68B extension base units on which AnS Series power supply
QA1S6 B
module, I/O module, special function module can be mounted

28
CHAPTER 2 INSTRUCTION TABLES

2.1 Types of Instructions

2
The major types of CPU module instructions consist of sequence instructions, basic instructions, application instructions, data
link instructions, QCPU instructions and redundant system instructions. These types of instructions are listed in the following
Table. 3
Reference
Types of Instruction Meaning
Chapter
Contact instruction Operation start, series connection, parallel connection 4
Ladder block connection, store/read operation results, creation of pulses from
Association instruction
operation results

Sequence
Output instruction Bit device output, pulse output, output reversal
Page 132, 5
Shift instruction Bit device shift
instruction CHAPTER 5
Master control instruction Master control
Termination instruction Program termination
Program stop, instructions such as no operation which do not fit in the above
6
Other instruction
categories
Comparison operation
instruction
Comparisons such as , ,
7
Arithmetic operation
Addition, subtraction, multiplication or division of BIN or BCD
instruction
BCD BIN conversion
Conversion from BCD to BIN and from BIN to BCD 8
instruction
Basic Page 181,
Data transfer instruction Transmits designated data
instruction CHAPTER 6
Program branch instruction Program jumps
Program run control
Enables or inhibits interrupt programs
instruction

2.1
I/O refresh Executes partial refresh

Types of Instructions
Instructions for: Counter increment/decrement, teaching timer, special
Other convenient instruction
function timer, rotary table shortest direction control, etc.
Logical operation instruction Logical operations such as logical sum, logical product, etc.
Rotation instruction Rotation of designated data
Shift instruction Shift of designated data
Bit processing instruction Bit set and reset, bit test, batch reset of bit devices
Data processing instruction 16-bit data searches, data processing such as decoding and encoding
Structure creation instruction Repeated operation, subroutine program calls, indexing in ladder units
Table operation instruction Data table read/write
Buffer memory access
Data read/write from/to an intelligent function module
instruction
Application Page 316,
Display instruction Print ASCII code, etc.
instruction CHAPTER 7
Debugging and failure
Check, status latch, sampling trace
diagnosis instruction
Conversion between BIN/BCD and ASCII; conversion between BIN and
Character string processing
character string; conversion between floating decimal point data and
instruction
character strings, character string processing, etc.
Trigonometric functions, conversion between angles and radians, exponential
Special function instruction
operations, automatic logarithms, square roots
Data control instruction Upper and lower limit controls, dead band controls, zone controls
Switching instruction File register block No. switches, designation of file registers and comment files

29
 Reference
Types of Instruction Meaning
Chapter
Reading/writing of the values of year, month, day, hour, minute, second, and
day of the week; addition/subtraction of the values of hour, minute, and
Clock instruction second; conversion of the values of hour, minute, and second into second;
comparison between the values of year, month, and day; and comparison
between the values of hour, minute, and second
Application Page 316,
Reading of the values of year, month, day, hour, minute, second, millisecond,
instruction CHAPTER 7
Expansion clock instruction and day of the week; addition/subtraction of the values of hour, minute,
second, and millisecond
Program control instruction Instructions to switch program execution conditions
Instructions that do not fit in the above categories, such as watchdog timer
Other instruction
reset instructions and timing clock instructions
Link refresh instruction Designated network refresh
Routing information read/
Data link Reads, writes, and registers routing information Page 683,
write instruction
instruction CHAPTER 8
Refresh device write/read
Reads or writes the refresh device.
instruction
Multiple
CPU Multiple CPU dedicated Page 706,
Writing to host CPU shared memory, Reading from other CPU shared memory
dedicated instruction CHAPTER 9
instruction
Multiple
CPU
high-speed Multiple CPU device write/ Page 720,
Writes/reads devices to/from another CPU.
transmission read instruction CHAPTER 10
dedicated
instruction
Redundant
Instruction for Redundant Page 737,
system System switching
CPU CHAPTER 11
instruction

30
2.2 How to Read Instruction Tables

The instruction tables found from Page 33, Section 2.3 to Page 55, Section 2.5 have been made according to the following
format:
2

1) 2) 3) 4) 5) 6) 7) 8)
7

Description
1)............Classifies instructions according to their application.
8
2)............Indicates the instruction symbol added to the instruction in a program.
Instruction code is built around the 16-bit instruction. The following notations are used to mark 32-bit instructions,
instructions executed only at the leading edge of OFF to ON, real number instructions, and character string

2.2
instructions:
• 32-bit instruction........The letter "D" is added to the first line of the instruction.

How to Read Instruction Tables

Example + D+

16-bit instruction 32-bit instruction

• Instructions executed only at the leading edge of OFF to ON

...................................The letter "P" is added to the end of the instruction.
Example + +P

Instruction executed Instruction executed

when ON only at the leading
edge of OFF to ON

• Real number instructions

...................................The letter "E" is added to the first line of the instruction.
Example + E+

Real number instructions

• Character string instructions

...................................A dollar sign $ is added to the first line of the instruction.
Example + $+

Character string instructions

31
3)............Shows symbol diagram on the ladder.
+ S D + S1 S2 D

Indicates destination. Indicates destination.

Indicates source. Indicates source.
Indicates instruction symbol. Indicates instruction symbol.

Fig. 2.1 Symbol Diagram on the Ladder

Destination...............Indicates where data will be sent after operation.
Source..................... Stores data prior to operation.
4)............Indicates the type of processing that is performed by individual instructions.
(D+1, D) +(S+1, S) (D +1,D)

(D)+(S) (D) 16 bits 16 bits

Indicates 16 bits. Indicates 32 bits.

D+1 D
Upper 16 bits Lower 16 bits

Fig. 2.2 Type of Processing Performed by Individual Instructions

5)............The details of conditions for the execution of individual instructions are as follows:
Symbol Execution Condition
Instruction executed under normal circumstances, with no regard to the ON/OFF status of conditions prior to
No symbol
the instruction.
recorded
If the precondition is OFF, the instruction will conduct OFF processing.
Executed during ON; instruction is executed only while the precondition is ON. If the preconditions is OFF, the
instruction is not executed, and no processing is conducted.
Executed once at ON; instruction executed only at leading edge when precondition goes from OFF to ON.
Following execution, instruction will not be executed and no processing conducted even if condition remains
ON.
Executed during OFF; instruction is executed only while the precondition is OFF. If the precondition is ON, the
instruction is not executed, and no processing is conducted.
Executed once at OFF; instruction executed only at trailing edge when precondition goes from ON to OFF.
Following execution, instruction will not be executed and no processing conducted even if condition remains
OFF.

6)............Indicates the basic number of steps for individual instructions.

See Page 118, Section 3.8 for a description of the number of steps.
7)............The mark indicates instructions for which subset processing is possible.
See Page 109, Section 3.5 for details on subset processing.
8)............Indicates the page numbers where the individual instructions are explained.

32
2.3 Sequence Instructions

2.3.1 Contact instructions

2

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
• Starts logic operation
LD
(Starts a contact logic operation)

LDI
• Starts logical NOT operation
(Starts b contact logic operation)
5
AND • Logical product (a contact series connection)
Page
*1

ANI
• Logical product NOT (b contact series 132 6
connection)

OR • Logical sum (a contact parallel connection)

ORI
• Logical sum NOT (b contact parallel 7
connection)

LDP • Starts leading edge pulse operation

8
LDF • Starts trailing edge pulse operation

ANDP • Leading edge pulse series connection

Page
Contact *1
134
ANDF • Trailing edge pulse series connection

2.3.1
2.3 Sequence Instructions
ORP • Leading edge pulse parallel connection

Contact instructions
ORF • Trailing edge pulse parallel connection

3
LDPI • Starts leading edge pulse NOT operation
*2*3
3
LDFI • Starts trailing edge pulse NOT operation
*2*3
4
ANDPI • Leading edge pulse NOT series connection
*2*3 Page
4 136
ANDFI • Trailing edge pulse NOT series connection
*2*3
4
ORPI • Leading edge pulse NOT parallel connection
*2*3
4
ORFI • Trailing edge pulse NOT parallel connection
*2*3

*1: The number of steps may vary depending on the device being used.
Device Number of Steps
Internal device, file register (R0 to R32767) 1
Direct access input (DX) 2
Devices other than above 3

33
 *2: The number of steps may differ, depending on the device or CPU module to be used.
• Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU.
Device Number of Steps
Internal device, file register (R0 to R32767) 1
Direct access input (DX) 1
Devices other than above 3
• Universal model QCPU and LCPU
Device Number of Steps
Internal device, file register (R0 to R32767) Number of Basic Steps
Serial number access format file register (ZR), Extended data register (D),
Number of Basic Steps +1
Extended link register (W), Multiple CPU shared device (U3En\G10000)
Direct access input (DX) Number of Basic Steps +1
Devices other than above Number of Basic Steps +2
*3: For the High-speed Universal model QCPU, the number of basic steps is two.

2.3.2 Association instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• AND between logical blocks

ANB
ANB (Series connection between logical blocks) Page
1 -
• OR between logical blocks 139
ORB
ORB (Series connection between logical blocks)

MPS • Memory storage of operation results

MPS • Read of operation results stored with MPS
MRD Page
MRD instruction 1 -
140
MPP • Read and reset of operation results stored
MPP
with MPS instruction
Page
Connection INV • Inversion of operation result 1 -
143
• Conversion of operation result to leading
MEP
edge pulse Page
1 -
• Conversion of operation result to trailing edge 144
MEF
pulse
• Conversion of operation result to leading
EGP Vn edge pulse 1
(Stored at Vn) Page
-
• Conversion of operation result to trailing edge 145
EGF Vn pulse *1

(Stored at Vn)

*1: The number of steps may differ, depending on CPU modules.

CPU module Number of Basic Steps
High Performance model QCPU
Process CPU
Redundant CPU 1
Universal model QCPU
LCPU
Basic model QCPU 2

34
2.3.3 Output instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
Page
147
Page
149
4
OUT • Device output *1 -
Page
152
Page 5
154
Page
155
SET SET D • Sets device
*2
*1 -
Page
6
159
Output Page

RST RST D • Resets device

*2
*1 -
157 7
Page
159
• Generates 1 cycle program pulse at leading
PLS PLS D
edge of input signal. Page
8
2 -
• Generates 1 cycle program pulse at trailing 161
PLF PLF D
edge of input signal.
Page
FF FF D • Reversal of device output 2 -
163

2.3.3
2.3 Sequence Instructions
DELTA DELTA D Page
• Pulse conversion of direct output 2 -
DELTAP 164
DELTAP D

Output instructions
*1: The number of steps may vary depending on the device being used.
See description pages of individual instructions for number of steps.

*2: The execution condition applies only when an annunciator (F) is in use.

2.3.4 Shift instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

SFT SFT D Page

Shift • 1-bit shift of device 2 -
SFTP 166
SFTP D

35
2.3.5 Master control instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Master MC MC n D • Starts master control 2 Page

-
control MCR • Resets master control 1 168
MCR n

2.3.6 Termination instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Page
FEND FEND • Termination of main program
172
Termination 1*1 -
Page
END END • Termination of sequence program
174

*1: For the High-speed Universal model QCPU, the number of basic steps is two.

2.3.7 Other instructions Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

• Terminates sequence operation after

input condition has been met.
Page
Stop STOP STOP • Sequence program is executed by 1 -
176
placing the RUN/STOP key switch
back in the RUN position.
• Ignored (For program deletion or
NOP ––––––
space)
• Ignored (To change pages during Page
Ignored NOPLF NOPLF 1 -
printouts) 177
• Ignored (Subsequent programs will be
PAGE PAGE n
controlled from step 0 of page n)

36
2.4 Basic instructions

2.4.1 Comparison operation instructions

2

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
LD= S1 S2

AND= • Conductive status when (S1) (S2)

S1 S2
• Non-conductive status when (S1) (S2)
3 5
OR=
S1 S2

LD<> S1 S2 6
AND<> S1 S2 • Conductive status when (S1) (S2)
3
• Non-conductive status when (S1) (S2)
OR<> 7
S1 S2

LD> S1 S2

AND> S1 S2 • Conductive status when (S1) (S2)

8
3
• Non-conductive status when (S1) (S2)
OR>
BIN 16-bit S1 S2 Page
data
181
comparisons LD<=

2.4.1
2.4 Basic instructions
S1 S2

AND<= S1 S2 • Conductive status when (S1) (S2)

3
• Non-conductive status when (S1) (S2)

Comparison operation instructions

OR<=
S1 S2

LD< S1 S2

AND< S1 S2 • Conductive status when (S1) (S2)

3
• Non-conductive status when (S1) (S2)
OR<
S1 S2

LD>= S1 S2

AND>= S1 S2 • Conductive status when (S1) (S2)

3
• Non-conductive status when (S1) (S2)
OR>=
S1 S2

37
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

LDD= D S1 S2
• Conductive status when
ANDD= D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD= (S1+1, S1) (S2+1, S2)
D S1 S2

LDD<> D S1 S2
• Conductive status when
ANDD<> D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD<> (S1+1, S1) (S2+1, S2)
D S1 S2

LDD> D S1 S2
• Conductive status when
ANDD> D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when

BIN 32-bit ORD> (S1+1, S1) (S2+1, S2)

D S1 S2 Page
data
182
comparisons LDD<= D S1 S2
• Conductive status when
ANDD<= D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD<= (S1+1, S1) (S2+1, S2)
D S1 S2

LDD< D S1 S2
• Conductive status when
ANDD< D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD< (S1+1, S1) (S2+1, S2)
D S1 S2

LDD>= D S1 S2
• Conductive status when
ANDD>= D S1 S2 (S1+1, S1) (S2+1, S2)
*1
• Non-Conductive status when
ORD>= (S1+1, S1) (S2+1, S2)
D S1 S2

*1: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
5 Note 1)
Process CPU designation is K8, and which use no Indexing.
Redundant CPU • Constant: No limitations
Devices other than above 3 Note 2)
Basic model QCPU
Universal model QCPU All devices that can be used 3 Note 2)
LCPU
Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU, the number of steps increases but
the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Page 118, Section 3.8.

38
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
LDE= E S1 S2
• Conductive status when
3
ANDE= E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when
ORE= (S1+1, S1) (S2+1, S2)
E S1 S2 4
LDE<> E S1 S2
• Conductive status when
ANDE<> E S1 S2 (S1+1, S1) (S2+1, S2)
• Non-Conductive status when
3 - 5
ORE<> (S1+1, S1) (S2+1, S2)
E S1 S2

LDE> E S1 S2
6
• Conductive status when
ANDE> E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
Floating • Non-Conductive status when
decimal ORE> (S1+1, S1) (S2+1, S2)
7
point data E S1 S2 Page
comparisons 184
LDE<= E S1 S2
(Single • Conductive status when
8
precision) ANDE<= E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when
ORE<= (S1+1, S1) (S2+1, S2)
E S1 S2

LDE<

2.4.1
2.4 Basic instructions
E S1 S2
• Conductive status when
ANDE< E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when

Comparison operation instructions

ORE< (S1+1, S1) (S2+1, S2)
E S1 S2

LDE>= E S1 S2
• Conductive status when
ANDE>= E S1 S2 (S1+1, S1) (S2+1, S2)
3 -
• Non-Conductive status when
ORE>= (S1+1, S1) (S2+1, S2)
E S1 S2

39
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

LDED= • Conductive status when

ED S1 S2
(S1+3, S1+2, S1+1, S1)
ANDED= ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED= (S1+3, S1+2, S1+1, S1)
ED S1 S2
(S2+3, S2+2, S2+1, S2)

LDED<> • Conductive status when

ED S1 S2
(S1+3, S1+2, S1+1, S1)
ANDED<> ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED<> (S1+3, S1+2, S1+1, S1)
ED S1 S2
(S2+3, S2+2, S2+1, S2)

LDED> • Conductive status when

ED S1 S2
(S1+3, S1+2, S1+1, S1)
ANDED> ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
Floating • Non-Conductive status when
decimal ORED> (S1+3, S1+2, S1+1, S1)
ED S1 S2
point data (S2+3, S2+2, S2+1, S2) Page
comparisons LDED<= • Conductive status when 186
ED S1 S2
(Double (S1+3, S1+2, S1+1, S1)
precision) ANDED<= ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED<= (S1+3, S1+2, S1+1, S1)
ED S1 S2
(S2+3, S2+2, S2+1, S2)

LDED< • Conductive status when

ED S1 S2
(S1+3, S1+2, S1+1, S1)
ANDED< ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED< (S1+3, S1+2, S1+1, S1)
ED S1 S2
(S2+3, S2+2, S2+1, S2)

LDED>= • Conductive status when

ED S1 S2
(S1+3, S1+2, S1+1, S1)
ANDED>= ED S1 S2 (S2+3, S2+2, S2+1, S2)
3 -
• Non-Conductive status when
ORED>= (S1+3, S1+2, S1+1, S1)
ED S1 S2
(S2+3, S2+2, S2+1, S2)

40
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
• Compares character string S1 and character
LD$= $ S1 S2
string S2 one character at a time. *2 3
AND$= $ S1 S2 • Conductive status when (character string S1)
3 -
(character string S2)
• Non-Conductive status when (character string
OR$=
$ S1 S2
S1) (character string S2)
4
• Compares character string S1 and character
LD$<> $ S1 S2
string S2 one character at a time. *2
AND$<> $ S1 S2 • Conductive status when (character string S1) 5
3 -
(character string S2)
OR$<> • Non-Conductive status when (character string
$ S1 S2
S1) (character string S2) 6
LD$> • Compares character string S1 and character
$ S1 S2
string S2 one character at a time. *2
AND$> • Conductive status when (character string S1)
7
$ S1 S2
3 -
(character string S2)
OR$> • Non-Conductive status when (character string
Character $ S1 S2
S1) (character string S2) Page
string data
comparisons LD$<= $ S1 S2
• Compares character string S1 and character 186 8
string S2 one character at a time. *2
AND$<= $ S1 S2 • Conductive status when (character string S1)
3 -
(character string S2)
OR$<= • Non-Conductive status when (character string

2.4.1
2.4 Basic instructions
$ S1 S2
S1) (character string S2)
• Compares character string S1 and character
LD$< $ S1 S2
string S2 one character at a time. *2

Comparison operation instructions

AND$< $ S1 S2 • Conductive status when (character string S1)
3 -
(character string S2)
OR$< • Non-Conductive status when (character string
$ S1 S2
S1) (character string S2)
• Compares character string S1 and character
LD$>= $ S1 S2
string S2 one character at a time. *2
AND$>= $ S1 S2 • Conductive status when (character string S1)
3 -
(character string S2)
OR$>= • Non-Conductive status when (character string
$ S1 S2
S1) (character string S2)
*2: The conditions under which character string comparisons can be made are as shown below:
• Match: All characters in the strings must match
• Larger string: If character strings are different, determines the string with the largest number of character codes.
If the lengths of the character strings are different, determines the longest character string.
• Smaller string: If the character strings are different, determines the string with the smallest number of character codes.
If the lengths of the character strings are different, determines the shortest character string.

41
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

BKCMP= BKCMP S1 S2 D n

BKCMP<> BKCMP S1 S2 D n

BKCMP> BKCMP S1 S2 D n

BKCMP<= BKCMP S1 S2 D n
• This instruction compares BIN 16-bit data
BKCMP< BKCMP S1 S2 D n
stored in n-point devices starting from the
BIN 16-bit
BKCMP>= BKCMP S1 S2 D n device specified by S1 with BIN 16-bit
Block Page
data stored in n-point devices starting 5 -
data BKCMP=P 191
BKCMP P S1 S2 D n from the device specified by S2, and then
comparisons
stores the result into the nth device
BKCMP<>P BKCMP P S1 S2 D n
specified by (D) and up.
BKCMP>P BKCMP P S1 S2 D n

BKCMP<=P BKCMP P S1 S2 D n

BKCMP<P BKCMP P S1 S2 D n

BKCMP>=P BKCMP P S1 S2 D n

DBKCMP= DBKCMP S1 S2 D n

DBKCMP<> DBKCMP S1 S2 D n

DBKCMP> DBKCMP S1 S2 D n

DBKCMP<= DBKCMP S1 S2 D n
• This instruction compares BIN 32-bit data
DBKCMP< DBKCMP S1 S2 D n
stored in n-point devices starting from the
BIN
DBKCMP>= DBKCMP S1 S2 D n device specified by S1 with BIN 32-bit data
32-bit block Page
stored in n-point devices starting from the 5 -
data DBKCMP=P DBKCMP P S1 S2 D n 193
device specified by a constant and S2, and
comparisons
then stores the result into the nth device
DBKCMP<>P DBKCMP P S1 S2 D n
specified by (D) and up.
DBKCMP>P DBKCMP P S1 S2 D n

DBKCMP<=P DBKCMP P S1 S2 D n

DBKCMP<P DBKCMP P S1 S2 D n

DBKCMP>=P DBKCMP P S1 S2 D n

42
2.4.2 Arithmetic operation instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
+ + S D Page

+P +P S D
• (D)+(S) (D) 3
197 4
+ + S1 S2 D Page
BIN 16-bit • (S1)+(S2) (D) 4
addition and +P +P S1 S2 D
198 5
subtraction
- S D Page
operations • (D)-(S) (D) 3
-P P S D
197
6
- S1 S2 D Page
• (S1)-(S2) (D) 4
198
-P P S1 S2 D
7
D+ D+ S D Page
• (D+1, D)+(S+1, S) (D+1, D) *1
D+P 200
8
D+P S D

D+ D+ S1 S2 D Page
BIN 32-bit • (S1+1, S1)+(S2+1, S2) (D+1, D) *2
D+P 201
addition and D+P S1 S2 D
subtraction D- D S D Page
operations • (D+1, D)-(S+1, S) (D+1, D) *1

2.4.2
2.4 Basic instructions
D-P 200
D P S D

D- D S1 S2 D

Arithmetic operation instructions

Page
• (S1+1, S1)-(S2+1, S2) (D+1, D) *2
D-P 201
D P S1 S2 D

* * S1 S2 D
BIN 16-bit • (S1) (S2) (D+1,D) *3

multiplication *P S1 S2 D Page
and division / 203
/ S1 S2 D • (S1) / (S2)
operations 4 *4
/P /P S1 S2 D Quotient(D), Remainder (D+1)

D* S1 S2 D
BIN 32-bit • (S1+1,S1) (S2+1,S2) (D+3,D+2,D+1,D) 4*4
multiplication D*P S1 S2 D Page
and division D/ 205
D/ S1 S2 D • (S1+1, S1) / (S2+1, S2)
operations 4*4
D/P D/P S1 S2 D Quotient (D+1, D), Remainder (D+3, D+2)

43
 *1: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
5 Note 1)
Process CPU designation is K8, and which use no indexing.
Redundant CPU • Constant: No limitations
Devices other than above 3 Note 2)
Basic model QCPU
Universal model QCPU All devices that can be used 3 Note 2)
LCPU
Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU, the number of steps increases but
the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Page 118, Section 3.8.
*2: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
6 Note 1)
Process CPU designation is K8, and which use no indexing.
Redundant CPU • Constant: No limitations
Devices other than above 4 Note 2)
Basic model QCPU 4 Note 2)
Universal model QCPU All devices that can be used
3 Note 2)
LCPU
Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU, the number of steps increases but
the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Page 118, Section 3.8.
*3: The number of steps may differ, depending on the device or CPU module to be used.
CPU module Device Number of Steps
• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
QCPU 3
designation is K8, and which use no indexing.
LCPU
• Constant: No limitations
Devices other than above 4 Note 1)
Note 1) The number of steps may increase due to the conditions described in Page 118, Section 3.8.
*4: The number of basic steps is three for the Universal model QCPU and LCPU only.

44
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
B+ B+ S D Page
• (D)+(S) (D) 3
207
3
B+P B+P S D

B+ B+ S1 S2 D Page
BCD 4-digit
B+P B+P S1 S2 D
• (S1)+(S2) (D) 4 -
209 4
addition and
subtraction B- B S D Page
operations • (D)-(S) (D) 3
B-P B P S D
207 5
B- B S1 S2 D Page
• (S1)-(S2) (D) 4 -
B-P B P S1 S2 D
209
6
DB+ DB+ S D Page
• (D+1, D)+(S+1, S) (D+1, D) 3 -
210
DB+P DB+P S D
7
DB+ DB+ S1 S2 D Page
BCD 8-digit • (S1+1, S1)+(S2+1, S2) (D+1, D) 4 -
DB+P 212
addition and
subtraction
DB+P S1 S2 D
8
DB- DB S D Page
operations • (D+1, D)-(S+1, S) (D+1, D) 3 -
DB-P 210
DB P S D

DB- DB S1 S2 D Page
4 -

2.4.2
2.4 Basic instructions
• (S1+1, S1)-(S2+1, S2) (D+1, D)
DB-P 212
DB P S1 S2 D

B*

Arithmetic operation instructions

B S1 S2 D
BCD 4-digit
• (S1) (S2) (D+1,D) 4
multiplication B*P B P S1 S2 D Page
and
B/ 213
division B/ S1 S2 D
• (S1) / (S2) Quotient(D), Remainder (D+1) 4
operations
B/P B/P S1 S2 D

DB* DB S1 S2 D
BCD 8-digit
• (S1+1,S1) (S2+1,S2) (D+3,D+2,D+1,D) 4 -
multiplication DB*P DB P S1 S2 D Page
and
DB/ 215
division DB/ S1 S2 D • (S1+1, S1) / (S2+1, S2) Quotient (D+1, D),
4
operations Remainder (D+3, D+2)
DB/P DB/P S1 S2 D

45
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

E+ E+ S D Page
• (D+1, D)+(S+1, S) (D+1, D) 3
E+P *6 217
E+P S D
Floating
decimal E+ E+ S1 S2 D 4 Page
point data • (S1+1, S1)+(S2+1, S2) (D+1, D)
E+P
*5 *6 219
addition and E+P S1 S2 D
subtraction E- E S D Page
operations • (D+1, D)-(S+1, S) (D+1, D) 3
E-P *6 217
(Single E P S D
precision)
E- E S1 S2 D Page
4
• (S1+1, S1)-(S2+1, S2) (D+1, D)
E-P
*5 *6 219
E P S1 S2 D

ED+ ED+ S D • (D+3, D+2, D+1, D)+(S+3, S+2, S+1, S) Page

3
ED+P (D+3, D+2, D+1, D) 221
ED+P S D
Floating
decimal ED+ ED+ S1 S2 D • (S1+3, S1+2, S1+1, S1)+
Page
point data (S2+3, S2+2, S2+1, S2) 4
ED+P 223
addition and ED+P S1 S2 D (D+3, D+2, D+1, D)
subtraction ED- ED S D • (D+3, D+2, D+1, D)-(S+3, S+2, S+1, S) Page
operations 3
ED-P (D+3, D+2, D+1, D) 221
(Double ED P S D
precision)
ED- ED S1 S2 D • (S1+3, S1+2, S1+1, S1)-
Page
(S2+3, S2+2, S2+1, S2) 4
ED-P 223
ED P S1 S2 D (D+3, D+2, D+1, D)
Floating
E* S1 S2 D
decimal
• (S1+1,S1) (S2+1,S2) (D+1,D) 3
point data *6
E*P S1 S2 D
multiplication Page
and division E/ 225
E/ S1 S2 D
operations
• (S1+1, S1) / (S2+1, S2) Quotient (D+1, D) 4
(Single *6
E/P E/P S1 S2 D
precision)
Floating
ED* ED S1 S2 D • (S1+3,S1+2,S1+1,S1)
decimal
(S2+3,S2+2,S2+1,S2) 4
point data *6
ED*P ED P S1 S2 D (D+3,D+2,D+1,D)
multiplication Page
and division ED/ 227
ED/ S1 S2 D • (S1+3, S1+2, S1+1, S1) /
operations
(S2+3, S2+2, S2+1, S2) 4
(Double *6
ED/P ED/P S1 S2 D Quotient (D+3, D+2, D+1, D)
precision)
*5: The number of basic steps is three for the Universal model QCPU and LCPU only.
*6: The subset is effective only with Universal model QCPU and LCPU.

46
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
• This instruction adds BIN 16-bit data stored in
BK+ BK+ S1 S2 D n n-point devices starting from the device 3
specified by (S1) to the n-point data stored in 5 -
BIN 16-bit
BK+P BK+P S1 S2 D n the devices starting from the device specified
data block
by (S2) in batch. Page
addition and
• This instruction substracts BIN 16-bit data 229 4
subtraction BK- BK S1 S2 D n stored in the n-point devices starting from the
operations
devices specified by (S2) from BIN 16-bit data 5 -
BK-P BK P S1 S2 D n stored in n-point devices starting from the 5
device specified by (S1) in batch.
• Adds BIN 32-bit data stored in the n-point
DBK+ DBK+ S1 S2 D n devices starting from the device specified by
(S1) and a constant to BIN 32-bit data stored
6
5 -
in the n-point devices starting from the device
BIN 32-bit DBK+P DBK+P S1 S2 D n specified by (S2) and stores the result into the
data block nth device specified by (D) and up.
Page
7
addition and • Subtracts BIN 32-bit data stored in the n-point
231
subtraction devices starting from the device specified by
DBK- DBK S1 S2 D n
operations (S2) or a constant from BIN 32-bit data stored 8
in n-point devices starting from the device 5 -
specified by (S1) and stores the operation
DBK-P DBK P S1 S2 D n result into the nth device specified by (D) and
up.

$+ • Links character string designated with (S) to

2.4.2
2.4 Basic instructions
$+ S D Page
character string designated with (D), and 3 -
Character $+P 234
$+P S D stores the result from (D) onward.
string data

Arithmetic operation instructions

$+ • Links character string designated with (S2) to
Connection $+ S1 S2 D Page
character string designated with (S1), and 4 -
$+P 235
$+P S1 S2 D stores the result from (D) onward.

INC INC D Page

• (D)+1 (D) 2
INCP 237
INCP D

DINC DINC D Page

• (D+1, D)+1 (D+1, D) *7
DINCP 238
BIN data DINCP D
increment DEC DEC D Page
• (D)-1 (D) 2
DECP 237
DECP D

DDEC DDEC D Page

• (D+1, D)-1 (D+1, D) *7
DDECP 238
DDECP D

47
 *7: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
3 Note 1)
Process CPU designation is K8, and which use no indexing.
Redundant CPU • Constant: No limitations
Devices other than above 2 Note 2)
Basic model QCPU
Universal model QCPU All devices that can be used 2 Note 2)
LCPU
Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU, the number of steps increases but
the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Page 118, Section 3.8.

2.4.3 Data conversion instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

BCD BCD S D BCD conversions 3

(S) (D)
*1
BCD BCDP BCDP S D BIN (0 to 9999) Page
conversions DBCD BCD conversions
240
DBCD S D 3
(S+1, S) (D+1, D)
*1
DBCDP DBCDP S D BIN (0 to 99999999)

BIN BIN S D BIN conversions 3

(S) (D)
*1
BINP BINP S D BCD (0 to 9999)
BIN Page
conversions DBIN DBIN S D BIN conversions 242
(S+1, S) (D+1, D) 3
*1
DBINP DBINP S D BCD (0 to 99999999)

BIN FLT FLT S D Conversion to real number

3
(S) (D+1, D)
*1 *2
FLTP FLTP S D BIN( 32768 to 32767)
Floating point Page
conversions DFLT DFLT S D Conversion to real number 244
(Single (S+1, S) (D+1, D) 3
BIN( 2147483648 to *1 *2
precision) DFLTP DFLTP S D
2147483647)

BIN FLTD FLTD S D Conversion to real number

(S) ( D+3, D+2, D+1, D) 4
*2
FLTDP FLTDP S D BIN( 32768 to 32767)
Floating point Page
conversions DFLTD DFLTD S D Conversion to real number 246
(Double (S+1, S) (D+3, D+2, D+1, D)
4
precision) BIN( 2147483648 to *2
DFLTDP DFLTDP S D
2147483647)

*1: The number of basic steps is two for the Universal model QCPU and LCPU only.
*2: The subset is effective only with Universal model QCPU and LCPU.

48
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Floating point INT INT S D

(S+1, S)
Conversion to BIN
(D)
*1
3
3
*2
INTP INTP S D Real number (-32768 to 32767)
BIN Page
conversions DINT Conversion to BIN 247
(Single
DINT S D
(S+1, S) (D+1, D) 3 4
Real number (-2147483648 to *1 *2
precision) DINTP DINTP S D
2147483647)

Floating point INTD INTD S D Conversion to BIN

(S+3, S+2, S+1, S) (D) 5
3
Real number (-32768 to 32767) *2
INTDP INTDP S D
BIN Page
conversions
(Double
DINTD DINTD S D Conversion to BIN
(S+3, S+2, S+1, S) (D+1, D)
249
6
3
precision) Real number (-2147483648 to *2
DINTDP DINTDP S D
2147483647)

DBL DBL S D Conversion Page

7
BIN (S) (D+1, D) 3 *3 -
16-bit 251
DBLP DBLP S D BIN (-32768 to 32767)

32-bit WORD WORD S D Conversion Page

8
(S+1, S) (D) *3 -
conversion 3
252
WORDP WORDP S D BIN (-32768 to 32767)

GRY GRY S D Conversion to gray code

(S) (D) 3*3 -

2.4.3
2.4 Basic instructions
BIN
GRYP GRYP S D BIN (-32768 to 32767)
Page
Gray code DGRY Conversion to gray code 253

Data conversion instructions

DGRY S D
conversions (S+1, S) (D+1, D)
3*3 -
DGRYP BIN (-2147483648 to
DGRYP S D
2147483647)

GBIN GBIN S D Conversion to BIN data

Gray code (S) (D) 3*3 -
GBINP GBINP S D Gray code (-32768 to 32767)
Page
BIN DGBIN Conversion to BIN data 254
DGBIN S D
conversions (S+1, S) (D+1, D) *3
3 -
DGBINP Gray code (-2147483648 to
DGBINP S D
2147483647)
*1: The number of basic steps is two for the Universal model QCPU and LCPU only.
*2: The subset is effective only with Universal model QCPU and LCPU.
*3: For the High-speed Universal model QCPU, the number of basic steps is two.

49
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

NEG NEG D
(D) (D)
2 -
NEGP NEGP D BIN data
Page
DNEG 256
DNEG D
(D+1, D) (D+1, D)
2 -
DNEGP DNEGP D BIN data
Complement
to 2 ENEG ENEG D Page
(D+1, D) (D+1, D)
2 -
ENEGP Real number data 257
ENEGP D

EDNEG EDNEG D Page

(D+3, D+2, D+1, D) (D+3, D+2, D+1, D)
3 -
EDNEGP Real number data 258
EDNEGP D

BKBCD BKBCD S D n • Batch converts BIN data n points from (S) to

Page
BCD data and stores the result from (D) 4 -
BKBCDP 259
Block BKBCDP S D n onward.
conversion BKBIN • Batch converts BCD data n points from (S)
BKBIN S D n Page
to BIN data and stores the result from (D) 4 -
BKBINP 261
BKBINP S D n onward.
Floating-point
Single ECON ECON S D
precision Conversion to double precision Page
(S+1, S) (D+3, D+2, D+1, D) 3 -
262
32-bit floating-point real number
Double ECONP ECONP S D
precision
Floating-point
Double EDCON EDCON S D
precision Conversion to single precision Page
(S+3, S+2, S+1, S) (D+1, D) 3 -
263
64-bit floating-point real number
Single EDCONP EDCONP S D
precision

50
2.4.4 Data transfer instructions

Number of Basic Steps

See for Description

Instruction Symbol 2

Subset
Execution
Category Symbol Processing Details
Condition

3
16-bit data MOV MOV S D
(S) ( D) *1
transfer MOVP MOVP S D Page 4
DMOV 265
32-bit data DMOV S D
(S+1,S) (D+1,D) *2
transfer DMOVP DMOVP S D
Floating
5
EMOV EMOV S D
decimal point
(S+1, S) (D+1, D) Page
data transfer *2
266
(Single EMOVP EMOVP S D
Real number data *3
6
precision)

Floating
EDMOV
7
EDMOV S D
decimal point
(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) Page
data transfer 2
Real number data *3 268
(Double
EDMOVP EDMOVP S D
precision)

Character
8
$MOV $MOV S D • Transfers character string designated by (S) Page
string data 3 -
$MOVP to device designated by (D) onward. 269
transfer $MOVP S D

16-bit data CML CML S D

negation (S) (D) *1

2.4.4
2.4 Basic instructions
transfer CMLP CMLP S D Page
32-bit data DCML 271
DCML S D

Data transfer instructions

negation (S+1,S) (D+1,D) *2

transfer DCMLP DCMLP S D

Block BMOV BMOV S D n (S) (D) Page

4
transfer BMOVP
n 274
BMOVP S D n

Identical 16- FMOV FMOV S D n (D)

bit data block (S) 4
n
transfers FMOVP FMOVP S D n Page
Identical 32- DFMOV 277
DFMOV S D n (D+1,D)
bit data block (S+1,S) 4
n
transfers DFMOVP DFMOVP S D n

16-bit data XCH XCH D1 D2

(D1) (D2) 3
exchange XCHP XCHP D1 D2 Page
DXCH 279
32-bit data DXCH D1 D2
(D1+1,D1) (D2+1,D2) 3
exchange DXCHP DXCHP D1 D2

51
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Block data BXCH BXCH S D n (S) (D) Page

4 -
exchange BXCHP
n 282
BXCHP S D n

b15 to b8 b7 to b0
Exchange of SWAP SWAP D (S) 8 bits 8 bits
Page
upper and 3 -
284
lower bytes SWAPP SWAPP D b15 to b8 b7 to b0
(D) 8 bits 8 bits
*1: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
QCPU 2
designation is K4, and which use no indexing.
LCPU
• Constant: No limitations
Devices other than above 3 Note 1)
Note 1) The number of steps may increase due to the conditions described in Page 118, Section 3.8.
*2: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
3
Process CPU designation is K8, and which use no indexing.
Redundant CPU • Constant: No limitations
Devices other than above 3 Note 1)
• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
designation is K8, and which use no indexing. 2
Basic model QCPU
• Constant: No limitations
(The number of steps is 3 when the above device + constant are used.)
Devices other than above 3 Note 1)
Universal model QCPU
All devices that can be used 2 Note 1)
LCPU
Note 1) The number of steps may increase due to the conditions described in Page 118, Section 3.8.
*3: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
• Bit device: Devices whose device Nos. are multiples of 16, whose digit
QCPU 2
designation is K4, and which use no indexing.
LCPU
• Constant: No limitations
Devices other than above 3 Note 1)
Note 1) The number of steps may increase due to the conditions described in Page 118, Section 3.8.

52
2.4.5 Program branch instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
• Jumps to Pn when input conditions are
CJ CJ Pn 2
met.
Page
SCJ SCJ Pn
• Jumps to Pn from the scan after the
meeting of input condition.
2 285 4
Jump
JMP JMP Pn • Jumps unconditionally to Pn. 2

GOEND GOEND
• Jumps to END instruction when input
condition is met.
1 -
Page
288
5

6
2.4.6 Program execution control instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition 8

Disable
DI DI • Prohibits the running of an interrupt program. 1 -

2.4.5
2.4 Basic instructions
interrupts
Enable • Resets interrupt program execution
EI EI 1 -
interrupts prohibition. Page

Program branch instructions

Interrupt 289
disable/ • Inhibits or permits interrupts for each interrupt
IMASK IMASK S 2 -
enable program.
setting
• Returns to sequence program from an Page
Return IRET IRET 1 -
interrupt program. 295

2.4.7 I/O refresh instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

RFS RFS S n Page

I/O Refresh • Refreshes the relevant I/O area during scan. 3 -
RFSP 296
RFSP S n

53
2.4.8 Other convenient instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

(S)+0
Up Down Up Page
UDCNT1 UDCNT1 S D n (S)+1 4 -
Present Cn value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 -1 -2 -3 -2 -1 0 298
Up/Down Cn contact

counter (S)+0
(S)+1 Page
UDCNT2 UDCNT2 S D n 4 -
Present Cn value 0 1 2 3 4 5 4 3 2 1 0 -1 300
Cn contact

Teaching (Time that TTMR is ON) n (D) Page

TTMR TTMR D n 3 -
timer 302
n=0:1, n=1:10, n=2:100
• The 4 points from the bit device designated
by (D) operate as shown below, depending
on the ON/OFF status of the input
Special conditions for the STMR instruction: Page
STMR STMR S n D (D)+0: Off delay timer output 3 -
timer 303
(D)+1: One shot after off timer output
(D)+2: One shot after on timer output
(D)+3: On delay and off delay timer output
• Rotates a rotary table with n1 divisions
Shortest
from the stop position to the position Page
direction ROTC ROTC S n1 n2 D 5 -
designated by (S+1) in the shortest 305
control
direction.
Ramp • Changes device data designated by D1 Page
RAMP RAMP n1 n2 D1 n3 D2 6 -
signal from n1 to n2 in n3 scans. 307
• Counts the pulse input from the device
Pulse designated by (S) for the duration of time Page
SPD SPD S n D 4 -
density designated by n, and stores the count in 309
the device designated by (D).
Pulse (n1)Hz (D) Page
PLSY PLSY n1 n2 D 4 -
output Output n2 times 311

n1
Pulse width Page
PWM PWM n1 n2 D n2 4 -
modulation 312
(D)
• Reads data of 16 points n rows from the
devices starting from the one specified by Page
Matrix input MTR MTR S D1 D2 n 5 -
(S), and stores them to the devices starting 313
from the one specified by (D2).

54
2.5 Application Instructions

2.5.1 Logical operation instructions

2

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
WAND WAND S D Page
(D) (S) (D) 3
WANDP 317
WANDP S D
5
WAND WAND S1 S2 D Page
4
(S1) (S2) (D)
WANDP
*1 319
WANDP S1 S2 D
6
DAND DAND S D Page
Logical
(D+1,D) (S+1,S) (D+1,D) *2
product DANDP 317
DANDP S D

DAND DAND S1 S2 D
7
Page
(S1+1,S1) (S2+1,S2) (D+1,D) *3
DANDP 319
DANDP S1 S2 D

BKAND BKAND S1 S2 D n (S1) (S2) (D)

Page
8
5 -
BKANDP n 321
BKANDP S1 S2 D n

WOR WOR S D Page

(D) (S) (D) 3
323

2.5.1
2.5 Application Instructions
WORP WORP S D

WOR WOR S1 S2 D Page

4

Logical operation instructions

(S1) (S2) (D)
WORP
*1 325
WORP S1 S2 D

DOR DOR S D Page

Logical sum (D+1,D) (S+1,S) (D+1,D) *2
DORP 323
DORP S D

DOR DOR S1 S2 D Page

(S1+1,S1) (S2+1,S2) (D+1,D) *3
DORP 325
DORP S1 S2 D

BKOR BKOR S1 S2 D n (S1) (S2) (D)

Page
5 -
BKORP n 327
BKORP S1 S2 D n

WXOR WXOR S D Page

(D) (S) (D) 3
WXORP 329
WXORP S D

Exclusive WXOR WXOR S1 S2 D Page

4
(S1) (S2) (D)
OR WXORP
*1 331
WXORP S1 S2 D

DXOR DXOR S D Page

(D+1,D) (S+1,S) (D+1,D) *2
DXORP 329
DXORP S D

55
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

DXOR DXOR S1 S2 D Page

(S1+1,S1) (S2+1,S2) (D+1,D) *3
DXORP 331
Exclusive DXORP S1 S2 D
OR BKXOR BKXOR S1 S2 D n (S1) (S2) (D)
Page
5 -
BKXORP n 333
BKXORP S1 S2 D n

WXNR WXNR S D Page

(D) (S) (D) 3
WXNRP 335
WXNRP S D

WXNR WXNR S1 S2 D Page

4
(S1) (S2) (D)
WXNRP
*1 337
WXNRP S1 S2 D

NON DXNR DXNR S D Page

exclusive (D+1,D) (S+1,S) (D+1,D) *2
DXNRP 335
logical sum DXNRP S D

DXNR DXNR S1 S2 D Page

(S1+1,S1) (S2+1,S2) (D+1,D) *3
DXNRP 337
DXNRP S1 S2 D

BKXNR BKXNR S1 S2 D n (S1) (S2) (D)

Page
5 -
BKXNRP n 339
BKXNRP S1 S2 D n

*1: The number of basic steps is three for the Universal model QCPU and LCPU only.
*2: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
5 Note 1)
Process CPU designation is K8, and which use no indexing.
Redundant CPU • Constant: No limitations
Devices other than above 3 Note 2)
Basic model QCPU
Universal model QCPU All devices that can be used 3 Note 2)
LCPU
Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU, the number of steps increases but
the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Page 118, Section 3.8.

56
 *3: The number of steps may differ, depending on the device or CPU module to be used.
Number of
CPU module Device
Steps
• Word device: Internal device (except for file register ZR)
High Performance model QCPU • Bit device: Devices whose device Nos. are multiples of 16, whose digit
6 Note 1)
Process CPU designation is K8, and which use no indexing.
Redundant CPU • Constant: No limitations 2
Devices other than above 4 Note 2)
Basic model QCPU 4 Note 2)
Universal model QCPU All devices that can be used 3
3 Note 2)
LCPU
Note 1) When using a High Performance model QCPU, Process CPU or Redundant CPU, the number of steps increases but
the processing speed becomes faster.
Note 2) The number of steps may increase due to the conditions described in Page 118, Section 3.8.
4

2.5.2 Rotation instructions 5

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition
7

ROR ROR D n b15 (D) b0 SM700

3 8
*1
RORP RORP D n Right rotation by n bits Carry flag
Right Page
rotation 341
RCR RCR D n b15 (D) b0 SM700
3

2.5.2
2.5 Application Instructions
*1
RCRP RCRP D n Right rotation by n bits Carry flag

Rotation instructions
ROL ROL D n SM700 b15 (D) b0
3
*1
ROLP ROLP D n Carry flag Left rotation by n bits
Left Page
rotation 344
RCL RCL D n SM700 b15 (D) b0
3
*1
RCLP RCLP D n Carry flag Left rotation by n bits

DROR (D+1) (D)

DROR D n b31 to b16 b15 to b0 SM700 3
*1
DRORP DRORP D n
Right Right rotation by n bits Carry flag Page
rotation (D+1) (D) 346
DRCR DRCR D n b31 to b16 b15 to b0 SM700 3
*1
DRCRP DRCRP D n Right rotation by n bits Carry flag

57
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

DROL (D+1) (D)

DROL D n SM700 b31 to b16 b15 to b0 3
*1
DROLP DROLP D n
Left Carry flag Left rotation by n bits Page
rotation (D+1) (D) 348
DRCL DRCL D n SM700 b31 to b16 b15 to b0
3
*1
DRCLP DRCLP D n
Carry flag Left rotation by n bits
*1: For the High-speed Universal model QCPU, the number of basic steps is four.

2.5.3 Shift instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

SFR SFR D n b15 bn b0

3
Carry flag *1
SFRP SFRP D n b15 b0 SM700
n-bit shift of 0 to 0 Page
16-bit data 350
SFL SFL D n b15 bn b0
3
Carry flag *1
SFLP SFLP D n SM700 b15 b0
0 to 0

n
BSFR BSFR D n
(D)
Carry flag 3 -
BSFRP SM700
BSFRP D n
1-bit shift of 0 Page
n-bit data n 352
BSFL BSFL D n
(D)
Carry flag 3 -
BSFLP BSFLP D n SM700
0

58
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

SFTBR n1
SFTBR D n1 n2
n2 3
(D) 4 -
Carry flag
SFTBRP SFTBRP D n1 n2
SM700
n-bit shift of 0 0 Page 4
n-bit data n1 354
SFTBL SFTBL D n1 n2
n2
(D)

SFTBLP
Carry flag
4 -
5
SFTBLP D n1 n2
SM700
0 0

DSFR DSFR D n
n
(D)
6
3
1-word DSFRP DSFRP D n
shift of 0 Page 7
n-words n 357
DSFL DSFL D n
data (D)
3
DSFLP DSFLP D n
8
0

n1
SFTWR SFTWR D n1 n2 n2

(D) 4 -

2.5.3
2.5 Application Instructions
n-words SFTWRP SFTWRP D n1 n2
shift of 0 0 Page

Shift instructions
n-words n1 359
data SFTWL SFTWL D n1 n2
n2
(D)
4 -
SFTWLP SFTWLP D n1 n2
0 0
*1: For the High-speed Universal model QCPU, the number of basic steps is four.

59
2.5.4 Bit processing instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

BSET BSET D n (D)

b15 bn b0
3
BSETP BSETP D n
Bit 1 Page
set/reset (D) 362
BRST BRST D n
b15 bn b0
3
BRSTP BRSTP D n 0

TEST (S1)
TEST S1 S2 D b15 to b0 (D)
4 -
TESTP TESTP S1 S2 D
Bit designated by (S2) Page
Bit tests
(S1) 363
DTEST DTEST S1 S2 D (D)
b31 to b0
4 -
DTESTP DTESTP S1 S2 D
Bit designated by (S2)
(D) ON (D) OFF
Batch reset BKRST BKRST D n OFF OFF
Reset Page
of bit n 3 -
365
devices BKRSTP ON OFF
BKRSTP D n
ON OFF

2.5.5 Data processing instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

SER (S2)
SER S1 S2 D n (S1)
n
5 -
SERP SERP S1 S2 D n (D): Match No.
Data (D + 1): Number of matches Page
searches 32 bits 367
DSER DSER S1 S2 D n (S2)
(S1)
n 5 -
DSERP DSERP S1 S2 D n (D): Match No.
(D + 1): Number of matches

60
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
SUM SUM S D (S)
b15 b0
3 3
SUMP SUMP S D Page
(D): Number of 1s
Bit checks
369
DSUM DSUM S D (S + 1) (S)
3 4
DSUMP DSUMP S D (D): Number of 1s

DECO DECO S D n Decode from 8 to 256

Page
Decode
DECOP
(S) Decode
(D)
n
2 bits
4 -
371 5
DECOP S D n n

ENCO ENCO S D n Decode from 256 to 8

Encode
(S)
n
Encode (D) 4 -
Page
372
6
ENCOP ENCOP S D n 2 bits n

SEG SEG S D to 0
7-segment
decode
(S) (D) 3
Page
373
7
SEGP SEGP S D 7SEG

DIS • Separates 16-bit data designated by (S) into

DIS S D n Page
DISP
4-bit units, and stores at the lower 4 bits of n 4 -
375 8
DISP S D n points from (D). (n 4)

UNI UNI S D n • Links the lower 4 bits of n points from the

Page
device designated by (S) and stores at the 4 -
UNIP 376
UNIP S D n device designated by (D). (n 4)

2.5.5
2.5 Application Instructions
• Separates the data in the devices starting
NDIS NDIS S1 D S2 from the one specified by (S1) into bits
specified by the devices from (S2), and stores

Data processing instructions

NDISP NDISP S1 D S2 them to the devices starting from the one
specified by (D). Page
4 -
Separating 378
• Links the data in the devices starting from the
and linking NUNI NUNI S1 D S2
one specified by (S1) with bits specified by
the devices from (S2), and stores them to the
NUNIP NUNIP S1 D S2 devices starting from the one specified by (D).

WTOB WTOB S D n • Breaks n points of 16-bit data from the device

designated by (S) into 8-bit units, and stores
WTOBP WTOBP S D n in sequence at the device designated by (D).
Page
4 -
• Links the lower 8 bits of 16-bit data of n points 381
BTOW BTOW S D n
from the device designated by (S) into 16-bit
units, and stores in sequence at the device
BTOWP BTOWP S D n designated by (D).

61
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Searches the data of n points from the

MAX MAX S D n
device designated by (S) in 16-bit units, Page
and stores the maximum value at the 384
MAXP MAXP S D n device designated by (D).
4 -
• Searches the data of n points from the
MIN MIN S D n
device designated by (S) in 16-bit units, Page
and stores the minimum value at the 386
MINP MINP S D n device designated by (D).
Search
• Searches the data of 2n points from the
DMAX DMAX S D n
device designated by (S) in 32-bit units, Page
and stores the maximum value at the 384
DMAXP DMAXP S D n device designated by (D).
4 -
• Searches the data of 2n points from the
DMIN DMIN S D n
device designated by (S) in 32-bit units, Page
and stores the minimum value at the 386
DMINP DMINP S D n device designated by (D).

SORT S1 n S2 D1 D2
· S2: Number of comparisons to be • Sorts data of n points from device
SORT made during a single run designated by (S1) in 16-bit units.
· D1: Device to be turned ON at the (n x (n-1)/2 scans required)
completion of sort
· D2: For system use Page
Sort 6 -
388
DSORT S1 n S2 D1 D2
· S2: Number of comparisons to be • Sorts data of 2n points from device
DSORT made during a single run designated by (S1) in 32-bit units.
· D1: Device to be turned ON at the
completion of sort (n x (n-1)/2 scans required)
· D2: For system use

WSUM WSUM S D n • Adds 16 bit BIN data of n points from

Page
the device specified by (S), and stores
391
WSUMP WSUMP S D n it in the device specified by (D).
Total value
4 -
calculations
DWSUM DWSUM S D n • Adds 32 bit BIN data of n points from
Page
the device specified by (S), and stores
392
DWSUMP DWSUMP S D n it in the device specified by (D).

• Calculates the mean of n-point devices

MEAN MEAN S D n
(in 16-bit units) starting from the device
specified by (S), and then stores the
MEANP MEANP S D n
Calculation result into the device specified by (D). Page
4 -
of averages • Calculates the mean of n-point devices 393
DMEAN DMEAN S D n
(in 32-bit units) starting from the device
specified by (S), and then stores the
DMEANP DMEANP S D n result into the device specified by (D).

62
2.5.6 Structure creation instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
FOR FOR n • Executes n times between the FOR 2 - Page
NEXT and NEXT . 1 - 395
Number of NEXT
4
repeats BREAK • Forcibly ends the execution of the
BREAK D Pn Page
FOR to NEXT cycle and jumps 3 -
BREAKP 397
5
BREAKP D Pn pointer Pn.

CALL Pn
CALL • Executes subroutine program Pn when *1
CALL Pn S1 Sn input condition is met. (S1 to Sn are 2 Page

CALLP Pn
arguments sent to subroutine program. + *3 398 6
CALLP n 5) n
CALLP Pn S1 Sn

RET RET • Returns from subroutine program 1 -

Page 7
402

FCALL Pn • Performs non-execution processing of

Subroutine
FCALL
FCALL Pn S1 Sn
subroutine program Pn if input
*1
2 Page
8
program conditions have not been met. (S1 to -
+ 403
calls
FCALLP Pn Sn are arguments sent to subroutine
FCALLP n
program. n 5)
FCALLP Pn Sn S1

2.5.6
2.5 Application Instructions
ECALL Pn

ECALL ECALL Pn S1 Sn • Executes subroutine program Pn from

*2

Structure creation instructions

within designated program name when
: File name 3 Page
input condition is met. (S1 to Sn are -
+ 407
ECALLP arguments sent to subroutine program.
n
ECALLP n 5)
ECALLP Pn S1 Sn

: File name

*1: n indicates number of arguments for subroutine program.

*2: n indicates the total of the number of arguments used in the subroutine program and the number of program name steps. The
number of program name steps is calculated as "number of characters in the program/2" (decimal fraction is rounded up).
*3: The subset is effective only with the Universal model QCPU and LCPU.

63
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

EFCALL Pn

EFCALL EFCALL Pn S1toSn • Performs non-execution processing of *2

subroutine program Pn if input 3
:File name Page
conditions have not been met. (S1 to + -
411
EFCALLP Pn Sn are arguments sent to subroutine n
EFCALLP program. N 5)
Subroutine EFCALLP Pn S1toSn
program :File name
calls
• Executes subroutine program Pn when
input condition is met.
*1
• Performs non-execution processing of
2 Page
XCALL XCALL Pn S1 Sn subroutine program Pn if input -
+ 416
conditions have not been met. (S1 to
n
Sn are arguments sent to subroutine
program. N 5)
• Performs auto refresh of intelligent
function modules, link refresh, auto Page
COM COM 1 -
refresh of CPU shared memory, and 419
communications with peripherals.
Select refresh • Performs auto refresh of intelligent Page
CCOM CCOM function modules, auto refresh of CPU 1 -
424
shared memory, and communications
with peripherals after the input Page
CCOMP CCOMP 1 -
conditions are met. 421

IX IX S 2 -
• Perform indexing for individual devices Page
Device indexing ladder
used in device indexing ladder. 426
IXEND IXEND 1 -

Fixed
indexing IXDEV IXDEV • Stores indexing value used for indexing 1 -

performed between the IX and Page

IXSET S D
IXEND to the device designated by D 429
IXSET 3 -
or later.
Designates indexing value.
*1: n indicates number of arguments for subroutine program.
*2: n indicates the total of the number of arguments used in the subroutine program and the number of program name steps. The
number of program name steps is calculated as "number of characters in the program/2" (decimal fraction is rounded up).

64
2.5.7 Data table operation instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
FIFW (S) (D) Pointer Pointer + 1
FIFW S D
Page
3 -
FIFWP FIFWP S D Device at
431 4
pointer + 1
(S) Pointer Pointer - 1 (D)
FIFR FIFR S D
3 -
Page 5
432
FIFRP FIFRP S D

FPOP FPOP S D
(S) Pointer Pointer - 1 (D) 6
Data table Page
3 -
processing 434
FPOPP
7
FPOPP S D
Device at pointer + 1

FDEL (S) Pointer Pointer - 1 (D)

FDEL S D n
4 -
FDELP FDELP S D n
8
Designated by n Page
(S) (D) Pointer Pointer + 1 436
FINS FINS S D n
4 -
FINSP

2.5.7
2.5 Application Instructions
FINSP S D n Designated by n

Data table operation instructions

65
2.5.8 Buffer memory access instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

FROM FROM n1 n2 D n3 • Reads data in 16-bit units from an intelligent

5 -
FROMP function module.
FROMP n1 n2 D n3 Page
Data read
DFRO 439
DFRO n1 n2 D n3 • Reads data in 32-bit units from an intelligent
5 -
DFROP function module.
DFROP n1 n2 D n3

TO TO n1 n2 S n3 • Writes data in 16-bit units to an intelligent

5 -
TOP function module.
TOP n1 n2 S n3 Page
Data write
DTO 441
DTO n1 n2 S n3 • Writes data in 32-bit units to an intelligent
5 -
DTOP function module.
DTOP n1 n2 S n3

2.5.9 Display instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Outputs ASCII code of 8 points (16

When SM701 is OFF
PR characters) from device designated by (S) to
PR S D Page
output module.
445
When SM701 is ON • Outputs ASCII code from device designated
ASCII print PR 3 -
PR S D by (S) to 00H to output module.
• Converts comments from device designated
Page
PRC PRC S D by (S) to ASCII code and outputs to output
448
module.
Page
Reset LEDR LEDR • Resets an annunciator. 1 -
451

66
2.5.10 Debugging and failure diagnosis instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
• The CHK instruction is executed when
CHKST is executable.
CHKST CHKST • Jumps to the step following the CHK
instruction when CHKST is in a
4
non-executable status. Page
1 -
• During normal conditions SM80 : 453

Checks CHK OFF, SD80 : 0 5

CHK
Check condition • During abnormal conditions SM80 :
ON, SD80 : Failure No.

CHKCIR CHKCIR
• Starts update in ladder pattern being 6
checked by the CHK instruction. Page
1 -
• Ends update in ladder pattern being 457
CHKEND CHKEND
checked by the CHK instruction.
7

2.5.11 Character string processing instructions 8

Number of Basic Steps

See for Description

Instruction Symbol

Subset

2.5.10 Debugging and failure diagnosis instructions

2.5 Application Instructions
Execution
Category Symbol Processing Details
Condition

BINDA BINDA S D • Converts 1-word BIN value designated by (S)

to a 5-digit, decimal ASCII value, and stores 3 -
BIN BINDAP BINDAP S D it at the word device designated by (D).
Page
Decimal • Converts 2-word BIN value designated by (S) 460
DBINDA DBINDA S D
ASCII to a 10-digit, decimal ASCII value, and stores
3 -
it at word devices following the word device
DBINDAP DBINDAP S D
number designated by (D).

• Converts 1-word BIN value designated by (S)

BINHA BINHA S D
to a 4-digit, hexadecimal ASCII value, and
3 -
BIN stores it at a word device following the word
BINHAP BINHAP S D
device number designated by (D). Page
Hexadecimal • Converts 2-word BIN value designated by (S) 462
DBINHA DBINHA S D
ASCII to an 8-digit, hexadecimal ASCII value, and
3 -
stores it at word devices following the word
DBINHAP DBINHAP S D
device number designated by (D).

67
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Converts 1-word BCD value designated by

BCDDA BCDDA S D
(S) to a 4-digit, decimal ASCII value, and
3 -
BCD stores it at a word device following the word
BCDDAP BCDDAP S D
device number designated by (D). Page
Decimal • Converts 2-word BCD value designated by 465
DBCDDA DBCDDA S D
ASCII (S) to an 8-digit, decimal ASCII value, and
3 -
stores it at word devices following the word
DBCDDAP DBCDDAP S D
device number designated by (D).

• Converts a 5-digit, decimal ASCII value

DABIN DABIN S D
designated by (S) to a 1-word BIN value, and
3 -
Decimal stores it at a word device number designated
DABINP DABINP S D
ASCII by (D). Page
• Converts a 10-digit, decimal ASCII value 468
DDABIN DDABIN S D
BIN designated by (S) to a 2-word BIN value, and
3 -
stores it at a word device number designated
DDABINP DDABINP S D
by (D).

• Converts a 4-digit, hexadecimal ASCII value

HABIN HABIN S D
designated by (S) to a 1-word BIN value, and
3 -
Hexadecimal stores it at a word device number designated
HABINP HABINP S D
ASCII by (D). Page
• Converts an 8-digit, hexadecimal ASCII 470
DHABIN DHABIN S D
BIN designated by (S) value to a 2-word BIN
3 -
value, and stores it at a word device number
DHABINP DHABINP S D
designated by (D).
• Converts a 4-digit, decimal ASCII value
DABCD DABCD S D
designated by (S) to a 1-word BCD value,
3 -
Decimal and stores it at a word device number
DABCDP DABCDP S D
ASCII designated by (D). Page
• Converts a 8-digit decimal ASCII value 472
DDABCD DDABCD S D
BCD designated by (S) to a 2-word BCD value,
3 -
and stores it at the word device number
DDABCDP DDABCDP S D
designated by (D).
Device
COMRD COMRD S D
comment • Stores comment from device designated by Page
3 -
read (S) at a device designated by (D). 474
COMRDP COMRDP S D
operation
Character LEN LEN S D • Stores data length (number of characters) in
Page
string length character string designated by (S) at a 3 -
476
detection LENP LENP S D device designated by (D).

68
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
• Converts a 1-word BIN value designated by
STR STR S1 S2 D (S2) to a decimal character string with the 3
total number of digits and the number of
4 -
decimal fraction digits designated by (S1)
BIN
STRP STRP S1 S2 D and stores them at a device designated by
(D). Page 4
Decimal
• Converts a 2-word BIN value designated by 478
character
DSTR DSTR S1 S2 D (S2) to a decimal character string with the
string
total number of digits and the number of
decimal fraction digits designated by (S1)
4 - 5
DSTRP DSTRP S1 S2 D and stores them at a device designated by
(D).
• Converts a character string including decimal 6
VAL VAL S D1 D2
point designated by (S) to a
1-word BIN value and the number of 4 -
Decimal
character VALP VALP S D1 D2 decimal fraction digits, and stores them into
devices designated by (D1) and (D2). Page
7
string
• Converts a character string including decimal 482
DVAL DVAL S D1 D2
point designated by (S) to a
BIN
2-word BIN value and the number of 4 - 8
DVALP DVALP S D1 D2 decimal fraction digits, and stores them into
devices designated by (D1) and (D2).

Floating
ESTR ESTR S1 S2 D
decimal point • Converts the 32-bit floating decimal point

2.5.11 Character string processing instructions

2.5 Application Instructions
Page
data designated by (S) to a character string, 4 -
485
Character and stores it in devices designated by (D).
ESTRP ESTRP S1 S2 D
string

Character
EVAL EVAL S D
string • Converts the character string designated by
Page
(S) to a 32-bit floating decimal point data, 3 -
490
Floating and stores it in devices designated by (D).
EVALP EVALP S D
decimal point

• Converts the 1-word BIN value at the device

Hexadecimal ASC ASC S D n numbers designated by (S) to
BIN Page
hexadecimal ASCII, and stores n 4 -
494
ASCP ASCP S D n characters of them at the device numbers
ASCII
designated by (D) and after.
ASCII • Converts n hexadecimal ASCII characters of
HEX HEX S D n
the device numbers designated by (S) and Page
4 -
Hexadecimal after to BIN values, and stores them at the 496
HEXP HEXP S D n device numbers designated by (D).
BIN

69
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

RIGHT RIGHT S D n • Stores n characters from the end of a

character string designated by (S) at the
RIGHTP RIGHTP S D n device designated by (D). Page
4 -
• Stores n characters from the beginning of a 498
LEFT LEFT S D n
character string designated by (S) at the
LEFTP LEFTP S D n device designated by (D).

• Stores the designated number of characters

MIDR MIDR S1 D S2
in the character string designated by (S1)
from the position designated by (S2) at the
MIDRP MIDRP S1 D S2
device designated by (D). Page
4 -
500
Character MIDW MIDW S1 D S2 • Stores the character string of (S1) in the
string specified number to the character string of
MIDWP MIDWP S1 D S2 (D) at the position specified by (S2).

INSTR INSTR S1 S2 D n • Searches character string (S1) from the nth

Page
character of character string (S2), and stores 5 -
504
INSTRP INSTRP S1 S2 D n matched positions at (D).

STRINS • Inserts the character string data specified by

STRINS S D n
(S) to the (n)th character (insert position) Page
4 -
STRINSP from the initial character string data specified 506
STRINSP S D n
by (D).

STRDEL STRDEL D n1 n2 • Deletes the (n2) characters data specified by

Page
(D) starting from the device(insert position) 4 -
STRDELP 508
STRDELP D n1 n2 specified by n1.

Floating EMOD EMOD S1 S2 D • Converts 32-bit floating decimal point data

decimal point (S1) to BCD data with number of decimal Page
4 -
fraction digits designated by (S2) , and stores 510
BCD EMODP EMODP S1 S2 D at device designated by (D).

BCD EREXP EREXP S1 S2 D • Converts BCD data (S1) to 32-bit floating

decimal point data with the number of Page
4 -
Floating decimal fraction digits designated by (S2), 512
decimal point EREXPP EREXPP S1 S2 D and stores at device designated by (D).

70
2.5.12 Special function instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
SIN SIN S D Page
Sin (S+1,S) (D+1,D) 3 -
514
SINP SINP S D
4
COS COS S D Page
Cos(S+1,S) (D+1,D) 3 -
517
COSP COSP S D
5
TAN TAN S D
Trigonometric Page
Tan(S+1,S) (D+1,D) 3 -
functions 520
TANP
6
TANP S D
(Floating-
point single- ASIN ASIN S D Page
precision) Sin -1 (S+1,S) (D+1,D) 3 -
523
ASINP ASINP S D
7
ACOS ACOS S D Page
Cos-1(S+1,S) (D+1,D) 3 -
527
ACOSP ACOSP S D
8
ATAN ATAN S D Page
Tan-1(S+1,S) (D+1,D) 3 -
530
ATANP ATANP S D

SIND SIND S D
Sin(S+3, S+2, S+1, S) Page
3 -

2.5.12 Special function instructions

2.5 Application Instructions
(D+3, D+2, D+1, D) 515
SINDP SINDP S D

COSD COSD S D
Cos(S+3, S+2, S+1, S) Page
3 -
(D+3, D+2, D+1, D) 518
COSDP COSDP S D

TAND TAND S D
Trigonometric Tan(S+3, S+2, S+1, S) Page
3 -
functions (D+3, D+2, D+1, D) 522
TANDP TANDP S D
(Floating-
point double- ASIND ASIND S D -1 Page
Sin (S+3, S+2, S+1, S) 3 -
precision) (D+3, D+2, D+1, D) 525
ASINDP ASINDP S D

ACOSD ACOSD S D -1
Cos (S+3, S+2, S+1, S) Page
3 -
(D+3, D+2, D+1, D) 528
ACOSDP ACOSDP S D

ATAND ATAND S D -1
Tan (S+3, S+2, S+1, S) Page
3 -
(D+3, D+2, D+1, D) 532
ATANDP ATANDP S D

71
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

RAD RAD S D
(S+1, S) (D+1, D) Page
3 -
Conversion from angles to radians 533
RADP RADP S D

RADD RADD S D (S+3, S+2, S+1, S) (D+3, D+2, D+1, D) Page

Angles 3 -
Conversion from angle to radian 535
RADDP RADDP S D
Radians DEG DEG S D Page
conversion (S+1, S) (D+1, D)
3 -
Conversion from radians to angles 536
DEGP DEGP S D

DEGD DEGD S D
(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) Page
3 -
Conversion from radian to angle 537
DEGDP DEGDP S D

SQR SQR S D Page

(S+1,S) (D+1,D) 3 -
542
SQRP SQRP S D
Square root
SQRD SQRD S D Page
(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) 3 -
544
SQRDP SQRDP S D

EXP EXP S D Page

e(S+1,S) (D+1,D) 3 -
545
EXPP EXPP S D
Exponent
operations
EXPD EXPD S D Page
e(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) 3 -
547
EXPDP EXPDP S D

LOG LOG S D Page

Loge (S+1,S) (D+1,D) 3 -
549
LOGP LOGP S D
Natural
logarithms
LOGD LOGD S D Page
Loge(S+3, S+2, S+1, S) (D+3, D+2, D+1, D) 3 -
550
LOGDP LOGDP S D

POW POW S1 S2 D Page

• (S1+1,S1)
(S2+1,S2)
(D+1,D) 4 -
POWP 552
Expone POWP S1 S2 D
ntiation POWD POWD S1 S2 D Page
• (S1+3,S1+2,S1+1,S1)
(S2+3,S2+2,S2+1,S2)
(D+3,D+2,D+1,D) 4 -
POWDP POWDP S1 S2 D 553

LOG10 LOG10 S D Page

• log10(S+1,S) (D+1,D) 3 -
LOG10P 552
Common LOG10P S D
logarithm
LOG10D LOG10D S D Page
• log10(S+3,S+2S+1,S) (D+3,D+2,D+1,D) 3 -
LOG10DP 553
LOG10DP S D

72
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
Random RND RND D • Generates a random number (from 0 to less
number than 32767) and stores it at the device 3
generation RNDP RNDP D designated by (D).
Page
Random 2 -
SRND SRND D • Updates random number series according to 554
number
series
the 16-bit BIN data stored in the device 4
SRNDP SRNDP D designated by (S).
update

BSQR BSQR S D
(S) (D)+0 Integer part 3 - 5
BSQRP +1 Decimal fraction part
BSQRP S D Page
Square root
555
BDSQR BDSQR S D
(S+1, S) (D)+0 Integer part 3 - 6
BDSQRP +1 Decimal fraction part
BDSQRP S D

BSIN Sin(S)
7
BSIN S D (D)+0 Sign Page
+1 Integer part 3 -
557
BSINP BSINP S D +2 Decimal fraction part

BCOS BCOS S D Cos(S) (D)+0 Sign

+1 Integer part 3 -
Page
559
8
BCOSP BCOSP S D +2 Decimal fraction part

BTAN BTAN S D Tan(S) (D)+0 Sign Page

+1 Integer part 3 -
561
BTANP BTANP S D +2 Decimal fraction part
Trigonometric

2.5.12 Special function instructions

2.5 Application Instructions
functions Sin -1 (S)
BASIN BASIN S D (D)+0 Sign
Page
+1 Integer part 3 -
562
BASINP BASINP S D +2 Decimal fraction part

BACOS BACOS S D Cos -1 (S) (D) +0 Sign Page

+1 Integer part 3 -
564
BACOSP BACOSP S D +2 Decimal fraction part

BATAN BATAN S D Tan -1 (S) (D) +0 Sign Page

+1 Integer part 3 -
566
BATANP BATANP S D +2 Decimal fraction part

73
2.5.13 Data control instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• When (S3) (S1)

LIMIT LIMIT S1 S2 S3 D ...........Stores value of (S1) at (D)
• When (S1) (S3) (S2)
5 -
...........Stores value of (S3) at (D)
LIMITP LIMITP S1 S2 S3 D • When (S2) (S3)
Upper and ...........Stores value of (S2) at (D)
lower Page
limit • When ((S3)+1, (S3)) ((S1)+1, S1) 568
controls DLIMIT DLIMIT S1 S2 S3 D ...Stores value of ((S1)+1, (S1)) at ((D)+1, (D))
• When ((S1)+1, (S1)) ((S3)+1, (S3))
(S2+1, S2) 5 -
...Stores value of ((S3)+1, (S3)) at ((D)+1, (D))
DLIMITP DLIMITP S1 S2 S3 D • When ((S2), (S2)+1) ((S3), (S3)+1)
...Stores value of ((S2)+1, (S2)) at ((D)+1, (D))

BAND BAND S1 S2 S3 D • When (S1) (S3) (S2)...............0 (D)

• When (S3) (S1)...........(S3)-(S1) (D) 5 -
BANDP BANDP S1 S2 S3 D • When (S2) (S3)...........(S3)-(S2) (D)

• When ((S1)+1, (S1)) ((S3)+1, (S3))

Dead band DBAND Page
DBAND S1 S2 S3 D ((S2)+1, (S2))........................0 ((D)+1, (D))
controls 570
• When ((S3)+1, (S3)) ((S1)+1, (S1))...........
5 -
((S3)+1, (S3))-((S1)+1, (S1)) ((D)+1, (D))

DBANDP • When ((S2)+1, (S2)) ((S3)+1, (S3))..........

DBANDP S1 S2 S3 D
((S3)+1, (S3))-((S2)+1, (S2)) ((D)+1, (D))

ZONE ZONE S1 S2 S3 D • When (S3) 0.................................0 (D)

• When (S3) 0....................(S3)+(S2) (D) 5 -
ZONEP ZONEP S1 S2 S3 D • When (S3) 0................(S3)-(S1) (D)

• When ((S3)+1, (S3)) 0

Zone DZONE ...............................0 ((D)+1, (D)) Page
DZONE S1 S2 S3 D
controls • When ((S3)+1, (S3)) 0 573
.........................((S3)+1, (S3))+((S2)+1, (S2))
5 -
((D)+1, (D))
• When ((S3)+1, (S3)) 0
DZONEP DZONEP S1 S2 S3 D ........................((S3)+1, (S3)) + ((S1)+1, (S1))
((D)+1, (D))

74
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

• Executes scaling for the scaling conversion

SCL SCL S1 S2 D data (16-bit data units) specified by (S2) with 3
the input value specified by (S1), and then
stores the result into the device specified by 4 -
(D). The scaling conversion is executed 4
SCLP SCLP S1 S2 D based on the scaling conversion data stored
Point-by-
in the device specified by (S2) and up.
point Page
coordinate
• Executes scaling for the scaling conversion
575 5
data
DSCL DSCL S1 S2 D data (32-bit data units) specified by (S2) with
the input value specified by (S1), and then
stores the result into the device specified by
(D). The scaling conversion is executed
4 -
6
DSCLP DSCLP S1 S2 D based on the scaling conversion data stored
in the device specified by (S2) and up.
7
• Executes scaling for the scaling conversion
SCL2 SCL2 S1 S2 D data (16-bit data units) specified by (S2) with
the input value specified by (S1), and then
stores the result into the device specified by 4 -
8
(D). The scaling conversion is executed
SCL2P SCL2P S1 S2 D based on the scaling conversion data stored
X or Y in the device specified by (S2) and up.
Page
coordinate

2.5.13 Data control instructions

2.5 Application Instructions
578
data • Executes scaling for the scaling conversion
DSCL2 DSCL2 S1 S2 D data (32-bit data units) specified by (S2) with
the input value specified by (S1), and then
stores the result into the device specified by 4 -
(D). The scaling conversion is executed
DSCL2P DSCL2P S1 S2 D based on the scaling conversion data stored
in the device specified by (S2) and up.

75
2.5.14 Switching instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Block RSET RSET S • Converts extension file register block number Page
number 2 -
to number designated by (S). 581
switching RSETP RSETP S
*1
QDRSET QDRSET File name
2 Page
• Sets file names used as file registers. -
+ 582
QDRSETP QDRSETP File name
n
File set
*1
QCDSET QCDSET File name
2 Page
• Sets file names used as comment files. -
+ 584
QCDSETP QCDSETP File name
n

*1: n ([number of file name characters] / 2) indicates a step. (Decimal fractions are rounded up.)

2.5.15 Clock instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

(Clock elements) (D) +0 Year

DATERD DATERD D +1 Month
+2 Day Page
+3 Hour 2 -
587
+4 Minute
DATERDP DATERDP D +5 Sec.
Read/write +6 Day of the week
clock data (D) +0 Year (Clock elements)
DATEWR DATEWR S +1 Month
+2 Day Page
+3 Hour 2 -
+4 588
Minute
DATEWRP DATEWRP S +5 Sec.
+6 Day of the week

DATE+ DATE+ S1 S2 D (S1) (S2) (D)

Hour Hour Hour Page
4 -
Clock data Minute + Minute Minute 590
DATE+P DATE+P S1 S2 D Sec. Sec. Sec.
addition/
subtraction DATE- DATE- S1 S2 D (S1) (S2) (D)
Hour Hour Hour Page
4 -
Minute Minute Minute 592
DATE-P DATE-P S1 S2 D Sec. Sec. Sec.

76
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
SECOND SECOND S D (S) (D)
Hour
Minute
Sec. (Lower 16 bits)
Sec. (Upper 16 bits)
3 -
Page
594
3
SECONDP SECONDP S D
Clock data Sec.
translation
HOUR HOUR S D (S) (D)
Sec. (Lower 16 bits)
Sec. (Upper 16 bits)
Hour
Minute
3 -
Page
595
4
HOURP HOURP S D Sec.
LDDT= DT S1 S2 n

ANDDT= DT S1 S2 n
S1 Year S2 Year
5
Comparison
S1 +1 Month S2 +1 Month operation result 4 -
S1 +2 Day S2 +2 Day
ORDT=
DT S1 S2 n 6
LDDT<> DT S1 S2 n
S1 Year S2 Year
ANDDT<> DT S1 S2 n
S1 +1 Month S2 +1 Month
Comparison
operation result 4 - 7
S1 +2 Day S2 +2 Day
ORDT<>
DT S1 S2 n

LDDT< DT S1 S2 n 8
S1 Year S2 Year
ANDDT< DT S1 S2 n Comparison
S1 +1 Month S2 +1 Month operation result 4 -
S1 +2 Day S2 +2 Day
ORDT<
Date DT S1 S2 n
Page

2.5.15 Clock instructions

2.5 Application Instructions
comparison LDDT<= 596
DT S1 S2 n
S1 Year S2 Year
ANDDT<= DT S1 S2 n Comparison
S1 +1 Month S2 +1 Month operation result 4 -
S1 +2 Day S2 +2 Day
ORDT<=
DT S1 S2 n

LDDT> DT S1 S2 n
S1 Year S2 Year
ANDDT> DT S1 S2 n Comparison
S1 +1 Month S2 +1 Month operation result 4 -
S1 +2 Day S2 +2 Day
ORDT>
DT S1 S2 n

LDDT>= DT S1 S2 n
S1 Year S2 Year
ANDDT>= DT S1 S2 n Comparison
S1 +1 Month S2 +1 Month operation result 4 -
S1 +2 Day S2 +2 Day
ORDT>=
DT S1 S2 n

77
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

LDTM= TM S1 S2 n
S1 Hour S2 Hour
ANDTM= TM S1 S2 n Comparison
S1 +1 Minute S2 +1 Minute operation result 4 -
S1 +2 Second S2 +2 Second
ORTM=
TM S1 S2 n

LDTM<> TM S1 S2 n
S1 Hour S2 Hour
ANDTM<> TM S1 S2 n Comparison
S1 +1 Minute S2 +1 Minute operation result 4 -
S1 +2 Second S2 +2 Second
ORTM<>
TM S1 S2 n

LDTM< TM S1 S2 n
S1 Hour S2 Hour
ANDTM< TM S1 S2 n Comparison
S1 +1 Minute S2 +1 Minute operation result 4 -
S1 +2 Second S2 +2 Second
ORTM<
Clock TM S1 S2 n
Page
comparison LDTM<= 601
TM S1 S2 n
S1 Hour S2 Hour
ANDTM<= TM S1 S2 n Comparison
S1 +1 Minute S2 +1 Minute operation result 4 -
S1 +2 Second S2 +2 Second
ORTM<=
TM S1 S2 n

LDTM> TM S1 S2 n
S1 Hour S2 Hour
ANDTM> TM S1 S2 n Comparison
S1 +1 Minute S2 +1 Minute operation result 4 -
S1 +2 Second S2 +2 Second
ORTM>
TM S1 S2 n

LDTM>= TM S1 S2 n
S1 Hour S2 Hour
ANDTM>= TM S1 S2 n Comparison
S1 +1 Minute S2 +1 Minute operation result 4 -
S1 +2 Second S2 +2 Second
ORTM>=
TM S1 S2 n

78
2.5.16 Expansion clock instructions

Number of Basic Steps

See for Description

Instruction Symbol
2

Subset
Execution
Category Symbol Processing Details
Condition

3
(Clock elements) (D) +0 Year
Reading S.DATERD S.DATERD D +1 Month

4
+2 Day
data of the +3 Hour Page
+4 6 -
expansion Minute 605
+5 Sec.
clock SP.DATERD +6 Day of the week
SP.DATERD D
+7 1/1000 sec.
5
(S1) (S2) (D)
S.DATE+ S.DATE+ S1 S2 D Hour Hour Hour
Minute Minute Minute Page
Adding or
subtracting SP.DATE+
Sec. + Sec. Sec. 8 -
607 6
SP.DATE+ S1 S2 D 1/1000 sec. 1/1000 sec. 1/1000 sec.
data values
of the
7
(S1) (S2) (D)
expansion S.DATE- S.DATE S1 S2 D Hour Hour Hour
Minute Minute Minute Page
clock Sec. Sec. Sec. 8 -
610
SP.DATE- SP.DATE S1 S2 D 1/1000 sec. 1/1000 sec. 1/1000 sec.
8

2.5.16 Expansion clock instructions

2.5 Application Instructions

79
2.5.17 Program control instructions

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

*1
PSTOP PSTOP File name
• Places designated program in standby 2 Page
-
status. + 614
PSTOPP PSTOPP File name
n
*1
POFF POFF File name • Turns OUT instruction coil of
2 Page
designated program OFF, and places -
+ 615
POFFP POFFP File name program in standby status.
n
*1
PSCAN PSCAN File name
• Registers designated program as scan 2 Page
Program -
execution type. + 616
control PSCANP PSCANP File name
n
instructions *1
PLOW PLOW File name
• Registers designated program as 2 Page
-
low-speed execution type. + 617
PLOWP PLOWP File name
n

LDPCHK PCHK File name

• In conduction when program of *1
ANDPCHK PCHK File name specified file name is being executed. 2 Page
-
• In non-conduction when program of + 619
ORPCHK specified file name is not executed. n
PCHK File name

*1: n ([number of file name characters] / 2) indicates a step. (Decimal fractions are rounded up.)

2.5.18 Other instructions Number of Basic Steps

See for Description

Instruction Symbol

Subset

Execution
Category Symbol Processing Details
Condition

WDT WDT
WDT • Resets watchdog timer during Page
1 -
reset sequence program. 621
WDTP WDTP

Timing (D) Page

DUTY DUTY n1 n2 D n1 scans n2 scans 4 -
clock 622
SM420 to SM424, SM430 to SM434
• Turns ON device specified by (D) if
measured ON time of input condition Page
Time check TIMCHK TIMCHK S1 S2 D 4 -
is longer than preset time 623
continuously.

80
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2
ZRRDB ZRRDB n D 0 Lower 8 bits ZR0
1
2
Upper 8 bits
Lower 8 bits ZR1 3 -
Page 3
3 Upper 8 bits 624
ZRRDBP ZRRDBP n D
n 8 bits (D)

Direct read/write ZRWRB ZRWRB n S (S) 0 Lower 8 bits

ZR0
4
1 Upper 8 bits
operations in 1- Page
2 Lower 8 bits 3 -
3 ZR1 625
byte units ZRWRBP Upper 8 bits
ZRWRBP n S
n 8 bits 5
ADRSET ADRSET S D (S) (D)
Indirect address of Page
3 -
627
6
designated device
ADRSETP ADRSETP S D
Device name
• Takes in ASCII data for 8 points of
Numerical key input unit designated by (S), converts
Page
input from KEY KEY S n D1 D2 to hexadecimal value following device 5 -
628
7
keyboard number designated by (D1), and
stores.

Batch save of
ZPUSH ZPUSH D • Saves the contents of index registers
to a location starting from the device
8
index register
ZPUSHP ZPUSHP D designated by (D). Page
2 -
• Reads the data stored in the location 632
ZPOP ZPOP D
Batch recovery of
starting from the device designated
index register
ZPOPP ZPOPP D by (D) to index registers.

2.5.18 Other instructions

2.5 Application Instructions
• Reads the module information stored
UNIRD UNIRD n1 D n2 in the area starting from the I/O No.
Reading module designated by (n) by the points Page
4 -
information designated by (n2), and stores it in 634
UNIRDP UNIRDP n1 D n2 the area starting from the device
designated by (D).
• Reads the module model name of the
TYPERD TYPERD n D
Module model head I/O No. designated by (n) and Page
3 -
name read stores it in the area starting from the 638
TYPERDP TYPERDP n D
device designated by (D).
• Stores the trace data set with
peripheral device by the number of
Trace set TRACE TRACE times set when SM800, SM801 and 1 -
Page
SM802 turn on, to the sampling trace
643
file.
• Resets the data set the TRACE
Trace reset TRACER TRACER 1 -
instruction.
Writing data to
Page
the designated SP.FWRITE SP.FWRITE U0 S0 D0 S1 S2 D1 • Writes data to the designated file. 11 -
644
file
Reading data
Page
from designated SP.FREAD SP.FREAD U0 S0 D0 S1 S2 D1 • Reads data from the designated file. 11 -
654
file
Writing data to • Writes data to the device data storage Page
S.DEVST SP.DEVST n1 S n2 D 9 -
standard ROM file in the standard ROM. 665

81
 Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

Reading data S.DEVLD S.DEVLD n1 D n2 • Reads data from the device data Page
from standard 8 -
SP.DEVLD storage file in the standard ROM. 667
ROM SP.DEVLD n1 D n2
• Transfers the program stored in a
Loading program memory card or standard memory Page
PLOADP PLOADP S D 3 -
from memory (other than drive 0) to drive 0 and 668
places the program in standby status.
Unloading
• Deletes the standby program stored Page
program from PUNLOADP PUNLOADP S D 3 -
in standard memory (drive 0). 671
program memory
• Deletes standby program stored in
standard memory (drive 0)
Load designated by (S1). Then, transfers
Page
+ PSWAPP PSWAPP S1 S2 D the program stored in a memory card 4 -
673
Unload or standard memory (other than drive
0) designated by (S2) to drive 0 and
places it in standby status.

• Transfers n points of 16-bit data from

High-speed block RBMOV RBMOV S D n
the device designated by (S) to the Page
transfer of file 4 -
devices of n points starting from the 675
register RBMOVP RBMOVP S D n one designated by (D).

• Displays the specified character

Page
User message UMSG UMSG S strings on the display unit as a user 2 -
680
message.

82
2.6 Instructions for Data Link

2.6.1 Instructions for Network refresh

2

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
S.ZCOM S.ZCOM Jn
Link
instruction:
SP.ZCOM SP.ZCOM Jn
Refreshes the designated network. 5 -
Page 5
Network 683
S.ZCOM S.ZCOM Un
refresh
SP.ZCOM SP.ZCOM Un
6

2.6.2 Instructions for Reading/Writing Routing Information 7

Number of Basic Steps

8

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

2.6.1
2.6 Instructions for Data Link
Reading S.RTREAD S.RTREAD n D Page

Instructions for Network refresh

routing Reads data set at routing parameters. 7 -
SP.RTREAD 687
information SP.RTREAD n D

Registering S.RTWRITE S.RTWRITE n S Writes routing information to the area Page

routing 8 -
SP.RTWRITE designated by routing parameters. 688
information SP.RTWRITE n S

83
2.6.3 Refresh device write/read instruction

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

S.REFDVWRB S.REFDVWRB n1 S1 S2 n2 D1
Writes data in 1-bit units to the Page
11 -
specified refresh device. 690
Refresh SP.REFDVWRB SP.REFDVWRB n1 S1 S2 n2 D1
device write
instruction S.REFDVWRW S.REFDVWRW n1 S1 S2 n2 D1
Writes data in 16-bit units to the Page
11 -
specified refresh device. 694
SP.REFDVWRW SP.REFDVWRW n1 S1 S2 n2 D1

S.REFDVRDB S.REFDVRDB n1 S1 D1 n2 D2
Reads data in 1-bit units from the Page
11 -
specified refresh device. 698
Refresh SP.REFDVRDB SP.REFDVRDB n1 S1 D1 n2 D2
device read
instruction S.REFDVRDW S.REFDVRDW n1 S1 D1 n2 D2
Reads data in 16-bit units from the Page
11 -
specified refresh device. 702
SP.REFDVRDW SP.REFDVRDW n1 S1 D1 n2 D2

84
2.7 Multiple CPU dedicated instruction

2.7.1 Instructions for Writing to the CPU Shared Memory of Host CPU
2

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

4
S. TO S.TO n1 n2 n3 n4 D • Writes device data of the host station to the Page
5 -
host CPU shared memory. 707
SP. TO SP.TO n1 n2 n3 n4 D
5
Write to host TO TO n1 n2 S n3 • Writes device data of the host station to the
CPU shared 5 -
host CPU shared memory.
memory TOP n1 n2 S n3
6
TOP Page
710
DTO DTO n1 n2 S n3 • Writes device data of the host station to the
5 -
host CPU shared memory in 32-bit units.
DTOP DTOP n1 n2 S n3
7

2.7.2 Instructions for Reading from the CPU Shared Memory of Another 8
CPU

Number of Basic Steps

See for Description

Instruction Symbol

2.7.1
2.7 Multiple CPU dedicated instruction
Subset
Execution
Category Symbol Processing Details
Condition

Instructions for Writing to the CPU Shared Memory of Host CPU

FROM FROM n1 n2 D n3 • Reads device data from the other CPU
Read from shared memories, and stores the data in 5 -
FROMP FROMP n1 n2 D n3 the host station.
other CPU Page
shared • Reads device data from the other CPU 715
DFRO DFRO n1 n2 D n3
memory shared memories in 32-bit units, and 5 -
DFROP DFROP n1 n2 D n3 stores the data in the host station.

85
2.8 Multiple CPU high-speed transmission dedicated instruction

2.8.1 Instructions for Multiple CPU high-speed transmission

Number of Basic Steps

See for Description

Instruction Symbol

Subset
Execution
Category Symbol Processing Details
Condition

In multiple CPU system, data stored in a

Writing D.DDWR D.DDWR n S1 S2 D1 D2 10 -
device specified by host CPU ( S2 ) or later is
Devices to Page
stored by the number of write points specified
Another 730
DP.DDWR by ( D2 +1) into a device specified by another 10 -
CPU DP.DDWR n S1 S2 D1 D2
CPU (n) ( D1 ) or later

Reading In multiple CPU system, data stored in a

D.DDRD D.DDRD n S1 S2 D1 D2 10 -
Devices device specified by another CPU (n) ( D1 ) or
Page
from lrater is stored by the number of read points
733
Another specified by ( S1 +1) into a device specified by
DP.DDRD DP.DDRD n S1 S2 D1 D2 10 -
CPU host CPU ( S2 ) or late

2.9 Redundant system instructions (For Redundant CPU)

2.9.1 Instructions for Redundant system (For Redundant CPU)

Number of Basic Steps

See for Description

Instruction Symbol

Execution Subset
Category Symbol Processing Details
Condition

Switches between the control system and

System SP.CONT standby system at the END processing of the Page
SP.CONTSW S D 8 -
switching SW scan executed with the SP.CONTSW 737
instruction.

86
CHAPTER 3 CONFIGURATION OF INSTRUCTIONS

3.1 Configuration of Instructions

2
Most CPU module instructions consist of an instruction part and a device part.
Each part is used for the following purpose:
• Instruction part......indicates the function of the instruction. 3
• Device part...........indicates the data that is to be used with the instruction.
The device part is classified into source data, destination data, and number of devices.
(1) Source (S) 4
(a) Source is the data used for operations.
(b) The following source types are available, depending on the designated device:
• Constant...............................................Designates a numeric value to be used in the operation.
5
This is set when the program is created, and cannot be changed during
the execution of the program.
Constants should be indexed when used as variable data.
6
• Bit devices and word devices...............Designates the device that stores the data to be used in the operation.
Data must be stored in the designated device until the operation is
executed. 7
By changing the data stored in a designated device during program
execution, the data to be used in the instruction can be changed.
(2) Destination (D)
8
(a) The destination stores the data after the operation has been conducted. However, some instructions require storing
the data to be used in an operation at the destination prior to the operation execution.
Example An addition instruction involving BIN 16-bit data

3.1
+ S D + S1 S2 D

Configuration of Instructions
Stores the data needed for operation Stores only the
before the actual operation. operation results.

(b) A device for the data storage must always be set to the destination.
(3) Number of devices and number of transfers (n)
(a) The number of devices and number of transfers designate the numbers of devices and transfers used by
instructions involving multiple devices.
Example Block transfer instruction

BMOV S D n

Designates the number of transfers

used by a BMOV instruction
(b) The number of devices or number of transfers can be set between 0 and 32767.
However, if the number is 0, the instruction will be a no-operation instruction.

87
3.2 Designating Data

The following six types of data can be used with CPU module instructions.

Data that can be handled by Bit data ...Page 88, Section 3.2.1
CPU module
Numeric data Integer data Word data ...Page 89, Section 3.2.2

Double-word data ...Page 90, Section 3.2.3

Real number
(floating point) data Single-precision ...Page 93,
floating point data
Section 3.2.4 (1)

Double-precision ...Page 94,

floating point data
Character string data ...Page 97, Section 3.2.4 (2)
Section 3.2.5

3.2.1 Using bit data

Bit data is data used in one-bit units, such as for contacts or coils.
"Bit devices" and "Bit designated word devices" can be used as bit data.
(1) When using bit devices
Bit devices are designated in one-point units.
Designation of 1 point
of bit device M0

M0
SET Y10

Designation of 1 point
of bit device Y10
(2) Using word devices
(a) Word devices enable the use of a designated bit number 1/0 as bit data by the designation of that bit number.
b15 to b0
Word device 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0

Each bit of a word device can be

used (1=ON, 0=OFF)

(b) Word device bit designation is done by designating " Word device . Bit No. ".
(Designation of bit numbers is done in hexadecimal.)
For example, bit 5 (b5) of D0 is designated as D0.5, and bit 10 (b10) of D0 is designated as D0.A. However, there
can be no bit designation for timers (T), retentive timers (ST), counters (C) or index register (Z). (Example Z0.0 is
not available).
Bit designated for word device
X0 (Bit 5 (b5) of D0 is turned ON if X0 is ON.)
SET D0.5

Bit designated for word device

(Turns ON Y10 if bit 5 (b5) of D0 is ON (1).)
D0.5
SET Y10

88
3.2.2 Using word (16 bits) data

Word data is 16-bit numeric data used by basic instructions and application instructions.
The following two types of word data can be used with CPU module:
• Decimal constants...............K-32768 to K32767
• Hexadecimal constants.......H0000 to HFFFF
2
Word devices and bit devices designated by digit can be used as word data.
For direct access input (DX) and direct access output (DY), word data cannot be designated by digit. (For details of direct 3
access input and direct access output, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).
(1) When Using Bit Devices
4
(a) Bit devices can deal with word data when digits are designated.

Digit designation of bit devices is done by designating " Number of digits Head number of bit device ".
Digit designation of bit devices can be done in 4-point (4-bit) units, and designation can be made for K1 to K4. 5
(For link direct devices, designation is done by "J Network No. \ Number of digits

Head number of bit device ". 6

When X100 to X10F are designated for Network No.2, it is done by J2\K4X100).
For example, if X0 is designated for digit designation, the following points would be designated:
• K1X0.........The 4 points X0 to X3 are designated. 7
• K2X0.........The 8 points X0 to X7 are designated.
• K3X0.........The 12 points X0 to XB are designated.
• K4X0.........The 16 points X0 to XF are designated. 8
XF to XC XB to X8 X7 to X4 X3 to X0

K1 designation
range

3.2.2
3.2 Designating Data
(4 points)
K2 designation range

Using word (16 bits) data

(8 points)
K3 designation range
(12 points)
K4 designation range
(16 points)
Fig 3.1 Digit Designation Setting Range for 16-Bit Instruction

(b) In cases where digit designation has been made at the source (S), the numeric values shown in the following Table
are those which can be dealt with as source data.
Number of Digits Designated With 16-Bit Instruction
K1 (4 points) 0 to 15
K2 (8 points) 0 to 255
K3 (12 points) 0 to 4095
K4 (16 points) -32768 to 32767

(c) When destination (D) data is a word device

The word device for the destination becomes 0 following the bit designated by digit designation at the source.
Ladder Example Processing
With 16-Bit Instruction K1X0 X3 X2 X1 X0
X010
MOV K1X0 D0 Filled with 0s
b15 b4 b3 b2 b1 b0
Source (S) data D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0

Fig 3.2 Ladder Example and Processing Conducted

89
 (d) In cases where digit designation is made at the destination (D), the number of points designated are used as the
destination.
Bit devices below the number of points designated as digits do not change.
Ladder Example Processing
When source (S) data is a numerical value 1 2 3 4

H1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
X010
MOV H1234 K2M0
M15 M8 M7 M0
Destination (D) K2M0 0 0 1 1 0 1 0 0

Not changed 3 4
When source (S) data is a word device b15 b8 b7 b0
D0 1 1 1 0 1 0 1 0 1 0 0 1 1 1 0 1
X10
MOV D0 K2M100
M115 M108 M107 M100
K2M100 1 0 0 1 1 1 0 1
Destination (D)
Not changed

Fig 3.3 Ladder Example and Processing Conducted

(2) Using word devices
Word devices are designated in 1-point (16 bits) units.
M0
MOV K100 D0

Designation of 1 point of word

device D0 (16 bits)

1. When digit designation processing is conducted, a random value can be used for the bit device initial device number.
2. Digit designation cannot be made for the direct access I/O (DX, DY).

3.2.3 Using double word data (32 bits)

Double word data is 32-bit numerical data used by basic instructions and application instructions.
The two types of double word data that can be dealt with by CPU module are as follows:
• Decimal constants.............K-2147483648 to K2147483647
• Hexadecimal constants.....H00000000 to HFFFFFFFF
Word devices and bit devices designated by digit designation can be used as double word data.
For direct access input (DX) and direct access output (DY), designation of double word data is not possible by digit
designation.

90
(1) When Using Bit Devices
(a) Digit designation can be used to enable a bit device to deal with double word data.
Digit designation of bit devices is done by designating

" Number of digits Head number of bit device ". For link direct devices, designation is done by

"J Network No. \ Number of digits Head number of bit device ". When X100 to X11F are
designated for Network No.2, it is done by J2\K8X100. Digit designation of bit devices can be done in 4-point (4-bit)
2
units, and designation can be made for K1 to K8. For example, if X0 is designated for digit designation, the following
points would be designated:
• K1X0.......The 4 points X0 to X3 are designated. • K5X0.......The 20 points X0 to X13 are designated.
3
• K2X0.......The 8 points X0 to X7 are designated. • K6X0.......The 24 points X0 to X17 are designated.
• K3X0.......The 12 points X0 to XB are designated. • K7X0.......The 28 points X0 to X1B are designated.
• K4X0.......The 16 points X0 to XF are designated. • K8X0.......The 32 points X0 to X1F are designated. 4
X1F X1C X1B X18 X17 X14 X13 X10 XF XC XB X8 X7 X4 X3 X0
5
K1
designation
range
(4 points)
K2 designation
range
6
(8 points)
K3 designation range
(12 points) 7
K4 designation range
(16 points)
K5 designation range
(20 points) 8
K6 designation range
(24 points)
K7 designation range
(28 points)
K8 designation range

3.2.3
3.2 Designating Data
(32 points)
Fig 3.4 Digit Designation Setting Range for 32-Bit Instructions
(b) In cases where digit designation has been made at the source (S) , the numeric values shown in the following Table

Using double word data (32 bits)

are those which can be dealt with as source data.
Number of Digits Designated With 32 Bit Instructions Number of Digits Designated With 32 Bit Instructions
K1 (4 points) 0 to 15 K5 (20 points) 0 to 1048575
K2 (8 points) 0 to 255 K6 (24 points) 0 to 16777215
K3 (12 points) 0 to 4095 K7 (28 points) 0 to 268435455
K4 (16 points) 0 to 65535 K8 (32 points) -2147483648 to 2147483647

(c) When destination (D) data is a word device

The word device for the destination becomes 0 following the bit designated by digit designation at the source.
Ladder Example Processing
With 32 bit Instructions K1X0 X3 X2 X1 X0

Filled with 0s
X10
b15 b4 b3 b2 b1 b0
DMOV K1X0 D0
D0 0 0 0 0 0 0 0 0 0 0 0 0 X3 X2 X1 X0
D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Source (S) data b31 b16

Filled with 0s

Fig 3.5 Ladder Example and Processing Conducted

91
 (d) In cases where digit designation is made at the destination (D), the number of points designated are used as the
destination. Bit devices below the number of points designated as digits do not change.
Ladder Example Processing
When source (S) data is a numerical value
H78123456
0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0

3 4 5 6
0 1 1 1 1 0 0 0 0 0 0 1 0 0 1 0
X10
DMOV H78123456 K5M0 7 8 1 2
K5M0
M15 M8 M7 M0
Destination (D) 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0
M31 M20 M19 M16
0 0 1 0

Not changed
When source (S) data is a word device b15 b8 b7 b0
D0 1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1
b15 b8 b7 b0
D1 0 0 1 1 0 1 0 0 1 0 0 1 0 1 1 1
X10
DMOV D0 K5M10
M25 M18 M17 M10
1 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1
Destination (D)
M41 M30M29 M26
0 1 1 1

Not changed

Fig 3.6 Ladder Example and Processing Conducted

1. When digit designation processing is conducted, a random value can be used for the bit device initial device number.
2. Digit designation cannot be made for the direct access I/O (DX, DY).

(2) Using word devices

A word device designates devices used by the lower 16 bits of data. A 32-bit instruction uses (designation device
number) and (designation device number + 1).
M0
DMOV K100 D0

Designation of 2 points of
word devices D0 and D1 (32 bits)
32-bit data transfer instruction

92
3.2.4 Using single/double-precision real number data

Real number data is floating decimal point data used with basic instructions and application instructions.
Only word devices are capable of storing real number data.
(1) Single-precision real number data (single-precision floating-point data)
Instructions which deal with single-precision floating-point data designate devices which are used for the lower 16 bits of
2
data.
Single-precision floating-point data are stored in the 32 bits which make up (designated device number) and (designated
device number + 1).
3
M0
EMOV R100 D0
4
Designation of 2 points of word devices D0 and D1
(32 bits)
Designation of 2 points of R100 and R101 (32 bits) 5
Single-precision floating-point data transfer instruction

Remark 6
(1) In a sequence program, floating-point data are designated by E .
(2) Single-precision floating-point data can be represented as follows, using two word devices.
[Sign] 1. [Mantissa] 2[Exponent] 7
The bit configuration and meaning for the internal representation of single-precision floating-point data are described
below:

8
b31 b30 to b23 b22 to b16 b15 to b0

b31 b23 to b30 b0 to b22

Sign Exponent Mantissa
• Sign: The most significant bit, b31, is the sign bit.

3.2.4
3.2 Designating Data
0: Positive
1: Negative
• Exponent: The 8 bits, b23 to b30, represent the excess n of 2n.

Using single/double-precision real number data

The following shows the excess n according to the binary values in b23 to b30.

b23 to b30 FFH FEH FDH 81 80 7FH 7EH 02 01 00

n Not used 127 126 2 1 0 -1 -125 -126 Not used

• Mantissa: Each of the 23 bits, b0 to b22, represents the "XXXXXX..." portion when the data is represented in
binary, "1.XXXXXX...".

93
(2) Double-precision real number data (double-precision floating-point data)
Instructions which deal with double-precision floating-point datadesignate devices which are used for the lower 16 bits of
data.
Double-precision floating-point data are stored in the 64 bits which make up (designated device number) to (designated
device number + 3).

M0
EDMOV R100 D0

Designation of 4 points of word devices D0, D1, D2

and D3 (64 bits)
Designation of 4 points of R100, R101, R102 and
R103 (64 bits)
Double-precision floating-point data transfer
instruction

Remark
(1) In a sequence program, floating-point data are designated by E .
(2) Double-precision floating-point data can be represented as follows, using four word devices.
[Sign] 1. [Mantissa] 2[Exponent]
The bit configuration and meaning for the internal representation of double-precision floating-point data are described
below:

b63 b62 to b52 b51 to b16 b15 to b0

b63 b52 to b62 b0 to 51

Sign Exponent Mantissa
• Sign: The most significant bit, b63, is the sign bit.
0: Positive
1: Negative
Exponent: The 11 bits, b52 to b62, represent the excess n of 2n.
The following shows the excess n according to the binary values in b52 to b62.

b52 to b62 7FFH 7FEH 7FDH 400H 3FFH 3FEH 3FDH 3FCH 02H 01H 00H

n Not used 1023 1022 1 0 -1 -2 -3 -1021 -1022 Not used

• Mantissa: Each of the 52 bits, b0 to b51, represents the "XXXXXX..." portion when the data is represented in
binary, "1.XXXXXX...".

94
(3) Precautions when an input value of a single/double-precision real number is set using a programming tool
(a) Single-precision real number
Because single-precision real number data are processed as the 32-bit single-precision in a programming tool, the
number of significant digits becomes approximately 7. An input value of the single-precision real number data
exceeds 7 digits, 8th digit is rounded.
If the value after rounding exceeds the range of -2147483648 to 2147483647, an operation error occurs. 2
Example 1: When '2147483647' is set for the input value

3
8th digit '6' is rounded.
The value is handled as '2147484000'.

Example 2: When 'E1.1754943562' is set for the input value

4

8th digit '3' is rounded. 5

The value is handled as 'E1.175494'.
(b) Double-precision real number
Because double-precision real number data are processed as the 64-bit double-precision in a programming tool,
6
the number of significant digits becomes approximately 15. An input value of the double-precision real number data
exceeds 15 digits, 16th digit is rounded.
If the value after rounding exceeds the range of -2147483648 to 2147483647, an operation error occurs.
7
Example 1: When '2147483646.12345678' is set for the input value

8
16th digit '6' is rounded.
The value is handled as '2147483646.12346'.

Example 2: When 'E1.7976931348623157+307' is set for the input value

3.2.4
3.2 Designating Data
Using single/double-precision real number data
16th digit '5' is rounded.
The value is handled as 'E1.79769313486232+307'.

95
 1. The CPU module floating decimal point data can be monitored using the monitoring function of a peripheral device.
2. When floating-point data is used to express 0, all data in the following range are turned to 0.
(a) Single-precision floating-point data: b0 to b31
(b) Double-precision floating-point data: b0 to b63
3. The setting range of floating decimal point data is as follows. *1
(a) Single-precision floating-point data
-2128 < Device data -2-126, 0, 2-126 Device data < 2128
(b) Double-precision floating-point data
-21024 < Device data -2-1022,0,2-1022 Device data < 21024
4. Do not specify -0 in floating-point data (only when the most significant bit of the floating-point real number is 1). (An
operation error will occur if floating-point operation is performed with -0.)
When -0 is specified, the following CPU module internally converts the value to 0 to perform a floating-point operation.
Therefore an operation error does not occur.
• The High Performance model QCPU with the internal processing set to "double precision". *2(Double
precision is set by default for the floating-point operation processing.)
When -0 is specified, the following CPU module performs a floating-point operation with -0, keeping its processing speed.
Therefore an operation error occurs.
• Basic model QCPU *3
• High Performance model QCPU where internal operation is set to single precision *2
• Process CPU
• Redundant CPU
• Universal model QCPU
• LCPU

*1: For operations when a real number is out of range and operations when an invalid value is input, refer to the QnUCPU User's
Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation,
Program Fundamentals).
*2: Switch between single precision and double precision of the internal operation of floating-point operation in the PLC system of
the PLC parameter dialog box. For the single precision and double precision of floating-point operation, refer to the QnUCPU
User's Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function
Explanation, Program Fundamentals).
*3: The Basic model QCPU can perform floating-point operation if its first five digits of serial No. are "04122 or later".

96
3.2.5 Using character string data

Character string data is character data used by basic instructions and application instructions.
The target ranges from the designated character to the NULL code (00H) that indicates the end of the character string.

(1) When designated character is the NULL code 2

One word is used to store the NULL code.

3
M0
$MOV " " D0

D0 NULL
4
Designation of NULL code (00H)
Character string data transfer instruction

(2) When character string is even 5

Uses (number of characters/2 + 1) words, and stores character string and NULL code.
For example, if "ABCD" is transferred to D0, the character string ABCD is stored at D0 and D1, and the NULL code is
stored at D2. (The NULL code is stored as the last one word.)
6
M0
$MOV "ABCD" D0
7
D0 42H 41H
D1 44H 43H 8
D2 NULL

Designation of a character string

composed of even numbers
Character string data transfer instruction

3.2.5
3.2 Designating Data
(3) When number of characters is odd

Uses (number of characters/2) words (rounds up decimal fractions) and stores the character string and NULL code.

Using character string data

For example, if "ABCDE" is transferred to devices starting from D0, the character string (ABCDE) and the NULL code are
stored from D0 to D2. (The NULL code is stored into the upper 8 bits of the last one word.)
M0
$MOV "ABCDE" D0

D0 42H 41H
D1 44H 43H
D2 NULL 45H

Designation of a character string

composed of odd numbers
Character string data transfer instruction

97
3.3 Indexing

(1) Overview of indexing

(a) Indexing is an indirect setting made by using an index register.
When an Indexing is used in a sequence program, the device to be used will become the device number specified
directly plus the contents of the index register.
For example, if D2Z2 has been specified, the specified device is calculated as follows: D(2+3) = D5 and the content
of Z2 is 3 become the specified device.
(b) Indexing with 32-bit index registers in addition to 16-bit index registers is available with the Universal model QCPU
and LCPU.
(2) Indexing with 16-bit index registers
(a) Example of indexing
Each index register can be set between -32768 and 32767.*1
Indexing is performed in the way shown below:
X0
MOV K 1 Z0 Stores -1 at Z0.

X0
Stores the data of D10Z0=
MOV D10Z0 D0 D{10+(-1)} = D9 at D0.

Indexing
*1: For the specifications of index registers, refer to the User's Manual (Function Explanation, Program Fundamentals) for the
CPU module used.

(b) Devices to which indexing can be used

With the exception of the restrictions noted below, Indexing can be used with devices used with contacts, coils,
basic instructions, and application instructions.
1) Devices to which indexing can not be used
Device Meaning
E Floating decimal point data
$ Character string data
. Bit designated for word device
FX, FY, FD Function devices
P Pointers used as labels
I Interrupt pointers used as labels
Z Index register
S Step relay*2
TR SFC transfer devices*1
BL SFC block devices*1 *2
*1: SFC transfer devices and SFC block devices are devices for SFC use.
Refer to the manual below for how to use these devices.
• MELSEC-Q / L / QnA Programming Manual (SFC)
*2: For the High-speed Universal model QCPU, the SFC block (BL) and step relay (S) can be modified using indices within the
following range.
• For the SFC block (BL), the range is BL0 to BL319.
• For the step relay (S), the range is specified in the device settings using parameters.

Note that if a step relay (S) in the SFC block is specified, index modification can be specified within the range of S0 to S511.

98
 2) Devices with limits for use with index registers*1
Device Meaning Application Example
T0Z0 K100
• Only Z0 and Z1 can be used for timer
T T1Z1
contacts and coils.

• Only Z0 and Z1 can be used for

C0Z1 K100 2
C C1Z0
counter contacts and coils.

*1: For the QnUDVCPU, there is no restriction.

3
Remark
For timer and counter present values, there are no limits on index register numbers used. 4
Value set for timer
X0 K100
T0
5
Present value of timer
SM400
BCD T0Z4 K4Y30
Value set for counter 6
X1 K10
C100

SM400
Present value of counter 7
BCD C100Z6 K2Y40

(c) A case where Indexing has been performed, and the actual process device, would be as follows:
(When Z0 20 and Z1 -5)

3.3
Ladder Example Actual Process Device
X0

Indexing
MOV K20 Z0 X1
MOV K2X64 K1M33

Description
MOV K 5 Z1 K2X(50 + 14) = K2X64
K2X50Z0

X1 Converts K20 into a hexadecimal number.

MOV K2X50Z0 K1M38Z1 K1M38Z1 K1M(38 - 5) = K1M33

X0
MOV K20 Z0 X1
MOV D20 K3Y12A

Description
MOV K 5 Z1
D0Z0 D (0 + 20) = D20
K3Y12FZ1 K3Y(12F - 5) = K3Y12A
X1
MOV D0Z0 K3Y12FZ1 Hexadecimal number

Fig. 3.7 Ladder Example and Actual Process Device

99
(3) Indexing with 32-bit (Universal model QCPU (excluding Q00UJCPU) and LCPU)
A method of specifying index registers in indexing with 32-bit can be selected from the following two methods.
• Specifying the index registers' range used for indexing with 32-bit.
• Specifying the 32-bit indexing using "ZZ" specification.

32-bit indexing with the "ZZ" specification is only available for the following CPU modules. See the programming tool
operating manual for the available programming tools.
• The first five digits of the serial No. for QnU(D)(H)CPU is “10042” or higher. (excluding Q00UJCPU)
• Built-in Ethernet port QCPU
• LCPU

(a) Example of specifying the range of index registers for use of 32-bit indexing.
1) Each index register can be set between -2147483648 and 2147483647.
An example of indexing is shown below.
X0
DMOV K40000 Z0 Stores 40000 at Z0.

X0
MOV ZR10Z0 D0 Stores the data of ZR10Z0=
ZR{10+40000}=ZR40010 at D0.

Indexing

2) Specification method
For indexing with a 32-bit index register, specify the head number of an index register to be used on the Device
tab of the Q parameter setting screen.

GX Developer 8.68R or earlier GX Developer 8.68W or later

Fig. 3.8 Setting windows for ZR device indexing setting parameter

When the head number of the index register used is changed on the Device tab of the Q parameter setting screen, do not
change the parameters only or do not write only the parameters into the programmable controller. Be sure to write the
parameter into the programmable controller with the program.
When the parameter is forced to be written into the programmable controller, an error of CAN'T EXE. PRG. occurs. (Error
code: 2500)

3) Device that indexing can be used

Indexing can be used only for the device shown below.
Device Meaning
ZR Serial number access format file register
D Extended data register (D)
W Extended link register (W)

100
 4) Usable range of index registers
The following table shows the usable range of index registers for indexing with 32-bit index registers.
For indexing with 32-bit index registers, the specified index register (Zn) and the next index register of the
specified register (Zn+1) are used. Be sure not to overlap index registers to be used.
Setting Value Index Registers to be Used Setting Value Index Registers to be Used
Z0 Z0, Z1 Z10 Z10, Z11 2
Z1 Z1, Z2 Z11 Z11, Z12
Z2 Z2, Z3 Z12 Z12, Z13
Z3 Z3, Z4 Z13 Z13, Z14
Z4 Z4, Z5 Z14 Z14, Z15
3
Z5 Z5, Z6 Z15 Z15, Z16
Z6 Z6, Z7 Z16 Z16, Z17
Z7 Z7, Z8 Z17 Z17, Z18 4
Z8 Z8, Z9 Z18 Z18, Z19
Z9 Z9, Z10 Z19 Cannot be specified

5) An example of indexing and the actual process device are as follows. 5

(When Z0 (32-bit) 100000 and Z2 (32-bit) -20)
Ladder Example Actual Process Device
6
X0 X1
DMOV K100000 Z0 MOV ZR101000 D12980

DMOV K-20 Z2
Description ZR1000Z0
D13000Z2
ZR (1000 + 100000) = ZR101000
D (13000 - 20) = D12980
7
X1
MOV ZR1000Z0 D13000Z2

8
Fig. 3.9 Ladder Example and Actual Process Device
(b) Example of specifying 32-bit indexing with "ZZ" specification.
1) One index register can specify 32-bit indexing by using "ZZ" specification such as "ZR0ZZ4".
The 32-bit indexing with "ZZ" specification is as follows.

3.3
M0

Indexing
DMOVP K100000 Z4 Stores 100000 at Z4 and Z5.

M0 Indexing ZR device with 32-bit

MOVP K100 ZR0ZZ4 index registers (Z4 and Z5)
ZR (0+100000) =ZR100000

2) Specification method
To perform 32-bit indexing by using "ZZ" specification, select "Use of ZZ" in "Indexing Setting for ZR Device" in
PC parameter.

Fig. 3.10 Setting window for indexing setting parameter for ZR device

101
 3) Device that indexing can be used
The following device is available for indexing.
Device Meaning
ZR Serial number access format file register
D Extended data register (D)
W Extended link register (W)
*1 Internal relay
M
B*1 Link relay
*1 Data register
D
*1 Link register
W
Jn\B*1 Link relay
Jn\W*1 Link register

*1: This device can be used only for the High-speed Universal model QCPU.

4) Usable range of index registers

The following table shows the usable range of index registers in 32-bit indexing used “ZZ” specification.
The 32-bit indexing with “ZZ” specification is specified as the format ZRmZZn.
Specifying ZRmZZn enables Zn and Zn+1 of 32-bit values to index the device number, ZRm,
“ZZ” specification*1 Index Registers Used “ZZ” specification*1 Index Registers Used

ZZ0 Z0, Z1 ZZ10 Z10, Z11

ZZ1 Z1, Z2 ZZ11 Z11, Z12

ZZ2 Z2, Z3 ZZ12 Z12, Z13

ZZ3 Z3, Z4 ZZ13 Z13, Z14

ZZ4 Z4, Z5 ZZ14 Z14, Z15

ZZ5 Z5, Z6 ZZ15 Z15, Z16

ZZ6 Z6, Z7 ZZ16 Z16, Z17

ZZ7 Z7, Z8 ZZ17 Z17, Z18

ZZ8 Z8, Z9 ZZ18 Z18, Z19

ZZ9 Z9, Z10 ZZ19 Not available

*1: Refers to device name (ZR) for indexing target.
5) The 32-bit indexing used "ZZ" specification and the actual processing device are as follows.
(Z0 (32-bit) 100000.Z2 (32-bit) -20)
Ladder Example Actual Process Device

X0 X1
DMOV K100000 Z0 MOV ZR101000 D10

END
MOV K-20 Z2

X1 Description
MOV ZR1000ZZ0 D30Z2
ZR1000ZZ0 ZR(1000+100000)=ZR101000
D30Z2 D(30-20)=D10

Fig.3.10 Ladder Example and Actual Process Device

102
 6) Available functions for "ZZ" specification
The 32-bit indexing specification with "ZZ" specification applies in the following functions.
No. Function Name and Description
1 Specifying devices in program instruction
2 Monitoring device registrations
3 Testing devices execution type
4 Testing devices with conditions 2
5 Setting monitor conditions
6 Tracing sampling (Trace point (specifying devices), trace target device)
7 Data logging function (Sampling interval (specifying devices), logging target data) 3

ZZn cannot be used alone as a device like "DMOV K100000 ZZ0". When setting values of index registers to specify 32-bit 4
indexing with "ZZ" specification, set the value of Zn (Z0~Z19).
ZZn alone cannot be input to each function.

(4) Index modification using extended data register (D) and extended link register (W)
5
(Universal model QCPU (excluding Q00UJCPU) and LCPU)
Like index modification using data register (D) and link register (W) of internal user device, a device can be specified by
index modification within the range of the extended data register (D) and extended link register (W).
6
Index modification in internal
user device
User Program
Image of D device
7
Z0=0
D100 Internal user
device
MOV K1234
8
D1100
Z0=1000

Z1=0 Extended data

D20000

3.3
register
MOV K1234

Indexing
D22000
Z1=2000

Index modification in
extended data register

1) Index modification where the device number crosses over the boundary between the internal user device and
the extended data register (D) or extended link register (W)
The specification of index modification where the device number crosses over the boundary between the
internal user device and the extended data register (D) or extended link register (W) cannot be made.
If doing so, an error occurs when the device range check is enabled at index modification (error code: 4101).

Index modification in internal

user device Image of D device
User Program
Z0=0
D100 Internal user
device
MOV K1234

D20100 Extended data

Z0=20000 register
Index modification where the device number
crosses over the boundary between the
internal user device and the extended data
register is not possible.

103
 2) Index modification where the device number crosses over the boundary among the file register (ZR), extended
data register (D), and extended link register (W)
Index modification where the device number crosses over the boundary among the file register (ZR), extended
data register (D), and extended link register (W) will not cause an error.
However, an error occurs if the index modification result of file register (ZR), extended data register (D), and
extended link register exceeds the file register range (error code: 4101).

Index modification where the device

number crosses over the boundary
among the file register (ZR), extended
data register (D) will not cause an error.
File register files
User Program
File
ZR100 register
Z0=0 (8k)
MOV K1234
Z0=10000 Extended data
D14196
register (D)
(8k)
D20000 D12288~
Z1=0
MOV K1234 Z20000Z1
Extended link
Z1=4000 register (W)
W2DC0
(8k)
W2000~
Index modification where the device number
crosses over the boundary among the
extended data register (D), and extended
link register (W) will not cause an error.

Extended link register exceeds

the file register range.
Z1=10000

(5) Other index modifications

(a) Bit data
Device numbers can be index modified when performing digit designation. However, Indexing is not possible by
digit designation.

BIN K4X0Z2 D0
Setting is possible since this indicates
Indexing for device number.
If Z2=3, then (X0+3)=X3

BIN K4Z3X0 D0

Setting is not possible since this indicates

Indexing by digit designation.

(b) Both I/O numbers and buffer memory number can be performed indexing with intelligent function module devices*1.

MOV U10Z1\G0Z2 D0

If Z1=2 and Z2=8,

then U(10+2)\G(0+8)=U12\G8

104
 (c) Both network numbers and device numbers can be performed indexing with link direct devices*1.

MOV J1Z1\K4X0Z2 D0

If Z1=2 and Z2=8,

then J(1+2)\K4X(0+8)=J3\K4X8
*1: For the intelligent function module device, link direct devices, refer to the QnUCPU User's Manual (Function Explanation, 2
Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals)
(d) When indexing is used for multiple CPU shared devices*2, indexing for the head I/O numbers of CPU modules and
indexing for the CPU shared memory address are automatically executed. 3
MOV U3E0Z1\G0Z2 D0
4
If Z1=2 and Z2=8,
then U3E(0+2)\G(0+8)=U3E2\G8
*2: For the multiple CPU shared device, refer to the QnUCPU User’s Manual (Function Explanation, Program Fundamentals) or
Qn(H)/QnPH/QnPRHCPU User’s Manual (Function Explanation, Program Fundamentals) 5
(e) Index modification using extended data register (D) and extended link register (W) by 32 bits (Universal model
QCPU(except Q00UJCPU) and LCPU.)
Like index modification using file register (ZR), index modification using extended data register (D) and extended 6
link register (W) by 32 bits can be performed by the following two methods.
• Specifying the index registers' range used for indexing with 32-bit.
• Specifying the 32-bit indexing using "ZZ" specification. 7

32-bit indexing with the "ZZ" specification is only available for the following CPU modules. See the programming tool 8
operating manual for the available programming tools.
• The first five digits of the serial No. for QnU(D)(H)CPU is "10042" or higher. (except Q00UJCPU)
• Built-in Ethernet port QCPU
• LCPU

3.3
(6) Cautions
(a) Performing indexing between the FOR and NEXT instructions

Indexing
Pulses can be output between the FOR and NEXT instructions by use of the edge relay (V). However, pulse output
using the PLS/PLF/pulse ( P) instruction is not allowed.

[When edge relay is used] [When edge relay is not used]

(M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.)
SM400 SM400
MOV K0 Z1 MOV K0 Z1

FOR K10 FOR K10

X0Z1 V0Z1 X0Z1
M0Z1 PLS M0Z1
SM400 SM400
INC Z1 INC Z1

NEXT NEXT

Remark
The ON/OFF data of X0Z1 is stored by the edge relay V0Z1.
For example, the ON/OFF data of X0 is stored by V0, and that of X1 by V1.

105
 (b) Performing indexing with the CALL instruction
Pulses can be output with the CALL instruction by use of the edge relay (V). However, pulse output using the PLS/
PLF/pulse ( P) instruction is not allowed.

[When edge relay is used] [When edge relay is not used]

(M0Z1 provides normal pulse output.) (M0Z1 does not provide normal pulse output.)
SM400 SM400
MOV K0 Z1 MOV K0 Z1

CALL P0 CALL P0

SM400 SM400
MOV K1 Z1 MOV K1 Z1

CALL P0 CALL P0

FEND FEND
X0Z1 V0Z1 X0Z1
P0 M0Z1 P0 PLS M0Z1

RET RET

(c) Device range check during indexing

1) Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU
Device range checks are not conducted during indexing.
Therefore, when the data after index modification exceed the user specified device range, the data is written to
another device without causing an error.
(Note, however, that when the data after index modification is written to the device for system use exceeding the
user specified device range, an error occurs. (Error code: 1103))
Take extra precaution when using indexing in programming.
2) Universal model QCPU and LCPU
The device range is checked for indexing.
With changing the settings of the PLC parameter, the device range is not checked.
(d) Changing indexing with 16-bit index register for indexing with 32-bit index register
For changing indexing with 16-bit index register for indexing with 32-bit index register, check if the program has
enough spaces for indexing.
For indexing with 32-bit index registers, the specified index register (Zn) and the next index register of the specified
register (Zn+1) are used. Be sure not to overlap index registers to be used.

106
3.4 Indirect Specification

(1) Indirect Specification

(a) Indirect specification is a method that specifies address of the device to be used in a sequence program using two
word devices (two points of word device). Use indirect specification as index modification when the index register is 2
insufficient.

ADRSET D100 D0 Stores the address of

MOV K50 Z0 DMOV K50 W0

D100 to D0.
3
DMOV K10000 D150 DMOV K10000 D150

DMOV D100Z0 D110 D+ D0 W0 D10 (Address of D100) + 50 =

(Address of D150) 4
Specification of
MOV @D10 D110
D (100 + 50) = D150
Specification of

[When index resister is used]

address of D150

[When indirect specification is used]

5
(b) Specify the device to be used for specifying the address as "@ + (word device number)". For example, when
@D100 is specified, the device address will be the contents of D101 and D100.
6
(c) The address of the device specified indirectly can be confirmed with the ADRSET instruction.
For the ADRSET instruction, refer to Page 627, Section 7.18.6.
(2) Indirect specification available devices 7
The following table shows that the CPU module devices can be specified indirectly.
Availability of Indirect
Device Type Example of Indirect Specification

Bit device *1
Specification
N/A ––––––––––
8
Internal user device • @D100
Word device *1 Available
• @D100Z2 *2
Bit device *1 N/A ––––––––––
Link direct device • @J1\W10

3.4
Word device *1 Available*3
• @J1Z1\W10Z2 *2
• @U10\G0

Indirect Specification
Intelligent function module device Available*3
• @U10Z1\G0Z2 *2
Index register N/A ––––––––––
• @R0, @ZR20000
File register Available
• @R0Z1,@ZR20000Z1 *2
Extended data register (D) • @D1000
Available
Extended link register (W) • @W1000
Nesting ––––––––––
Pointer ––––––––––
Constants ––––––––––
SFC block device N/A
SFC transition device
Other ––––––––––
Network No. specification device
I/O No. specification device
*1: For the device names, refer to the QnUCPU User’s Manual (Function Explanation, Program Fundamentals) or Qn(H)/QnPH/
QnPRHCPU User’s Manual (Function Explanation, Program Fundamentals)
*2: Indicates when index modification by an index register is performed.
*3: Indirect specification is possible, but the address can not be written with the ADRSET instruction.

107
(3) Precautions
(a) The address for indirect specification uses two words. Therefore, to substitute indirect specification for index
modification, the addition/subtraction of 32-bit data is required. The following is the ladder used for the address
addition/subtraction of the device stored in D1 and D0 for indirect specification.
[To add "1" to the address of the device for indirect specification]

DINCP D0

Device used for indirect specification

32-bit instruction

[To subtract "1" from the address of the device for indirect specification]

DDECP D0

Device used for indirect specification

32-bit instruction

(b) Indirect specification of extended data register (D) and extended link register (W)
Indirect specification with indirect address can be performed in the extended data register (D) and extended link
register (W).
Note that when indirect specification is performed to the extended data register (D) and data register (D) in internal
device or to the extended link register (W) and link register (W) in internal device, the areas of the internal user
device and extended data register (D) or extended link register (W) are not treated as a sequence.
Internal user device

Setting an address D0
ADRSET D12000 D100 Data register
"D12000 h to D100 and D101
D12000
Setting the address that D12287
is an addition of 1000 to
D+ K1000 D100 D102
the address of D12000 to
D102 and D103

MOV K1234 @D102

File register files

File register

D12288
Extended data
register(D)
D13000
Since the areas of the data register and
extended data register are not sequence,
D63487
D13000 is inaccessible.
Extended link
register (W)

108
3.5 Reducing Instruction Processing Time

3.5.1 Subset Processing

Subset processing is used to place limits on bit devices used by basic instructions and application instructions in order to
2
increase processing speed.
However, the instruction symbol does not change.
3
To shorten scans, run instructions under the conditions indicated below.
(1) Conditions which each device must meet for subset processing
(a) When using word data
Device Condition
4
• Designates a bit device number in a factor of 16.
Bit device • Only K4 can be designated for digit designation.
• Does not perform indexing. 5
• Internal user device.
• File register (R, ZR *4)
Word device
• Multiple CPU shared device *1, *2 6
• Index register (Z) / Standard device register (Z) *3
Constants • No limitations

(b) When using double word data

7
Device Condition
• Designates a bit device number in a factor of 16.
Bit device • Only K8 can be designated for digit designation. 8
• Does not perform indexing.
• Internal user device.
• File register (R, ZR *4)
Word device
• Multiple CPU shared device *1, *2

3.5.1
3.5 Reducing Instruction Processing Time
• Index register (Z) / Standard device register (Z) *3
Constants • No limitations

Subset Processing
(c) When using bit data
Device Condition
Bit device • Internal user device (indexing possible)
• Bit specification of internal user device
Word device • Bit specification of file register (R, ZR *4)
• Bit specification of multiple CPU shared device *1, *2
*1: Only for Universal model QCPU
*2: Valid only for the multiple CPU high speed transmission area (from U3En\G10000)
(Excluding the case that indexing is executed for the head I/O number of the CPU module (U3En\G10000))
*3: Applies only to Universal model QCPU and LCPU.
*4: Applies only to Universal model QCPU (excluding Q00UJCPU) and LCPU.

109
(2) Instructions for which subset processing can be used
Types of Instructions Instruction Symbols
Contact instructions LD,LDI,AND,ANI,OR,ORI,LDP,LDF,ANDP,ANDF,ORP,ORF,LDPI,ANDPI,ANDFI,ORPI,ORFI
Output instructions OUT,SET,RST
Comparison operation instruction • , , , , , ,D ,D ,D ,D ,D ,D
• +,-,*,/,INC,DEC,D+,D-,D*,D/,DINC,DDEC
Arithmetic operation
• B+,B-,B*,B/, E+,E-,E*,E/
Data conversion instructions • BCD, BIN, DBCD, DBIN, FLT, DFLT, INT, DINT
• MOV, DMOV, CML, DCML, XCH, DXCH
Data transfer instruction
• FMOV, BMOV, EMOV
Program branch instruction • CJ, SCJ, JMP
Logic operations • WAND, DAND, WOR, DOR, WXOR, DXOR, WXNR, DXNR
Rotation instruction • RCL, DRCL, RCR, DRCR, ROL, DROL, ROR, DROR
Shift instruction • SFL, DSFL, SFR, DSFR
Data processing instructions • SUM, SEG
Structure creation instructions • FOR, CALL

3.5.2 Operation processing with standard device registers (Z) (Universal

model QCPU and LCPU only)

Operation processing time can be reduced with standard device registers (Z).
The following shows an example program with standard device registers.

+ D0 D10 D20

Using data registers takes three steps and the operation processing time of
28.5 ns. (With the Q26UDEHCPU)

+ Z0 Z1 Z2

Using standard device registers instead of data registers takes one step and the
operation processing time of 9.5 ns. (With the Q26UDEHCPU)

Operation processing time is reduced with the instructions that the subset processing is possible.
For the number of steps, refer to Page 118, Section 3.8.
For the operation time for each instruction, refer to Page 740, Appendix 1.

Because standard device registers are the same devices as index registers, do not use device numbers of the standard
device registers for the index registers.

110
3.6 Cautions on Programming (Operation Errors)

Operation errors are returned in the following cases when executing basic instructions and application instructions with CPU
module:
• An error listed on the explanatory page for the individual instruction occurred. 2
• When an intelligent function module device is used, no intelligent function module is installed at the specified I/O number
position.
• When an intelligent function module device is used, the specified buffer memory address does not exist.
3
• The relevant network does not exist when using a link device.
• When a link device is used, no network module is installed at the specified I/O number position.
• When a multiple CPU shared device is used, a CPU module is not installed at the head I/O number position of the specified
4
CPU module.
• When a multiple CPU shared device is used, the specified shared memory address does not exist.
• The setting of the device number crosses over the boundary between the internal user device and the extended data
5
register (D) or extended link register (W).
(Universal model QCPU (excluding Q00UJCPU) and LCPU)

6
If data is read from or written to a file register when no file register file is set in parameter or the file register file set in
parameter is not found, the following occurs.
(1) For the High Performance model QCPU, Process CPU, and Redundant CPU 7
An error does not occur even when writing/reading to/from file register is performed. However, “0H” is stored when
reading from file register is performed.
(2) For the Universal model QCPU and LCPU
The OPERATION ERROR (error code:4101) occurs when writing/reading to/from file register is performed. Note that 8
the device range check can be disabled using the PLC Parameter so that an error will not be detected.

(1) Device range check

Device range checks for the devices used by basic instructions and application instructions in CPU module are as

3.6
indicated below:

Cautions on Programming (Operation Errors)

(a) Instructions for specified each device, including MOV and DMOV
1) For the Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU
The device range is not checked. In cases where the corresponding device range is exceeded, data is written to
other devices. *1
For example, in a case where the data register has been allocated 12k points, there will be no error even if it
exceeds D12287.

DMOV K100 D12287

This designates D12287 and D12288 as the

target devices for executing the DMOV instruction.
However, since D12288 does not exist,
data in another device is corrupted.
Device range checks are not conducted also in cases where indexing is being performed.
In cases where the corresponding device range is exceeded as the result of performing indexing, data is written
to other devices.*1
*1: For the assignment order of internal user devices, refer to this Section (c) Character string data.

111
 2) Universal model QCPU and LCPU
The device range is checked. When the device number is outside the device range, an operation error occurs.
For example, when12 k points are assigned to a data register, an error occurs if the device number of the data
register exceeds D12287.

DMOV K100 D12287

When D12287 is specified with the DMOV instruction,

the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.
The device range is checked even though indexing is executed.
With changing the settings of the PLC parameter, the device range is not checked.*2
*2: For the method that the device range check is disabled when the index modification is specified, refer to the User's Manual
(Function Explanation, Program Fundamentals) for the CPU module used.
(b) Instructions for a block of devices, including BMOV and FMOV
1) For the Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU
The device range is checked.
When the device number is outside the device range, an operation error occurs.
For example, when 12 k points are assigned to a data register, an error occurs if the device number of the data
register exceeds D12287.

BMOV D0 D12287 K2

This designates D12287 and D12288 as the

target devices for executing the BMOV instruction.
However, since D12288 does not exist,
an operation error occurs.

Device range checks are also conducted when indexing is performed.

However, if indexing has been conducted, there will be no error returned if the initial device number exceeds the
relevant device range.

MOV K2 Z1

BMOV D0 D12285Z1 K2

When D12287 is specified with the BMOV instruction,

the target devices are D12287 and D12288.
However, an operation error occurs because D12288
BMOV D0 D12287Z1 K2 does not exist.

An operation error occurs since head device number

is D12289 that exceeds the device range.

2) Universal model QCPU and LCPU

The device range is checked.
When the device number is outside the device range, an operation error occurs.
For example, when12 k points are assigned to a data register, an error occurs if the device number of the data
register exceeds D12287.

BMOV D0 D12287 K2

When D12287 is specified with the BMOV instruction,

the target devices are D12287 and D12288.
However, an operation error occurs because D12288
does not exist.

112
 The device range is checked even though indexing is executed.
An error occurs when the head device number of the devices with indexing exceeds the device range.

MOV K2 Z1

BMOV D0 D12285Z1 K2 2
When D12287 is specified with the BMOV instruction,
the target devices are D12287 and D12288.

BMOV D0 D12287Z1 K2
However, an operation error occurs because D12288
does not exist. 3
An operation error occurs since head device number
is D12289 that exceeds the device range.

With changing the settings of the PLC parameter, the device range is not checked.*2
4
*2: For the method that the device range check is disabled when the index modification is specified, refer to the User's Manual
(Function Explanation, Program Fundamentals) for the CPU module used.
(c) Character string data 5
1) For the Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU.
Because all character string data is of variable length, device range checks are performed.
In cases where the corresponding device range has been exceeded, an operation error will be returned. 6
For example, in a case where the data register has been allocated 12k points, there will be an error if it exceeds
D12287.
7
$MOV "ABC" D12287

This designates D12287 and D12288 as the

target devices for executing the $MOV instruction.
However, since D12288 does not exist,
8
an operation error occurs.
The device range check is performed even when the index modification is specified. In case that the index
modification is specified, if the start device number exceeds the device range, an error does not occur. Another
device is accessed.

3.6
2) For the Universal model QCPU and LCPU

Cautions on Programming (Operation Errors)

Because all character string data is of variable length, device range checks are performed.
In cases where the corresponding device range has been exceeded, an operation error will be returned.
For example, in a case where the data register has been allocated 12k points, there will be an error if it exceeds
D12287.

$MOV "ABC" D12287

This designates D12287 and D12288 as the

target devices for executing the $MOV instruction.
However, since D12288 does not exist,
an operation error occurs.
The device range check is performed even when the index modification is specified. In case that the index
modification is specified, an error occurs if the start device number exceeds the device range. By using the PLC
Parameter, the device range check can also be disabled.*2
*2: For the method that the device range check is disabled when the index modification is specified, refer to the User's Manual
(Function Explanation, Program Fundamentals) for the CPU module used.

(d) Device range checks are conducted when indexing is performed by direct access output (DY).

113
 (e) Precautions for using the extended data register (D) or extended link register (W) (for the Universal model QCPU
except the Q00UJCPU, and LCPU )
With the following specification methods, data cannot be specified crossing over the boundary of the internal user
device and extended data register (D) or extended link register (W). Doing so causes "OPERATION ERROR" (error
code: 4101).
• Index modification
• Indirect specification
• Specification with the instructions that handle data blocks*1

Data block where the device number

crosses over the boundary between the
internal user device and the extended data
register (D) cannot be handled. Image of D device
User Program

D100 Internal user

device
FMOV K0 D100 K200

D199

FMOV K0 D12200 K200

D12200

FMOV K0 D20000 K200 D12299 Extended data

register (D)
D20100

D20299

*1 Data block indicates the following data.

• Data used in the instructions, such as FMOV, BMOV, BK+, which multiple words are targeted for operation
• Control data, composed of two or more words, specified in the instructions, such as SP.FWRITE, SP.FREAD
• Data whose data type is 32-bit or more (BIN 32-bit, real number, indirect address of the device)

114
 (1) For the Universal model QCPU and LCPU, an error occurs if any of the following accesses is performed using the
following instructions and data. (Error code: 4101)
(a) Instructions that handle fixed-length devices (such as MOV or DMOV)
(b) Instructions that handle variable-length devices (such as BMOV or FMOV that specifies the number of transfers)
(c) Character string data
2
• Access crossing the boundary of devices caused by index modification (range of A area)
The allocation order of individual devices is shown below:
SM
SD 3
X
Y

4
M
L
B
F
SB
V
5
Area A
S
Contact and coil of T
Contact and coil of ST
Contact and coil of C
6
Present value of T
Present value of ST
Present value of C 7
D
W

8
SW
Empty area
File register Boundary B
(32K points)

• Access crossing the boundary of file registers caused by index modification

• Access to file registers (R, ZR) without setting file register files
• Access to file registers (R, ZR) exceeded the range of file register files

3.6
Note that the device range check can be disabled using the PLC Parameter so that an error will not be detected even

Cautions on Programming (Operation Errors)

when the above accesses are performed. As shown in the following table, the operation of the Universal model QCPU
may differ, depending on the serial number.

Setting device range in First 5 digits of serial No. for Universal model QCPU
LCPU
indexing Serial No."10021" or lower Serial No."10022" or higher
Set Detected errors in accesses 1) to 4)
Detected errors in accesses
Not set Not detected
2) to 4)

*2: For the method that the device range check is disabled when the index modification is specified, refer to the User's Manual
(Function Explanation, Program Fundamentals) for the CPU module used.

(2) For Universal model QCPU and LCPU, the index modification that crosses internal user devices (SW) and file
registers (R) cannot be applied. (Error code: 4101)

Remark
For how to change the internal user device allocation, refer to the User’s Manual (Functions Explanation, Program
Fundamentals) for the CPU module used.

115
(2) Device data check

Device data checks for the devices used by basic instructions and application instructions in CPU module are as
indicated below:
(a) When using BIN data
No error is returned even if the operation results in overflow or underflow. The carry flag (SM700) does not go on at
such times, either.
(b) When using BCD data
1) Each digit is check for BCD value (0 to 9). An operation error is returned if individual digits are outside the 0 to 9
(A to F) range.
2) No error is returned even if the operation results in overflow or underflow. The carry flag (SM700) does not go
on at such times, either.
(c) When using floating-point data
1) An operation error occurs when the following operation results are returned with the single-precision floating-
point operation instruction.
When the absolute value of the floating decimal point data is 1.0 2-127 or lower
When absolute value of floating decimal point data is 1.0 2128 or higher
2) An operation error occurs when the following operation results are returned with the double-precision floating-
point operation instruction.
When the absolute value of the floating decimal point data is 1.0 2-1023 or lower
When absolute value of floating decimal point data is 1.0 21024 or higher
(d) Using character string data
No data check is conducted.
(3) Buffer memory access
For accessing buffer memories, using instructions with intelligent function module devices (from Un\G0) is
recommended.
(4) Multiple CPU shared memory access
For accessing multiple CPU shared memories, using instructions with multiple CPU shared devices (from U3En\G10000)
is recommended.

116
3.7 Conditions for Execution of Instructions

The following four types of execution conditions exist for the execution of CPU module sequence instructions, basic
instructions, and application instructions:
• Non-conditional execution...........Instructions executed without regard to the ON/OFF status of the device 2
Example LD X0, OUT Y10
• Executed at ON...........................Instructions executed while input condition is ON
Example MOV instruction, FROM instruction
3
• Executed at leading edge............Instructions executed only at the leading edge of the input condition (when it goes from
OFF to ON) Example
PLS instruction, MOVP instruction.
4
• Executed at trailing edge.............Instructions executed only at the trailing edge of the input condition (when it goes from
ON to OFF) Example
PLF instruction.
5
For coil or equivalent basic instructions or application instructions, where the same instruction can be designated for either
execution at ON or leading edge execution, a "P" is added after the instruction name to specify the condition for execution.
6
• Instruction to be executed at ON Instruction name
• Instruction to be executed at leading edge Instruction name +P 7

Execution at ON and execution at leading edge for the MOV instruction are designated as follows:
8
MOV K4X0 D0

Execution during ON

3.7
Conditions for Execution of Instructions
MOVP K4X0 D0

Execution at leading edge

117
3.8 Counting Step Number

The number of steps in CPU module sequence instructions, basic instructions, and application instructions differs depending
on whether indirect setting of the device used is possible or not.
(1) Counting the number of basic steps

The basic number of steps for basic instructions and application instructions is calculated by adding the device number
and 1.
For example, the "+ instruction" would be calculated as follows:

+ D0 D10
(1) (2) Number of devices 2 Number of basic steps: 3

+ D0 D10 D20
(1) (2) (3) Number of devices 3 Number of basic steps: 4

(2) Conditions for increasing the number of steps

The number of steps is increased over the number of basic steps in cases where a device is used that is designated
indirectly or for which the number of steps is increased.
(a) When device is designated indirectly
In cases where indirect designation is done by @ , the number of steps is increased 1 step over the number of
basic steps.
For example, when a 3-step MOV instruction is designated indirectly (example: MOV K4X0 @D0), one step is
added and the instruction becomes 4 steps.
(b) Devices with additional steps (the Basic Model QCPU, High Performance model QCPU, Process CPU, and
Redundant CPU)
Devices with Additional Steps Added Steps Example
Intelligent function module device MOV U4\G10 D0
Multiple CPU shared device MOV U3E1\G0 D0
Link direct device MOV J3\B20 D0
Index register 1 MOV Z0 D0
Serial number access format file register MOV ZR123 D0
32-bit constant DMOV K123 D0
Real constant EMOV E0.1 D0
For even numbers: (number of characters) / 2
Character string constant $MOV "123" D0
For odd numbers: (number of characters + 1) / 2

(c) Devices with additional steps (Universal model QCPU(except Q00UJCPU) and LCPU)
1) Instructions applicable to subset processing
The following table shows steps depending on the devices.
Added Steps
Basic Number
Instruction Symbols Devices with Additional Steps (Number of
of Steps
Instruction Steps)
Serial number access format file register,
LD,LDI,AND,ANI,OR,ORI, Extended data register (D),
1(2) 1
LDP,LDF,ANDP,ANDF,ORP,ORF Extended link register (W)
Multiple CPU shared device*3
Serial number access format file register,
Extended data register (D),
LDPI,LDFI 1(4) 3
Extended link register (W)
Multiple CPU shared device*3

118
 Added Steps
Basic Number
Instruction Symbols Devices with Additional Steps (Number of
of Steps
Instruction Steps)
Serial number access format file register,
Extended data register (D),
ANDPI,ANDFI,ORPI,ORFI 1(5) 4
Extended link register (W)
Multiple CPU shared device*3 2
Serial number access format file register
Extended data register (D),
SET 1(2) 1
Extended link register (W)
3
Multiple CPU shared device*3
Timer/Counter 3(4)
Serial number access format file register
OUT Extended data register (D), 1
4
1(2)
Extended link register (W)
Multiple CPU shared device*3
Serial number access format file register 5
Extended data register (D),
RST (bit device) 1(2) 1
Extended link register (W)
Multiple CPU shared device*3 6
Timer/Counter
2(4)
(Bit/word device)
Serial number access format file register
RST (word device)
Extended data register (D), 1(3)
2 7
Extended link register (W)
Multiple CPU shared device*3 1(3)
Standard device register *2 -1 8
LD=,LD<>,LD<,LD<=,LD>,LD>=, Serial number access format file register
AND=,AND<>,AND<,AND<=,AND>,AND>=, Extended data register (D), 3
1
OR=,OR<>,OR<.OR<=,OR>,OR>= Extended link register (W)
Multiple CPU shared device*3

3.8
Standard device register *2 -1
Serial number access format file register

Counting Step Number

LDD=,LDD<>,LDD<,LDD<=,LDD>,LDD>=,
Extended data register (D),
ANDD=,ANDD<>,ANDD<,ANDD<=,ANDD>,
Extended link register (W) 3
AND>=,ORD=,ORD<>,ORD<.ORD<=, 1
3
ORD>,ORD>= Multiple CPU shared device*
Decimal constant, hexadecimal
constant, real constant

Standard device register *2 D :-1

+,-,+P,-P,WAND,WOR,WXOR,WXNR, Serial number access format file register
WANDP,WORP,WXORP,WXNRP Extended data register (D), 3
(2 devices) Extended link register (W) S1 :1, D :3
Multiple CPU shared device*3

Standard device register *2 D :-1

Serial number access format file register
D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR, Extended data register (D),
DANDP,DORP,DXORP,DXNRP Extended link register (W) S1 :1, D :3 3
(2 devices) 3
Multiple CPU shared device*
Decimal constant, hexadecimal
S1 :1
constant, real constant
Serial number access format file register
+,-,+P,-P,WAND,WOR,WXOR,WXNR,
Extended data register (D),
WANDP,WORP,WXORP,WXNRP
Extended link register (W) S1 , S2 :1, D :2 3
(3 devices)*1
Multiple CPU shared device*3

119
 Added Steps
Basic Number
Instruction Symbols Devices with Additional Steps (Number of
of Steps
Instruction Steps)
Serial number access format file register
Extended data register (D),
D+,D-,D+P,D-P,DAND,DOR,DXOR,DXNR,
Extended link register (W) S1 , S2 :1, D :2
DANDP,DORP,DXORP,DXNRP 3
Multiple CPU shared device*3
(3 devices)*1
Decimal constant, hexadecimal
S1 , S2 :1
constant, real constant
Serial number access format file register
Extended data register (D),
*, *P, /, /P
Extended link register (W) S1 , S2 :1, D :2 3

Multiple CPU shared device*3

Serial number access format file register
Extended data register (D),
Extended link register (W) S1 , S2 :1, D :2
D*, D*P, D/, D/P, E*, E*P 3
Multiple CPU shared device*3
Decimal constant, hexadecimal
S1 , S2 :1
constant, real constant
Index register/Standard device register *2 -1
Serial number access format file register
INC,INCP,DEC,DECP,DINC,DINCP,
Extended data register (D), 2
DDEC,DDECP 3
Extended link register (W)
Multiple CPU shared device*3
Serial number access format file register
Extended data register (D),
MOV,MOVP 1 2
Extended link register (W)
Multiple CPU shared device*3
Serial number access format file register
Extended data register (D),
Extended link register (W)
DMOV,DMOVP,EMOV,EMOVP 1 2
Multiple CPU shared device*3
Decimal constant, hexadecimal
constant, real constant
Serial number access format file register
Extended data register (D),
BCD,BCDP,BIN,BINP,FLT,FLTP,CML,CMLP
Extended link register (W) S1 : 1, S2 :2 2

Multiple CPU shared device*3

Serial number access format file register
Extended data register (D),
Extended link register (W) S1 : 1, S2 :2
DBCD,DBCDP,DBIN,DBINP,INT,INTP,DINT,
2
DINTP,DFLT,DFLTP,DCML,DCMLP Multiple CPU shared device*3
Decimal constant, hexadecimal
S1 :1
constant, real constant
*1: If the same device is used for S1 and S2 , the number of basic steps increases by one.
*2: The number of steps decreases with a standard device register.
*3: Not available with LCPU.

120
 When multiple standard device registers are used in an instruction applicable to subset processing, the number
of steps decreases. The following table shows the number of steps for each instruction.
Added Steps
Locations Where Standard Device Basic Number
Instruction Symbols (Number of
Register Is Used of Steps
Instruction Steps)
LD=,LD<>,LD<,LD<=,LD>,LD>=,
AND=,AND<>,AND<,AND<=,AND>,AND>=, 2
OR=,OR<>,OR<.OR<=,OR>,OR>=
LDD=,LDD<>,LDD<,LDD<=,LDD>,LDD>=, S1 and S2 -2(1) 3
ANDD=,ANDD<>,ANDD<,ANDD<=,ANDD>,
AND>=,ORD=,ORD<>,ORD<.ORD<=,
3
ORD>,ORD>=
+,-,+P,-P,D+,D-,D+P,D-P,
WAND,WOR,WXOR,WXNR, 4
DAND,DOR,DXOR,DXNR,
S1 and D -2(1) 3
WANDP,WORP,WXORP,WXNRP,
DANDP,DORP,DXORP,DXNRP
(2 devices)
5
S1 , S2 , and D -2(1)

S1 , or S2 and D -1(2) 6
+,-,+P,-P,D+,D-,D+P,D-P,
S1 and S2
WAND,WOR,WXOR,WXNR,
(only when that device that the
DAND,DOR,DXOR,DXNR,
WANDP,WORP,WXORP,WXNRP,
number of steps does not increase is
±0(3)
3 7
DANDP,DORP,DXORP,DXNRP specified for D )
1
(3 devices)*
S1 and S2
8
(only when a serial number access format +2(5)

file register is specified for D )

S1 , S2 , and D -2(1)
*, *P, /, /P 3

3.8
S1 , or S2 and D -1(2)

Counting Step Number

S1 , S2 , and D -2(1)

S1 , or S2 and D -1(2)

S1 and S2

(only when that device that the

±0(3)
D*, D*P, D/, D/P, E*, E*P number of steps does not increase is 3

specified for D )

S1 and S2

(only when a serial number access format +2(5)

file register is specified for D )

MOV,MOVP,DMOV,DMOVP,EMOV,EMOVP S1 and D -1(1) 2

BCD,BCDP,BIN,BINP,DBCD,DBCDP,
DBIN,DBINP,FLT,FLTP,DFLT,DFLTP,
S1 and D -1(1) 2
INT,INTP,DINT,DINTP,CML,CMLP,
DCML,DCMLP

*1: If the same device is used for S1 and D , the number of basic steps increases by one.

121
 2) Except Instructions applicable to subset processing
The following table shows steps depending on the devices.
Devices with Additional Steps Added Steps Example
Intelligent function module device MOV U4\G10 D0
Multiple CPU shared device MOV U3E1\G10000 D0
Link direct device MOV J3\B20 D0
Index register / standard device register MOV Z0 D0
Serial number access format file register 1 MOV ZR123 D0
Extended data register(D) MOV D123
Extended link register(W) MOV W123
32-bit constant DMOV K123 D0
Real constant EMOV E0.1 D0
For even number: (number of characters) / 2
Character string constant $MOV "123" D0
For odd numbers: (number of characters + 1) / 2

(d) In cases where the conditions described in (a) to (c) above overlap, the number of steps becomes a culmination of
the two.
Example MOV If U1\G10 ZR123 has been designated, a total of 2 steps are added.

U1\
MOV G10 ZR123

Serial number access format file registers : 1 step

+
Intelligent function module devices : 1 step
=

Increased by 2 steps

122
3.9 Operation when the OUT, SET/RST, or PLS/PLF
Instructions Use the Same Device

The following describes the operation for executing multiple instructions of the OUT, SET/RST, or PLS/PLF that use the same
device in one scan. 2
(1) OUT instructions using the same device
Do not program more than one OUT instruction using the same device in one scan. If the OUT instructions using the
same device are programmed in one scan, the specified device will turn ON or OFF every time the OUT instruction is 3
executed, depending on the operation result of the program up to the relevant OUT instruction. Since turning ON or OFF
of the device is determined when each OUT instruction is executed, the device may turn ON and OFF repeatedly during
one scan. The following diagram shows an example of a ladder that turns the same internal relay (M0) with inputs X0 4
and X1 ON and OFF.
[Ladder]
X0 5
M0

X1
6
M0

[Timing Chart]
7
X0 X0
M0 M0
X1 X1 8
M0 M0
END END END

ON

3.9
X0 OFF
ON

Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device
X1 OFF

ON
M0 OFF

M0 turns ON because X1 is ON.

M0 turns OFF because X1 is OFF.
M0 turns ON because X0 is ON. M0 remains OFF because X0 is OFF.
With the refresh type CPU module, when the output (Y) is specified by the OUT instruction, the ON/OFF status of the last
OUT instruction of the scan will be output.
(2) SET/RST instructions using the same device
(a) The SET instruction turns ON the specified device when the execution command is ON and performs nothing when
the execution command is OFF.
For this reason, when the SET instructions using the same device are executed two or more times in one scan, the
specified device will be ON if any one of the execution commands is ON.
(b) The RST instruction turns OFF the specified device when the execution command is ON and performs nothing
when the execution command is OFF.
For this reason, when the RST instructions using the same device are executed two or more times in one scan, the
specified device will be OFF if any one of the execution commands is ON.

123
 (c) When the SET instruction and RST instruction using the same device are programmed in one scan, the SET
instruction turns ON the specified device when the SET execution command is ON and the RST instruction turns
OFF the specified device when the RST execution command is ON.
When both the SET and RST execution commands are OFF, the ON/OFF status of the specified device will not be
changed.
[Ladder]
X0
SET M0

X1
RST M0

[Timing Chart]
X0 X0
SET M0 SET M0
X1 X1
RST M0 RST M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

RST M0 is not executed M0 turns OFF because X1 is ON.

because X0 is OFF.
(M0 remains ON.) SET M0 is not executed
because X0 is OFF.
M0 turns ON because X0 is ON.
(M0 remains ON.)
When using a refresh type CPU module and specifying output (Y) in the SET/RST instruction, the ON/OFF status of the
device at the execution of the last instruction in the scan is returned as the output (Y).
(3) PLS instructions using the same device
The PLS instruction turns ON the specified device when the execution command is turned ON from OFF.
It turns OFF the device at any other time (OFF to OFF, ON to ON, or ON to OFF).
If two or more PLS instructions using the same device are executed in one scan, each instruction turns ON the device
when the corresponding execution command is turned ON from OFF and turns OFF the device in other cases.
For this reason, if multiple PLS instructions using the same device are executed in a single scan, a device that has been
turned ON by the PLS instruction may not be turned ON during one scan.

[Ladder]
X0
PLS M0

X1
PLS M0

124
 [Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON throughout the scan.)
X0 X0
PLS M0 PLS M0
X1 X1
PLS M0 PLS M0 2
END END END

ON
X0 OFF
3
ON
X1
4
OFF

ON ON
M0 OFF

M0 turns OFF because X1 M0 turns ON because X1

5
status is other than OFF ON. goes ON (OFF ON).
M0 turns ON because M0 turns OFF because X0 status
is other than OFF ON.
X0 goes ON (OFF ON).
(M0 remains OFF.) 6
• The X0 and X1 turn ON from OFF at the same time.
X0 X0
PLS M0 PLS M0 7
X1 X1
PLS M0 PLS M0

8
END END END

ON
X0 OFF
ON
X1 OFF

3.9
ON

Operation when the OUT, SET/RST, or PLS/PLF Instructions Use the Same Device
M0 OFF

M0 turns ON because X1 M0 turns OFF because X1 status is

goes ON (OFF ON). other than OFF ON.
(M0 remains ON.) (M0 remains OFF.)

M0 turns ON because M0 turns OFF because X0 status is other

X0 goes ON (OFF ON). than OFF ON.
When using a refresh type CPU module and specifying output (Y) in the PLS instructions, the ON/OFF status of the
device at the execution of the last PLS instruction in the scan is returned as the output (Y).
(4) PLF instructions using the same device
The PLF instruction turns ON the specified device when the execution command is turned OFF from ON.
It turns OFF the device at any other time (OFF to OFF, OFF to ON, or ON to ON).
If two or more PLF instructions using the same device are executed in one scan, each instruction turns ON the device
when the corresponding execution command is turned OFF from ON and turns OFF the device in other cases.
For this reason, if multiple PLF instructions using the same device are executed in a single scan, a device that has been
turned ON by the PLF instruction may not be turn ON during one scan.

125
 [Ladder]
X0
PLF M0

X1
PLF M0

[Timing Chart]
• The ON/OFF timing of the X0 and X1 is different. (The specified device does not turn ON throughout the scan.)
X0 X0
PLF M0 PLF M0
X1 X1
PLF M0 PLF M0
END END END

ON
X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns OFF because X1 M0 turns OFF because X1 status is

status is other than ON OFF. other than ON OFF.
M0 turns ON because (M0 remains OFF.)
X0 goes OFF (ON OFF). M0 turns OFF because X0 status is
other than ON OFF
(M0 remains OFF.)
• The X0 and X1 turn OFF from ON at the same time.
X0 X0
PLF M0 PLF M0
X1 X1
PLF M0 PLF M0
END END END

ON

X0 OFF
ON
X1 OFF

ON
M0 OFF

M0 turns ON because M0 turns OFF because X1 status is

X1 goes OFF (ON OFF). other than ON OFF.
(M0 remains ON.) (M0 remains OFF.)
M0 turns ON because M0 turns OFF because X1 status is
X0 goes OFF (ON OFF). other than ON OFF.
When using a refresh type CPU module and specifying output (Y) in the PLF instructions, the ON/OFF status of the
device at the execution of the last PLF instruction in the scan is returned as the output (Y).

126
3.10 Precautions for Use of File Registers

This section explains the precautions for use of the file registers in the QCPU and LCPU.
(1) CPU modules that cannot use file registers
The Q00JCPU and Q00UJCPU cannot use the file registers. When using the file registers, use the CPU module of other 2
than the Q00JCPU and Q00UJCPU.
(2) Setting of file registers to be used
When using the file registers, the file registers to be used must be set with the PLC parameter or QDRSET instruction. 3
(The PLC parameters of the Q00CPU, Q01CPU and LCPU need not be set since they are preset to "Use file register".
QDRSET instructions are not available with LCPU.) If the file registers to be used have not been set, normal operation
cannot be performed with the instructions that use the file registers. 4

Even when file registers to be used are not set in the PLC parameter, a program that uses file registers can be created. For
the CPU module other than the Universal model QCPU and LCPU, an error does not occur when that program is written to
5
the CPU module.
However, note that the correct data cannot be written/read to/from the file register.
For the Universal model QCPU and LCPU, an error occurs if the program where file registers are used is executed.
6
(3) Securing of file register area
(a) Basic Model QCPU
7
The user does not need to secure a file register area, because such a file register area is reserved in advance in the
standard RAM.
(b) High Performance model QCPU, Process CPU, Redundant CPU, and Universal model QCPU (except High-speed
8
Universal model QCPU)
Register file registers in the standard RAM/memory card to secure a file register area.
(c) High-speed Universal model QCPU, and LCPU
Register file registers in the standard RAM to secure a file register area.

3.10 Precautions for Use of File Registers

Remark
For the setting method for file registers and, memories available for the file registers of CPU modules, refer to the User's
Manual (Function Explanation, Program Fundamentals) for the CPU module used.

127
(4) Designation of file register number in excess of the registered number of points
(a) Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU
An error will not occur if data are written or read to or from the file registers that have numbers greater than the
registered number of points. However, note that the read/write of correct data to/from the file registers cannot be
performed.
(b) Universal model QCPU and LCPU
When data are written to or read from the file registers that are not registered, an error occurs. (Error code: 4101)
(5) File register specifying method
There are the block switching method and serial number access method to specify the file registers.
(a) Block switching method
In the block switching method, specify the number of used file register points in units of 32k points (one block). For
file registers of 32k points or more, specify the file registers by switching the block No. to be used with the RSET
instruction. Specify each block as R0 to R32767.

RSET K1 Specifying R0 Standard RAM/Memory card

for block 1 R0

to
MOV D0 R0 Block 0

R32767

RSET K2 R0
Specifying R0
for block 2 to Block 1

MOV D0 R0 R32767
R0
to Block 2

(b) Serial number access method

In the serial number access method, specify the file registers beyond 32k points with consecutive device numbers.
The file registers of multiple blocks can be used as consecutive file registers. Use "ZR" as the device name.

Standard RAM/Memory card

MOV D0 ZR32768
ZR0

to (Block 0)

ZR32767
MOV D0 ZR65536 ZR32768

to (Block 1)

ZR65535
ZR65536

to (Block 2)

(6) Settings and restrictions when refreshing file registers

(a) Settings
The settings of refresh devices are as follows.
• Refresh settings for CC-Link IE Controller Network (Cannot be set on LCPU.)
• Refresh settings for CC-Link IE Field Network (Cannot be set on Basic model QCPU, High Performance model
QCPU, Process CPU, Redundant CPU, Universal model QCPU whose serial number (first five digits) is "12011"
or earlier, and LCPU whose serial number (first five digits) is "13011" or earlier.)
• Refresh settings for MELSECNET/H (Cannot be set on LCPU.)
• Refresh settings for CC-Link
• Auto refresh settings for the intelligent function module
• Auto refresh settings for the multiple CPU system (Cannot be set on LCPU.)

128
 (b) Restrictions
The restrictions when specifying file registers to refresh devices are as follows.
1) On QCPU, Refresh cannot be performed correctly if the use of file register which has the same name as the
program is specified by the PLC parameter.
When the file register which has the same name as the program is used, refresh is performed to the data of the
file register having the same name as the program that is set at the last number in the [Program] tab page of 2
PLC parameter. To read/write the refresh data, specify the file register to the refresh device after switching the
file register to the corresponding one with the QDRSET instruction.
2) Refresh cannot be performed correctly if the file name of file register or the drive number is changed by the 3
QDRSET instruction. (QDRSET instructions are not available with LCPU.)
If the file name of file register or the drive number is changed by the QDRSET instruction, link refresh is
performed to the data of the setting file at the time of the END instruction execution. To read/write the refresh 4
data, specify the file register of the setting file at the time of the END instruction execution.
If the drive number is changed by the QDRSET instruction when "ZR" is specified for the device in the CPU
modules other than the Universal model QCPU, an error (LINK PARA ERROR (3101)) occurs. (Note that an 5
error does not occur when "R" is specified for the device.)
3) When a block number is switched by the RSET instruction, refresh is performed to the data of the file register
(R) in the switched block number. 6
When a block number is switched by the RSET instruction, refresh is performed to the data of the file register
(R) in the block number at the time of the END instruction execution. To read/write the refresh data, specify the
file register of the block number at the time of the END instruction execution. 7
(7) Precautions when file registers in the flash memory are used
This section explains the precautions for use of the flash memory.
(a) The following flash memory can be used. 8
• Flash card
(b) File registers in the flash memory can be only read in a sequence program.
(Write to the flash memory cannot be performed in a sequence program.)

3.10 Precautions for Use of File Registers

Sequence program Flash memory

BMOV D100 R0 K10

Write

File register
BMOV R100 D0 K10
Read

When using the flash memory for the file registers, write data in advance.
Using GX Developer or GX Works2, write data to the flash card.

129
CHAPTER 4 HOW TO READ INSTRUCTIONS

The description of instructions that are contained in the following chapters are presented in the following format.

1)
2)
3)

4)

5)

6)

7)

8)

9)

1) Code used to write instruction (instruction symbol).

2) Section number described.
3) Shows if instructions are enabled or disabled for each CPU module type.
Icon
Basic High Universal
Process Redundant Meaning
model Performance model LCPU
CPU CPU
QCPU model QCPU QCPU

High A normal icon means the corresponding instruction can

Basic performance Process Redundant Universal LCPU
be used.

Ver. Ver. Ver. Ver. Ver. Ver. The icon with Ver. means the instruction can be used
Basic High
Process Redundant Universal LCPU with some restrictions (e.g., function version, software
performance
version).

The icon with (cross) means the corresponding

High
Basic performance Process Redundant Universal LCPU instruction cannot be used.

130
4) Indicates ladder mode expressions and execution conditions for instructions.
Non-
Executed One Time Executed One
Execution Condition conditional
Execution
Executed while ON
at ON
Executed while OFF
Time at OFF 2
Code recorded on No symbol
description page recorded

5) Indicates the data set for each instruction and the data type.
2
Data Type Meaning
Bit Bit data or head number in bit data
BIN 16 bits BIN 16-bit data or head number in word device 3
BIN 32 bits BIN 32-bit data or head number in double word device
BCD 4-digit 4-digit BCD data
BCD 8-digit 8-digit BCD data 4
Real number Floating decimal point data
Character string Character string data
Device name Device name data
5
6) Devices which can be used by the instruction in question are indicated with circle. The types of devices that can be used
are as indicated below:
Internal Devices
(System, User)
File
Link direct device *4
J \
Intelligent
function Index register Constant
6
Setting Data Register Others *5
module Zn *5
Bit Word R, ZR Bit Word
U \G

X, Y, M, L, T, ST, C, *3 J \X P, I, J, U, 7
Applicable SM, F, D, W, SD, J \Y J \W DX, DY, N,
R, ZR U \G Z K, H , E, $
devices *1 B, SB, SW, FD, BL, TR,
J \B J \SW
FX, FY *2 @ BL \ S,V
J \SB
8
*1: For the description for the individual devices, refer to the QnUCPU User’s Manual
(Function Explanation, Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User’s Manual
(Function Explanation, Program Fundamentals)
*2: FX and FY can be used only for bit data, and FD only for word data.
*3: When T, ST and C are used for other than the instructions below, only word data can be used.
(Bit data cannot be used.)
[Instructions that can be used with bit data]
LD, LDI, AND, ANI, OR, ORI, LDP, LDF, ANDP, ANDF, ORP, ORF, LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI, OUT, RST
*4: Usable with the CC-Link IE Controller Network, CC-Link IE Field Network, MELSECNET/H, and MELSECNET/10.
*5: Devices which can be set are recorded in the "Constant" and the "Other" columns.
7) Indicates the function of the instruction.
8) Indicates conditions under which error is returned, and error number. See Page 111, Section 3.6 for errors not included
here.
9) Indicates both ladder and list for simple program example. Also indicates the types of individual devices used when the
program is executed.

131
 LD, LDI, AND, ANI, OR, ORI

CHAPTER 5 SEQUENCE INSTRUCTIONS

5.1 Contact Instructions

5.1.1 LD, LDI Operation start

AND, ANI Series connection

5.1.1
OR, ORI Parallel connection

LD, LDI, AND, ANI, OR, ORI Basic High

performance Process Redundant Universal LCPU

Bit device number / Word device bit designation ( S )

X1/D0.1
LD

X1/D0.1
LDI

X2/D0.2
AND

X2/D0.2
ANI

OR

X3/D0.3

ORI

X3/D0.3

S : Devices used as contacts (bits)

Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DX
S ––

When BL, S, TR, BL\S, or BL\TR is used, refer to SFC control instructions of the MELSEC-Q/L/QnA Programming Manual
(SFC).

Function
LD, LDI
(1) LD is the A contact operation start instruction, and LDI is the B contact operation start instruction. They read ON/OFF
information from the designated device*1, and use that as an operation result.
*1: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of the designated
bit.

132
 LD, LDI, AND, ANI, OR, ORI

AND, ANI
(1) AND is the A contact series connection instruction, and ANI is the B contact series connection instruction. They read the
ON/OFF data of the designated bit device*2, perform an AND operation on that data and the operation result to that
1
point, and take this value as the operation result.
*2: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of the designated
bit. 2
(2) There are no restrictions on the use of AND or ANI, but the following applies with a peripheral device used in the ladder
mode:
(a) Write........When AND and ANI are connected in series, a ladder with up to 24 stages can be displayed. 3
(b) Read........When AND and ANI are connected in series, a ladder with up to 24 stages can be displayed. If the
number exceeds 24 stages, up to 24 will be displayed.
4
OR, ORI
(1) OR is the A contact single parallel connection instruction, and ORI is the B contact single parallel connection instruction.
They read ON/OFF information from the designated device*3, and perform an OR operation with the operation results to 5
that point, and use the resulting value as the operation result.
*3: When a bit designation is made for a word device, the device turns ON or OFF depending on the 1/0 status of the designated
bit.
(2) There are no limits on the use of OR or ORI, but the following applies with a peripheral device used in the ladder mode.
6
(a) Write........OR and ORI can be used to create connections of up to 23 ladders.
(b) Read........OR and ORI can be used to create connections of up to 23 ladders.
7
The 24th or subsequent ladders cannot be displayed properly.

Remark 8
Word device bit designations are made in hexadecimal.
Bit b11 of D0 would be D0.0B.
See Page 88, Section 3.2.1 for more information on word device bit designation.

5.1.1
5.1 Contact Instructions
Operation Error

LD, LDI, AND, ANI, OR, ORI

(1) There is no operation error in the LD, LDI, AND, ANI, OR, or ORI instruction.

Program Example
(1) A program using the LD, AND, OR, and ORI instructions.
[Ladder Mode] [List Mode]

Step Instruction Device

b15 b5 b0 Bit designated

1 for word
D0 0
device

133
 LDP, LDF, ANDP, ANDF, ORP, ORF

(2) A program linking contacts using the ANB and ORB instructions.
[Ladder Mode] [List Mode]

Step Instruction Device

b15 b4 b1b0
1 1
D6 0 0
Bit designated
ORB for word
device

ANB

(3) A parallel program with the OUT instruction.

[Ladder Mode] [List Mode]

Step Instruction Device

5.1.2 LDP, LDF Pulse operation start

ANDP, ANDF Pulse series connection

5.1.2
ORP, ORF Pulse parallel connection

LDP, LDF, ANDP, ANDF, ORP, ORF Basic High

performance Process Redundant Universal LCPU

Bit device number / Word device bit designation ( S )

X1/D0.1
LDP
X1/D0.1
LDF
X2/D0.2
ANDP
X2/D0.2
ANDF

ORP
X3/D0.3

ORF

X3/D0.3

S : Devices used as contacts (bits)

Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DX
S ––

134
 LDP, LDF, ANDP, ANDF, ORP, ORF

Function
1
LDP, LDF
(1) LDP is the leading edge pulse operation start instruction, and is ON only at the leading edge of the designated bit device
(when it goes from OFF to ON). If a word device has been designated, it is ON only when the designated bit changes 2
from 0 to 1.
In cases where there is only an LDP instruction, it acts identically to instructions for the creation of a pulse that are
executed during ON( P). 3
Ladder using an LDP instruction Ladder not using an LDP instruction
X0 X0
MOV K0 D0 MOVP K0 D0
4
X0 X0
M0 PLS M0

(2) LDF is the trailing edge pulse operation start instruction, and is ON only at the trailing edge of the designated bit device 5
(when it goes from ON to OFF).
If a word device has been designated, it is ON only when the designated bit changes from 1 to 0.

ANDP, ANDF
6
(1) ANDP is a leading edge pulse series connection instruction, and ANDF is a trailing edge pulse series connection
instruction. They perform an AND operation with the operation result to that point, and take the resulting value as the
operation result.
7
The ON/OFF data used by ANDP and ANDF are indicated in the table below:
Device Specified in ANDP or ANDF
Bit Designated for ANDP State ANDF State 8
Bit Device
Word Device
OFF to ON 0 to 1 ON
OFF 0 OFF
ON 1 OFF

5.1.2
5.1 Contact Instructions
ON to OFF 1 to 0 ON

ORP, ORF

LDP, LDF, ANDP, ANDF, ORP, ORF

(2) ORP is a leading edge pulse parallel connection instruction, and ORF is a trailing edge pulse serial connection
instruction. They perform an OR operation with the operation result to that point, and take the resulting value as the
operation result.
The ON/OFF data used by ORP and ORF are indicated in the table below:
Device Specified in ORP or ORF
Bit Designated for ORP State ORF State
Bit Device
Word Device
OFF to ON 0 to 1 ON
OFF 0 OFF
ON 1 OFF
ON to OFF 1 to 0 ON

135
 LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI

Operation Error
(1) There is no operation error in the LDP, LDF, ANDP, ANDF, ORP, or ORF instruction.

Program Example
(1) The following program executes the MOV instruction at input X0, or at the leading edge of b10 (bit 11) of data register
D0.
[Ladder Mode] [List Mode]

Step Instruction Device

*1

*1: Word device bit designation is performed in hexadecimal. Bit b10 of D0 will be D0.A.

5.1.3 LDPI, LDFI Pulse NOT operation start

ANDPI, ANDFI Pulse NOT series connection
ORPI, ORFI Pulse NOT parallel connection

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

5.1.3 LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI • digits) is "10102" or later
Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

Bit device number / Word device bit designation ( S )

X1/D0.1
LDPI
X1/D0.1
LDFI
X2/D0.2
ANDPI
X2/D0.2
ANDFI

ORPI
X3/D0.3

ORFI

X3/D0.3

S : Devices used as contacts (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word DX
S ––

136
 LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI

Function
1
LDPI, LDFI
(1) LDPI is the leading edge pulse NOT operation start instruction that is on only at the leading edge of the specified bit
device (when the bit device goes from on to off) or when the bit device is on or off. If a word device has been specified, 2
LDPI is on only when the specified bit is 0, 1, or changes from 1 to 0.
(2) LDFI is the trailing edge pulse NOT operation start instruction that is on only at the trailing edge of the specified bit device
(when the bit device goes from off to on) or when the bit device is on or off. If a word device has been specified, LDFI is 3
on only when the specified bit is 0, 1, or changes from 0 to 1.
Device Specified in LDPI or LDFI

Bit Device
Bit Designated for
Word Device
LDPI State LDFI State
4
OFF to ON 0 to 1 OFF ON
OFF 0 ON ON
ON 1 ON ON 5
ON to OFF 1 to 0 ON OFF

ANDPI, ANDFI 6
(1) ANDPI is a leading edge pulse NOT series connection, and ANDFI is a trailing pulse NOT series connection. ANDPI and
ANDFI execute an AND operation with the previous operation result, and take the resulting value as the operation result.
The on or off data used by ANDPI and ANDFI are indicated in the table below. 7
Device Specified in ANDPI or ANDFI
Bit Designated for LDPI State LDFI State
Bit Device
Word Device
OFF to ON 0 to 1 OFF ON
8
OFF 0 ON ON
ON 1 ON ON
ON to OFF 1 to 0 ON OFF

5.1.3
5.1 Contact Instructions
ORPI, ORFI
(1) ORPI is a leading edge pulse NOT parallel connection, and ORFI is a trailing pulse NOT parallel connection. ORPI and

LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI

ORFI execute an OR operation with the previous operation result, and take the resulting value as the operation result.
The on or off data used by ORPI and ORFI are indicated in the table below.
Device Specified in ORPI or ORFI
Bit Designated for ORPI State ORFI State
Bit Device
Word Device
OFF to ON 0 to 1 OFF ON
OFF 0 ON ON
ON 1 ON ON
ON to OFF 1 to 0 ON OFF

Operation Error
(1) There is no operation error in the LDPI, LDFI, ANDPI, ANDFI, ORPI, or ORFI instruction.

137
 LDPI, LDFI, ANDPI, ANDFI, ORPI, ORFI

Program Example
(1) The following program stores 0 into D0 when X0 is on, off, or turns from on to off, or M0 is on, off, or turns from off to on.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program stores 0 into D0 when X0 is on and b10 (bit 11) of D0 is on, off, or turns from on to off.
[Ladder Mode] [List Mode]

Step Instruction Device

138
 ANB, ORB

5.2 Association Instructions

1
5.2.1 ANB Ladder block series connection

5.2.1
ORB Ladder block parallel connection

ANB, ORB Basic High

Process Redundant Universal LCPU
2
performance

ANB

ANB 3

Block A

Block A
Block B
4
ORB

ORB
5
Block B
For parallel connection of 1 contact,
OR or ORI is used.
6
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– –– 7

Function
8
ANB
(1) Performs an AND operation on block A and block B, and takes the resulting value as the operation result.
(2) The symbol for ANB is not the contact symbol, but rather is the connection symbol.
(3) When programming in the list mode, up to 15 ANB instructions (16 blocks) can be written consecutively.

5.2.1
5.2 Association Instructions
ORB

ANB, ORB
(1) Conducts an OR operation on Block A and Block B, and takes the resulting value as the operation result.
(2) ORB is used to perform parallel connections for ladder blocks with two or more contacts.
For ladder blocks with only one contact, use OR or ORI; there is no need for ORB in such cases.
[Ladder Mode] [List Mode]
X0 X1 X2 0 LD X0
0 Y10 1 LD X1
2 AND X2
X3 X4 3 LD X3
4 AND X4
5 ORB
X5
6 OR X5
7 ANB
8 OUT Y10
(3) The ORB symbol is not the contact symbol, but rather is the connection symbol.
(4) When programming in the list mode, it is possible to use up to 15 ORB instructions successively (16 blocks).

139
 MPS, MRD, MPP

Operation Error
(1) There is no operation error in the ANB or ORB instruction.

Program Example
(1) A program using the ANB and ORB instructions.
[Ladder Mode] [List Mode]

Step Instruction Device

5.2.2 MPS Operation results push

MRD Operation results read

5.2.2
MPP Operation results pop

MPS, MRD, MPP Basic High

performance Process Redundant Universal LCPU

In the ladder display, MPS, MRD and MPP are not displayed.
Command Command
MPS
Command
MRD

Command
MPP

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
MPS
(1) Stores the memory of the operation result (ON or OFF) immediately prior to the MPS instruction.
(2) Up to 16 MPS instructions can be used successively.
If the MPP instruction is used during this process, the number of uses calculated for the MPS instruction will be
decremented by one.

MRD
(1) Reads the operation result stored for the MPS instruction, and uses that result to perform the operation in the next step.

MPP
(1) Reads the operation result stored for the MPS instruction, and uses that result to perform the operation in the next step.
(2) Clears the operation results stored by the MPS instruction.
(3) Subtracts 1 from the number of MPS instruction times of use.

140
 MPS, MRD, MPP

1. The following shows ladders both using and not using the MPS, MRD, and MPP instructions.
1
Ladder Using the MPS, MRD and MPP Instructions Ladder not Using MPS, MRD, and MPP Instructions

X0 X1 X2 X0 X1 X2
Y10 Y10
2
X3 X4 X0 X1 X3 X4
Y11 Y11
X5
Y12
X0 X1 X5
Y12 3
2. The MPS and MPP instructions must be used the same number of times. Failure to observe this will not correctly display
the ladder in the ladder mode of the peripheral device.
4

Operation Error 5
(1) There is no operation error in the MPS, MRD, or MPP instruction.

6
Program Example
(1) A program using the MPS, MRD, and MPP instructions.
[Ladder Mode] [List Mode] 7
1) Step Instruction Device

1) 8
2)
3) 4) 2)

3)
5) 4)

5.2.2
5.2 Association Instructions
6) 5)
7)

MPS, MRD, MPP

6)

8)
7)

9) 8)

10) 9)

10)

141
 MPS, MRD, MPP

(2) A program using the MPS and MPP instructions successively.

[Ladder Mode]

[List Mode]

Step Instruction Device

142
 INV

5.2.3 INV Operation results inversion

5.2.3 INV Basic High

performance Process Redundant Universal LCPU
1
Command
INV 2

Setting Internal Devices

R, ZR
J \
U \G Zn Constants Other 3
Data Bit Word Bit Word
–– ––

4
Function
Inverts the operation result immediately prior to the INV instruction.
Operation Result Immediately Prior to Operation Result Following the 5
the INV Instruction Execution of the INV Instruction
OFF ON
ON OFF 6
Operation Error
7
(1) There is no operation error in the INV instruction.

Program Example 8
(1) A program which inverts the X0 ON/OFF data, and outputs from Y10.
[Ladder Mode] [List Mode]

Step Instruction Device

5.2.3
5.2 Association Instructions
INV
[Timing Chart]
ON
OFF
X0

ON
Y10
OFF

1. The INV instruction operates based on the results of calculation made until the INV instruction is given. Accordingly, use it
in the same position as that of the AND instruction.
The INV instruction cannot be used at the LD and OR positions.
2. When a ladder block is used, the operation result is inverted within the range of the ladder block. To operate a ladder using
the INV instruction in combination with the ANB instruction, pay attention to the range that will be inverted.

Range inverted
M0 M1 M2
0 Y10

M10 M20
ANB

10 END

For details of the ANB instruction, refer to Page 139, Section 5.2.1

143
 MEP, MEF

5.2.4 MEP, MEF Operation results conversion

5.2.4 MEP, MEF Basic High

performance Process Redundant Universal LCPU

Command
MEP

Command
MEF

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
MEP
(1) If operation results up to the MEP instruction are leading edge (from OFF to ON), goes ON (continuity status).
If operation results up to the MEP instruction are anything other than leading edge, goes OFF (non-continuity status).
(2) Use of the MEP instruction simplifies pulse conversion processing when multiple contacts are connected in series.

MEF
(1) If operation results up to the MEF instruction are trailing edge (from ON to OFF), goes ON (continuity status).
If operation results up to the MEF instruction are anything other than trailing edge, goes OFF (non-continuity status).
(2) Use of the MEF instruction simplifies pulse conversion processing when multiple contacts are connected in series.

Operation Error
(1) There is no operation error in the MEP or MEF instruction.

Program Example
(1) A program which performs pulse conversion to the operation results of X0 and X1
[Ladder Mode] [List Mode]

Step Instruction Device

1. The MEP and MEF instructions will occasionally not function properly when pulse conversion is conducted for a contact
that has been indexed by a subroutine program or by the FOR to NEXT instructions. If pulse conversion is to be
conducted for a contact that has been indexed by a subroutine program or by the FOR to NEXT instructions, use the EGP/
EGF instructions.
2. The MEP or MEF instruction operates based on the operation result performed starting from the LD instruction immediately
before the MEP or MEF instruction to immediately before the MEP or MEF instruction. Therefore, use them at the same
position as that of the AND instruction.
The MEP and MEF instructions cannot be used at the LD or OR position.

144
 EGP, EGF

5.2.5 EGP, EGF Pulse conversion of edge relay operation results

5.2.5 EGP, EGF Basic High

performance Process Redundant Universal LCPU
1
Command D
EGP
2
Command D
EGF
3
D : Edge relay number where operation results are stored (bits)
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word V
D ––
4

Function 5
EGP
(1) Operation results up to the EGP instruction are stored in memory by the edge relay (V).
6
(2) Goes ON (continuity status) at the leading edge (OFF to ON) of the operation result up to the EGP instruction.
If the operation result up to the EGP instruction is other than a leading edge (i.e., from ON to ON, ON to OFF, or OFF to
OFF), it goes OFF (non-continuity status).
7
(3) The EGP instruction is used for subroutine programs, and for conducting pulse operations for programs designated by
indexing between the FOR and NEXT instructions.
(4) The EGP instruction can be used like an AND instruction. 8
EGF
(1) Operation results up to the EGF instruction are stored in memory by the edge relay (V).
(2) Goes ON at the trailing edge (from ON to OFF) of the operation result up to the EGF instruction.

5.2.5
5.2 Association Instructions
If the operation result up to the EGF instruction is other than a trailing edge (i.e., from OFF to ON, ON to ON, or OFF to
OFF), it goes OFF (non-continuity status).

EGP, EGF
(3) The EGF instruction is used for subroutine programs, and for conducting pulse operations for programs designated by
indexing between the FOR and NEXT instructions.
(4) The EGF instruction can be used like an AND instruction.

Operation Error
(1) There is no operation error in the EGP or EGF instruction.

145
 EGP, EGF

Program Example
(1) A program using the EGP instruction in the subroutine program using the EGD instruction
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
END processing (1) (2) (1) (2) (1) (2) (1) (2) (1) (2)

ON ON
X0 OFF OFF

ON
X1 OFF
ON Turns OFF as X0 remains ON. ON
V0 OFF
Turns ON at the leading ON
edge of X0. Turns OFF as X1 remains ON.
V1 OFF
Turns ON at the leading edge of X1.
D0 1 2

D1 1

1. The EGP or EGF instruction operates based on the operation result performed starting from the LD instruction immediately
before the EGP or EGF instruction to immediately before the EGP or EGF instruction. Therefore, use them at the same
position as that of the AND instruction.
(Refer to Page 132, Section 5.1.1.)
The EGP and EGF instruction cannot be used at the position of the LD or OR instruction.
2. EGP and EGF instructions cannot be used at the ladder block positions shown below.

X0 X1 V0
SET M0

X2

146
 OUT

5.3 Output Instructions

1
5.3.1 OUT Out (excluding timers, counters, and annunciators)

5.3.1 OUT Basic High

performance Process Redundant Universal LCPU
2
Bit device number ( D )

OUT
Command
Y35
3

4
Word device
Command bit designation ( D )
D0.5

D : Number of the device to be turned ON and OFF (bits) 5

Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY

6
D (Other than ––
T, C, F)

7
Function
(1) Operation results up to the OUT instruction are output to the designated device.
(a) When Using Bit Devices
8
Operation Results Coil
OFF OFF
ON ON

(b) When Bit Designation has been Made for Word Device

5.3.1
5.3 Output Instructions
Operation Results Bit Designated
OFF 0

OUT
ON 1

Operation Error
(1) There is no operation error in the OUT instruction.

Program Example
(1) When using bit devices
[Ladder Mode] [List Mode]

Step Instruction Device

147
 OUT

(2) When bit designation has been made for word device
[Ladder Mode] [List Mode]

Step Instruction Device

b15 b7 b6 b5 b0

D0

Remark
The number of basic steps for the OUT instructions is as follows:
• When using internal device or file register (R): 1
• When using direct access output (DY): 2
• When using serial number access format file register
(Only for Universal model QCPU and LCPU): 2
(Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU): 3
• Devices other than above: 3

148
 OUT T, OUTH T, OUT ST, OUTH ST

5.3.2 OUT T Low-speed timer

OUTH T High-speed timer
OUT ST Low-speed retentive timer

5.3.2
OUTH ST High-speed retentive timer

OUT T, OUTH T, OUT ST, OUTH ST 1

High
Basic performance Process Redundant Universal LCPU

Command K50 Set value

T0 Setting in the range
from 1 to 32767 is valid. 2
OUT T
(Low-speed timer) Command D10 Set value
T0 Data register value in
the range from 1 to
32767 is valid. 3
Command H K50 Set value
T0 Setting in the range

OUTH T
from 1 to 32767 is valid.
4
(High-speed timer) Command H D10 Set value
T0 Data register value in
the range from 1 to
32767 is valid. 5
Command K50 Set value
ST0 Setting in the range
from 1 to 32767 is valid.
OUT ST
(Low-speed retentive timer) Command D10 Set value
6
ST0 Data register value in
the range from 1 to
32767 is valid.

Command H K50 Set value

7
ST0 Setting in the range
from 1 to 32767 is valid.
OUTH ST
(High-speed retentive timer) Command H D10 Set value
Data register value in
8
ST0
the range from 1 to
32767 is valid.

D : Timer number (bit)

Set value: Value set for timer (BIN 16 bits *1)

5.3.2
5.3 Output Instructions
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K

OUT T, OUTH T, OUT ST, OUTH ST

D (Only T) –– –– –– –– –– –– ––

(Other
Set value –– –– –– *2 ––
than T, C)
*1: The value setting for the timer cannot be designated indirectly.
@D0 Indirect designation is
T0 not permitted.

See Page 107, Section 3.4 for further information on indirect designation.
*2: Timer values can be set only as a decimal constant (K). Hexadecimal constants (H) and real numbers cannot be used for
timer settings.

Function
(1) When the operation results up to the OUT instruction are ON, the timer coil goes ON and the timer counts up to the value
that has been set; when the time up status (total numeric value is equal to or greater than the setting value), the contact
responds as follows:
A Contact Continuity
B Contact Non-continuity

149
 OUT T, OUTH T, OUT ST, OUTH ST

(2) The contact responds as follows when the operation result up to the OUT instruction is a change from ON to OFF:
Present Value Prior to Time Up After Time Up
Type of Timer Timer Coil
of Timer A Contact B Contact A Contact B Contact
Low speed timer
OFF 0 Non-continuity Continuity Non-continuity Continuity
High speed timer
Low speed
retentive timer Maintains the
OFF Non-continuity Continuity Continuity Non-continuity
High speed present value
retentive timer

(3) To clear the present value of a retentive timer and turn the contact OFF after time up, use the RST instruction.

(4) A negative number (-32768 to -1) cannot be set as the setting value for the timer.*3
If the setting value is 0, the timer will time out when the time the OUT instruction is executed.
*3: When specifying a setting value for the timer using a word device (D, W, R, ZR, J \ or U \ ), whether the value is in
the setting range is not checked. Check the value in the user program so that a negative number is not set.
(5) The following processing is conducted when the OUT instruction is executed:
• OUT T coil turned ON or OFF
• OUT T contact turned ON or OFF
• OUT T present value updated
In cases where a JMP instruction or the like is used to jump to an OUT T instruction while the OUT T instruction is
ON, no present value update or contact ON/OFF operation is conducted.
Also, if the same OUT T instruction is conducted two or more times during the same scan, the present value of the
number of repetitions executed will be updated.
(6) Indexing for timer coils or contacts can be conducted only by Z0 or Z1.
Timer setting value has no limitation for indexing.

Remark
1. Timer's time limit
Time limit of the timer is set in the PLC system of the PLC parameter dialog box.
Basic Model QCPU,
Universal model QCPU,
High Performance model QCPU,
LCPU
Type of Timer Process CPU, Redundant CPU
Setting Setting
Setting Range Setting Range
Unit Unit
Low speed timer
1 ms to 1000 ms 1 ms to 1000 ms
Low speed 1 ms 1 ms
(Default: 100 ms) (Default: 100 ms)
retentive timer
High speed timer
0.1 ms to 100.0 ms 0.01 ms to 100.0 ms
High speed 0.1 ms 0.01 ms
(Default: 10.0 ms) (Default: 10.0 ms)
retentive timer
2. For information on timer counting methods, refer to the User's Manual (Functions Explanation, Program Fundamentals) for
the CPU module used.
3. The number of basic steps of the OUT C instruction is 4.

Operation Error
(1) There is no operation error in the OUT instruction.

150
 OUT T, OUTH T, OUT ST, OUTH ST

Caution
1
(1) When creating a program in which the operation the timer contact triggers the operation of other timer, create the
program for the timer that operates later first.
In the following cases, all timers go ON at the same scan if the program is created in the order the timers operate.
• If the set value is smaller than a scan time.
2
• If "1" is set
Example 3
• For timers T0 to T2, the program is created in the order the timer operates later.
T1 K1
T2 T2 timer starts measurement from the next scan after
turning ON of the contact of T1 timer.
4
T0 K1
T1 T1 timer starts measurement from the next scan after
turning ON of the contact of T0 timer. 5
X0 K1
T0 T0 timer starts measurement when X0 is turned ON.

6
• For timers T0 to T2, the program is created in the order of timer operation.
X0 K1 7
T0 T0 timer starts measurement when X0 is turned ON.

T0 K1
T1 8
Contacts of T1 and T2 timers are turned ON
T1 K1 when the contact of T0 timer is turned ON.
T2

5.3.2
5.3 Output Instructions
Program Example

OUT T, OUTH T, OUT ST, OUTH ST

(1) The following program turns Y10 and Y14 ON 10 seconds after X0 has gone ON.
[Ladder Mode] [List Mode]
*3
Step Instruction Device

*3: The setting value of the low-speed timer indicates its default time limit (100 ms).

151
 OUT C

(2) The following program uses the BCD data at X10 to X1F as the timer's set value.
[Ladder Mode]

Converts the BCD data at X10 to X1F to BIN

and stores the converted value at D10.
When X2 is turned ON, T2 starts measurement
using the data stored in D10 as the set value.
Y15 goes ON at the count-up of T2.

[List Mode]

Step Instruction Device

(3) The following program turns Y10 ON 250 ms after X0 goes ON.
[Ladder Mode] [List Mode]
*4 Instruction Device
Step

*4: The setting value of the high-speed timer indicates its default time limit (10 ms).

5.3.3 OUT C Counter

5.3.3 OUT C Basic High

performance Process Redundant Universal LCPU

Command K50 Set value

C0 Setting in the range
from 1 to 32767 is valid.
OUT C
Command D10 Set value
C1 Data register value in
the range from 1 to
32767 is valid.

D : Counter number (bits)

Set value: Counter setting value (BIN 16 bits *1)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K
D (Only C) –– –– –– –– –– –– ––
(Other *2
Set value –– –– –– ––
than T, C)
*1: Counter value cannot be set by indirect designation.

@D0 Indirect designation is

C0 not permitted.

See Page 107, Section 3.4 for further information on indirect designation.
*2: Counter value can be set only with a decimal constant (K). A hexadecimal constant (H) or a real number cannot be used for
the counter value setting.

152
 OUT C

Function
1
(1) When the operation results up to the OUT instruction change from OFF to ON, 1 is added to the present value (count
value) and the count up status (present value set value), and the contacts respond as follows:
A Contact
B Contact
Continuity
Non-continuity
2
(2) No count is conducted with the operation results at ON. (There is no need to perform pulse conversion on count input.)
(3) After the count up status is reached, there is no change in the count value or the contacts until the RST instruction is 3
executed.
(4) A negative number (-32768 to -1) cannot be set as the setting value for the timer.
If the set value is 0, the processing is identical to that which takes place for 1. 4
(5) Indexing for the counter coil and contact can use only Z0 and Z1.
Counter setting value has no limitation for indexing.
5
Remark
1. For counter counting methods, refer to the User's Manual (Functions Explanation, Program Fundamentals) for the CPU
module used.
6
2. The number of basic steps of the OUT C instruction is 4.

7
Operation Error
(1) There is no operation error in the OUT instruction. 8

Program Example
(1) The following program turns Y30 ON after X0 has gone ON 10 times, and resets the counter when X1 goes ON.

5.3.3
5.3 Output Instructions
[Ladder Mode] [List Mode]

OUT C
Step Instruction Device

(2) The following program sets the value for C10 at 10 when X0 goes ON, and at 20 when X1 goes ON.
[Ladder Mode]

Stores 10 at D0 when X0 goes ON.

Stores 20 at D0 when X1 goes ON.

C10 executes counting using the data

stored in D0 as the set value.
Y30 goes ON at the count-up of C10.

153
 OUT F

[List Mode]

Step Instruction Device

5.3.4 OUT F Annunciator output

5.3.4 OUT F Basic High

performance Process Redundant Universal LCPU

Annunciator number
Command
OUT F F35

D : Number of the annunciator to be turned ON (bits)

Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D (Only F) ––

Function
(1) Operation results up to the OUT instruction are output to the designated annunciator.
(2) The following responses occur when an annunciator (F) is turned ON.
• The "USER"/"ERR." LED goes ON.
• The annunciator numbers which are ON (F numbers) are stored in special registers (SD64 to SD79).
• The value of SD63 is incremented by 1.
(3) If the value of SD63 is 16 (which happens when 16 annunciators are already ON), even if a new annunciator is turned
ON, its number will not be stored at SD64 to SD79.
(4) The following responses occur when the annunciator is turned OFF by the OUT instruction.
The coil goes OFF, but there are no changes in the status of the "USER" / "ERR." LED and the contents of the values
stored in SD63 to SD79.
Use the RST F instruction to make the "USER"/"ERR." LED go OFF as well as to delete the annunciator which was
turned OFF by the OUT F instruction from SD63 to SD79.

Operation Error
(1) There is no operation error in the OUT instruction.

Remark
1. For details of annunciators, refer to the User's Manual (Functions Explanation, Program Fundamentals) for the CPU
module used.
2. The number of basic steps for the OUT module F instruction is 2.
3. For the LED which turns on when an annunciator is turned on, refer to the following table depending on the CPU module
used.
CPU module LED which turns on
High Performance model QCPU, Process CPU, Redundant CPU, Universal model QCPU, LCPU "USER" LED
Basic model QCPU "ERR." LED

154
 SET

Program Example
1
(1) The following program turns F7 ON when X0 goes ON, and stores the value 7 from SD64 to SD79.
[Ladder Mode] [List Mode]

Step Instruction Device

2

3
[Operation]
X0 ON
Adds 1 4
SD63 0 SD63 1
SD64 0 SD64 7
SD65 0 SD65 0
SD66 0 SD66 0 5
SD67 0 SD67 0

6
SD79 0 SD79 0

5.3.5 SET Setting devices (excluding annunciators) 7

5.3.5 SET Basic High
performance Process Redundant Universal LCPU

8
Command
SET SET D

D : Bit device number to be set (ON)/Word device bit designation (bits)

Setting Internal Devices J \ Other

5.3.5
5.3 Output Instructions
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY
D (Other than T, C) ––

SET
When BL, S, TR, BL\S, or BL\TR is used, refer to SFC control instructions of the MELSEC-Q/L/QnA Programming Manual
(SFC).

Function
(1) When the execution command is turned ON, the status of the designated devices becomes as shown below:
Device Device Status
Bit device Coils and contacts turned ON
When Bit Designation has been Made for Word Device Designation bit set at 1

(2) Devices turned ON by the instruction remain ON when the same command is turned OFF.
Devices turned ON by the SET instruction can be turned OFF by the RST instruction.

Command ON
X5
SET Y10 X5 OFF
ON
X7
RST Y10 X7 OFF
Command
ON

Y10 OFF
(3) When the execution command is OFF, the status of devices does not change.

155
 SET

Operation Error
(1) There is no operation error in the SET instruction.

Program Example
(1) The following program sets Y8B (ON) when X8 goes ON, and resets Y8B (OFF) when X9 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program sets the value of D0 bit 5 (b5) to 1 when X8 goes ON, and set the bit value to 0 when X9 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

Sets b5 of D0 at 1.

Sets b5 of D0 at 0.

B5 B0
D0

Remark
1. The number of basic steps for the SET instruction is as follows:
• When internal device or file register (R0 to R32767) are in use: 1
• When direct access output (DY) or SFC program device (BL) are in use: 2
• When using serial number access format file register
(Only for Universal model QCPU and LCPU): 2
(Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU): 3
• When some other device is in use: 3
2. When using X as a device, use the device numbers that are not used for the actual input. If the same number is used for
the actual input device and input X, the data of the actual input will be written over the input X specified in the SET
instruction.

156
 RST

5.3.6 RST Resetting devices (excluding annunciators)

5.3.6 RST Basic High

performance Process Redundant Universal LCPU
1
Command
RST RST D
2
D : Bit device number to be reset/ Word device bit designation (bits) Word device number to be reset (BIN 16 bits)
Word device number to be reset (BIN 16 bits)
3
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY
D ––
4

When BL, S, TR, BL\S, or BL\TR is used, refer to SFC control instructions of the MELSEC-Q/L/QnA Programming Manual
(SFC).
5

Function 6
(1) When the execution command is turned ON, the status of the designated devices becomes as shown below:
Device Device Status 7
Bit device Turns coils and contacts OFF
Timers and counters Sets the present value to 0, and turns coils and contacts OFF
When Bit Designation has been Made for Word Device
Word devices other than timers and counters
Sets value of designated bit to 0
Sets contact to 0
8
(2) When the execution command is OFF, the status of devices does not change.
(3) The functions of the word devices designated by the RST instruction are identical to the following ladder:

5.3.6
5.3 Output Instructions
Command Command
X10 X10
RST D50 MOV K0 D50

RST
Device number Device number

Operation Error
(1) There is no operation error in the RST instruction.

Remark
The basic number of steps of the RST instruction is as follows.
a) For bit processing
• Internal device (bit to be specified by bit device or word device): 1
• Direct access output: 2
• Timer, counter: 4
• When using serial number access format file register
(Only for Universal model QCPU and LCPU): 2
(Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU): 3
• Other than above: 3
b) For word processing
• Internal device: 2
• Index resister: 2
• When using serial number access format file register
(Only for Universal model QCPU and LCPU): 2
(Basic Model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU): 3
• Other than above: 3

157
 RST

Program Example
(1) The following program sets the value of the data register to 0.
[Ladder Mode]

Stores the contents at X10 to X1F in D8

when X0 is turned ON.
Resets D8 to 0 when X5 is turned ON.

[List Mode]

Steps Instruction Device

(2) The following program resets the 100 ms retentive timer and counter.
[Ladder Mode]

When ST225 is set as retentive timer, it is

turned ON when X4 ON time reaches 30 min.
Counts the number of times ST225 was
turned ON.
Resets the coil, contact and present value of
ST225 when the contact of ST225 is turned ON.
Y55 goes ON at the count-up of C23.

Resets C23 to 0 when X5 is turned ON.

[List Mode]
Step Instruction Device

158
 SET F, RST F

5.3.7 SET F Setting annunciators

5.3.7
RST F Resetting annunciators

SET F, RST F Basic High

1
performance Process Redundant Universal LCPU

Command
SET D
2
SET

Command
RST RST D

SET D : Number of the annunciator to be set (F number) (bits) 3

RST D : Number of the annunciator to be reset (F number) (bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
4
D (Only F) ––

Function 5
SET
(1) The annunciator designated by D is turned ON when the execution command is turned ON. 6
(2) The following responses occur when an annunciator (F) is turned ON.
• The "USER" LED goes ON.*1
• The annunciator numbers which are ON (F numbers) are stored in special registers (SD64 to SD79). 7
• The value of SD63 is incremented by 1.
*1: When using the Basic model QCPU, the "ERR."LED goes ON.
(3) If the value of SD63 is 16 (which happens when 16 annunciators are already ON), even if a new annunciator is turned 8
ON, its number will not be stored at SD64 to SD79.

RST
(1) The annunciator designated by D is turned OFF when the execution command is turned ON.

5.3.7
5.3 Output Instructions
(2) The annunciator numbers (F numbers) of annunciators that have gone OFF are deleted from the special registers (SD64
to SD79), and the value of SD63 is decremented by 1.

SET F, RST F
Remark
1. For details of annunciators, refer to the User's Manual (Functions Explanation, Program Fundamentals) for the CPU
module used.
2. The number of basic steps for the SET F and RST F instructions is 2.

159
 SET F, RST F

(3) When the value of SD63 is "16", the annunciator numbers are deleted from SD64 to SD79 by the use of the RST
instruction. If the annunciators whose numbers are not registered in SD64 to SD79 are ON, these numbers will be
registered.
If all annunciator numbers from SD64 to SD79 are turned OFF, the "USER" LED in the front of the CPU module turns
OFF.*1
*1: When using the Basic model QCPU, the "ERR." LED goes OFF.

[Operations which take place when SD63 is 16]

Turns F30 ON. Resets F90.

SD63 16 16 16
SD64 233 SD64 233 SD64 233
SD65 90 SD65 90 SD65 700
SD66 700 SD66 700 SD66 28 F number in
SD67 is stored.

SD77 145
SD78 145 SD78 145 SD78 1027
SD79 1027 SD79 1027 SD79 30
Contents of SD63 and F30, which was ON,
those of SD64 to SD79 is stored in SD79.
are not changed.

Operation Error
(1) There is no operation error in the SET F or RST F instruction.

Program Example
(1) The following program turns annunciator F11 ON when X1 goes ON, and stores the value 11 at the special register
(SD64 to SD79). Further, the program resets annunciator F11 if X2 goes ON, and deletes the value 11 from the special
registers (SD64 to SD79).
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
When X1 is ON When X2 is ON
Adds 1 Subtracts 1
SD63 0 SD63 1 SD63 0
SD64 0 SD64 11 SD64 0
SD65 0 SD65 0 SD65 0
SD66 0 SD66 0 SD66 0
SD67 0 SD67 0

SD78 0 SD78 0 SD78 0

SD79 0 SD79 0 SD79 0

160
 PLS, PLF

5.3.8 PLS Leading edge output

5.3.8
PLF Trailing edge output

PLS, PLF Basic High

1
performance Process Redundant Universal LCPU

Command
PLS PLS D
2
Command
PLF PLF D

3
D : Pulse conversion device (bits)
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY
D ––
4

Function 5
PLS
(1) Turns ON the designated device when the execution command is turned OFF ON, and turns OFF the device in any
6
other case the execution command is turned OFF ON (i.e., at ON ON, ON OFF or OFF OFF of the execution
command).
When there is one PLS instruction for the device designated by D during one scan, the specified device turns ON one
7
scan.
See Page 123, Section 3.9 for the operation to be performed when the PLS instruction for the same device is executed
more than once during one scan.
8
ON

X5 OFF
X5
PLS M0 ON

5.3.8
5.3 Output Instructions
M0 OFF
1 scan 1 scan

(2) If the RUN/STOP key switch is changed from RUN to STOP after the execution of the PLS instruction, the PLS

PLS, PLF
instruction will not be executed again even if the switch is set back to RUN.
X0 Operating the Operating the
PLS M0 RUN/STOP RUN/STOP
key switch of key switch of
Operating the
Operating the CPU module CPU module
RUN/STOP
RUN/STOP key "STOP RUN". "STOP RUN".
key switch of
switch of CPU module CPU module
LD X0 "RUN STOP". "RUN STOP".
LD X0 LD X0
PLS
PLS M0 PLS M0
END 0 M0 END END 0
CPU operation CPU operation
ON stop time stop time

X0 OFF ON

M0 OFF
1 scan of PLS M0

(3) When designating a latch relay (L) for the execution command and turning the power supply OFF to ON with the latch
relay ON, the execution command turns OFF to ON at the first scan, executing the PLS instruction and turning ON the
designated device.
The device turned ON at the first scan after power-ON turns OFF at the next PLS instruction.

161
 PLS, PLF

PLF
(1) Turns ON the designated device when the execution command is turned ON OFF, and turns OFF the device in any
other case the execution command is turned ON OFF (i.e., at OFF OFF, OFF ON or ON ON of the execution
command).
When there is one PLF instruction for the device designated by D during one scan, the specified device turns ON one
scan.
See Page 123, Section 3.9 for the operation to be performed when the PLF instruction for the same device is executed
more than once during one scan.
ON

X5 OFF
X5
PLF M0 ON

M0 OFF

1 scan 1 scan

(2) If the RUN/STOP key switch is changed from RUN to STOP after the execution of the PLF instruction, the PLF
instruction will not be executed again even if the switch is set back to RUN.

Note that the device designated by D may remain ON for more than one scan if the PLS or PLF instruction is jumped by
the CJ instruction or if the executed subroutine program was not called by the CALL instruction.

Operation Error
(1) There is no operation error in the PLS or PLF instruction.

Program Example
(1) The following program executes the PLS instruction when X9 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Timing Chart]
ON

X9 OFF
ON

M9 OFF
1 scan

(2) The following program executes the PLF instruction when X9 goes OFF.
[Ladder Mode] [List Mode]

Step Instruction Device

162
 FF

[Timing Chart]
ON

X9 OFF
1
ON

M9 OFF
1 scan 2
5.3.9 FF Bit device output inversion

5.3.9 FF Basic High

performance Process Redundant Universal LCPU 3

FF
Command
FF D
4

D : Device number of the device to be reversed (bits)

Setting Internal Devices J \ Other
5
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY
––
D
6
Function
(1) Reverses the output status of the device designated by D when the execution command is turned OFF ON.
7
Device Status
Device
Prior to FF Execution After FF Execution
OFF ON 8
Bit device
ON OFF
0 1
Bit designated for word device
1 0

5.3.9
5.3 Output Instructions
Operation Error

FF
(1) There is no operation error in the FF instruction.

Program Example
(1) The following program reverses the output of Y10 when X9 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Timing Chart]
ON
X9 OFF

ON
Y10 OFF

163
 DELTA, DELTAP

(2) The following program reverses b10 (bit 10) of D10 when X0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Timing Chart]
ON
X0 OFF

D10 of b10 0 1 0

5.3.10 DELTA, DELTAP Pulse conversion of direct output

5.3.10 DELTA, DELTAP Basic High

performance Process Redundant Universal LCPU

Command
DELTA DELTA D

Command
DELTAP DELTAP D

D : Bit for which pulse conversion is to be conducted (bits)

Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY
D ––

Function
(1) Conducts pulse output of direct access output (DY) designated by D .
If DELTA DY0 has been designated, the resulting operation will be identical to the ladder shown below, which uses the
SET/RST instructions.
[Ladder using the DELTA instruction] [Ladder using the SET/RST instructions]
X100 X100
DELTA DY0 SET DY0

RST DY0

[Operation]
END processing DELTA DY0 DELTA DY0

ON
X100 OFF
ON ON
DY0 OFF
(2) The DELTA (P) instruction is used by commands for leading edge execution for an intelligent function module.

164
 DELTA, DELTAP

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
The specified direct access output number exceeds the CPU module
4101
output range.
3
Program Example
(1) The following program presets CH1 of the QD62 mounted at slot 0 of the main base unit, when X20 goes ON. 4
[Ladder Mode]

Stores the preset value (0) in the buffer

memory addresses (0 and 1) of the QD62. 5
Outputs the preset command.

6
[List Mode]

Step Instruction Device

7
0 LD X20
1 DMOVP K0 U0\G0
6
8
DELTAP
END
DY1
8

5.3.10 DELTA, DELTAP

5.3 Output Instructions

165
 SFT, SFTP

5.4 Shift Instructions

5.4.1 SFT, SFTP Bit device shift

5.4.1 SFT, SFTP Basic High

performance Process Redundant Universal LCPU

Command
SFT SFT D

Command
SFTP SFTP D

D : Device number to shift (bits)

Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word DY
D (Other than T, C) ––

Function
(1) When bit device is used
(a) Shifts to a device designated by D the ON/OFF status of the device immediately prior to the one designated by D ,
and turns the prior device OFF.
For example, if M11 has been designated by the SFT instruction, when the SFT instruction is executed, it will shift
the ON/OFF status of M10 to M11, and turn M10 OFF.
(b) Turn the first device to be shifted ON with the SET instruction.
(c) When the SFT and SFTP are to be used consecutively, the program starts from the device with the larger number.
Shift range
Shift input
M0 M15 M14 M13 M12 M11 M10 M9 M8
SFTP M14 (1) 0 0 0 0 0 1 1 0 X02 ON
0
(2) 0 0 0 0 1 0 1 0 After the 1st shift input
SFTP M13 0
(3) 0 0 0 1 0 0 1 0 After the 2nd shift input

SFTP M12 (4) 0 0 0 1 0 1 1 0 X02 ON

0
(5) 0 0 1 0 1 0 1 0 After the 3rd shift input
SFTP M11 0
(6) 0 1 0 1 0 0 1 0 After the 4th shift input
X2 0
SET M10 (7) 0 0 1 0 0 0 1 0 After the 5th shift input

Head device to shift * At M8 to M15, "1" indicates ON and "0" indicates OFF.

(2) When word device bit designation is used

(a) Shifts to a bit in the device designated by D the 1/0 status of the bit immediately prior to the one designated by D ,
and turns the prior bit to 0.
For example, if D0.5 (bit 5 [b5] of D0) has been designated by the SFT instruction, when the SFT instruction is
executed, it will shift the 1/0 status of b4 of D0 to b5, and turn b4 to 0.
b15 to b5 b4 to b0
Before the
0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1
execution of shift
D0 0
After the
0 1 0 0 1 0 0 0 1 1 1 0 0 0 0 1
execution of shift

166
 SFT, SFTP

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
The points of the specified device exceed those of the corresponding
4101
device.
3
Program Example
(1) The following program shifts Y57 to Y5B when X8 goes ON. 4
[Ladder Mode]

5
Executes shift for Y57 to Y5B when X8 goes

6
ON.
Start programming from the device having
a large number.

Turns Y57 ON when X7 goes ON.

7

8
[Timing Chart] [List Mode]
ON
Step Instruction Device
OFF
X8
ON

5.4.1
5.4 Shift Instructions
OFF
X7
ON

SFT, SFTP
OFF
Y57
ON
OFF
Y58
ON
OFF
Y59
ON
OFF
Y5A
ON
OFF
Y5B

167
 MC, MCR

5.5 Master Control Instructions

5.5.1 MC Setting the master control

5.5.1
MCR Resetting the master control

MC, MCR Basic High

performance Process Redundant Universal LCPU

Command
MC n MC n D
D

Master control ladder

MCR MCR n

n : Nesting (N0 to N14) (Nesting)

D : Device number to be turned ON (bits)
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word N DY
n –– –– ––
D –– ––

Function
The master control instruction is used to enable the creation of highly efficient ladder switching sequence programs, through
the opening and closing of a common bus for ladders.
A ladder using the master control is as follows:
Ladder as displayed in GPP ladder mode Ladder as it actually operates
X0 X0
MC n1 M0 MC n1 M0
n1 M0 n1 M0
X1 X3 M7 X1 X3 M7
Y47 Y47
Executed
M5 M5 only when
X0 is ON.
Y4F Y4F

X6 X4 X6 X4

MCR n1 MCR n1

XF XF
Y40 Y40

Remark
Inputting of contacts on the vertical bus is not necessary when programming in the write mode of a peripheral device.
These will be automatically displayed when the "conversion" operation is conducted after the creation of the ladder and
then "read" mode is set.

168
 MC, MCR

MC
(1) If the execution command of the MC instruction is ON when master control is started, the result of the operation from the
MC instruction to the MCR instruction will be exactly as the instruction (ladder) shows. 1
If the execution command of the MC instruction is OFF, the result of the operation from the MC instruction to the MCR
instruction will be as shown below:
Device Device Status 2
High speed timer
Count value goes to 0, coils and contacts all go OFF.
Low speed timer
High speed retentive timer
Coils go OFF, but counter values and contacts all maintain 3
Low speed retentive timer
current status.
Counter
Devices in OUT instruction All turned OFF
SET, RST
4
SFT Basic, Devices in the following instructions: Maintain current status
Application

(2) Even when the MC instruction is OFF, instructions from the MC instruction to the MCR instruction will be executed, so
5
scan time will not be shortened.

6
When a ladder with master control contains instructions that do not require any contact instruction (such as FOR to NEXT,
EI, DI instructions), the CPU module executes these instructions regardless of the ON/OFF status of the MC instruction
execution command. 7
(3) By changing the device designated by D , the MC instruction can use the same nesting (N) number as often as desired.
(4) Coils from devices designated by D are turned ON when the MC instruction is ON. 8
Further, using these same devices with the OUT instruction or other instructions will cause them to become double coils,
so devices designated by D should not be used within other instructions.

MCR

5.5.1
5.5 Master Control Instructions
(1) This is the instruction for recovery from the master control, and indicates the end of the master control range of
operation.

MC, MCR
(2) Do not place contact instructions before the MCR instruction.
(3) Use the MC instruction and MCR instruction of the same nesting number as a set.
However, when the MCR instructions are nested in one place, all master controls can be terminated with the lowest
nesting (N) number.
(Refer to the "Precautions for nesting" in the program example.)

Operation Error
(1) There is no operation error in the MC or MCR instruction.

169
 MC, MCR

Program Example
The master control instruction can be used in nesting. The different master control regions are distinguished by nesting (N).
Nesting can be performed from N0 to N14.
The use of nesting enables the creation of ladders which successively limit the execution condition of the program.
A ladder using nesting would appear as shown below:
[Ladder as displayed in the GPP ladder mode] [Ladder as it actually operates]
A A
MC N0 M15 MC N0 M15
NO M15 NO M15
Executed
when A is ON.
B B
MC N1 M16 MC N1 M16
N1 M16 N1 M16 Executed
when A and
B are ON.
C C
MC N2 M17 MC N2 M17
N2 M17 N2 M17 Executed
when A, B
and C are ON.
MCR N2 MCR N2

Executed
when A and
B are ON.
MCR N1 MCR N1

Executed
when A is ON.

MCR N0 MCR N0

Not related
to the status
of A, B or C.

170
 MC, MCR

Cautions when Using Nesting Architecture

(1) Nesting can be used up to 15 times (N0 to N14)
When using nesting, nests should be inserted from the lower to higher nesting number (N) with the MC instruction, and 1
from the higher to the lower order with the MCR instruction.
If this order is reversed, there will be no nesting architecture, and the CPU module will not be capable of performing
correct operations. For example, if nesting is designated in the order N1 to N0 by the MC instruction, and also 2
designated in the N1 to N0 order by the MCR instruction, the vertical bus will intersect and a correct master control
ladder will not be produced.
[Ladder as displayed in the GPP ladder mode] [Ladder as it actually operates] 3
A A
MC N1 M15 MC N1 M15
N1 M15 N1 M15 4
B

N0 M16
MC N0 M16
N0 M16
MC N0 M16
5

MCR N1 MCR N1 6

7
MCR N0 MCR N0

8
(2) If the nesting architecture results in MCR instructions concentrated in one location, all master controls can be terminated
by use of just the lowest nesting number (N).
X1 X1
MC NO M15 MC NO M15

5.5.1
5.5 Master Control Instructions
NO M15 NO M15

MC, MCR
X2 X2
MC N1 M16 MC N1 M16
N1 M16 N1 M16

X3 X3
MC N2 M17 MC N2 M17
N2 M17 N2 M17

MCR N2 MCR N0

MCR N1

MCR N0

171
 FEND

5.6 Termination Instructions

5.6.1 FEND Main routine program end

5.6.1 FEND Basic High

performance Process Redundant Universal LCPU

FEND FEND

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
(1) The FEND instruction is used in cases where the CJ instruction or other instructions are used to cause a branch in the
sequence program operations, and in cases where the main routine program is to be split from a subroutine program or
an interrupt program.
(2) Execution of the FEND instruction will cause the CPU module to terminate the program it was executing.
(3) Even sequence programs following the FEND instruction can be displayed in ladder display at a peripheral device.
(Peripheral devices continue to display ladders until encountering the END instruction.)

Operation 0 CALL P
Main routine
performed program Jump caused Main routine
when the CJ by the CJ instruction program
instruction is CJ P
not executed Operation FEND
Main routine
program performed P Subroutine
when the CJ program
FEND instruction is
executed I
P Main routine Interrupt program
program
END
FEND
END

(a) When the CJ instruction is used (b) When there are subroutine and
interrupt programs

172
 FEND

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The FEND instruction was executed after the execution of the FOR
4200
instruction, and before the execution of the NEXT instruction. 3
The FEND instruction was executed after the execution of the CALL,
4211 FCALL, ECALL, or EFCALL instruction, and before the execution of the
RET instruction.
The FEND instruction was executed before the execution of the IRET
4
4221
instruction in an interrupt program.
The FEND instruction was executed between the CHKCIR and
4230
CHKEND instructions. 5
The FEND instruction was executed between the IX and IXEND
4231
instructions.

6
Program Example
(1) The following program uses the CJ instruction.
7
[Ladder Mode]

8
When XB is ON, the program jumps to
label P23 and the steps that follow P23
are executed.

Executed when XB is OFF.

5.6.1
5.6 Termination Instructions
FEND
Indicates the termination of the sequence
program to be executed when XB is OFF.

[List Mode]

Step Instruction Device

173
 END

5.6.2 END Sequence program end

5.6.2 END Basic High

performance Process Redundant Universal LCPU

END END

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
(1) Indicates termination of programs, including main routine program, subroutine program, and interrupt programs.
Execution of the END instruction will cause the CPU module to terminate the program that was being executed.
0

Sequence program

END

(2) The END instruction cannot be used during the execution of the main sequence program.
If it is necessary to perform END processing during the execution of a program, use the FEND instruction.
(3) When programming in the ladder mode of a peripheral device, it is not necessary to input the END instruction.
(4) The use of the END and FEND instructions is broken down as follows for main routine programs, subroutine programs,
and interrupt programs:

Main routine program

FEND (FEND instruction is necessary.)

Subroutine program Main sequence

program area

Interrupt program

END (END instruction is necessary.)

174
 END

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The END instruction was executed before the execution of the NEXT
4200
instruction and after the execution of the FOR instruction. 3
The END instruction was executed before the execution of the RET
4211 instruction and after the execution of the CALL, FCALL, ECALL, or
EFCALL instruction.
The END instruction was executed before the execution of the IRET
4
4221
instruction in an interrupt program.
The END instruction was executed between the CHKCIR to CHKEND
4230
instructions. 5
The END instruction was executed between the IX to IXEND
4231
instructions.

5.6.2
5.6 Termination Instructions
END

175
 STOP

5.7 Other instructions

5.7.1 STOP Sequence program stop

5.7.1 STOP Basic High

performance Process Redundant Universal LCPU

Command
STOP STOP

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
(1) Resets the output (Y) and stops the CPU module operation when the execution command is turned ON.
(The same result will take place if switch is turned to the STOP setting.)
(2) Execution of the STOP instruction will cause the value of b4 to b7 of the special register SD203 to become "3".
b15 to b12 b11 to b8 b7 to b4 b3 to b0
SD203 0 0 1 1

Sets value "3".

(3) In order to restart CPU module operations after the execution of the STOP instruction, return switch, which has been
changed from RUN to STOP, back to the RUN position.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The STOP instruction was executed before the execution of the NEXT
4200
instruction and after the execution of the FOR instruction.
The STOP instruction was executed before the execution of the RET
4211 instruction and after the execution of the CALL/FCALL/ECALL/ –– –– –– ––
EFCALL/XCALL instruction.
The STOP instruction was executed before the execution of the IRET
4221
instruction in an interrupt program.
The STOP instruction was executed in the fixed scan execution type
4223
program.
The STOP instruction was executed between the CHKCIR to CHKEND
4230
instructions.
The STOP instruction was executed between the IX to IXEND
4231
instructions.

176
 NOP, NOPLF, PAGE n

Program Example
1
(1) The following program stops the CPU module when X8 goes ON.
[Ladder Mode]

Stops the programmable controller when X8 goes ON.

2

Sequence program 3

4
[List Mode]

Instruction Device
Step
5

6
5.7.2 NOP, NOPLF, PAGE n No operations

5.7.2 NOP, NOPLF, PAGE n Basic High

performance Process Redundant Universal LCPU 7

Command
In the ladder display, NOP is not displayed.
8
NOP NOP

NOPLF NOPLF

5.7.2
5.7 Other instructions
PAGE n PAGE n

NOP, NOPLF, PAGE n

Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
NOP
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) The NOP instruction is used in the following cases:
(a) To insert space for sequence program debugging.
(b) To delete an instruction without having to change the number of steps. (Replace the instruction with NOP.)
(c) To temporarily delete an instruction.

177
 NOP, NOPLF, PAGE n

NOPLF
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) The NOPLF instruction is used when printing from a peripheral device to force a page change at any desired location.
(a) When printing ladders
• A page break will be inserted between ladder blocks with the presence of the NOPLF instruction.
• The ladder cannot be displayed correctly if an NOPLF instruction is inserted in the midst of a ladder block.
Do not insert an NOPLF instruction in the midst of a ladder block.
(b) When printing instruction lists
• The page will be changed after the printing of the NOPLF instruction.
(3) Refer to the Operating Manual for the peripheral device in use for details of printouts from peripheral devices.

PAGE n
(1) This is a no operation instruction that has no impact on any operations up to that point.
(2) No processing is performed at peripheral devices with this instruction.

Operation Error
(1) There is no operation error in the NOP, NOPLF, or PAGE instruction.

Program Example
NOP
(1) Contact closed ... Deletes the AND or ANI instruction.
[Ladder Mode] [List Mode]

Before change

Step Instruction Device

Changing to NOP

After change

Step Instruction Device

178
 NOP, NOPLF, PAGE n

(2) Contact closed ... LD, LDI changed to NOP. (Note carefully that changing the LD and LDI instructions to NOP completely
changes the nature of the ladder.)
[Ladder Mode] [List Mode] 1
Before change

Step
Step Instruction
Instruction Device
Device 2

Changing to NOP 3

4
After change

Step Instruction Device

5

6
[Ladder Mode] [List Mode]

Before change
7
Step Instruction Device
8
Changing to LD T3
Changing to NOP

5.7.2
5.7 Other instructions
NOP, NOPLF, PAGE n
After change

Step Instruction Device

NOPLF
[Ladder Mode] [List Mode]

Step Instruction Device

179
 NOP, NOPLF, PAGE n

• Printing the ladder will result in the following:

X0
0 MOV K1 D30

MOV K2 D40

5 NOPLF NOPLF instruction, inserted as a delimiter

of ladder blocks, causes print out page to
be changed forcibly.

X1
6 Y40

8 END

• Printing an instruction list with the NOPLF instruction will result in the following:

0 LD X0

1 MOV K1 D30

3 MOV K2 D40

5 NOPLF Changes print output page

after printing NOPLF.

6 LD X1

7 OUT Y40

8 END

PAGE n
[Ladder Mode] [List Mode]

Step Instruction Device

NOP

180
 =, <>, >, <=, <, >=

CHAPTER 6 BASIC INSTRUCTIONS

1
6.1 Comparison Operation Instructions
2
6.1.1 =, <>, >, <=, <, >= BIN 16-bit data comparisons

6.1.1 =, <>, >, <=, <, >= Basic High

performance Process Redundant Universal LCPU
3

indicates an instruction symbol of .

4
/ / / / /

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2 6
S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored (BIN 16 bits)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word K, H
S1 ––
S2 –– 8
Function
(1) Treats BIN 16-bit data from device designated by S1 and BIN 16-bit data from device designated by S2 as an a normally-

6.1.1
6.1 Comparison Operation Instructions
open contact, and performs comparison operation.
(2) The results of the comparison operations for the individual instructions are as follows:

=, <>, >, <=, <, >=

Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result
= S2 = S1 = S1 S2

<> S1 S2 <> S2 = S1

> S1 > S2 > S1 S2

Continuity Non-continuity
<= S1 S2 <= S1 > S2

< S1 < S2 < S1 S2

>= S1 S2 >= S1 < S2

(3) When S1 and S2 are assigned by a hexadecimal constant and the numerical value (8 to F) whose most significant bit
(b15) is "1" is designated as a constant, the value is considered as a negative BIN value in comparison operation.

Operation Error
(1) There is no operation error in the , , , , , or instruction.

181
 D=, D<>, D>, D<=, D<, D>=

Program Example
(1) The following program compares the data at X0 to XF with the data at D3, and turns Y33 ON if the data is identical.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program compares BIN value K100 to the data at D3, and establishes continuity if the data in D3 is
something other than 100.
[Ladder Mode] [List Mode]

Step Instruction Device

(3) The following program compares the BIN value 100 with the data at D3, and establishes continuity if the D3 data is less
than 100.
[Ladder Mode] [List Mode]

Step Instruction Device

(4) The following program compares the data in D0 and D3, and if the data in D0 is equal to or less than the data in D3,
establishes continuity.
[Ladder Mode] [List Mode]

Step Instruction Device

6.1.2 D=, D<>, D>, D<=, D<, BIN 32-bit data comparisons

6.1.2
D>=

D=, D<>, D>, D<=, D<, D>= Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of D / D /D /D /D / D .

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

182
 D=, D<>, D>, D<=, D<, D>=

Function
1
(1) Treats BIN 32-bit data from device designated by S1 and BIN 32-bit data from device designated by S2 as an a normally-
open contact, and performs comparison operation.
(2) The results of the comparison operations for the individual instructions are as follows: 2
Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result
D= S2 = S1 D= S1 S2
3
D<> S1 S2 D<> S2 = S1

D> S1 > S2 D> S1 S2

Continuity Non-continuity
D<= S1 S2 D<= S1 > S2
4
D< S1 < S2 D< S1 S2

D>= S1 S2 D>= S1 < S2

(3) When S1 and S2 are assigned by a hexadecimal constant and the numerical value (8 to F) whose most significant bit
(b31) is "1" is designated as a constant, the value is considered as a negative BIN value in comparison operation.
(4) Data used for comparison should be designated by a 32-bit instruction (DMOV instruction, etc.).
If designation is made with a 16-bit instruction (MOV instruction, etc.), comparisons of large and small values cannot be 6
performed correctly.

7
Operation Error
(1) There is no operation error in the D , D ,D ,D ,D , or D instruction.
8
Program Example
(1) The following program compares the data at X0 to X1F with the data at D3 and D4, and turns Y33 ON, if the data at X0
to X1F and the data at D3 and D4 match.

6.1.2
6.1 Comparison Operation Instructions
[Ladder Mode] [List Mode]

D=, D<>, D>, D<=, D<, D>=

Step Instruction Device

(2) The following program compares BIN value K38000 to the data at D3, and D4, and establishes continuity if the data in
D3 and D4 is something other than 38000.
[Ladder Mode] [List Mode]

Step Instruction Device

(3) The following program compares BIN value K-80000 to the data at D3 and D4, and establishes continuity if the data in
D3 and D4 is less than -80000.
[Ladder Mode] [List Mode]
Step Instruction Device

183
 E=, E<>, E>, E<=, E<, E>=

(4) The following program compares the data in D0 and D1 with the data in D3 and D4, and establishes continuity if the data
in D0 and D1 is equal to or less than the data in D3 and D4.
[Ladder Mode] [List Mode]
Step Instruction Device

6.1.3 E=, E<>, E>, E<=, E<, Floating-point data comparisons (Single precision)
E>=

Ver.
High
Basic performance Process Redundant Universal LCPU

6.1.3 E=, E<>, E>, E<=, E<, E>= • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

indicates an instruction symbol of E / E /E /E /E / E .

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S1 –– –– *1 ––
S2 –– –– *1 ––
*1: Available only in multiple Universal model QCPU and LCPU
(1) The 32-bit floating decimal point data from device designated by S1 and 32-bit floating decimal point data from device
designated by S2 as A normally-open contact, and performs comparison operation.
(2) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result
E= S2 = S1 E= S1 S2

E<> S1 S2 E<> S2 = S1

E> S1 > S2 E> S1 S2

Continuity Non-continuity
E<= S1 S2 E<= S1 > S2

E< S1 < S2 E< S1 S2

E>= S1 S2 E>= S1 < S2

Note that use of the E= instruction can on occasion result in situations where errors cause the two values not to be equal.
Example X0
EMOV E1.23 D0

E* D0 E4.56 D2

E/ D2 E4.56 D2

E D0 D2 M0

Two values may not be equal.

(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

184
 E=, E<>, E>, E<=, E<, E>=

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
4100 The specified device value is -0. *2 –– ––
The specified device value is not within the following range: 3
-126 128
0, 2 | Specified device value | < 2
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± . 4
*2: There are CPU modules that will not result in an operation error if -0 is specified. For details, refer to Page 93, Section 3.2.4.

Program Example
(1) The following program compares 32-bit floating decimal point real number data at D0 and D1 to 32-bit floating decimal
point real number data at D3 and D4. 6
[Ladder Mode] [List Mode]

Step Instruction Device

7

(2) The following program compares the floating decimal point real number 1.23 to the 32-bit floating decimal point real 8
number data at D3 and D4.
[Ladder Mode] [List Mode]

Step Instruction Device

6.1.3
6.1 Comparison Operation Instructions
E=, E<>, E>, E<=, E<, E>=
(3) The following program compares 32-bit floating decimal point real number data at D0 and D1 to 32-bit floating decimal
point real number data at D3 and D4.
[Ladder Mode] [List Mode]

Step Instruction Device

(4) The following program compares the 32-bit floating decimal point data at D0 and D1 to the floating decimal point real
number 1.23.
[Ladder Mode] [List Mode]

Step Instruction Device

185
 ED=, ED<>, ED>, ED<=, ED<, ED>=

6.1.4 ED=, ED<>, ED>, ED<=,Floating-point data comparisons (Double precision)

ED<, ED>=

6.1.4 ED=, ED<>, ED>, ED<=, ED<, ED>= Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of ED /ED /ED /E /E /E

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S1 –– –– –– ––
S2 –– –– –– ––

Function
(1) The 64-bit floating decimal point real number from device designated by S1 and 64-bit floating decimal point real number from
device designated by S2 as A normally-open contact, and performs comparison operation.
(2) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbol in Operation Result Symbol in Operation Result
ED= S2 = S1 ED= S1 S2

ED<> S1 S2 ED<> S2 = S1

ED> S1 > S2 ED> S1 S2

Continuity Non-continuity
ED<= S1 S2 ED<= S1 > S2

ED< S1 < S2 ED< S1 S2

ED>= S1 S2 ED>= S1 < S2

(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022
| Specified device value | < 21024 –– –– –– ––
The specified device value is -0.

186
 ED=, ED<>, ED>, ED<=, ED<, ED>=

Program Example
1
(1) The following program compares 64-bit floating decimal point real number data at D0 to D3 with 64-bit floating decimal
point real number data at D4 to D7.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
(2) The following program compares the floating decimal point real number 1.23 with the 64-bit floating decimal point real
number data at D4 to D7.
4
[Ladder Mode] [List Mode]

Step Instruction Device

(3) The following program compares 64-bit floating decimal point real number data at D0 to D3 with 64-bit floating decimal
point real number data at D4 to D7.
6
[Ladder Mode] [List Mode]

Step Instruction Device 7

8
(4) The following program compares the 64-bit floating decimal point data at D0 to D3 with the floating decimal point real
number 1.23.
[Ladder Mode] [List Mode]

6.1.4
6.1 Comparison Operation Instructions
Step Instruction Device

ED=, ED<>, ED>, ED<=, ED<, ED>=

Caution
(1) Since the number of digits of the real number that can be input by Programing Tool is up to 15 digits, the comparison with
the real number whose number of significant digits is 16 or more cannot be made by the instruction shown in this section.
When judging match/mismatch with the real number whose significant digits is 16 or more by the instruction in this
section, compare it with the approximate values of the real number to be compared and judge by the sizes.
Example When judging the match of E1.234567890123456+10 (Number of significant digits is 16) and the double-
precision floating-point data.

E1.23456789012345+10 E1.234567890123456+10 E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are excluded.)

187
 $=, $<>, $>, $<=, $<, $>=

Example When judging the mismatch of E1.234567890123456+10 (Number of significant digits is 16) and the
double-precision floating-point data.

E1.23456789012345+10 E1.234567890123456+10 E1.23456789012346+10

Whether D0 to D3 is within this range is checked.(Values on boundaries are included.)

6.1.5 $=, $<>, $>, $<=, $<, Character string data comparisons
$>=

6.1.5 $=, $<>, $>, $<=, $<, $>= Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of $ /$ /$ / $ /$ / $ .

LD S1 S2

Command
AND S1 S2

Command Command

OR
S1 S2

S1 , S2 : Data for comparison or head number of the devices where the data for comparison is stored (character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $
S1 –– –– ––

S2 –– –– ––

Function
(1) Compares the character string data designated by S1 with the character string data designated by S2 as a normally-open
contact.
(2) A comparison operation involves the character-by-character comparison of the ASCII code of the first character in the
character string.
(3) The character string data of S1 and S2 for comparison refers to the data stored at the range from the designated device
number to the device number where "00H" code is stored.
(a) If all character strings match, the comparison result will be matched.
b15 b8 b7 b0 b15 b8 b7 b0
S1 42H (B) 41H (A) S2 42H (B) 41H (A)
S1 +1 44H (D) 43H (C) S2 +1 44H (D) 43H (C)
S1 +2 00H 45H (E) S2 +2 00H 45H (E)
"ABCDE" "ABCDE"

Instruction Symbol in Comparison Operation Result Instruction Symbol in Comparison Operation Result
$= Continuity $<= Continuity
$<> Non-continuity $< Non-continuity
$> Non-continuity $>= Continuity

188
 $=, $<>, $>, $<=, $<, $>=

(b) If the character strings are different, the character string with the larger character code will be the larger.
b15 b8 b7 b0 b15 b8 b7 b0
S1 42H (B)
S1 +1 44H (D)
41H (A)
43H (C)
S2 42H (B)
S2 +1 44H (D)
41H (A)
43H (C)
1
S1 +2 00H 46H (F) S2 +2 00H 45H (E)
"ABCDF" "ABCDE"

Instruction Symbol in Comparison Operation Result Instruction Symbol in Comparison Operation Result
2
$= Non-continuity $<= Non-continuity
$<> Continuity $< Non-continuity
$> Continuity $>= Continuity 3
(c) If the character strings are different, the first different sized character code will determine whether the character
string is larger or smaller.
b15 b8 b7 b0 b15 b8 b7 b0
4
S1 32H (2) 31H (1) S2 32H (2) 31H (1)
S1 +1 34H (4) 33H (3) S2 +1 33H (3) 34H (4)
S1 +2 00H 35H (5) S2 +2 00H 35H (5)
"12345" "12435"

Instruction Symbol in Comparison Operation Result Instruction Symbol in Comparison Operation Result
$= Non-continuity $<= Continuity 6
$<> Continuity $< Continuity
$> Non-continuity $>= Non-continuity

(4) If the character strings designated by S1 and S2 are of different lengths, the data with the longer character string will be 7
larger.
b15 b8 b7 b0 b15 b8 b7 b0
S1 32H (2)
S1 +1 34H (4)
31H (1) S2 32H (2) 31H (1) 8
33H (3) S2 +1 34H (4) 33H (3)
S1 +2 36H (6) 35H (5) S2 +2 36H (6) 35H (5)
S1 +3 00H 37H (7) S2 +3 00H 00H
"1234567" "123456"

6.1.5
6.1 Comparison Operation Instructions
Instruction Symbol in Comparison Operation Result Instruction Symbol in Comparison Operation Result
$= Non-continuity $<= Non-continuity
$<> Continuity $< Non-continuity

$=, $<>, $>, $<=, $<, $>=

$> Continuity $>= Continuity

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The code "00H" does not exist within the range of the relevant device,
4101 starting from the device specified by S1 and S2 . ––
The number of character strings of S1 and S2 exceeds 16383.

189
 $=, $<>, $>, $<=, $<, $>=

The character string data comparison instruction checks the device range while comparing the designated character string
data. For this reason, if the "00H" code does not exist in the relevant device range, the instruction outputs the comparison
result instead of returning an operation error when no match of characters is detected.

Example $ D12287 D10 M0

S1 S2

Data of S1 Data of S2

D12287 B A D10 Z A
W0 00 H C D11 00 H C
If S1 and S2 data are as shown above, the second character of S1 does not match with that of S2 , and the comparison
result is expressed as S1 S2 (the operation result is "non-conductive"). Though the "00H" code is not included within the
S1 device range, no operation error is returned, because the no-match is detected at D12287, which is within the device
range.

Program Example
(1) The following program compares character strings stored following D0 and characters following D10.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program compares the character string "ABCDEF" with the character string stored following D10.
[Ladder Mode] [List Mode]
Step Instruction Device

(3) The following program compares the character string stored following D10 with the character string stored following
D100.
[Ladder Mode] [List Mode]

Step Instruction Device

(4) The following program compares the character string stored following D200 with the character string "12345".
[Ladder Mode] [List Mode]

Step Instruction Device

190
 BKCMP, BKCMPP

6.1.6 BKCMP, BKCMPP BIN 16-bit block data comparisons

6.1.6 BKCMP, BKCMPP Basic High

performance Process Redundant Universal LCPU
1
indicates an instruction symbol of / / / / / .

BKCMP
Command
BKCMP S1 S2 D n
2
Command
n
BKCMP P
3
BKCMP P S1 S2 D

S1 : Data to be compared or head number of the devices where the data to be compared is stored (BIN 16 bits)
S2 : Head number of the devices where the comparison data is stored (BIN 16 bits)
4
D : Head number of the devices where the comparison operation result will be stored (bits)
n : Number of comparison data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– –– ––
–– –– –– ––
S2

D –– –– ––
6
n ––

7
Function
(1) Compares BIN 16-bit data the nth point from the device number designated by with BIN 16-bit data the nth point from
S1
8
the device number designated by S2 , and stores the result from the device designated by D onward.
(a) If the comparison condition has been met, the device designated by D will be turned ON.
(b) If the comparison condition has not been met, the device designated by D will be turned OFF.
Operation Results

6.1.6
6.1 Comparison Operation Instructions
S1 1234 (BIN) S2 5321 (BIN) D OFF (0)
S1 1 5678 (BIN) S2 1 3399 (BIN) D 1 ON (1)
S1 2 5000 (BIN) S2 2 5678 (BIN) D 2 OFF (0)

BKCMP, BKCMPP
n n n

S1 (n 2) 7777 (BIN) S2 (n 2) 6543 (BIN) D (n 2) ON (1)

S1 (n 1) 4321 (BIN) S2 (n 1) 1200 (BIN) D (n 1) ON (1)

(2) The comparison operation is conducted in 16-bit units.

(3) The constant designated by S1 can be between -32768 and 32767 (BIN 16-bit data).
Operation Results
S2 32000 (BIN) D ON (1)
S2 1 4321 (BIN) D 1 OFF (0)
S2 2 32000 (BIN) D 2 ON (1)
S1 32000 (BIN) n n
S2 (n 2) 1234 (BIN) D (n 2) OFF (0)
S2 (n 1) 5678 (BIN) D (n 1) OFF (0)

(4) The results of the comparison operations for the individual instructions are as follows:
Instruction Comparison Instruction Comparison
Condition Condition
Symbols Operation Result Symbols Operation Result
BKCMP= S2 = S1 BKCMP= S1 S2

BKCMP<> S1 S2 BKCMP<> S2 = S1

BKCMP> S1 > S2 BKCMP> S1 S2

ON (1) OFF (0)
BKCMP<= S1 S2 BKCMP<= S1 > S2

BKCMP< S1 < S2 BKCMP< S1 S2

BKCMP>= S1 S2 BKCMP>= S1 < S2

(5) If all comparison results stored n points from D are ON (1), SM704 (block comparison signal) goes ON.

191
 BKCMP, BKCMPP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceeds those of each device specified in S1 ,
S2 , or D .
The ranges of devices starting from the one specified in S1 and D
4101 –– –– –– ––
overlap by n points.
The ranges of devices starting from the one specified in S2 and D

overlap by n points.

Program Example
(1) The following program compares, when X20 is turned ON, the data stored at D100 to D103 with the data stored at R0 to
R3 and stores the operation result into the area starting from M10.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b0 b15 b0
D100 1000 (BIN) R0 1000 (BIN) M10 ON
D101 2000 (BIN) R1 2000 (BIN) M11 ON
D102 3000 (BIN) R2 5000 (BIN) M12 OFF
D103 4000 (BIN) R3 4000 (BIN) M13 ON

D0 4
(2) The following program compares, when X1C is turned ON, the constant K1000 with the data stored at D10 to D13, and
stores the operation result at b4 to b7 in D0.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b0
D10 2000 (BIN)
b15 b0 D11 1000 (BIN)
1000 (BIN)
D12 1000 (BIN)
D13 2222 (BIN)

b15 b7 b4 b0
D0 before 0 10000 1000 100000
operation

b15 b7 b4 b0
D0 after 0 10000 10100 10000
operation

192
 DBKCMP, DBKCMPP

(3) The following program compares, when X20 is turned ON, the data at D10 to D12 with the data at D30 to D32, and
stores the operation result into the area starting from M100.
The following program transfers the character string "ALL ON" to D100 onward when all devices from M100 onward have 1
reached the 1 "ON" state.
[Ladder Mode] [List Mode]

Step Instruction Device 2

[Operation]
4
b15 b0 b15 b0
D10 1234 (BIN) D30 4321 (BIN) M100 ON SM704
D11 5678 (BIN) D31 5678 (BIN) M101 ON ON
D12 9876 (BIN) D32 9999 (BIN) M102 ON

b15 b8 b7 b0
D100 4CH (L) 41H (A)
D101 20H ( ) 4CH (L)
$MOV
6
D102 4EH (N) 4FH (O)

6.1.7 DBKCMP,
DBKCMPP
BIN 32-bit block data comparisons
7
Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five 8

6.1.7 DBKCMP, DBKCMPP digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

indicates an instruction symbol of / / / / / .

6.1.7
6.1 Comparison Operation Instructions
Command
DBKCMP DBKCMP S1 S2 D n

Command

DBKCMP, DBKCMPP
DBKCMP P DBKCMP P S1 S2 D n

S1 : Data to be compared or head number of the devices where the data to be compared are stored (BIN 32 bits)
S2 : Head number of the devices where the comparison data are stored (BIN 32 bits)
D : Head number of the devices where the comparison operation result will be stored (bits)
n : Number of comparison data blocks (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– –– ––

S2 –– –– –– ––

D –– –– –– ––

n –– ––

193
 DBKCMP, DBKCMPP

Function
(1) This instruction compares BIN 32-bit data stored in n-point devices starting from the device specified by S1 with BIN 32-
bit data stored in n-point devices starting from the device specified by a constant and S2 and then stores the result into
the nth device specified by D and up.
(a) If the comparison condition has been met, the corresponding devices specified by D will be turned on.
(b) If the comparison condition has not been met, the corresponding devices specified by D will be turned off.

b31 b0 b31 b0 Operation result

S1 +1, S1 1090 (BIN) S2 +1, S2 1000 (BIN) D OFF (0)
S1 +3, S1 +2 2080 (BIN) S2 +3, S2 +2 2000 (BIN) D +1 OFF (0)
S1 +5, S1 +4 5060 (BIN) n S2 +5, S2 +4 5060 (BIN) n D +2 ON (1) n

S1 +(2n-1), S1 +(2n-2) 1106 (BIN) S2 +(2n-1), S2 +(2n-2) 1106 (BIN) D +(n-1) ON (1)

(2) The comparison operation is executed in 32-bit units.

(3) The constant in the device specified by S1 can be between -2147483648 and 2147483647 (BIN 32-bit data).

b31 b0 Operation result

S2 +1, S2 32700 (BIN) D ON (1)
b31 b0 S2 +3, S2 +2 40000 (BIN) D +1 OFF (0)
S1 +1, S1 32800 (BIN) S2 +5, S2 +4 32800 (BIN) n D +2 ON (1) n

S2 +(2n-1), S2 +(2n-2) 2147400 (BIN) D +(n-1) OFF (0)

(4) D specifies out of the device range of n-point devices starting from the device specified by S1 and S2 .

(5) The following table shows the results of the comparison operations for each individual instruction.
Instruction Comparison Instruction Comparison
Condition Condition
Symbols Operation Result Symbols Operation Result
DBKCMP= S2 = S1 DBKCMP= S1 S2

DBKCMP<> S1 S2 DBKCMP<> S2 = S1

DBKCMP> S1 > S2 DBKCMP> S1 S2

ON (1) OFF (0)
DBKCMP<= S1 S2 DBKCMP<= S1 > S2

DBKCMP< S1 < S2 DBKCMP< S1 S2

DBKCMP>= S1 S2 DBKCMP>= S1 < S2

(6) If all comparison results stored into the devices starting from the device specified by D to nth device are on(1), or one of
the results is off(2), the special relays will be on or off in accordance with the conditions as follows.
When all results of comparison operations are When results of comparison operations have a result
on(1) of off(0)
No. Number Initial Interrupt (other Interrupt (other
Initial execution/
execution/ than l45)/Fixed Interrupt(l45) than l45)/Fixed Interrupt(l45)
Scan
Scan scan execution scan execution
1 SM704 ON ON ON OFF OFF OFF
2 SM716 ON –– –– OFF –– ––
3 SM717 –– ON –– –– OFF ––
4 SM718 –– –– ON –– –– OFF
In a standby program, a special relay depending on the caller program turns on or off.
(7) If the value specified by n is 0, the instruction will be not processed.

194
 DBKCMP, DBKCMPP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
4100 A negative value is specified for n. –– –– –– ––
The points specified in n exceeds those of each device specified in S1 , 3
S2 , or D .
The ranges of devices starting from the one specified in S1 and D
4101 –– –– –– ––
overlap by n points. 4
The ranges of devices starting from the one specified in S2 and D

overlap by n points.

Program Example
(1) The following program compares the value data stored at R0 to R5 with the value data stored at D20 to D25, and then 6
stores the operation result into Y0 to Y2, when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device 7

[Operation]
8
b31 b0 b31 b0
R1,R0 -2147483000 D21,D20 -2147483000 Y0 OFF (0)
R3,R2 0 D23,D22 1 Y1 ON (1)
R5,R4 2147483000 D25,D24 2147482999 Y2 ON (1)

6.1.7
6.1 Comparison Operation Instructions
(2) The following program compares the constant with the value data stored at D0 to D9, and then stores the operation result
into D10.5 to D10.9, when M0 is turned on.

DBKCMP, DBKCMPP
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b31 b0
D1,D0 -70000 D10.5 ON (1)
b31 b0 D3,D2 50000 D10.6 OFF (0)
-60000 D5,D4 -32768 D10.7 OFF (0)
D7,D6 32767 D10.8 OFF (0)
D9,D8 0 D10.9 OFF (0)

195
 DBKCMP, DBKCMPP

When certain bits are specified in a word device, bits other than the certain bits that store the operation result do not
change.
D10.F D10.0
Before execution 0 0 1 0 1 1 1 1 1 0 0 1 1 0 0 0

D10.F D10.0
After execution 0 0 1 0 1 1 0 0 0 0 1 1 1 0 0 0

No change No change

(3) The following program compares the value data stored at D0 to D5 with the value data stored at D10 to D15, and then
stores the operation result into M20 to M22, when M0 is turned on. Also, the program transfers the character string "ALL
ON" to D100 and up when all devices from M20 to M22 have reached the on status.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b31 b0 b31 b0
D1,D0 -2147483000 D11,D10 -2147483000 M20 ON (1)
D3,D2 60000 D13,D12 60001 M21 ON (1)
D5,D4 -900000 D15,D14 -899999 M22 ON (1)

When all operation results are on(1),

the special relays corresponding to SM704 ON (1)
each program turn on(1).
(Since this program examples refer SM716 ON (1)
to scan programs, SM704 and SM716 SM717 OFF (0)
turn on(1), SM7171 and SM718 do not SM718 OFF (0)
change in the scan program)

196
 +, +P, -, -P

6.2 Arithmetic Operation Instructions

1
6.2.1 +, +P, -, -P BIN 16-bit addition and subtraction operations

6.2.1 +, +P, -, -P Basic High

performance Process Redundant Universal LCPU
2
When two data are set ( D + S D , D - S D )

indicates an instruction symbol of +/ .

3
Command
+, S D

Command 4
+P, P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits)
D : Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– 6
D –– ––

7
Function
+
(1) Adds 16-bit BIN data designated by D to 16-bit BIN data designated by S and stores the result of the addition at the
8
device designated by D .
D S D

b15 b0 b15 b0 b15 b0

6.2.1
6.2 Arithmetic Operation Instructions
5678 (BIN) 1234 (BIN) 6912 (BIN)

(2) Values for S and D can be designated between -32768 and 32767 (BIN, 16 bits).

+, +P, -, -P
(3) The judgment of whether data is positive or negative is made by the most significant bit (b15).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.
K32767 +K2 K 32767 Since bit 15 value is "1",
(7FFFH) (0002H) (8001H) result of operation takes a negative value.
K 32768 +K 2 K32766 Since bit 15 value is "0",
(8000H) (FFFEH) (7FFEH) result of operation takes a positive value.

–
(1) Subtracts 16-bit BIN data designated by D from 16-bit BIN data designated by S and stores the result of the subtraction
at the device designated by D .
D S D

b15 b0 b15 b0 b15 b0

5678 (BIN) 1234 (BIN) 4444 (BIN)

(2) Values for S and D can be designated between -32768 and 32767 (BIN, 16 bits).
(3) The judgment of whether data is positive or negative is made by the most significant bit (b15).
• 0: Positive
• 1: Negative

197
 +, +P, -, -P

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.

K 32768 K2 K32766 Since bit 15 value is "0",

(8000H) (0002H) (7FFEH) result of operation takes a positive value.
K32767 K 2 K 32767 Since bit 15 value is "1",
(7FFFH) (FFFEH) (8001H) result of operation takes a negative value.

Operation Error
(1) There is no operation error in the +(P) or -(P) instruction.

When three data are set ( S1 + S2 D , S1 - S2 D )

indicates an instruction symbol of +/ .

Command
+, S1 S2 D

Command
+P, P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 16 bits)
D : Head number of the devices where the addition/subtraction operation result will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

D –– ––

Function
+
(1) Adds 16-bit BIN data designated by S1 to 16-bit BIN data designated by S2 and stores the result of the addition at the
device designated by D .

S1 S2 D

b15 b0 b15 b0 b15 b0

5678 (BIN) 1234 (BIN) 6912 (BIN)

(2) Values for S1 , S2 and D can be designated between D -32768 and 32767 (BIN, 16 bits).
(3) The judgment of whether data is positive or negative is made by the most significant bit (b15).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.
K32767 +K2 K 32767 Since bit 15 value is "1",
(7FFFH) (0002H) (8001H) result of operation takes a negative value.

K 32768 +K 2 K32766 Since bit 15 value is "0",

(8000H) (FFFEH) (7FFEH) result of operation takes a positive value.

198
 +, +P, -, -P

–
(1) Subtracts 16-bit BIN data designated by from 16-bit BIN data designated by and stores the result of the subtraction
1
S1 S2

at the device designated by D .

S1 S2 D

b15 b0 b15 b0 b15 b0 2

5678 (BIN) 1234 (BIN) 4444 (BIN)

(2) Values for S1 , S2 and D can be designated between D -32768 and 32767 (BIN, 16 bits).
(3) The judgment of whether data is positive or negative is made by the most significant bit (b15). 3
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
4
The carry flag (SM700) in this case does not go ON.
K 32768 K2 K32766 Since bit 15 value is "0",
(8000H) (0002H) (7FFEH) result of operation takes a positive value.

K32767 K 2 K 32767 Since bit 15 value is "1",

(7FFFH) (FFFEH) (8001H) result of operation takes a negative value.
6
Operation Error
(1) There is no operation error in the +(P) or -(P) instruction. 7

Program Example 8
(1) The following program adds, when X5 is turned ON, the data at D3 and D0 and outputs the operation result at Y38 to
Y3F.
[Ladder Mode] [List Mode]
Instruction Device

6.2.1
6.2 Arithmetic Operation Instructions
Step

+, +P, -, -P
(2) The following program outputs the difference between the set value for timer T3 and its present value in BCD to Y40 to
Y53.
[Ladder Mode] [List Mode]

Step Instruction Device

199
 D+, D+P, D-, D-P

6.2.2 D+, D+P, D-, D-P BIN 32-bit addition and subtraction operations

6.2.2 D+, D+P, D-, D-P Basic High

performance Process Redundant Universal LCPU

When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, D )-( S +1, S ) ( D +1, D ))

indicates an instruction symbol of D+/D .

Command
D+, D S D

Command
D+P, D P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 32 bits)
D : Head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

Function
D+
(1) Adds 32-bit BIN data designated by D to 32-bit BIN data designated by S , and stores the result of the addition at the
device designated by D .

D +1 D S +1 S D +1 D

b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0

567890 (BIN) 123456 (BIN) 691346 (BIN)

(2) The values for S and D can be designated at between -2147483648 and 2147483647 (BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most significant bit (b31).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.
K2147483647 +K2 K 2147483647 Since bit 31 value is "1",
(7FFFFFFFH) (00000002H) (80000001H) result of operation takes a negative value.

K 2147483648 +K 2 K2147483646 Since bit 31 value is "0",

(80000000H) (FFFFFFFEH) (7FFFFFFEH) result of operation takes a positive value.

D-
(1) Subtracts 32-bit BIN data designated by D from 32-bit BIN data designated by S and stores the result of the subtraction
at the device designated by D .
D +1 D S +1 S D +1 D

b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0

567890 (BIN) 123456 (BIN) 444434 (BIN)

(2) The values for S and D can be designated at between -2147483648 and 2147483647 (BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most significant bit (b31).
• 0: Positive
• 1: Negative

200
 D+, D+P, D-, D-P

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.
K 2147483648 K2 K2147483646 Since bit 31 value is "0", 1
(80000000H) (00000002H) (7FFFFFFEH) result of operation takes a positive value.

K2147483647 K 2 K 2147483647 Since bit 31 value is "1",

(80000000H) (FFFFFFFEH) (80000001H) result of operation takes a negative value. 2

Operation Error
3
(1) There is no operation error in the D+(P) or D-(P) instruction.

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D ))
4
indicates an instruction symbol of D+/ D .
Command
D+, D S1 S2 D

Command
D+P, D P P S1 S2 D
6
S1 : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BIN 32 bits)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BIN 32 bits)
D : Head number of the devices where the addition/subtraction operation result will be stored (BIN 32 bits) 7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
8
S2 ––
D –– ––

Function

6.2.2
6.2 Arithmetic Operation Instructions
D+

D+, D+P, D-, D-P

(1) Adds 32-bit BIN data designated by S1 to 32-bit BIN data designated by S2 , and stores the result of the addition at the
device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0

567890 (BIN) 123456 (BIN) 691346 (BIN)

(2) The values for S1 , S2 and D can be designated at between -2147483648 and 2147483647 (BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most significant bit (b31).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.
K2147483647 +K2 K 2147483647 Since bit 31 value is "1",
(7FFFFFFFH) (00000002H) (80000001H) result of operation takes a negative value.

K 2147483648 +K 2 K2147483646 Since bit 31 value is "0",

(80000000H) (FFFFFFFEH) (7FFFFFFEH) result of operation takes a positive value.

201
 D+, D+P, D-, D-P

D-
(1) Subtracts 32-bit BIN data designated by S1 from 32-bit BIN data designated by S2 and stores the result of the subtraction
at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0

567890 (BIN) 123456 (BIN) 444434 (BIN)

(2) The values for S1 , S2 and D can be designated at between -2147483648 and 2147483647 (BIN 32 bits).
(3) Judgment of whether the data is positive or negative is made on the basis of the most significant bit (b31).
• 0: Positive
• 1: Negative
(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.
K 2147483648 K2 K2147483646 Since bit 31 value is "0",
(80000000H) (00000002H) (7FFFFFFEH) result of operation takes a positive value.

K2147483647 K 2 K 2147483647 Since bit 31 value is "1",

(7FFFFFFFH) (FFFFFFFEH) (80000001H) result of operation takes a negative value.

Operation Error
(1) There is no operation error in the D+(P) or D-(P) instruction.

Program Example
(1) The following program adds 28-bit data from X10 to X2B to the data at D9 and D10 when X0 goes ON, and outputs the
result of the operation to Y30 to Y4B.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program subtracts the data from M0 to M23 from the data at D0 and D1 when XB goes ON, and stores the
result at D10 and D11.
[Ladder Mode] [List Mode]

Step Instruction Device

202
 *, *P, /, /P

6.2.3 *, *P, /, /P BIN 16-bit multiplication and division operations

6.2.3 *, *P, /, /P Basic High

performance Process Redundant Universal LCPU
1
indicates an instruction symbol of * , / .

*, /
Command
S1 S2 D
2
Command
*P, / P
3
P S1 S2 D

S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 16 bits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 16 bits)
D : Head number of the devices where the multiplication/division operation result will be stored (BIN 32 bits) 4
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

D –– ––
6
Function
* 7
(1) Multiplies BIN 16-bit data designated by S1 and BIN 16-bit data designated by S2 , and stores the result in the device
designated by D .
8
S1 S2 D D

b15 b0 b15 b0 b31 b16 b15 b0

5678 (BIN) 1234 (BIN) 7006652 (BIN)

(2) If D is a bit device, designation is made from the lower bits.

6.2.3
6.2 Arithmetic Operation Instructions
Example K1..........Lower 4 bits (b0 to b3)
K4..........Lower 16 bits (b0 to b15)

*, *P, /, /P
K8..........32 bits (b0 to b31)
(3) Values for S1 and S2 can be designated between -32768 and 32767 (BIN, 16 bits).
(4) Judgments whether S1 , S2 , and D are positive or negative are made on the basis of the most significant bit (b15 for S1 ,

and S2 , for D and b31).

• 0: Positive
• 1: Negative

203
 *, *P, /, /P

/
(1) Divides BIN 16-bit data designated by S1 and BIN 16-bit data designated by S2 , and stores the result in the device
designated by D .
Quotient Remainder
S1 S2 D D 1

b15 b0 b15 b0 b15 b0 b15 b0

5678 (BIN) 1234 (BIN) 4 (BIN) 742 (BIN)

(2) If a word device has been used, the result of the division operation is stored as 32 bits, and both the quotient and
remainder are stored; if a bit device has been used, 16 bits are used and only the quotient is stored.
Quotient: Stored at the lower 16 bits.
Remainder: Stored at the upper 16 bits (Stored only when using a word device).
(3) Values for S1 and S2 can be designated between -32768 and 32767 (BIN 16 bits).
(4) Judgment whether values for S1 , S2 , D and D +1 are positive or negative is made on the basis of the most significant bit
(b15). (Sign is attached to both the quotient and remainder.)
• 0: Positive
• 1: Negative

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

4100 The divisor is 0.

Program Example
(1) The following program multiplies "5678" by "1234" in BIN and stores the result at D3 and D4 when X5 turns ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program multiplies BIN data at X8 to XF by BIN data at X10 to X1B, and outputs the result of the
multiplication to Y30 to Y3F.
[Ladder Mode] [List Mode]
Step Instruction Device

(3) The following program divides, when X3 is turned ON, the data at X8 to XF by 3.14 and outputs the operation result at
Y30 to Y3F.
[Ladder Mode] [List Mode]

Step Instruction Device

204
 D*, D*P, D/, D/P

6.2.4 D*, D*P, D/, D/P BIN 32-bit multiplication and division operations

6.2.4 D*, D*P, D/, D/P Basic High

performance Process Redundant Universal LCPU
1
indicates an instruction symbol of D * D/ .
Command 2
D*, D/ S1 S2 D

Command
D*P, D/P P S1 S2 D
3
S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BIN 32 bits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BIN 32 bits) 4
D : Head number of the devices where the multiplication/division operation result will be stored (BIN 64 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

D –– ––
6
Function
7
D*
(1) Multiplies BIN 32-bit data designated by S1 and BIN 32-bit data designated by S2 , and stores the result in the device
designated by D . 8
S1 S1 S2 S2 D D D D
b31 b16 b15 b0 b31 b16 b15 b0 b63 b48 b47 b32 b31 b16 b15 b0
567890 (BIN) 123456 (BIN) 70109427840 (BIN)

6.2.4
6.2 Arithmetic Operation Instructions
(2) If D is a bit device, only the lower 32 bits of the multiplication result will be considered, and the upper 32 bits cannot be
designated.

D*, D*P, D/, D/P

Example K1...........Lower 4 bits (b0 to b3)
K4...........Lower 16 bits (b0 to b15)
K8...........Lower 32 bits (b0 to b31)
If the upper 32 bits of the bit device are required for the result of the multiplication operation, first temporarily store the
data in a word device, then transfer the word device data to the bit device by designating ( D +2) and ( D +3) data.
(3) The values for S1 and S2 can be designated at between -2147483648 and 2147483647 (BIN 32 bits).
(4) Judgments whether S1 , S2 , and D are positive or negative are made on the basis of the most significant bit (b31 for S1

and S2 , b63 for D ).

• 0: Positive
• 1: Negative

205
 D*, D*P, D/, D/P

D/
(1) Divides BIN 32-bit data designated by S1 and BIN 32-bit data designated by S2 , and stores the result in the device
designated by D .

S1 S1 S2 S2 D D D D
b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0 b31 b16 b15 b0
567890 (BIN) 123456 (BIN) 4 (BIN) 74066 (BIN)

(2) With a word device, the division operation result is stored in 64 bits and both the quotient and remainder are stored. With
a bit device, only the quotient is stored as the operation result in 32 bits.
Quotient : Stored at the lower 32 bits.
Remainder : Stored at the upper 32 bits (Stored only when using a word device).
(3) The values for S1 and S2 can be designated at between -2147483648 and 2147483647 (BIN 32 bits).
(4) Judgment whether values for S1 , S2 , D and D +2 are positive or negative is made on the basis of the most significant bit
(b31).
(Sign is attached to both the quotient and remainder.)
• 0: Positive
• 1: Negative

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) is turned ON, and the corresponding error
code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

4100 The divisor is 0.

Program Example
(1) The following program multiplies the BIN data at D7 and D8 by the BIN data at D18 and D19 when X5 is ON, and stores
the result at D1 to D4.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program outputs the value resulting when the data at X8 to XF is multiplied by 3.14 to Y30 to Y3F when X3
is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

206
 B+, B+P, B-, B-P

6.2.5 B+, B+P, B-, B-P BCD 4-digit addition and subtraction operations

6.2.5 B+, B+P, B-, B-P Basic High

performance Process Redundant Universal LCPU
1
When two data are set ( D + S D , D - S D )

2
indicates an instruction symbol of B+/B .
Command
B+, B S D

Command
3
B+P, B P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits) 4
D : Head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––
6
Function
B+ 7
(1) Adds the BCD 4-digit data designated by D and the BCD 4-digit data designated by S , and stores the result of the
addition at the device designated by D .
D S D
8
5 6 7 8 1 2 3 4 6 9 1 2

(2) 0 to 9999 (BCD 4 digits) can be assigned to S and D .

(3) If the result of the addition operation exceeds 9999, the higher bits are ignored.

6.2.5
6.2 Arithmetic Operation Instructions
The carry flag (SM700) in this case does not go ON.

B+, B+P, B-, B-P

6 4 3 2 3 5 8 3 0 0 1 5

B-
(1) Subtracts the BCD 4-digit data designated by S and the BCD 4-digit data designated by D , and stores the result of the
subtraction at the device designated by D .
D S D

0 6 7 8 0 2 3 4 0 4 4 4
Digits exceeding the designated
number of digits are assumed to be 0.

(2) 0 to 9999 (BCD 4 digits) can be assigned to S and D .

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag (SM700) in this case does not go ON.
0 0 0 1 0 0 0 3 9 9 9 8

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

4100 The S or D BCD data is outside the 0 to 9999 range.

207
 B+, B+P, B-, B-P

Program Example
(1) The following program adds BCD data 5678 and 1234, stores it at D993, and at the same time outputs it to from Y30 to
Y3F.
[Ladder Mode]

Stores 5678 in BCD to D993.

Adds 1234 in BCD to the value at D993,

and stores the result to D993.

Outputs the data in D993 to Y30 to Y3F.

[List Mode]

Step Instruction Device

(2) The following program subtracts the BCD data 4321 from 7654, stores the result at D10, and at the same time outputs it
to Y30 to Y3F.
[Ladder Mode]

Stores 7654 in BCD to D10.

Subtracts the value in D10 from 4321 in BCD,

and stores the result to D10.
Outputs the data in D10 to Y30 to Y3F.

[List Mode]

Step Instruction Device

When three data are set ( S1 + S2 D , S1 - S2 D )

indicates an instruction symbol of B+/B- .

Command
B+, B- S1 S2 D

Command
B+P, B-P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 4 digits)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 4 digits)
D : Head number of the devices where the addition/subtraction operation result will be stored (BCD 4 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

D –– ––

208
 B+, B+P, B-, B-P

Function
1
B+
(1) Adds the BCD 4-digit data designated by S1 and the BCD 4-digit data designated by S2 , and stores the result of the
addition at the device designated by D . 2
S1 S2 D

5 6 7 8 1 2 3 4 6 9 1 2
3
(2) 0 to 9999 (BCD 4 digits) can be assigned to S1 , S2 and D .
(3) If the result of the addition operation exceeds 9999, the higher bits are ignored.
The carry flag (SM700) in this case does not go ON. 4
6 4 3 2 3 5 8 3 0 0 1 5

B-
(1) Subtracts the BCD 4-digit data designated by S1 and the BCD 4-digit data designated by S2 , and stores the result of the
subtraction at the device designated by D .
S1 S2 D
6
0 6 7 8 0 2 3 4 0 4 4 4
Digits exceeding the designated
number of digits are assumed to be 0.
7
(2) 0 to 9999 (BCD 4 digits) can be assigned to S1 , S2 and D .
(3) The following will result if an underflow is generated by the subtraction operation: 8
The carry flag (SM700) in this case does not go ON.

0 0 0 1 0 0 0 3 9 9 9 8

Operation Error

6.2.5
6.2 Arithmetic Operation Instructions
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.

B+, B+P, B-, B-P

Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

4100 S1 or S2 BCD data is outside the 0 to 9999 range.

Program Example
(1) The following program adds the D3 BCD data and the Z1 BCD data when X20 goes ON, and outputs the result to Y8 to
Y17.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program subtracts the BCD data at D20 from the BCD data at D10 when X20 goes ON, and stores the
result at R10.
[Ladder Mode] [List Mode]

Step Instruction Device

209
 DB+, DB+P, DB-, DB-P

6.2.6 DB+, DB+P, DB-, DB-P BCD 8-digit addition and subtraction operations

6.2.6 DB+, DB+P, DB-, DB-P Basic High

performance Process Redundant Universal LCPU

When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, D )-( S +1, S ) ( D +1, D ))

indicates an instruction symbol of DB+/DB- .

Command
DB+, DB- S D

Command
DB+P, DB-P P S D

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits)
D : Head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

Function
DB+
(1) Adds the BCD 8-digit data designated by D and the BCD 8-digit data designated by S , and stores the result of the
addition at the device designated by D .
D D S S D D

(Upper 4 digits)(Lower 4 digits) (Upper 4 digits)(Lower 4 digits) (Upper 4 digits)(Lower 4 digits)

0 9 8 7 1 0 6 8 0 0 3 2 3 4 5 6 1 0 1 9 4 5 2 4

Digits exceeding the designated number

of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to S and D .

(3) If the result of the addition operation exceeds 99999999, the upper bits will be ignored.
The carry flag (SM700) in this case does not go ON.

9 9 0 0 0 0 0 0 0 1 6 5 4 3 2 1 0 0 6 5 4 3 2 1

DB-
(1) Subtracts the BCD 8-digit data designated by D and the BCD 8-digit data designated by S , and stores the result of the
subtraction at the device designated by D .
D +1 D S +1 S D +1 D

(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)
0 9 8 7 1 0 6 8 0 0 3 2 3 4 5 6 0 9 5 4 7 6 1 2

Digits exceeding the designated number

of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to S and D .

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag (SM700) in this case does not go ON.

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 9 9 9 9 9 9 9 9

210
 DB+, DB+P, DB-, DB-P

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
4100 The S or D BCD data is outside the 0 to 99999999 range.

3
Program Example
(1) The following program adds the BCD data 12345600 and 34567000, stores the result at D887 and D888, and at the 4
same time outputs them to from Y30 to Y4F.
[Ladder Mode]

Stores 12345600 in BCD to D887 and D888.

Adds 34567000 in BCD to the value in D887 and D888,

and stores the result to D887 and D888. 6
Outputs the data in D887 and D888 to Y30 to Y4F.

7
[List Mode]

Step Instruction Device

8

(2) The following program subtracts the BCD data 98765432 from 12345678, stores the result at D100 and D101, and at the
same time outputs it from Y30 to Y4F.

6.2.6
6.2 Arithmetic Operation Instructions
[Ladder Mode]

DB+, DB+P, DB-, DB-P

Stores 98765432 in BCD to D100 and D101.

Subtracts the value in D100 and D101 from 12345678

in BCD, and stores the result to D100 and D101.

Outputs the data in D100 and D101 to T30

to Y4F.

[List Mode]

Step Instruction Device

211
 DB+, DB+P, DB-, DB-P

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of DB+/ DB .

Command
DB+, DB- S1 S2 D

Command
DB+P, DB-P P S1 S2 D

S1 : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (BCD 8 digits)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (BCD 8 digits)
D : Head number of the devices where the addition/subtraction operation result is stored (BCD 8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––
D –– ––

Function
DB+
(1) Adds the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by S2 , and stores the result of the
addition at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)
5 6 7 8 9 1 2 3 + 0 1 2 3 4 5 6 7 5 8 0 2 3 6 9 0
Digits exceeding the designated number
of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to S1 , S2 and D .

(3) If the result of the addition operation exceeds 99999999, the upper bits will be ignored.
The carry flag (SM700) in this case does not go ON.

9 9 0 0 0 0 0 0 0 1 6 5 4 3 2 1 0 0 6 5 4 3 2 1

DB-
(1) Subtracts the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by S2 , and stores the result of the
subtraction at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)
5 6 7 8 9 1 2 3 0 1 2 3 4 5 6 7 5 5 5 5 4 5 5 6
Digits exceeding the designated
number of digits are assumed to be 0.

(2) 0 to 99999999 (BCD 8 digits) can be assigned to S1 , S2 and D .

(3) The following will result if an underflow is generated by the subtraction operation:
The carry flag (SM700) in this case does not go ON.

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 9 9 9 9 9 9 9 9 9

212
 B*, B*P, B/, B/P

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
4100 The S1 , S2 or D BCD data is outside the 0 to 99999999 range.

3
Program Example
(1) The following program adds the BCD data at D3 and D4 to the BCD data at Z1 and Z2 when X20 goes ON, and stores 4
the result at R10 and R11.
[Ladder Mode] [List Mode]

Step Instruction Device

6
6.2.7 B*, B*P, B/, B/P BCD 4-digit multiplication and division operations

6.2.7 B*, B*P, B/, B/P Basic High

performance Process Redundant Universal LCPU
7
indicates an instruction symbol of B * ,B/ .

B* , B/
Command 8
S1 S2 D

Command
B * P, B/P P S1 S2 D

6.2.7
6.2 Arithmetic Operation Instructions
S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 4 digits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 4 digits)

B*, B*P, B/, B/P

D : Head number of the devices where the multiplication/division operation result will be stored (BCD 8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

D –– ––

Function
B*
(1) Multiplies BCD data designated by S1 and BCD data designated by S2 , and stores the result in the device designated by
D .
D +1 D
S1 S2 (Upper 4 digits) (Lower 4 digits)

5 6 7 8 0 8 7 6 0 4 9 7 3 9 2 8

(2) 0 to 9999 (BCD 4 digits) can be assigned to S1 and S2 .

213
 B*, B*P, B/, B/P

B/
(1) Divides BCD data designated by S1 and BCD data designated by S2 , and stores the result in the device designated by D .
S1 S2 D (Quotient) D +1 (Remainder)

5 6 7 8 / 0 8 7 6 0 0 0 6 0 4 2 2
Digits exceeding the designated number of digits are
assumed to be 0.

(2) Uses 32 bits to store the result of the division as quotient and remainder
Quotient (BCD 4 digits) :Stored at the lower 16 bits.
Remainder (BCD 4 digits) :Stored at the upper 16 bits.
(3) If D has been designated as a bit device, the remainder of the operation will not be stored.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The S1 or S2 BCD data is outside the 0 to 9999 range.
4100
The divisor is 0.

Program Example
(1) The following program multiplies, when X20 is turned ON, the BCD data at X0 to XF by the BCD data at D8 and stores
the operation result at D0 to D1.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D8 D1 (Upper 4 digits) D0 (Lower 4 digits)
XF X0
9 7 5 3 8 6 4 2 8 4 2 8 5 4 2 6
Multiplicand Multiplier Multiplication result
(2) The following program divides 5678 by the BCD data 1234, stores the result at D502 and D503, and at the same time
outputs the quotient to Y30 to Y3F.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D502 D503

5 6 7 8 / 1 2 3 4 0 0 0 4 0 7 4 2
Quotient Remainder
Y3F Y30
0 0 0 4
Quotient

214
 DB*, DB*P, DB/, DB/P

6.2.8 DB*, DB*P, DB/, DB/P BCD 8-digit multiplication and division operations

6.2.8 DB*, DB*P, DB/, DB/P Basic High

performance Process Redundant Universal LCPU
1
indicates an instruction symbol of DB* , DB/.
Command 2
DB * , DB/ S1 S2 D

Command
DB * P, DB/P P S1 S2 D
3
S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (BCD 8 digits)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (BCD 8 digits) 4
D : Head number of the devices where the multiplication/division operation result will be stored (BCD 16 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

D –– –– 6
Function
7
DB*
(1) Multiplies the BCD 8-digit data designated by S1 and the BCD 8-digit data designated by S2 , and stores the product at the
device designated by D . 8
S1 +1 S1 S2 +1 S2

9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9

D +3 D +2 D +1 D

6.2.8
6.2 Arithmetic Operation Instructions
9 9 9 9 9 9 9 8 0 0 0 0 0 0 0 1

(2) If D has designated a bit device, the lower 8 digits (lower 32 bits) will be used for the product, and the higher 8 digits
(upper 32 bits) cannot be designated.

DB*, DB*P, DB/, DB/P

K1.....Lower 1 digit (b0 to 3), K4.....Lower 4 digits (b0 to 15), K8.....Lower 8 digits (b0 to 31)
(3) 0 to 99999999 (BCD 8 digits) can be assigned to S1 and S2 .

DB/
(1) Divides 8-digit BCD data designated by S1 and 8-digit BCD data designated by S2 , and stores the result in the device
designated by D .
S1 +1 S1 S2 +1 S2

5 6 7 8 9 1 2 3 / 0 1 2 3 4 5 6 7
Digits exceeding the designated number of digits
are assumed to be 0
D +1 D D +3 D +2
Quotient (Upper 4 digits) (Lower 4 digits) Remainder (Upper 4 digits) (Lower 4 digits)

0 0 0 0 0 0 4 5 0 1 2 3 3 6 0 8

(2) 64 bits are used for the result of the division operation, and stored as quotient and remainder.
Quotient (BCD 8 digits) :Stored at the lower 32 bits.
Remainder (BCD 8 digits) :Stored at the upper 32 bits.
(3) If D has been designated as a bit device, the remainder of the operation will not be stored.

215
 DB*, DB*P, DB/, DB/P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The S1 or S2 BCD data is outside the 0 to 99999999 range.
4100
The divisor is 0.

Program Example
(1) The following program multiplies the BCD data 67347125 and 573682, stores the result from D502 to D505, and at the
same time outputs the upper 8 digits to Y30 to Y4F.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D505 D504 D503 D502

6 8 3 4 7 1 2 5 0 0 5 7 3 6 8 2 0 0 3 9 2 0 9 5 1 5 3 6 4 2 5 0
Multiplicand Multiplier
Y4F Y30
0 0 3 9 2 0 9 5

(2) The following program divides the BCD data from X20 to X3F by the BCD data at D8 and D9 when X0B goes ON, and
stores the result from D765 to D768.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D9 (Upper 4 digits) D8 (Lower 4 digits)
X3F X20
9 9 8 6 4 3 2 1 / 1 5 2 6 3 7 4 8
Dividend Divisor
D766 D765 D768 D767
(Upper 4 digits) (Lower 4 digits) (Upper 4 digits) (Lower 4 digits)

0 0 0 0 0 0 0 6 0 8 2 8 1 8 3 3

Quotient Remainder

216
 E+, E+P, E-, E-P

6.2.9 E+, E+P, E-, E-P Addition and subtraction of floating-point data
(Single precision)

Ver.
Basic High
performance Process Redundant Universal LCPU 1
6.2.9 E+, E+P, E-, E-P • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

When two data are set (( D +1, D )+( S +1, S ) ( D +1, D ), ( D +1, D )-( S +1, S ) ( D +1, D ))
2

indicates an instruction symbol of E+/E- . 3

Command
E+, E- S D

E+P, E-P
Command
P S D
4

S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number)
D : Head number of the devices where the data to be added to/subtracted from is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––
6
D –– –– *1 –– ––
*1: Available only in multiple Universal model QCPU and LCPU
7
Function
E+ 8
(1) Adds the 32-bit floating decimal point type real number designated at D and the 32-bit floating decimal point type real
number designated at S , and stores the sum in the device designated at D .
D +1 D S +1 S D +1 D

6.2.9
6.2 Arithmetic Operation Instructions
+

32-bit floating-point 32-bit floating-point 32-bit floating-point

E+, E+P, E-, E-P

real number real number real number

(2) Values which can be designated at S and D and which can be stored, are as follows:
-126
0, 2 | Designated value (stored value) | < 2128
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

E-
(1) Subtracts a 32-bit floating decimal point type real number designated by D and a 32-bit floating decimal point type real
number designated by S , and stores the result at a device designated by D .
D +1 D S +1 S D +1 D

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

(2) Values which can be designated at S and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

217
 E+, E+P, E-, E-P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4100 0, 2-126 | Specified device value | < 2128 –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs):
2128 | Operation result |
The specified device value is -0, unnormalized number, nonnumeric,
4140 –– –– –– ––
and ± .

Program Example
(1) The following program adds the 32-bit floating decimal point type real numbers at D3 and D4 and the 32-bit floating
decimal point type real numbers at D10 and D11 when X20 goes ON, and stores the result at D3 and D4.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D4 D3 D11 D10 D4 D3
5961.437 12003.200 17964.637

(2) The following program subtracts the 32-bit floating decimal point type real number at D10 and D11 from the 32-bit
floating decimal point type real numbers at D20 and D21, and stores the result of the subtraction at D20 and D21.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D21 D20 D11 D10 D21 D20
97365.203 76059.797 21305.406

218
 E+, E+P, E-, E-P

When three data are set (( S1 +1, S1 )+( S2 +1, S2 ) ( D +1, D ), ( S1 +1, S1 )-( S2 +1, S2 ) ( D +1, D ))

1
indicates an instruction symbol of E+/E-.
Command
E+, E-
2
S1 S2 D

Command
E+P, E-P P S1 S2 D

3
S1 : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number)
D : Head number of the devices where the addition/subtraction operation result is stored (real number)

Setting Internal Devices J \ Constants

4
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S1 –– –– *1 ––
S2 –– –– *1 ––
D –– –– *1 –– ––
*1: Available only in multiple Universal model QCPU and LCPU
6
Function
E+ 7
(1) Adds the 32-bit floating decimal point type real number designated at S1 and the 32-bit floating decimal point type real
number designated at S2 , and stores the sum in the device designated at .
D
8
S1 +1 S1 S2 +1 S2 D +1 D
+

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

6.2.9
6.2 Arithmetic Operation Instructions
(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

E+, E+P, E-, E-P

E-
(1) Subtracts a 32-bit floating decimal point type real number designated by S1 and a 32-bit floating decimal point type real
number designated by S2 , and stores the result at a device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number
(2) Values which can be designated at S1 and S2 and D which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

219
 E+, E+P, E-, E-P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4100 0, 2-126 | Specified device value | < 2128 –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
The specified device is -0, unnormalized number, nonnumeric, and ±
4140 –– –– –– ––
.

Program Example
(1) The following program adds the 32-bit floating decimal point type real numbers at D3 and D4 and the 32-bit floating
decimal point type real numbers at D10 and D11 when X20 goes ON, and outputs the result to R0 and R1.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D4 D3 D11 D10 R1 R0
5961.437 12003.200 17964.637

(2) The following programs subtracts the 32-bit floating decimal point type real numbers at D20 and D21 from the 32-bit
floating decimal point type real numbers at D11 and D10, and stores the result at D30 and D31.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
D11 D10 D21 D20 D31 D30
97365.203 76059.797 21305.406

220
 ED+, ED+P, ED-, ED-P

6.2.10 ED+, ED+P, ED-, ED-P Addition and subtraction of floating-point data
(Double precision)

6.2.10 ED+, ED+P, ED-, ED-P Basic High

performance Process Redundant Universal LCPU 1
When two data are set (( D +3, D +2, D +1, D )+( S +3, S +2, S +1, S ) ( D +3, D +2, D +1, D ), ( D +3, D +2, D +1, D )-
( S +3, S +2, S +1, S ) ( D +3, D +2, D +1, D )) 2

Command
indicates an instruction symbol of ED+/ED-.
3
ED+, ED- S D

Command
ED+P, ED-P P S D 4
S : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number)
D : Head number of the devices where the data to be added to/subtracted from is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– –– 6
D –– –– –– ––

Function 7
ED+
(1) Adds the 64-bit floating decimal point type real number designated at D and the 64-bit floating decimal point type real 8
number designated at S , and stores the sum in the device designated at D .
D +3 D +2 D +1 D S +3 S +2 S +1 S D +3 D +2 D +1 D

6.2.10 ED+, ED+P, ED-, ED-P

6.2 Arithmetic Operation Instructions
64-bit floating-point 64-bit floating-point 64-bit floating-point
real number real number real number

(2) Values which can be designated at S and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

ED-
(1) Subtracts a 64-bit floating decimal point type real number designated by D and a 64-bit floating decimal point type real
number designated by S , and stores the result at a device designated by D .
D +3 D +2 D +1 D S +3 S +2 S +1 S D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number
(2) Values which can be designated at S and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

221
 ED+, ED+P, ED-, ED-P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The value of the specified device is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
1024
2 | Operation result |

Program Example
(1) The following program adds the 64-bit floating decimal point type real numbers at D3 to D6 and the 64-bit floating
decimal point type real numbers at D10 to D13 when X20 goes ON, and stores the result at D3 to D6.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D6 D5 D4 D3 D13 D12 D11 D10 D6 D5 D4 D3
5961.437 12003.200 17964.637

(2) The following program subtracts the 64-bit floating decimal point type real number at D10 to D13 from the 64-bit floating
decimal point type real numbers at D20 to D23, and stores the result of the subtraction at D20 to D23.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D23 D22 D21 D20 D13 D12 D11 D10 D23 D22 D21 D20
97365.203 76059.797 21305.406

222
 ED+, ED+P, ED-, ED-P

When three data are set (( S1 +3, S1 +2, S1 +1, S1 )+( S2 +3, S2 +2, S2 +1, S2 ) ( D +3, D +2, D +1, D ),
( S1 +3, S1 +2, S1 +1, S1 )-( S2 +3, S2 +2, S2 +1, S2 ) ( D +3, D +2, D +1, D ))
1
indicates an instruction symbol of ED+/ED-.

ED+, ED-
Command
S1 S2 D
2
Command
ED+P, ED-P P S1 S2 D
3
S1 : Data to be added to/subtracted from or head number of the devices where the data to be added to/subtracted from is stored (real number)
S2 : Data for adding/subtracting or head number of the devices where the data for adding/subtracting is stored (real number)
4
D : Head number of the devices where the addition/subtraction operation result is stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S1 –– –– ––
S2 –– –– ––

D –– –– –– ––
6
Function
7
ED+
(1) Adds the 64-bit floating decimal point type real number designated at S1 and the 64-bit floating decimal point type real
number designated at S2 , and stores the sum in the device designated at D . 8
S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D
+

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number

6.2.10 ED+, ED+P, ED-, ED-P

6.2 Arithmetic Operation Instructions
(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

ED-
(1) Subtracts a 64-bit floating decimal point type real number designated by S1 and a 64-bit floating decimal point type real
number designated by S2 , and stores the result at a device designated by D .
S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number
(2) Values which can be designated at S1 and S2 and D which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

223
 ED+, ED+P, ED-, ED-P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
1024
2 | Operation result |

Program Example
(1) The following program adds the 64-bit floating decimal point type real numbers at D3 to D6 and the 64-bit floating
decimal point type real numbers at D10 to D13 when X20 goes ON, and outputs the result at R0 to R3.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D6 D5 D4 D3 D13 D12 D11 D10 R3 R2 R1 R0
5961.437 12003.200 17964.637

(2) The following programs subtracts the 64-bit floating decimal point type real numbers at D20 to D23 from the 64-bit
floating decimal point type real numbers at D10 to D13, and stores the result at D30 to D33.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30
97365.203 76059.797 21305.406

224
 E*, E*P, E/, E/P

6.2.11 E*, E*P, E/, E/P Multiplication and division of floating-point data
(Single precision)

Ver.
Basic High
performance Process Redundant Universal LCPU 1
6.2.11 E*, E*P, E/, E/P • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

2
indicates an instruction symbol of E* , E/ .
Command
E* , E/ S1 S2 D
3
Command
E* P, E/P P S1 S2 D

4
S1 : Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (real number)
S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (real number)
D : Head number of the devices where the multiplication/division operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E

6
S1 –– –– *1 ––
S2 –– –– *1 ––

D –– –– *1 –– ––
*1: Available only in multiple Universal model QCPU and LCPU
7
Function
E*
8
(1) Multiplies the 32-bit floating decimal point real number designated by S1 by the 32-bit floating decimal point real number
designated by S2 and stores the operation result at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D

6.2.11 E*, E*P, E/, E/P

6.2 Arithmetic Operation Instructions
32-bit floating-point 32-bit floating-point 32-bit floating-point
real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-126 | Designated value (stored value) | < 2128

(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

E/
(1) Divides the 32-bit floating decimal point real number designated by S1 by the 32-bit floating decimal point real number
designated by S2 and stores the operation result at the device designated by D .
S1 +1 S1 S2 +1 S2 D +1 D
/

32-bit floating-point 32-bit floating-point 32-bit floating-point

real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:
-126
0, 2 | Designated value (stored value) | < 2128
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3) .

225
 E*, E*P, E/, E/P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

The specified device value is not within the following range:

0, 2-126 | Specified device value | < 2128 –– ––
4100
The specified device value is -0.

The divisor is 0. ––
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
The specified device value is -0, unnormalized number, nonnumeric,
4140 –– –– –– ––
and ± .

Program Example
(1) The following program multiplies the 32-bit floating decimal point real numbers at D3 and D4 and the 32-bit floating
decimal point real numbers at D10 and D11, and stores the result at R0 and R1.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D4 D3 D11 D10 R1 R0
36.7896 11.9278 438.8190

(2) The following program divides the 32-bit floating decimal point real numbers at D10 and D11 by the 32-bit floating
decimal point real numbers at D20 and D21, and stores the result at D30 and D31.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D11 D10 D21 D20 D31 D30
52171.39 9.73521 5359.041

226
 ED*, ED*P, ED/, ED/P

6.2.12 ED*, ED*P, ED/, ED/P Multiplication and division of floating-point data
(Double precision)

6.2.12 ED*, ED*P, ED/, ED/P Basic High

performance Process Redundant Universal LCPU 1

Command
indicates an instruction symbol of ED*, ED/.
2
ED*, ED/ S1 S2 D

3
Command
ED* P, ED/P P S1 S2 D

: Data to be multiplied/divided or head number of the devices where the data to be multiplied/divided is stored (real number)
4
S1

S2 : Data for multiplying/dividing or head number of the devices where the data for multiplying/dividing is stored (real number)
D : Head number of the devices where the multiplication/division operation result will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S1 –– –– ––
S2 –– –– ––

D –– –– –– –– 6

Function 7
ED*
(1) Multiplies the 64-bit floating decimal point real number designated by by the 64-bit floating decimal point real number
8
S1

designated by S2 and stores the operation result at the device designated by D .

S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point

6.2.12 ED*, ED*P, ED/, ED/P

6.2 Arithmetic Operation Instructions
real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

ED/
(1) Divides the 64-bit floating decimal point real number designated by S1 by the 64-bit floating decimal point real number
designated by S2 and stores the operation result at the device designated by D .
S1 +3 S1 +2 S1 +1 S1 S2 +3 S2 +2 S2 +1 S2 D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point 64-bit floating-point

real number real number real number

(2) Values which can be designated at S1 , S2 and D and which can be stored, are as follows:

0, 2-1022 | Designated value (stored value) | < 21024

(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

227
 ED*, ED*P, ED/, ED/P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
4100 The divisor is 0. –– –– –– ––
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example
(1) The following program multiplies the 64-bit floating decimal point real numbers at D3 to D6 and the 64-bit floating decimal
point real numbers at D10 to D13, and stores the result at R0 to R3.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D6 D5 D4 D3 D13 D12 D11 D10 R3 R2 R1 R0
36.7896 11.9278 438.8190

(2) The following program divides the 64-bit floating decimal point real numbers at D10 to D13 by the 64-bit floating decimal
point real numbers at D20 to D23, and stores the result at D30 to D33.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D13 D12 D11 D10 D23 D22 D21 D20 D33 D32 D31 D30
52171.39 9.73521 5359.041

228
 BK+, BK+P, BK-, BK-P

6.2.13 BK+, BK+P, BK-, BK-P BIN 16-bit data block addition and subtraction operations

6.2.13 BK+, BK+P, BK-, BK-P Basic High

performance Process Redundant Universal LCPU
1
indicates an instruction symbol of BK+, BK- .

Command 2
BK+, BK- S1 S2 D n

Command
BK+P, BK-P P S2 S2 D n 3
S1 : Head number of the devices where the data to be added to/subtracted from is stored (BIN 16 bits)
S2 : Data for additing/subtracting or head number of the devices where the data for additing/subtracting is stored (BIN 16 bits) 4
D : Head number of the devices where the operation result will be stored (BIN 16 bits)
n : Number of addition/subtraction data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– –– –– ––
S2 –– –– ––
6
D –– –– –– ––
n ––

7
Function
BK+ 8
(1) Adds n points of BIN data from the device designated by S1 and n-points of BIN data from the device designated by S2

and stores the result from the device designated by D onward.

b15 b0 b15 b0 b15 b0
S1 1234 (BIN) S2 4000 (BIN) D 5234 (BIN)

6.2.13 BK+, BK+P, BK-, BK-P

6.2 Arithmetic Operation Instructions
S1 +1 4567 (BIN) S2 +1 1234 (BIN) D +1 5801 (BIN)
S1 +2 2000 (BIN) S2 +2 1234 (BIN) D +2 3234 (BIN)
n n n
S1 +(n 2) 1234 (BIN) S2 +(n 2) 5000 (BIN) D +(n 2) 3766 (BIN)
S1 +(n 1) 4000 (BIN) S2 +(n 1) 4321 (BIN) D +(n 1) 8321 (BIN)

(2) Block addition is performed in 16-bit units.

(3) The constant designated by S2 can be between 32768 and 32767 (BIN 16-bit data).
b15 b0 b15 b0
S1 1234 (BIN) D 5555 (BIN)
S1 +1 4567 (BIN) D +1 8888 (BIN)
b15 b0
S1 +2 2000 (BIN) D +2 2321 (BIN)
S2 4321 (BIN)
n n
S1 +(n 2) 1234 (BIN) D +(n 2) 3087 (BIN)
S1 +(n 1) 4000 (BIN) D +(n 1) 8321 (BIN)

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.

K32767 +K2 K 32767

(7FFFH) (0002H) (8001H)

K 32767 +K 2 K32767
(8001H) (FFFEH) (7FFFH)

229
 BK+, BK+P, BK-, BK-P

BK-
(1) Subtracts n points of BIN data from the device designated by S1 and n-points of BIN data from the device designated by
S2 and stores the result from the device designated by D onward.
b15 b0 b15 b0 b15 b0
S1 8765 (BIN) S2 1234 (BIN) D 7531 (BIN)
S1 +1 8888 (BIN) S2 +1 5678 (BIN) D +1 3210 (BIN)
S1 +2 9325 (BIN) S2 +2 9876 (BIN) D +2 551 (BIN)
n n n
S1 +(n 2) 5000 (BIN) S2 +(n 2) 4321 (BIN) D +(n 2) 679 (BIN)
S1 +(n 1) 4352 (BIN) S2 +(n 1) 4000 (BIN) D +(n 1) 352 (BIN)

(2) Block subtraction is performed in 16-bit units.

(3) The constant designated by S2 can be between 32768 and 32767 (BIN 16-bit data).
b15 b0 b15 b0
S1 8765 (BIN) D 115 (BIN)
S1 +1 8888 (BIN) D +1 8 (BIN)
b15 b0
S1 +2 9325 (BIN) 8880 (BIN) D +2 445 (BIN)
S2
n n
S1 +(n 2) 5000 (BIN) D +(n 2) 3880 (BIN)
S1 +(n 1) 4352 (BIN) D +(n 1) 4528 (BIN)

(4) The following will happen when an underflow or overflow is generated in an operation result:
The carry flag (SM700) in this case does not go ON.

K 32768 K2 K32766
(8000H) (0002H) (7FFEH)

K32767 K 2 32767
(7FFFH) (FFFEH) (8001H)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
specified in S1 , S2 , or D .
The ranges of devices starting from the one specified in S1 and D

overlap by n points (except when the same device is specified in S1 and

4101
D ).
The ranges of devices starting from the one specified in S2 and D

overlap by n points (except when the same device is specified in S2 and

D ).

230
 DBK+, DBK+P, DBK-, DBK-P

Program Example
1
(1) The following program adds, when X20 is turned ON, the data stored at D100 to D103 to the data stored at R0 to R3 and
stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
[Operation]
b15 b0 b15 b0 b15 b0 4
D100 6789 (BIN) R0 1234 (BIN) D200 8023 (BIN)
D101 7821 (BIN) R1 2032 (BIN) D201 9853 (BIN)
D102 5432 (BIN) R2 3252 (BIN) D202 2180 (BIN)
D103 3520 (BIN) R3 1000 (BIN) D203 2520 (BIN)

D0 4

(2) The following program subtracts, when X1C is turned ON, the constant 8765 from the data at D100 to D102 and stores
the operation result into the area starting from R0.
6
[Ladder Mode] [List Mode]

Step Instruction Device 7

[Operation]
8
b15 b0 b15 b0
D100 12345 (BIN) b15 b0 R0 3580 (BIN)
D101 8701 (BIN) 8765 (BIN) R1 64 (BIN)
D102 3502 (BIN) R2 5263 (BIN)

6.2.14 DBK+, DBK+P, DBK-, DBK-P

6.2 Arithmetic Operation Instructions
6.2.14 DBK+, DBK+P, DBK-, BIN 32-bit data block addition and subtraction operations
DBK-P

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

6.2.14 DBK+, DBK+P, DBK-, DBK-P digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

indicates an instruction symbol of DBK+, DBK- .

Command
DBK+,DBK- S1 S2 D n

Command
DBKP+,DBK-P P S1 S2 D n

S1 : Head number of the devices where the data to be added and subtracted are stored (BIN 32 bits)
S2 : Addition and subtraction data or head number of the devices where the addition and subtraction data are stored (BIN 32 bits)
D : Head number of the devices where the addition and subtraction operation result will be stored (BIN 32 bits)
n : Number of addition and subtraction data blocks (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K,H
S1 –– –– –– ––
S2 –– –– ––

D –– –– –– ––
n –– ––

231
 DBK+, DBK+P, DBK-, DBK-P

Function
DBK+
(1) This instruction adds BIN 32-bit data stored in n-point devices starting from the device specified by S1 to BIN 32-bit data
stored in n-point devices starting from the device specified by S2 or a constant. and then stores the operation result into
the nth device specified by D and up,
When a device is specified for S2

b31 b0 b31 b0 b31 b0

S1 +1, S1 -30000 (BIN) S2 +1, S2 50000 (BIN) D +1, D 20000 (BIN)
S1 +3, S1 +2 40000 (BIN) S2 +3, S2 +2 20000 (BIN) D +3, D +2 60000 (BIN)
S1 +5, S1 +4 -50000 (BIN) n + S2 +5, S2 +4 -10000 (BIN) n D +5, D +4 -60000 (BIN) n

S1 +(2n-1), S1 +(2n-2) 60000 (BIN) S2 +(2n-1), S2 +(2n-2) -20000 (BIN) D +(2n-1), D +(2n-2) 40000 (BIN)

When a constant is specified for S2

b31 b0 b31 b0
S1 +1, S1 -30000 (BIN) D +1, D 20000 (BIN)
S1 +3, S1 +2 40000 (BIN) b31 b0 D +3, D +2 90000 (BIN)
S1 +5, S1 +4 -50000 (BIN) n + S2 +1, S2 50000 (BIN) D +5, D +4 0 (BIN) n

S1 +(2n-1), S1 +(2n-2) 60000 (BIN) D +(2n-1), D +(2n-2) 110000 (BIN)

(2) Block addition is executed in 32-bit units.

(3) The constant in the device specified by S2 can be between 2147483648 to 2147483647 (BIN 32-bit data).
(4) If the value specified by n is 0, the instruction will be not processed.
The following will happen if an overflow occurs in an operation result:
The carry flag (SM700) in this case does not go ON.

K2147483647+K2 K 2147483647
(7FFFFFFFH) (00000002H ) ( 80000001H)

K 2147483647 +K 2 K2147483647
(5) (80000001H) ( FFFFFFFEH) (7FFFFFFFH)

DBK-
(1) This instruction subtracts BIN 32-bit data stored in the n-point devices starting from the device specified by S2 or a
constant from BIN 32-bit data stored in n-point devices starting from the device specified by S1 , and then stores the
operation result into the nth device specified by D and up,
When a device is specified for S2

b31 b0 b31 b0 b31 b0

S1 +1, S1 -55555 (BIN) S2 +1, S2 44445 (BIN) D +1, D -1000000 (BIN)
S1 +3, S1 +2 33333 (BIN) S2 +3, S2 +2 3333 (BIN) D +3, D +2 30000 (BIN)
S1 +5, S1 +4 44444 (BIN) n - S2 +5, S2 +4 -10000 (BIN) n D +5, D +4 54444 (BIN) n

S1 +(2n-1), S1 +(2n-2) 13579 (BIN) S2 +(2n-1), S2 +(2n-2) 12345 (BIN) D +(2n-1), D +(2n-2) 1234 (BIN)

When a constant is specified for S2

b31 b0 b31 b0
S1 +1, S1 -99999 (BIN) D +1, D -109998 (BIN)
S1 +3, S1 +2 99999 (BIN) b31 b0 D +3, D +2 90000 (BIN)
S1 +5, S1 +4 -59999 (BIN) n - S2 +1, S2 9999 (BIN) D +5, D +4 69998 (BIN) n

S1 +(2n-1), S1 +(2n-2) 79999 (BIN) D +(2n-1), D +(2n-2) 70000 (BIN)

(2) Block subtraction is executed in 32-bit units.

(3) The constant in the device specified by S2 can be between 2147483648 to 2147483647 (BIN 32-bit data).
(4) If the value specified by n is 0, the instruction will be not processed.

232
 DBK+, DBK+P, DBK-, DBK-P

(5) D specifies out of the range of n-point devices starting from the device specified by S1 and S2 .

However, S1 and S2 can specify the same device.

The following will happen if an overflow occurs in an operation result: 1
The carry flag (SM700) in this case does not go ON.

K2147483647 K 2 K 2147483647
(7FFFFFFFH) (00000002 H ) ( 80000001H) 2
K 2147483647 K2 K2147483647
(80000001H) ( FFFFFFFEH ) ( 7FFFFFFFH ) 3

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 A negative value is specified for n.
The points specified in n exceed those of the corresponding device
6
specified in S1 , S2 , or D .
The ranges of devices starting from the one specified in and
7
S1 D

overlap by n points (except when the same device is specified in S1 and

4101
D ).
The ranges of devices starting from the one specified in and
8
S2 D

overlap by n points (except when the same device is specified in S2 and

D ).

Program Example

6.2.14 DBK+, DBK+P, DBK-, DBK-P

6.2 Arithmetic Operation Instructions
(1) The following program adds the value data stored at R0 to R5 to the constant, and then stores the operation result into
D30 to D35, when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b31 b0 b31 b0
R1,R0 600000 D31,D30 723456
R3,R2 -800000 + 123456 D33,D32 -676544
R5,R4 -123456 D35,D34 0

(2) The following program subtracts the value data stored at D50 to D59 from the value data stored at D100 to D109, and
then stores the operation result into R100 to R109, when M0 is turned on.
[Ladder Mode] [List Mode]
Step Instruction Device

233
 $+, $+P

[Operation]
b31 b0 b31 b0 b31 b0
D101,D100 12345 D51,D50 11111 R101,R100 1234
D103,D102 54321 D53,D52 -11111 R103,R102 65432
D105,D104 -12345 D55,D54 22222 R105,R104 -34567
D107,D106 -54321 D57,D56 -22222 R107,R106 -32099
D109,D108 99999 D58,D58 33333 R109,R108 66666

6.2.15 $+, $+P Linking character strings

6.2.15 $+, $+P Basic High

performance Process Redundant Universal LCPU

When two data are set ( D + S D )

Command
$+ $+ S D

Command
$+P $+P S D

S : Data for linking or head number of the devices where the data for linking is stored (character string)
D : Head number of the devices where the data to be linked is stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $
S –– –– ––

D –– –– –– ––

Function
(1) Links the character string data designated by S after the character string data designated by D and stores the result into
the area starting with the device number designated by D .
The object of character string data is that character string data stored from device numbers designated at D and S to
that stored at "00H".

b15 b8 b7 b0 b15 b8 b7 b0 b15 b8 b7 b0

D 42H (B) 41H (A) S 32H (2) 31H (1) 42H (B) 41H (A)
D +1 44H (D) 43H (C) S +1 34H (4) 33H (3) D +1 44H (D) 43H (C)
D +2 00H 45H (E) S +2 36H (6) 35H (5) D +2 31H (1) 45H (E)
S +3 00H D +3 33H (3) 32H (2)
"ABCDE"
D +4 35H (5) 34H (4)
"123456"
D +5 00H 36H (6)
"ABCDE123456"

(2) When character strings are linked, the "00H", which indicates the end of character string data designated at D , is
ignored, and the character string designated at S is appended to the last character of the D string.

234
 $+, $+P

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The number of device points starting from the device specified in D is
insufficient to store all character strings. 3
4101 The storage device numbers for the character strings specified by S

and D overlap.
The number of characters of S and D exceeds 16383. 4

Program Example
(1) The following program links the character string stored from D10 to D12 to the character string "ABCD" when X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device 6

7
[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D10 62 H (b) 61H (a)
+
D10 62 H (b) 61H (a) 8
D11 64 H (d) 63 H (c) "ABCD" D11 64 H (d) 63 H (c)
D12 00H 65 H (e) D12 41H (A) 65 H (e)
D13 43H (C) 42H (B)
D14 00H 44H (D)

6.2.15 $+, $+P

6.2 Arithmetic Operation Instructions
Automatically stores "00H".

When three data are set ( S1 + S2 D )

Command
$+ $+ S1 S2 D

Command
$+P $+P S1 S2 D

S1 : Data for linking or head number of the devices where the data for linking is stored (character string)
S2 : Data to be linked or head number of the devices where the data to be linked is stored (character string)
D : Head number of the devices where the linking result will be stored (character string)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $
S1 –– –– ––
S2 –– –– ––

D –– –– –– ––

235
 $+, $+P

Function
(1) Links the character string data designated by S2 after the character string data designated by S1 and stores the result into
the area starting with the device number designated by D .
b15 b8 b7 b0 b15 b8 b7 b0 b15 b8 b7 b0
S1 46H (F) 48H (H) S2 35H (5) 31H (1) D 46H (F) 48H (H)
S1 +1 2DH ( ) 41H (A) S2 +1 39H (9) 33H (3) D +1 2DH ( ) 41H (A)
S1 +2 00H S2 +2 00H 41H (A) D +2 35H (5) 31H (1)
D +3 39H (9) 33H (3)
D +4 00H 41H (A)

(2) When character strings are linked, the "00H" which indicates the end of character string data indicated by S1 , is ignored,
and the character string indicated by S2 is appended to the last character of the S1 string.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The number of device points starting from the device specified in D is
insufficient to store all character strings.
The storage device numbers for the character strings specified by S1

4101 and S2 overlap.

The storage device numbers for the character strings specified by S2

and D overlap.
The number of characters of S1 , S2 and D exceeds 16383.

Program Example
(1) The following program links the character string stored from D10 to D12 with the character string "ABCD" when X0 is
ON, and stores them in D100 onwards.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D10 62 H (b) 61 H (a) D100 62 H (b) 61H (a)
D11 64 H (d) 63 H (c) + "ABCD" D101 64 H (d) 63 H (c)
D12 00H 65 H (e) D102 41H (A) 65 H (e)
D103 43H (C) 42H (B)
D104 00H 44H (D)

Automatically stores "00H".

236
 INC, INCP, DEC, DECP

6.2.16 INC, INCP 16-bit BIN data increment

6.2.16
DEC, DECP 16-bit BIN data decrement

INC, INCP, DEC, DECP Basic High

Process Redundant Universal LCPU
1
performance

indicates an instruction symbol of INC/DEC.

Command
2
INC, DEC D

Command
INCP, DECP P D 3
D : Head number of devices for INC (+1)/DEC (-1) operation (BIN 16 bits)

Setting Internal Devices

R, ZR
J \
U \G Zn Constants Other
4
Data Bit Word Bit Word
D ––

Function
INC 6
(1) Adds 1 to the device designated by D (16-bit data).
D D

b15 b0 b15 b0
7
5678 (BIN) 5679 (BIN)

(2) When INC/INCP operation is executed for the device designated by , whose content is 32767, the value -32768 is
D
8
stored at the device designated by D .

DEC
(1) Subtracts 1 from the device designated by D (16-bit data).

6.2.16 INC, INCP, DEC, DECP

6.2 Arithmetic Operation Instructions
D D

b15 b0 b15 b0
5678 (BIN) 1 5677 (BIN)

(2) When DEC/DECP operation is executed for the device designated by D , whose content is -32768, the value 32767 is
stored at the device designated by D .

Operation Error
(1) There is no operation error in the INC(P) or DEC(P) instruction.

Program Example
(1) The following program outputs the present value at the counter C0 to C20 to the area Y30 to Y3F in BCD, every time X8
is turned ON. (When present value is less than 9999)
[Ladder Mode]

Outputs the present value of (0+Z1) to

Y30 to Y3F in BCD.
Executes Z1 + 1.

Sets Z1 at "0" when Z1=21 or X7

(reset input) is ON.

237
 DINC, DINCP, DDEC, DDECP

[List Mode]

Step Instruction Device

(2) The following is a down counter program.

[Ladder Mode]

Transfers 100 to D8 when X7 goes ON.

In the state M38=OFF, decrement at D8 (D8 - 1) is

executed when X8 goes from OFF to ON.
At D8=0, M38 goes ON.

[List Mode]
Step Instruction Device

6.2.17 DINC, DINCP 32-bit BIN data increment

6.2.17
DDEC, DDECP 32-bit BIN data decrement

DINC, DINCP, DDEC, DDECP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of DINC/DDEC.

Command
DINC, DDEC D

Command
DINCP, DDECP P D

D : Head number of devices for DINC(+1) or DDEC(-1) operation (BIN 32 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D ––

Function
DINC
(1) Adds 1 to the device designated by D (32-bit data).
D +1 D D +1 D

b31 b16 b15 b0 b31 b16 b15 b0

73500 (BIN) 73501 (BIN)

(2) When DINC/DINCP operation is executed for the device designated by D , whose content is 2147483647, the value
-2147483648 is stored at the device designated by D .

238
 DINC, DINCP, DDEC, DDECP

DDEC
(1) Subtracts -1 from the device designated by (32-bit data).
1
D

D +1 D D +1 D

b31 b16 b15 b0 b31 b16 b15 b0

73500 (BIN) 1 73499 (BIN)
2
(2) When DDEC/DDECP operation is executed for the device designated by D , whose content is 0, the value -1 is stored at
the device designated by D .
3
Operation Error
(1) There is no operation error in the DINC(P) or DDEC(P) instruction.
4
Program Example
(1) The following program adds 1 to the data at D0 and D1 when X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device 6

(2) The following program adds 1 to the data set at X10 to X27 when X0 goes ON, and stores the result at D3 and D4.
7
[Ladder Mode] [List Mode]

Step Instruction Device 8

6.2.17 DINC, DINCP, DDEC, DDECP

6.2 Arithmetic Operation Instructions
(3) The following program subtracts 1 from the data at D0 and D1 when X0 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program subtracts 1 from the data set at X10 to X27 when X0 goes ON, and stores the result at D3 and D4.
[Ladder Mode] [List Mode]
Step Instruction Device

239
 BCD, BCDP, DBCD, DBCDP

6.3 Data conversion instructions

6.3.1 BCD, BCDP Conversion from BIN data to BCD 4-digit data

6.3.1
DBCD, DBCDP Conversion from BIN data to BCD 8-digit data

BCD, BCDP, DBCD, DBCDP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of BCD/DBCD.

Command
BCD, DBCD S D

Command
BCDP, DBCDP P S D

S : BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits)
D : Head number of the devices where BCD data will be stored (BCD 4/8 digits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

Function
BCD
Converts BIN data (0 to 9999) at the device designated by S to BCD data, and stores it at the device designated by D .
-32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
S BIN 9999 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1
Must always be "0". BCD conversion
8000 4000 2000 1000 800 400 200 100 80 40 20 10 8 4 2 1
D BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Thousands digits Hundreds digits Tens digits Ones digits

DBCD
Converts BIN data (0 to 99999999) at the device designated by S to BCD data, and stores it at the device designated by D .
S +1 (Upper 16 bits) S (Lower 16 bits)
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20

S BIN 99999999 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1

Must always be "0" (upper 5 digits). BCD conversion

107

106

105

104

103

102

101

100
1

1
8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

D BCD 99999999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Ten Millions Hundred Ten Thousands Hundreds Tens Ones

millions digits thousands thousands digits digits digits digits
digits digits digits

D +1 (Upper 4 digits) D (Lower 4 digits)

240
 BCD, BCDP, DBCD, DBCDP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The data of S is other than 0 to 9999 when the BCD instruction is
4100
executed. 3
The data of S or S +1 is other than 0 to 99999999 when the DBCD
4100
instruction is executed.

4
Program Example
(1) The following program outputs the present value of C4 from Y20 to Y2F to the BCD display device.

Programmable Controller Output Module

COM

Y2D
Y2C
Y2E

Y2B
Y2A
Y2F

Y29
Y28

Y27
Y26
Y25
Y24

Y23
Y22
Y21
Y20
6
8000
4000
2000
1000

1
800
400
200
100

80
40
20
10

2
8
4

Output
power supply 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
7

8
7-segment display unit

[Ladder Mode] [List Mode]

Step Instruction Device

6.3.1
6.3 Data conversion instructions
BCD, BCDP, DBCD, DBCDP
(2) The following program outputs 32-bit data from D0 to D1 to Y40 to Y67.

Programmable Controller Output Module

Y67 to Y64 Y63 to Y60 Y5F to Y5C Y5B to Y58 Y57 to Y54 Y53 to Y50 Y4F to Y4C Y4B to Y48 Y47 to Y44 Y43 to Y40
Output
power supply

7-segment display unit

[Ladder Mode] [List Mode]

Step Instruction Device

241
 BIN, BINP, DBIN, DBINP

6.3.2 BIN, BINP Conversion from BCD 4-digit data to BIN data

6.3.2
DBIN, DBINP Conversion from BCD 8-digit data to BIN data

BIN, BINP, DBIN, DBINP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of BIN/DBIN.

Command
BIN, DBIN S D

Command
BINP, DBINP P S D

S : BCD data or head number of the devices where the BCD data is stored (BCD 4/8 digits)
D : Head number of the devices where BIN data will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

Function
BIN
Converts BCD data (0 to 9999) at device designated by S to BIN data, and stores at the device designated by D .
8000 4000 2000 1000 800 400 200 100 80 40 20 10 8 4 2 1
S BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Thousands digits Hundreds digits Tens digits Ones digits

BIN conversion
32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1
D BIN 9999 0 0 1 0 0 1 1 1 0 0 0 0 1 1 1 1
Always filled with 0s.

DBIN
Converts BCD data (0 to 99999999) at device designated by S to BIN data, and stores at the device designated by D .
S +1 S
107

106

105

104

103

102

101

100
1

1
8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

8
4
2

S BCD 99999999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

Ten Millions Hundred Ten Thousands Hundreds Tens Ones

millions digits thousands thousands digits digits digits digits
digits digits digits
BIN conversion
D +1 D
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
29
28
27
26
25
24
23
22
21
20

D BIN 99999999 0 0 0 0 0 1 0 1 1 1 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1

Always filled with 0s.

242
 BIN, BINP, DBIN, DBINP

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
4100 When values other than 0 to 9 are specified to any digits of S .

The error above can be suppressed by turning ON SM722. 3

However, the instruction is not executed regardless of whether SM722 is turned ON or OFF if the designated value is out
of the available range.
For the BINP/DBINP instruction, the next operation will not be performed until the command (execution condition) is 4
turned from OFF to ON regardless of the presence/absence of an error.

Program Example
(1) The following program converts the BCD data at X10 to X1B to BIN when X8 is ON, and stores it at D8.

BCD digital switch

6
Can be used
COM

COM

COM
in other purposes.
7
1
80
40

2
400

20

4
800

200

10
100

Input
power supply
0
0

0
0

0
1
1

1
0

0
COM

X1D
X1C
X1E

X1B
X1A
X1F

X19
X18

X17
X16
X15
X14

X13
X12
X11
X10

Programmable Controller input module

8
[Ladder Mode] [List Mode]

Step Instruction Device

6.3.2
6.3 Data conversion instructions
(2) The following program converts the BCD data at X10 to X37 to BIN when X8 is ON, and stores it at D0 and D1.

BIN, BINP, DBIN, DBINP

(Addition of the BIN data converted from BCD at X20 to X37 and the BIN data converted from BCD at X10 to X1F)
BCD digital switch

Input power supply

X37 to X34 X33 to X30 X2F to X2C X2B to X28 X27 to X24 X23 to X20 X1F to X1C X1B to X18 X17 to X14 X13 to X10

Programmable Controller Output Module

[Ladder Mode] [List Mode]

Step Instruction Device

If the data set at X10 to X37 is a BCD value which exceeds 2147483647, the value at D0 and D1 will be a negative value,
because it exceeds the range of numerical values that can be handled by a 32-bit device.

243
 FLT, FLTP, DFLT, DFLTP

6.3.3 FLT, FLTP Conversion from BIN 16-bit data to floating-point data
(Single precision)
DFLT, DFLTP Conversion from BIN 32-bit data to floating-point data
(Single precision)

Ver.
High
Basic performance Process Redundant Universal LCPU

6.3.3 FLT, FLTP, DFLT, DFLTP • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

indicates an instruction symbol of FLT/DFLT.

Command
FLT, DFLT S D

Command
FLTP, DFLTP P S D

S : Integer data to be converted to 32-bit floating decimal point data or head number of the devices where the integer data is stored (BIN 16/32 bits)
D : Head number of the devices where the converted 32-bit floating decimal point data will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– –– *1 –– ––
*1: Available only in multiple Universal model QCPU and LCPU

Function
FLT
(1) Converts 16-bit BIN data designated by S to 32-bit floating decimal point type real number, and stores at device number
designated by D .
S D +1 D
BIN 16 bits

32-bit floating-point
real number
(2) BIN values between -32768 to 32767 can be designated by S .

DFLT
(1) Converts 32-bit BIN data designated by S to 32-bit floating decimal point type real number, and stores at device number
designated by D .
S +1 S D +1 D
Upper 16 bits Lower 16 bits

BIN 32 bits 32-bit floating-point

real number
(2) BIN values between -2147483648 to 2147483647 can be designated by S +1 and S .

244
 FLT, FLTP, DFLT, DFLTP

(3) Due to the fact that 32-bit floating decimal point type real numbers are processed by simple 32-bit processing, the
number of significant digits is 24 bits if the display is binary and approximately 7 digits if the display is decimal.
For this reason, if the integer exceeds the range of -16777216 to 16777215 (24-bit BIN value), errors can be generated 1
in the conversion value.
As for the conversion result, the 25th bit from the upper bit of the integer is always filled with 1 and 26th bit and later bits
are truncated. 2
Integer After conversion
b31 b24 b23 b16 b15 b8 b7 b0

3
222030030 0 0 0 0 1 1 0 1 0 0 1 1 1 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 1 1 1 0 Result of operation
is 222030032.
Truncation
Always filled with 1
b31 b24 b23 b16 b15 b8 b7 b0
372588919 0 0 0 1 0 1 1 0 0 0 1 1 0 1 0 1 0 1 0 0 0 0 0 1 0 1 1 1 0 1 1 1 Result of operation 4
is 372588928.
Truncation
Always filled with 1

Operation Error
(1) There is no operation error in the FLT(P) or DFLT(P) instruction.
6

Program Example 7
(1) The following program converts the BIN 16-bit data at D20 to a 32-bit floating decimal point type real number and stores
the result at D0 and D1.
[Ladder Mode] [List Mode] 8
Step Instruction Device

6.3.3
6.3 Data conversion instructions
[Operation]
Integer

FLT, FLTP, DFLT, DFLTP

D20 conversion D1 D0
15923 15923
BIN value 32-bit floating-point
real number

(2) The following program converts the BIN 32-bit data at D20 and D21 to a 32-bit floating decimal point type real number,
and stores the result at D0 and D1.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Integer
D21 D20 D1 D0
conversion
16543521 16543521
BIN value 32-bit floating-point
Integer real number
D21 D20
conversion An error is generated in operation results since
173963112
the number of significant digits is "7".
BIN value D1 D0
173963120
32-bit floating-point
real number

245
 FLTD, FLTDP, DFLTD, DFLTDP

6.3.4 FLTD, FLTDP Conversion from BIN 16-bit data to floating-point data
(Double precision)
DFLTD, DFLTDP Conversion from BIN 32-bit data to floating-point data
(Double precision)

6.3.4 FLTD, FLTDP, DFLTD, DFLTDP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of FLTD/DFLTD.

Command
FLTD, DFLTD S D

Command
FLTDP, DFLTDP P S D

S : Integer data to be converted to 64-bit floating decimal point data or head number of the devices where the integer data is stored (BIN 16/32 bits)
D : Head number of the devices where the converted 64-bit floating decimal point data will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– –– –– ––

Function
FLTD
(1) Converts 16-bit BIN data designated by S to 64-bit floating decimal point type real number, and stores at device number
designated by D .
S D +3 D +2 D +1 D
BIN 16 bits

64-bit floating-point
real number

(2) BIN values between -32768 to 32767 can be designated by S .

DFLTD
(1) Converts 32-bit BIN data designated by S to 64-bit floating decimal point type real number, and stores at device number
designated by D .
S +1 S D +3 D +2 D +1 D
Upper 16 bits Lower 16 bits

BIN 32 bits 64-bit floating-point

real number

(2) BIN values between -2147483648 to 2147483647 can be designated by S +1 and S .

Operation Error
(1) There is no operation error in the FLT(P) or DFLT(P) instruction.

Program Example
(1) The following program converts the BIN 16-bit data at D20 to a 64-bit floating decimal point type real number and stores
the result at D0 to D3.
[Ladder Mode] [List Mode]

Step Instruction Device

246
 INT, INTP, DINT, DINTP

[Operation]
D20 Conversion to real number D3 D2 D1 D0
15923 15923 1
BIN value 64-bit floating-point
real number

(2) The following program converts the BIN 32-bit data at D20 and D21 to a 64-bit floating decimal point type real number, 2
and stores the result at D0 to D3.
[Ladder Mode] [List Mode]
Step Instruction Device 3

4
[Operation]

D21 D20 Conversion to real number D3 D2 D1 D0

16543521 16543521
BIN value 64-bit floating-point
real number

6.3.5 INT, INTP

DINT, DINTP
Conversion from floating-point data to BIN 16-bit data
(Single precision)
Conversion from floating-point data to BIN 32-bit data
(Single precision)
6
Ver.
High
Basic performance Process Redundant Universal LCPU

6.3.5 INT, INTP, DINT, DINTP • Basic model QCPU: The serial number (first five digits) is
"04122" or later.
7
indicates an instruction symbol of INT/DINT.

Command
8
INT, DINT S D

Command
INTP, DINTP P S D

6.3.5
6.3 Data conversion instructions
S : 32-bit floating decimal point data to be converted to BIN value or head number of the devices where the floating decimal point data is stored (real number)
D : Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits)

INT, INTP, DINT, DINTP

Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––

D –– ––
*1: Available only in multiple Universal model QCPU and LCPU

Function
INT
(1) Converts the 32-bit floating decimal point real number designated at S into BIN 16-bit data and stores it at the device
number designated at D .
S +1 S D
BIN16-bit

32-bit floating-point
real number

(2) The range of 32-bit floating decimal point type real numbers that can be designated at S +1 or S is from -32768 to
32767.
(3) Stores integer values stored at D as BIN 16-bit values.
(4) After conversion, the first digit after the decimal point of the real number is rounded off.
(5) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

247
 INT, INTP, DINT, DINTP

DINT
(1) Converts 32-bit floating decimal point type real number designated by S to BIN 32-bit data, and stores the result at the
device number designated by D .
S +1 S D +1 D
Upper 16 bits Lower 16 bits

32-bit floating-point BIN 32 bits

real number

(2) The range of 32-bit floating decimal point type real numbers that can be designated at S +1 or S is from -2147483648 to
2147483647.
(3) The integer value stored at D +1 and D is stored as BIN 32 bits.
(4) After conversion, the first digit after the decimal point of the real number is rounded off.
(5) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .
The 32-bit floating point data specified by S when the INT instruction is
4100
used is outside the -32768 to 32767 range.

The 32-bit floating point data specified by S when the DINT instruction
4100
is used is outside the -2147483648 to 2147483647 range.

Program Example
(1) The following program converts the 32-bit floating decimal point type real number at D20 and D21 to BIN 16-bit data, and
stores the result at D0.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

D21 D20 Integer D0

conversion
25915.6796 25916
32-bit floating-point BIN value
real number
D21 D20 Integer
conversion
-33562.3211 An operation error occurs
since "setting data < -32768."
32-bit floating-point
real number

248
 INTD, INTDP, DINTD, DINTDP

(2) The following program converts the 32-bit floating decimal point type real number at D20 and D21 to BIN 32-bit data and
stores the result at D0 and D1.
[Ladder Mode] [List Mode] 1
Step Instruction Device

2
[Operation]

D21 D20
Integer
D1 D0
3
conversion
-574968.321 -574968
32-bit floating-point BIN value
real number 4
Integer
D21 D20 conversion
2147483649.22 An operation error occurs
since "setting data > 2147483647."
32-bit floating-point
real number

6
6.3.6 INTD, INTDP Conversion from floating-point data to BIN 16-bit data
(Double precision)
DINTD, DINTDP Conversion from floating-point data to BIN 32-bit data
(Double precision)

6.3.6 INTD, INTDP, DINTD, DINTDP Basic High

performance Process Redundant Universal LCPU

7
indicates an instruction symbol of INTD/DINTD.

Command
INTD, DINTD S D
8
Command
INTDP, DINTDP P S D

S : 64-bit floating decimal point data to be converted to BIN value or head number of the devices where the floating decimal point data is stored (real number)

6.3.6
6.3 Data conversion instructions
D : Head number of the devices where the converted BIN value will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other

INTD, INTDP, DINTD, DINTDP

Data Bit Word Bit Word E
S –– –– –– ––

D –– –– –– ––

Function
INTD
(1) Converts the 64-bit floating decimal point real number designated at S into BIN 16-bit data and stores it at the device
number designated at D .
S +3 S +2 S +1 S D
BIN 16 bit

64-bit floating-point
real number

(2) The range of 64-bit floating decimal point type real numbers that can be designated at S +3, S +2, S +1 or S is from
-32768 to 32767.
(3) Stores integer values stored at D as BIN 16-bit values.
(4) The converted data is the value rounded 64-bit floating-point real number to the first digit after the decimal point.
(5) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

249
 INTD, INTDP, DINTD, DINTDP

DINTD
(1) Converts 64-bit floating decimal point type real number designated by S to BIN 32-bit data, and stores the result at the
device number designated by D .
S +3 S +2 S +1 S D +1 D
Upper 16 bits Lower 16 bits

64-bit floating-point BIN 32 bit

real number

(2) The range of 64-bit floating decimal point type real numbers that can be designated at S +3, S +2, S +1 or S is from
-2147483648 to 2147483647.
(3) The integer value stored at D +1 and D is stored as BIN 32 bits.
(4) The converted data is the value rounded 64-bit floating-point real number to the first digit after the decimal point.
(5) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
0, 2-1022 | Specified device value | < 21024
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .
The 64-bit floating point data specified by S when the INTD instruction
4100 –– –– –– ––
is used is outside the -32768 to 32767 range.

The 64-bit floating point data specified by S when the DINTD

4100 –– –– –– ––
instruction is used is outside the -2147483648 to 2147483647 range.

Program Example
(1) The following program converts the 64-bit floating decimal point type real number at D20 to D23 with BIN 16-bit data, and
stores the result at D0.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

D23 D22 D21 D20 Conversion to integer D0

25915.6796 25916
64-bit floating-point real number BIN value
D23 D22 D21 D20 Conversion to integer
33562.3211 An operation error occurs because the specified data is larger than -32768.
64-bit floating-point real number

250
 DBL, DBLP

(2) The following program converts the 64-bit floating decimal point type real number at D20 to D23 with BIN 32-bit data and
stores the result at D0 and D1.
[Ladder Mode] [List Mode] 1
Step Instruction Device

2
[Operation]

D23 D22 D21 D20 Conversion to integer D1 D0

3
574968.321 574968
64-bit floating-point real number BIN value
D23 D22 D21 D20 Conversion to integer 4
2147483649.22 An operation error occurs because the
64-bit floating-point real number specified data is larger than 2147483647.

6.3.7 DBL, DBLP Conversion from BIN 16-bit to BIN 32-bit data

6.3.7 DBL, DBLP Basic High

performance Process Redundant Universal LCPU

6
Command
DBL DBL S D

Command
7
DBLP DBLP S D

S : BIN 16-bit data or head number of the devices where the BIN 16-bit data is stored (BIN 16 bits)
8
D : Head number of the devices where the converted BIN 32-bit data will be stored (BIN 32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
––

6.3.7
6.3 Data conversion instructions
S

D –– ––

DBL, DBLP
Function
Converts BIN 16-bit data at device designated by S to BIN 32-bit data with sign, and stores the result at a device designated
by D .
S D +1 D
BIN 16-bit data Upper 16 bits Lower 16 bits

BIN 32-bit data

Operation Error
(1) There is no operation error in the DBL(P) instruction.

251
 WORD, WORDP

Program Example
(1) The following program converts the BIN 16-bit data stored at D100 to BIN 32-bit data when X20 is ON, and stores at
R100 and R101.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D100 R101 R100
FB2EH FFFFFB2EH
( 1234) ( 1234)

6.3.8 WORD, WORDP Conversion from BIN 32-bit to BIN 16-bit data

6.3.8 WORD, WORDP Basic High

performance Process Redundant Universal LCPU

Command
WORD WORD S D

Command
WORDP WORDP S D

S : BIN 32-bit data or head number of the devices where the BIN 32-bit data is stored (BIN 32 bits)
D : Head number of the devices where the converted BIN 16-bit data will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

Function
Converts BIN 32-bit data at device designated by S to BIN 16-bit data with sign, and stores the result at a device designated
by D .
Devices can be designated in the range from -32768 to 32767.
S +1 S D
Upper 16 bits Lower 16 bits BIN 16-bit data

BIN 32-bit data

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The data specified by S +1 and S are outside the range of -32768 to
4100
32767.

252
 GRY, GRYP, DGRY, DGRYP

Program Example
1
(1) The following program converts the BIN 32-bit data at R100 and R101 to BIN 16-bit data when X20 is ON, and stores it
at D100.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
[Operation]
R101 R100
FFFF8253 H
D100
8253H
4
(-32173) (-32173)

6.3.9 GRY, GRYP Conversion from BIN 16-bit data to Gray code

6.3.9
DGRY, DGRYP Conversion from BIN 32-bit data to Gray code

GRY, GRYP, DGRY, DGRYP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of GRY, DGRY.

6
Command
GRY, DGRY S D

Command
7
GRYP, DGRYP P S D

S : BIN data or head number of the devices where the BIN data is stored (BIN 16/32 bits)
8
D : Head number of the devices where the converted Gray code will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

6.3.9
6.3 Data conversion instructions
D –– ––

GRY, GRYP, DGRY, DGRYP

Function
GRY
Converts BIN 16-bit data at the device designated by S to Gray code, and stores result at device designated by D .

16 bits
b15 b0
S BIN 1234 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0

b15 b0
D Gray code 1234 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1

DGRY
Converts BIN 32-bit data at the device designated by S to Gray code, and stores result at device designated by D .

S +1 (Upper 16 bits) S (Lower 16 bits)

b31 b16 b15 b0

S BIN 305419896 000 100 1000 110 1000 10 10 1100 1111000

D +1 D

b31 b16 b15 b0

D Gray code 305419896 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0

253
 GBIN, GBINP, DGBIN, DGBINP

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

4100 The data at S is a negative value.

Program Example
(1) The following program converts the BIN data at D100 to Gray code when X10 is ON, and stores result at D200.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program converts the BIN data at D10 and D11 to Gray code when X1C is ON, and stores it at D100 and
D101.
[Ladder Mode] [List Mode]

Step Instruction Device

6.3.10 GBIN, GBINP Conversion from Gray code to BIN 16-bit data

6.3.10
DGBIN, DGBINP Conversion from Gray code to BIN 32-bit data

GBIN, GBINP, DGBIN, DGBINP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of GBIN/DGBIN.

Command
GBIN, DGBIN S D

Command
GBINP, DGBINP P S D

S : Gray code data or head number of the devices where the Gray code data is stored (BIN 16/32 bits)
D : Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

Function
GBIN
Converts Gray code data at device designated by S to BIN 16-bit data and stores at device designated by D .

16 bit
b15 b0
S Gray code 1234 0 0 0 0 0 1 1 0 1 0 1 1 1 0 1 1

b15 b0
D BIN 1234 0 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0

254
 GBIN, GBINP, DGBIN, DGBINP

DGBIN
Converts Gray code data at device designated by to BIN 32-bit data and stores at device designated by .
S D
1
S +1 (Upper 16 bits) S (Lower 16 bits)

b31 b16 b15 b0

S Gray code 305419896 0 0 0 1 1 0 1 1 0 0 1 0 1 1 1 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 0 2
D +1 D

b31 b16 b15 b0 3

D BIN 305419896 00010010001101000101011001111000

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
6
The data of S is other than 0 to 32767 when the GBIN instruction is
4100
executed.
The data of is other than 0 to 2147483647 when the DGBIN
7
S
4100
instruction is executed.

Program Example 8
(1) The following program converts the Gray code data at D100 when X10 is ON to BIN data, and stores the result at D200.
[Ladder Mode] [List Mode]

Step Instruction Device

6.3.10 GBIN, GBINP, DGBIN, DGBINP

6.3 Data conversion instructions
(2) The following program converts the Gray code data at D10 and D11 to BIN data when X1C is ON, and stores the result
at D0 and D1.
[Ladder Mode] [List Mode]
Step Instruction Device

255
 NEG, NEGP, DNEG, DNEGP

6.3.11 NEG, NEGP Complement of 2 of BIN 16-bit data (sign inversion)

6.3.11
DNEG, DNEGP Complement of 2 of BIN 32-bit data (sign inversion)

NEG, NEGP, DNEG, DNEGP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of NEG/DNEG.

Command
NEG, DNEG D

Command
NEGP, DNEGP P D

D : Head number of the devices where the data for which complement of 2 is performed is stored (BIN 16/32 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D ––

Function
NEG
(1) Reverses the sign of the 16-bit device designated by D and stores at the device designated by D .
16 bit
b15 b0
Before execution D 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 -21846

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sign conversion
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

b15 b0
After execution D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 21846

(2) Used when reversing positive and negative signs.

DNEG
(1) Reverses the sign of the 32-bit device designated by D and stores at the device designated by D .
32 bit
Before b31 b0
execution D 1 1 1 1 1 1 1 0 1 0 0 1 0 0 -218460

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Sign
conversion - 1 1 1 1 1 1 1 0 1 0 0 1 0 0

After b31 b0
execution D 0 0 0 0 0 0 0 1 0 1 1 1 0 0 218460

(2) Used when reversing positive and negative signs.

Operation Error
(1) There is no operation error in the NEG(P) or DNEG(P) instruction.

256
 ENEG, ENEGP

Program Example
1
(1) The following program calculates a total for the data at D10 through D20 when XA goes ON, and seeks an absolute
value if the result is negative.
[Ladder Mode] 2
M3 is turned ON if D10 < D20.

Executes "D10 - D20". 3

Calculates the absolute value
(complement of 2) when M3 is ON.
4
[List Mode]

Step Instruction Device

7
6.3.12 ENEG, ENEGP Floating-point sign inversion (Single precision)

Ver.
High
Basic performance Process Redundant Universal LCPU

6.3.12 ENEG, ENEGP • Basic model QCPU: The serial number (first five digits) is
"04122" or later. 8
Command
ENEG ENEG D

Command

6.3.12 ENEG, ENEGP

6.3 Data conversion instructions
ENEGP ENEGP D

D : Head number of the devices where the 32-bit floating decimal point data whose sign is to be reversed is stored (real number)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D –– –– *1 ––
*1: Available only in multiple Universal model QCPU and LCPU

Function
(1) Reverses the sign of the 32-bit floating decimal point type real number data designated by D , and stores at the device
designated by D .
(2) Used when reversing positive and negative signs.

257
 EDNEG, EDNEGP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .

Program Example
(1) The following program inverts the sign of the 32-bit floating decimal point type real number data at D100 and D101 when
X20 goes ON, and stores result at D100 and D101.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D101 D100 D101 D100
1.2345 1.2345

6.3.13 EDNEG, EDNEGP Floating-point sign inversion (Double precision)

6.3.13 EDNEG, EDNEGP Basic High

performance Process Redundant Universal LCPU

Command
EDNEG EDNEG D

Command
EDNEGP EDNEGP D

D : Head number of the devices where the 64-bit floating decimal point data whose sign is to be reversed is stored (real number)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D –– ––

Function
(1) Reverses the sign of the 64-bit floating decimal point type real number data designated by D , and stores at the device
designated by D .
(2) Used when reversing positive and negative signs.

258
 BKBCD, BKBCDP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– –– 3
The specified device value is -0.

Program Example 4
(1) The following program inverts the sign of the 64-bit floating decimal point type real number data at D0 to D3 when X20
goes ON, and stores result at D0 to D3.
[Ladder Mode] [List Mode]

Step Instruction Device

6

[Operation] 7
D3 D2 D1 D0 D3 D2 D1 D0
1.2345

6.3.14 BKBCD, BKBCDP Conversion from block BIN 16-bit data to BCD 4-digit data
8
6.3.14 BKBCD, BKBCDP Basic High
performance Process Redundant Universal LCPU

6.3.14 BKBCD, BKBCDP

6.3 Data conversion instructions
Command
BKBCD BKBCD S D n

Command
BKBCDP BKBCDP S D n

S : Head number of the devices where BIN data is stored (BIN 16 bits)
D : Head number of the devices where the converted BCD data will be stored (BCD 4 digits)
n : Number of variable data blocks (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––
D –– –– ––
n ––

259
 BKBCD, BKBCDP

Function
(1) Converts BIN data (0 to 9999) n points from device designated by S to BCD, and stores result following the device
designated by D .
Must always be "0".

8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1
S BIN 1234 00000 100110 10010
S +1 BIN 5678 000 10 11000 10 1110
S +2 BIN 1545 0000011000001001
n

S +(n 2) BIN 4321 000 10000 1110000 1

S +(n 1) BIN 5555 000 10 101101100 11

BCD conversion
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

D BCD 1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
D +1 BCD 5678 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
D +2 BCD 1545 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1
n

D +(n 2) BCD 4321 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1

D +(n 1) BCD 5555 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The nth data from the device specified by S is outside the 0 to 9999
4100
range.
The points specified in n exceed those of the corresponding device
4101 specified in S or D .
The same device is specified in S and D .

Program Example
(1) The following program converts, when X20 is turned ON, the BIN data stored at D100 to D102 to BCD and stores the
operation result into the area starting from D200.
[Ladder Mode] [List Mode]

Step Instruction Device

260
 BKBIN, BKBINP

[Operation]

8192
4096
2048
1024
512
256
128
1

64
32
16
8
4
2
1
D100 BIN 5432 000 10 10 100 111000
D101 BIN 4444 000 1000 10 10 11100
D102 BIN 3210 0000110010001010
2
BCD D0 3
conversion
8000
4000
2000
1000
800
400
200
3
100
80
40
20
10
8
4
2
1
D200 BCD 5432 0 1 0 1 0 1 0 0 0 0 1 1 0 0 1 0
D201 BCD 4444 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
D202 BCD 3210 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 4
6.3.15 BKBIN, BKBINP Conversion from block BCD 4-digit data to block BIN 16-bit

6.3.15
data

BKBIN, BKBINP Basic High

performance Process Redundant Universal LCPU

Command
BKBIN BKBIN S D n 6
Command
BKBINP BKBINP S D n

7
S : Head number of the devices where BCD data is stored (BCD 4 digits)
D : Head number of the devices where the converted BIN data will be stored (BIN 16 bits)
n : Number of variable data blocks (BIN 16 bits)
8
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– –– ––

6.3.15 BKBIN, BKBINP

6.3 Data conversion instructions
n ––

Function
(1) Converts BCD data (0 to 9999) n points from device designated by S to BIN, and stores result following the device
designated by D .
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

S BCD 1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
S +1 BCD 5678 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
S +2 BCD 1545 0 0 0 1 0 1 0 1 0 1 0 0 0 1 0 1
n

S +(n 2) BCD 4321 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1

S +(n 1) BCD 5555 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

BIN conversion
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

D BIN 1234 00000100110 100 10

D +1 BIN 5678 000 10 11000 10 1110
D +2 BIN 1545 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 1
n

D +(n 2) BIN 4321 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 1

D +(n 1) BIN 5555 0 0 0 1 0 1 0 1 1 0 1 1 0 0 1 1

261
 ECON, ECONP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The nth data from the device specified by S is outside the 0 to 9999
4100
range.
The points specified in n exceed those of the corresponding device
4101 specified in S or D .
The same device is specified in S and D .

Program Example
(1) The following program converts, when X20 is turned ON, the BCD data stored at D100 to D102 to BIN and stores the
operation result into the area starting from D200.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
8000
4000
2000
1000
800
400
200
100
80
40
20
10
8
4
2
1

D100 BCD 8080 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0

D101 BCD 7654 0 0 1 1 1 0 1 1 0 0 1 0 1 0 1 0
D102 BCD 9999 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1

BIN conversion
(when D0=3)
8192
4096
2048
1024
512
256
128
64
32
16
8
4
2
1

D200 BIN 8080 00 01111110010000

D201 BIN 7654 00 0111 011110 0110
D202 BIN 9999 0 010 0111000 01111

6.3.16 ECON, ECONP Conversion from Single precision to Double precision

6.3.16 ECON, ECONP Basic High

performance Process Redundant Universal LCPU

Command
ECON ECON S D

Command
ECONP ECONP S D

S : Conversion source data, or head number of the device where conversion source data is stored (Real number (single precision))
D : Head number of the device where the converted data is stored (Real number (double precision))

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

262
 EDCON, EDCONP

Function
1
(1) Converts 32-bit floating-point real number specified for S into 64-bit floating-point real number, and stores the
conversion result to the device specified for D .
S +1 S D +3 D +2 D +1 D 2
32-bit floating-point real number 64-bit floating-point real number
(2) When an input value is set using a programming tool, a rounding error may occur. 3
For precautions, refer to Page 95, Section 3.2.4 (3).

4
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 6
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .
7

Program Example 8
(1) The program which converts 32-bit floating-point real number of the devices, D10 to D11, into 64-bit floating-point real
number when X0 turns ON, and outputs the conversion result to the devices, D0 to D3.
[Ladder Mode] [List Mode]

6.3.17 EDCON, EDCONP

6.3 Data conversion instructions
Step Instruction Device

6.3.17 EDCON, EDCONP Conversion from Double precision to Single precision

6.3.17 EDCON, EDCONP Basic High

performance Process Redundant Universal LCPU

Command
EDCON EDCON S D

Command
EDCONP EDCONP S D

S : Conversion source data, or head number of the device where conversion source data is stored (Real number (double precision))
D : Head number of the device where the converted data is stored (Real number (single precision))

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– –– ––

D –– –– –– ––

263
 EDCON, EDCONP

Function
(1) Converts 64-bit floating-point real number specified for S into 32-bit floating-point real number, and stores the
conversion result to the device specified for D .
S +3 S +2 S +1 S D +1 D

64-bit floating-point real number 32-bit floating-point real number

(2) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0,2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The conversion result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
128
2 | Conversion result |

Program Example
(1) The program which converts 64-bit floating-point real number of the devices, D10 to D13, into 32-bit floating-point real
number when X0 turns ON, and outputs the conversion result to the devices, D0 to D1.
[Ladder Mode] [List Mode]

Step Instruction Device

264
 MOV, MOVP, DMOV, DMOVP

6.4 Data Transfer Instructions

1
6.4.1 MOV, MOVP 16-bit data transfer

6.4.1
DMOV, DMOVP 32-bit data transfer

MOV, MOVP, DMOV, DMOVP Basic High

Process Redundant Universal LCPU
2
performance

indicates an instruction symbol of MOV/DMOV.

Command 3
MOV, DMOV S D

Command
MOVP, DMOVP P S D 4
S : Data to be transferred or the number of the device where the data to be transferred is stored (BIN 16/32 bits)
D : Number of the device where the data will be transferred (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––
6
D –– ––

7
When BL, S, TR, BL\S, or BL\TR is used, refer to SFC control instructions of the MELSEC-Q/L/QnA Programming Manual
(SFC).

8
Function
MOV
(1) Transfers the 16-bit data from the device designated by to the device designated by .

6.4.1
6.4 Data Transfer Instructions
S D

b15 b0
Before transfer S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

MOV, MOVP, DMOV, DMOVP

Transfer
b15 b0
After transfer D 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

DMOV
(1) Transfers 32-bit data at the device designated by S to the device designated by D .
S +1 S
b15 b0 b15 b0
Before transfer S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

Transfer
D +1 D
b15 b0 b15 b0
After transfer D 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

Operation Error
(1) There is no operation error in the MOV(P) or DMOV(P) instruction.

265
 EMOV, EMOVP

Program Example
(1) The following program stores input data from X0 to XB at D8.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program stores the constant K155 at D8 when X8 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

009BH
b15 b8b7 b0
D8 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1

(3) The following program stores the data from D0 and D1 at D7 and D8.
[Ladder Mode] [List Mode]

Step Instruction Device

(4) The following program stores the data from X0 to X1F at D0 and D1.
[Ladder Mode] [List Mode]

Step Instruction Device

6.4.2 EMOV, EMOVP Floating-point data transfer (Single precision)

Ver.
High
Basic performance Process Redundant Universal LCPU

6.4.2 EMOV, EMOVP • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
EMOV EMOV S D

Command
EMOVP EMOVP S D

S : Data to be transferred or number of the device to which the data to be transferred is stored (real number)
D : The number of the device to which the transferred data will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––

D –– –– *1 –– ––
*1: Available only in multiple Universal model QCPU, LCPU

266
 EMOV, EMOVP

Function
1
(1) Transfers 32-bit floating decimal point type real number data being stored at the device designated by S to a device
designated by D .
S +1 S D +1 D 2
Transfer
4.23542 4.23542

32-bit floating-point
real number
32-bit floating-point
real number
3
(2) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).
4
Operation Error
(1) There is no operation error in the EMOV(P) instruction.

Program Example 6
(1) The following program stores the real numbers at D10 and D11 at D0 and D1.
[Ladder Mode] [List Mode]
7
Step Instruction Device

8
[Operation]
D11 D10 D1 D0
36.475 36.475

6.4.2
6.4 Data Transfer Instructions
(2) The following program stores the real number -1.23 at D10 and D11 when X8 is ON.
[Ladder Mode] [List Mode]

EMOV, EMOVP
Step Instruction Device

[Operation]
D11 D10
1.23 1.23

267
 EDMOV, EDMOVP

6.4.3 EDMOV, EDMOVP Floating-point data transfer (Double precision)

6.4.3 EDMOV, EDMOVP Basic High

performance Process Redundant Universal LCPU

Command
EDMOV EDMOV S D

Command
EDMOVP EDMOVP S D

S : Data to be transferred or number of the device to which the data to be transferred is stored (real number)
D : The number of the device to which the transferred data will be stored (real number)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––
D –– –– –– ––

Function
(1) Transfers 64-bit floating decimal point type real number data being stored at the device designated by S to a device
designated by D .
S +3 S +2 S +1 S Transfer D +3 D +2 D +1 D
4.23542 4.23542

64-bit floating-point real number 64-bit floating-point real number

(2) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) There is no operation error in the EDMOV(P) instruction.

Program Example
(1) The following program stores the 64-bit floating decimal point type real number at D10 to D13 at D0 to D3.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D13 D12 D11 D10 D3 D2 D1 D0
36.475 36.475

(2) The following program stores the real number -1.23 at D10 to D13 when X8 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D13 D12 D11 D10

268
 $MOV, $MOVP
6.4.4 $MOV, $MOVP Character string transfer

6.4.4 $MOV, $MOVP Basic High

performance Process Redundant Universal LCPU

1
Command
$MOV $MOV S D

Command 2
$MOVP $MOVP S D

S : Character string to be transferred (maximum string length: 32 characters) or head number of the devices where the character string to be transferred is
stored (character string)
3
D : Head number of the devices where the transferred character string will be stored (character string)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
$
Other 4
S –– –– ––

D –– –– –– ––

Function
(1) Transfers the character string data designated by S to the devices from the device designated by D and onward.
6
The character string data enclosed in " (double quotes) or devices from the number specified by S to the device number
storing "00H" are transferred all at once.
7
b15 b8 b7 b0 b15 b8 b7 b0
S 2nd character 1st character D 2nd character 1st character
S + 1 4th character 3rd character D + 1 4th character 3rd character
S + 2 6th character 5th character D + 2 6th character 5th character 8
00H nth character 00H nth character
Indicates the end of character string.

(2) Processing will be performed without error even in cases where the range for the devices storing the character data to be

6.4.4
6.4 Data Transfer Instructions
transferred ( S to S +n) overlaps with the range of the devices which will store the character string data after it has been
transferred ( D to D +n).

$MOV, $MOVP
The following occurs when the character string data that had been stored from D10 to D13 is transferred to D11 to D14:
b15 b8 b7 b0 b15 b8 b7 b0
D10 32 H (2) 31 H (1) D10 32 H (2) 31 H (1) Character string before
D11 34 H (4) 33 H (3) D11 32 H (2) 31 H (1) transfer is remained.
D12 36 H (6) 35 H (5) D12 34 H (4) 33 H (3)
D13 00 H D13 36 H (6) 35 H (5)
D14 D14 00 H

(3) If the "00H" code is being stored at lower bytes of S +n, "00H" will be stored at both the higher bytes and the lower bytes
of D +n.
b15 b8 b7 b0 b15 b8 b7 b0
S 42 H (B) 41 H (A) D 42 H (B) 41 H (A)
S +1 44 H (D) 43 H (C) D +1 44 H (D) 43 H (C)
S +2 45 H (E) 00 H D +2 00 H 00 H

Upper byte is not transferred. At the upper byte position,

"00H" is automatically stored.

269
 $MOV, $MOVP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
There is no "00H" code stored in the devices between the device
number specified by S and the corresponding device number.
The entire character string cannot be stored in the points between the
4101
device number specified by D and the last device number of the
corresponding device.
The character string of S exceeds 16383 characters.

Program Example
(1) The character string data stored in D10 to D12 is transferred to D20 to D22 when X0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D10 4DH (M) 2AH ( * ) D20 4DH (M) 2AH ( * )
D11 45H (E) 45H (E) D21 45H (E) 45H (E)
D12 00H D22 00H

(2) When X0 is turned ON, the character string "ABCD" is transferred to D20 and D21.
[Ladder Mode] [List Mode]

Step Instruction Device

270
 CML, CMLP, DCML, DCMLP

6.4.5 CML, CMLP 16-bit data negation transfer

6.4.5
DCML, DCMLP 32-bit data negation transfer

CML, CMLP, DCML, DCMLP Basic High

performance Process Redundant Universal LCPU

1
indicates an instruction symbol of CML, DCML.

2
Command
CML, DCML S D

Command
CMLP, DCMLP P S D
3
S : Data to be reversed or the number of the device where data to be reversed is stored (BIN 16/32 bits)
D : Number of the device where the reversing result will be stored (BIN 16/32 bits)

Setting Internal Devices

R, ZR
J \
Zn
Constants
Other
4
U \G
Data Bit Word Bit Word K, H
S ––

D –– ––

Function 6
CML
(1) Inverts 16-bit data designated by S bit by bit, and transfers the result to the device designated by D .
b15 b0
7
Before execution S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

b15
Inversion
b0 8
After execution D 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1

DCML
(1) Inverts 32-bit data designated by S bit by bit, and transfers the result to the device designated by D .

6.4.5
6.4 Data Transfer Instructions
S +1 S
b15 b0 b15 b0
Before execution S 1 0 1 1 0 1 0 0 0 1 1 1 0 0 1 0

CML, CMLP, DCML, DCMLP

D +1 Inversion D
b15 b0 b15 b0
After execution D 0 1 0 0 1 0 1 1 1 0 0 0 1 1 0 1

Operation Error
(1) There is no operation error in the CML(P) or DCML(P) instruction.

271
 CML, CMLP, DCML, DCMLP

Program Example
(1) The following program inverts the data from X0 to X7, and transfers result to D0.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
If "Number of bits of S < Number of bits of D "

X7 X0
These bits are all regarded as 0. 11010000

b15 b8 b7 b0
D0 1 1 1 1 1 1 1 1 0 0 1 0 1 1 1 1

(2) The following program inverts the data at M16 to M23, and transfers the result to Y40 to Y47.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
If "Number of bits of S < Number of bits of D "

M23 M16
These bits are all regarded as 0. 01011100

Y4B Y48Y47 Y40

111110100011

(3) The following program inverts the data at D0 when X3 is ON, and stores the result at D16.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
D0 1101100110101111

b15 b8 b7 b0
D16 0 0 1 0 0 1 1 0 0 1 0 1 0 0 0 0

(4) The following program inverts the data at X0 to X1F, and transfers results to D0 and D1.
[Ladder Mode] [List Mode]

Step Instruction Device

272
 CML, CMLP, DCML, DCMLP

[Operation]
If "Number of bits of S < Number of bits of D "

X1B X8 X7 X0
1
These bits are all regarded as 0. 0100 011100101100

b31 b28 b27 b24 b8 b7 b0 2

D0, 1 1 1 1 1 1 0 1 1 100011010011

(5) The following program inverts the data at M16 to M35, and transfers it to Y40 to Y63.
[Ladder Mode] [List Mode]
3
Step Instruction Device

[Operation]
If "Number of bits of S < Number of bits of D "

M35 M24 M23 M16

These bits are all regarded as 0. 0 10 0 0 1 1 10 0 10 1 10 0
6
Y63 Y56 Y48 Y47 Y40
1 1 1 1 10 1 1 10 0 0 1 10 10 0 1 1
7
(6) Inverts the data at D0 and D1 when X3 is ON, and stores the result at D16 and D17.
[Ladder Mode] [List Mode]

Step Instruction Device

8

[Operation]

6.4.5
6.4 Data Transfer Instructions
b31 b24 b8 b7 b0
D0,D1 0 0 0 0 0 1 0 0 0 11100101100

CML, CMLP, DCML, DCMLP

b31 b24 b8 b7 b0
D16,D17 1 1 1 1 1 0 1 1 1000 110 100 11

273
 BMOV, BMOVP

6.4.6 BMOV, BMOVP Block 16-bit data transfer

6.4.6 BMOV, BMOVP Basic High

performance Process Redundant Universal LCPU

Command
BMOV BMOV S D n

Command
BMOVP BMOVP S D n

S : Head number of the devices where the data to be transferred is stored (BIN 16 bits)
D : Head number of the devices of transfer destination (BIN 16 bits)
n : Number of transfers (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– ––

D –– ––
n ––

When BL, S, TR, BL\S, or BL\TR is used, refer to SFC control instructions of the MELSEC-Q/L/QnA Programming Manual
(SFC).

Function
(1) Transfers in batch 16-bit data of n points from the device designated by S to location n points from the device
designated by D .
b15 B0 b15 B0
S 1234 H D 1234 H
S +1 5678 H Block D +1 5678 H
transfer
S +2 7FF0 H D +2 7FF0 H
n n
S +(n-2) 6FFFH D +(n-2) 6FFF H
S +(n-1) 553F H D +(n-1) 553F H

274
 BMOV, BMOVP

(2) Transfers can be accomplished even in cases where there is an overlap between the source and destination device.
In the case of transmission to the smaller device number, transmission is from S ; for transmission to the larger device
number, transmission is from S + (n-1). 1
However, as shown in the example below, when transferring data from R to ZR, or from ZR to R, the range to be
transferred (source) and the range of destination must not overlap.
Transfer from R to R, or from ZR to ZR can be performed without any problem. 2
• ZR transfer range ((specified head No. of ZR) to (specified head No. of ZR + the number of transfers -1))
• R transfer range ((specified head No. of R + file register block No. 32768) to (specified head No. of R + file register
block No. 32768 + the number of transfers -1)) 3
Example
Transfer ranges of ZR and R overlap when transferring 10000 blocks of data from ZR30000 (source) to R10 (block No.1
of the destination).
4
• ZR transfer range (30000) to (30000+10000-1) (30000) to (39999)
• R transfer range (10+(1 32768)) to (10+(1 32768)+10000-1)
(32778) to (42777)
Therefore, the range 32778 to 39999 overlaps and the data is not correctly transferred.

Source of transfer Destination of transfer 6

ZR0 R0

Overlapped Block No. 0

7
ZR30000 R32767
ZR39999 R10

R10009 Block No. 1

8

6.4.6
6.4 Data Transfer Instructions
(3) When S is a word device and D is a bit device, the object for the word device will be the number of bits designated by
the bit device digit designation.

BMOV, BMOVP
If K1Y30 has been designated by D , the lower four bits of the word device designated by S will become the object.
b15 b4 b3 b2 b1b0 D +2 D +1 D
S D100 1011
Y3B Y38 Y37 Y34 Y33 Y30
S +1 D101 0011 n 011100111011
n
S +2 D102 0111

(4) If bit device has been designated for S and D , then S and D should always have the same number of digits.
(5) When using a link direct device and an intelligent function module device for S and D , only either of S or D can be
used.
(6) Selection whether to check a device range
Whether to check a device range during execution of the BMOV instruction can be selected with the device range check
inhibit flag (SM237) (only when the conditions for subset processing are established).
While SM237 is ON, whether S to S + (n) -1 and D to D + (n) - 1 are within the device range or not are not checked.

275
 BMOV, BMOVP

Caution
While SM237 is on, do not make the following access.
• The indexing target exceeds the device range.
• The value obtained from " D to D + (n) - 1" is over the boundaries of the device ranges.*1
• Accessing the file register with file register not set.
• Accessing the area where the multiple CPU high speed transmission area device is not available (only for the QCPU).
*1: Refer to the DFMOV instruction.

SM237 can be used only for the Universal model QCPU whose first 5 digits of serial number is 10012 or later and LCPU.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in S or D .

Program Example
(1) The following program outputs the lower 4 bits of data at D66 to D69 to Y30 to Y3F in 4-point units.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Before execution (source of transfer)
b15 b4b3 b0 After execution (destination of transfer)
D66 1110 1 1 1 0 1 Y33 to Y30
D67 00000 0 0 0 0 Y37 to Y34
D68 10011 0 0 1 1 Y3B to Y38
D69 0 110 1 1 1 0 1 Y3F to Y3C

Ignored

276
 FMOV, FMOVP

(2) The following program outputs the data at X20 to X2F to D100 to D103 in 4-point units.
[Ladder Mode] [List Mode]

Step Instruction Device 1

2
[Operation]
X2F X2CX2B X28X27 X24X23 X20
Before execution 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0
3
After execution (destination of transfer)
b15 b4 b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 D100

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 D101
4
4 points
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D102

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 D103

Filled with 0s.

6.4.7 FMOV, FMOVP Identical 16-bit data block transfer

6
6.4.7 FMOV, FMOVP Basic High
performance Process Redundant Universal LCPU

7
Command
FMOV FMOV S D n

Command 8
FMOVP FMOVP S D n

S : Data to be transferred or the head number of the devices where the data to be transferred is stored (BIN 16 bits)
D : Head number of the devices of transfer destination (BIN 16 bits)
n : Number of transfers (BIN 16 bits)

6.4.7
6.4 Data Transfer Instructions
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

FMOV, FMOVP
S ––

D –– ––
n ––

Function
(1) Transfers 16-bit data at the device designated by S to n points of devices starting from the one designated by D .
b15 b0
b15 b0 Transfer D 3456 H
S 3456 H D +1 3456 H
D +2 3456 H
n

D +(n-2) 3456 H
D +(n-1) 3456 H
(2) In cases where S designates a word device and D a bit device, the number of bits designated by digit designation for
the bit device will be the object bits for the word device S .
If K1Y30 has been designated by D , the lower 4 bits of the word device designated by S will become the object.
D +3 D +2 D +1 D
b15 b4 b3 b2 b1b0 Transfer Y3F Y3C Y3B Y38 Y37 Y34 Y33 Y30
S D100 1 011 1 01 1 1 01 11 01 1 1 01 1
n

(3) If bit device has been designated for S and D , then S and D should always have the same number of digits.

277
 FMOV, FMOVP

(4) Selection whether to check a device range

Whether to check a device range during execution of the FMOV instruction can be selected with the device range check
inhibit flag (SM237) (only when the conditions for subset processing are established).
While SM237 is ON, whether D to D + (n) - 1 is within the device range or not is not checked.
For details of SM237, refer to the User's Manual (Hardware design, Maintenance andInspection) for the CPU module
used.

Caution
While SM237 is on, do not make the following access.
• The indexing target exceeds the device range.
• The value obtained from " D to D + (n) - 1" is over the boundaries of the device ranges.*1
• Accessing the file register with file register not set.
• Accessing the area where the multiple CPU high speed transmission area device is not available (only for the QCPU).
*1: Refer to the DFMOV instruction.

SM237 can be used only for the Universal model QCPU whose first 5 digits of serial number is 10012 or later and LCPU.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in S or D .

Program Example
(1) The following program outputs the lower 4 bits of D0 when XA goes ON to Y10 to Y23 in 4-bit units.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b4 b3 b2 b1 b0
D0 1 1 0 1 1 0 1 1 1 0 0 1 1 0 1 1
1 0 1 1 Y13 to Y10
Ignored
1 0 1 1 Y17 to Y14
1 0 1 1 Y1B to Y18 5 points
Transfer 1 0 1 1 Y1F to Y1C
1 0 1 1 Y23 to Y20

(2) The following program outputs the data at X20 through X23 to D100 through D103 when XA goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

278
 DFMOV, DFMOVP

[Operation]
X2F X2CX2B X28X27 X24X23 X20
Before execution 1 0 1 1 0 1 1 1 0 0 1 0 1 1 1 0
1
Ignored After execution (destination of transfer)
b15 b4 b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D100

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D101
2
4 points
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D102

0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 D103 3
Filled with 0s.

6.4.8 DFMOV, DFMOVP Identical 32-bit data block transfer

4
Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

6.4.8 DFMOV, DFMOVP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

Command
6
DFMOV DFMOV S D n

DFMOVP
Command
DFMOVP S D n 7
S : Data to be transferred or head number of the devices where the data to be transferred are stored (BIN 32 bits)
D : Head number of the devices of transfer destination (BIN 32 bits) 8
n : Number of transfers (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

6.4.8
6.4 Data Transfer Instructions
D –– ––
n ––

DFMOV, DFMOVP
Function
(1) This instruction transfers 32-bit data of the device specified by S to the n-point devices starting from the device specified
by D.

b31 b0
b31 b0 Transfer D +1, D 1234567H
S +1, S 1234567H D +3, D +2 1234567H
D +5, D +4 1234567H n

D +(2n-1), D +(2n-2) 1234567H

279
 DFMOV, DFMOVP

(2) If S specifies data of a device with digit specification, the amount of data to be transferred will be the amount of the data
specified digit.
If K5Y0 is specified by S , the lower 20 bits (five digits) of the word device specified by S will be the object.
Y1F Y14 Y13 Y0
S +1, S

Ignored 20 bits (five digits) data

b31 b20 b19 b0

0 D +1, D

0 D +3, D +2

Transfer b31 b20 b19 b0

0 D +(2n 1), D +(2n 2)

Filled with 0s 20 bits (five digits) data

(3) If D specifies data of a device with digit specification, the amount of data stored in the device specified by D will be
transferred.
If K5Y0 is specified by D, the lower 20 bits of the word device specified by S will be the object.
If both S and D specify data of a device with digit specification, the amount of data specified by D will be transferred
regardless of the number of digits.
b31 b20 b19 b0
S +1, S

Amount of data specified digits by D

Transfer

D +(2n-1) … D +1 D

Y14n+19 Y14n Y27 Y14 Y13 Y0

(4) If the value specified by n is 0, the instruction will be not processed.

(5) Whether to check a device range during the execution of the FMOV instruction can be selected with the device range
check inhibit flag (SM237). (Only when the conditions of the subset processing are established)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value specified for n is negative. –– –– –– ––
Data points to be transferred (n) exceed the points of the device
4101 –– –– –– ––
specified in D .

Program Example
(1) The following program stores the value data stored at Y0 to Y13(20 bits) into D10 to D17,when M0 is turned on,
[Ladder Mode] [List Mode]

Step Instruction Device

280
 XCH, XCHP, DXCH, DXCHP

[Operation]
Y1F Y14 Y13 Y0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Ignored 20 bits (five digits) data 1

b31 b20 b19 b0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D11,D10

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D13,D12
2
Transfer

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D15,D14

0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D17,D16 3
20 bits (five digits)
Filled with 0s

6.4.9 XCH, XCHP 16-bit data exchanges

4
6.4.9
DXCH, DXCHP 32-bit data exchanges

XCH, XCHP, DXCH, DXCHP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of XCH, DXCH.

Command
XCH, DXCH
6
D1 D2

Command
XCHP, DXCHP P D1 D2

D1 , D2
7
: Head number of the devices where the data to be exchanged is stored (BIN 16/32 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D1 ––
8
D2 ––

Function

6.4.9
6.4 Data Transfer Instructions
XCH

XCH, XCHP, DXCH, DXCHP

(1) Conducts 16-bit data exchange between D1 and D2 .

D1 D2

b15 b8 b7 b0 b15 b8 b7 b0
Before execution 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1111 00001111 0000

D1 D2

b15 b8 b7 b0 b15 b8 b7 b0
After execution 1111000011110000 0111000000000111

DXCH
(1) Conducts 32-bit data exchange between D1 +1, D1 and D2 +1, D2 .

D1 +1 D1 D2+1 D2

b31 b16 b15 b0 b31 b16 b15 b0

Before execution 1 1 1 1 000111 0000 0000 111111 1111

D1 +1 D1 D2 +1 D2

b31 b16 b15 b0 b31 b16 b15 b0

After execution 0000 111111 1111 1111 000111 0000

281
 BXCH, BXCHP

Operation Error
(1) There is no error in the XCH (P) or DXCH (P) instruction.

Program Example
(1) The following program exchanges the present value of T0 with the contents of D0 when X8 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program exchanges the contents of D0 with the data from M16 to M31 when X10 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

(3) The following program exchanges the contents of D0 and D1 with the data at M16 to M47 when X10 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

(4) The following program exchanges the contents of D0 and D1 with those of D9 and D10 when M0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

6.4.10 BXCH, BXCHP Block 16-bit data exchanges

6.4.10 BXCH, BXCHP Basic High

performance Process Redundant Universal LCPU

Command
BXCH BXCH D1 D2 n

Command
BXCHP BXCHP D1 D2 n

D1 , D2 : Head number of the devices where the data to be exchanged is stored (BIN 16 bits)
n : Number of exchanges (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D1 –– –– ––
D2 –– –– ––
n ––

282
 BXCH, BXCHP

Function
1
(1) Exchanges 16-bit data of n points from device designated by D1 and 16-bit data of n points from device designated by
D2 .

b15 b8 b7 b0 b15 b8 b7 b0 2
D1 0000 111100001111 D2 00 11001100 110011
D1 +1 1111111100000000 D2 +1 110000 11110000 11
D1 +2 0000000011111111
n
D2 +2 1111111100000000
n
3
D1 +(n 2) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 D2 +(n 2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
D1 +(n 1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D2 +(n 1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
4

b15 b8 b7 b0 b15 b8 b7 b0
D1 00 11001100110011 D2 0000 111100001111
D1 +1 110000 11110000 11 D2 +1 1111111100000000
D1 +2 1111111100000000 D2
6
+2 0000000011111111
n n

D1 +(n 2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D2 +(n 2) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
D1 +(n 1) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 +(n 1) 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
7
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into 8
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

6.4.10 BXCH, BXCHP

6.4 Data Transfer Instructions
The points specified in n exceed those of the corresponding device
4101 specified in D1 or D2 .
The D1 and D2 devices overlap.

Program Example
(1) The following program exchanges 16-bit data for 3 points from D200 for 16-bit data for 3 points from R0 when X1C goes
ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D200 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1 R0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1
D201 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
D202 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R2 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0

b15 b8 b7 b0 b15 b8 b7 b0
D200 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 R0 0 0 1 1 1 1 0 0 1 1 1 1 1 1 1 1
D201 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
D202 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 R2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

283
 SWAP, SWAPP

6.4.11 SWAP, SWAPP Upper and lower byte exchanges

6.4.11 SWAP, SWAPP Basic High

performance Process Redundant Universal LCPU

Command
SWAP SWAP D

Command
SWAPP SWAPP D

D : Head number of the devices where the data is stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D ––

Function
(1) Exchanges the higher and lower 8 bits of the device designated by D .
b15 b12 b11 b8 b7 b4 b3 b0
D 0 10 1010 11010 10 10

b15 b12 b11 b8 b7 b4 b3 b0

D 10 10 10 100 10 10 10 1

Operation Error
(1) There is no operation error in the SWAP(P) instruction.

Program Example
(1) The following program exchanges the higher 8 bits and lower 8 bits of R10 when X10 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b12 b11 b8 b7 b4 b3 b0
R10 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

b15 b12 b11 b8 b7 b4 b3 b0

R10 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

284
 CJ, SCJ, JMP

6.5 Program Branch Instructions

1
6.5.1 CJ, SCJ, JMP Pointer branch

6.5.1 CJ, SCJ, JMP Basic High

performance Process Redundant Universal LCPU
2
Command
CJ CJ P**

Command 3
SCJ SCJ P**

JMP JMP P** 4

Label
Command
P**

P** : Pointer number of jump destination (Device name)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data
P
Bit Word Bit Word
––
6

Function 7
CJ
(1) Executes the program specified by the pointer number within the same program file, when the execution command is
ON.
8
(2) When the execution command is OFF, the program at the next step is executed.
ON

Execution command OFF

6.5.1
6.5 Program Branch Instructions
CJ, SCJ, JMP
CJ
Executed at each scan

SCJ
(1) Executes the program specified by the pointer number within the same program file starting with the scan immediately
after OFF ON of the execution command.
(2) When the execution command is OFF or turned ON OFF, the program at the next step is executed.
ON

Execution command OFF

SCJ
1 scan Executed at each scan

285
 CJ, SCJ, JMP

JMP
(1) Unconditionally executes program of designated pointer number within the same program file.

Note the following points when using the jump instruction.

1. After the timer coil has gone ON, accurate measurements cannot be made if there is an attempt to jump the timer of a coil
that has been turned ON using the CJ, SCJ or JMP instructions.
2. Scan time is shortened if the CJ, SCJ or JMP instruction is used to force a jump to the OUT instruction.
3. Scan time is shortened if the CJ, SCJ or JMP instruction is used to force a jump to the rear.
4. The CJ, SCJ, and JMP instructions can be used to jump to a step prior to the step currently being executed. However, it is
necessary to consider methods to get out of the loop so that the watchdog timer does not time out in the process.

P8 X0
Y40
When X3 is X7
ON, the loop CJ P9
is closed. X3 Exits the loop when
CJ P8 X7 is turned ON.
P9 X6
Y42

5. The device to which a jump has been made with the CJ, SCJ or JMP does not change.
XB Jumps to label P19
10 CJ P19 when XB turns ON.
XC Y43 and Y49 remain
14 Y43 unchanged regardless
XB of whether XB and XC are
16 Y49 turned ON/OFF during the
P19 execution of CJ instruction.
X9
18 Y4C

6. The label (P*) occupies step 1.

X8
10 CJ P9
M33
14 Y30
Occupies 1 step
M3
16 Y36
P9 M36
18 Y39
X9
21 Y3B

7. The jump instructions can be used only for pointer numbers within the same program file.
8. If a jump is made to a pointer number inside the skip range during a skip operation, program execution will be taken up
following the pointer number of the jump destination.

286
 CJ, SCJ, JMP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The specified pointer number is not set before the END instruction. A
4210 pointer number which is not in use as a label in the same program has 3
been specified. A common pointer in another program is specified.

Program Example 4
(1) The following program jumps to P3 when X9 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7
(2) The following program jumps to P3 from the next scan after XC goes ON.
[Ladder Mode] [List Mode] 8
Step Instruction Device

6.5.1
6.5 Program Branch Instructions
CJ, SCJ, JMP
Caution
(1) When using the Universal model QCPU and LCPU with the SCJ instruction, inserting "AND SM400" (or the NOP
instruction) in immediately before the SCJ instruction is required.
[Program example 1]
[Ladder Mode] [List Mode]

Step Instruction Device

0 LD M0
1 AND SM400
2 SCJ P0

[Program example 2]
[Ladder Mode] [List Mode]

Step Instruction Device

0 LD M0
1 OUT Y0
2 AND SM400
3 SCJ P0

287
 GOEND

6.5.2 GOEND Jump to END

6.5.2 GOEND Basic High

performance Process Redundant Universal LCPU

Command
GOEND GOEND

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
(1) Jumps to the FEND or END instruction in the same program file.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
After the FOR instruction was executed, the GOEND instruction was
4200
executed prior to the NEXT instruction.
After the CALL, ECALL instruction was executed, the GOEND
4211
instruction was executed prior to the the RET instruction.
During an interrupt program, the GOEND instruction was executed prior
4221
to the IRET instruction.
The GOEND instruction was executed during the CHKCIR to CHKEND
4230
instruction execution.
The GOEND instruction was executed during the IX to IXEND
4231
instruction execution.

Program Example
(1) The following program jumps to the END instruction if D0 holds a negative number.
[Ladder Mode] [List Mode]

Step Instruction Device

288
 DI, EI, IMASK

6.6 Program Execution Control Instructions

1
6.6.1 DI Interrupt disable
EI Interrupt enable

6.6.1
IMASK Interrupt program mask

DI, EI, IMASK High

2
Basic performance Process Redundant Universal LCPU

When the Basic model QCPU is used

3
DI DI

4
Sequence program

IMASK IMASK S

EI EI

S : Interrupt mask data or head number of the devices where the interrupt mask data is stored (BIN 16 bits)

Setting Internal Devices J \

Data Bit Word
R, ZR
Bit Word
U \G Zn Constants Other 6
S –– ––

7
Function
DI
(1) Disables the execution of an interrupt program until the EI instruction has been executed, even if a start cause for the 8
interrupt program occurs.
(2) A DI state is entered when power is turned ON or when the CPU module is reset.

EI

6.6.1
6.6 Program Execution Control Instructions
The EI instruction is used to clear the interrupt disable state resulting from the execution of the DI instruction, and to
create a state in which the interrupt program designated by the interrupt pointer number certified by the IMASK

DI, EI, IMASK

instruction can be executed.
When the IMASK instruction is not executed, I32 to I47 are disabled.

Sequence program

DI
Even if a cause of interrupt occurs during
Sequence program the execution of the sequence program
between the DI and EI instructions, execution
EI of the interrupt program is suspended until
FEND the processing of the sequence program
is completed.
In Interrupt programs

289
 DI, EI, IMASK

IMASK
(1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit
pattern of 8 points from the device designated by S .
• 1(ON).......Interrupt program execution enabled
• 0(OFF).....Interrupt program execution disabled
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
S I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

S+1 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16

S+2 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32

S+3 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48

S+4 I79 I78 I77 I76 I75 I74 I73 I72 I71 I70 I69 I68 I67 I66 I65 I64

S+5 I95 I94 I93 I92 I91 I90 I89 I88 I87 I86 I85 I84 I83 I82 I81 I80

S+6 I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

S+7 I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

(3) When the power is turned ON or when the CPU module has been reset, the execution of interrupt programs I0 to I31,I48
to I127 is enabled, and the execution of interrupt programs I32 to I47 is disabled.
(4) The statuses of devices S , S +1, S +2, and S +3 to S +7 are stored in SD715 to SD717 and SD781 to SD785 (storage
area for the IMASK instruction mask pattern).
(5) Although the special registers are separated as SD715 to SD717 and SD781 to SD785, device numbers should be
designated as S to S +7 successively.

1. An interrupt pointer occupies 1 step.

I 10 X1C
50 Y10
Stored at step 50
X5
53 Y30

55 IRET

2. For the information on interrupt conditions, link direct devices, refer to the QnUCPU User's Manual (Function Explanation,
Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals)
3. The DI state (interrupt disabled) is active during the execution of an interrupt program. Do not insert the EI instructions in
interrupt programs to attempt the execution of multiple interrupts, with interrupt programs running inside interrupt
programs.
4. If there are the EI and DI instructions within a master control, these instructions will be executed regardless of the
execution/non-execution status of the MC instruction.

Operation Error
(1) There is no operation error in the DI, EI, or IMASK instruction.

290
 DI, EI, IMASK

Program Example
1
(1) The following program is designed to enable the execution of only the interrupt programs having the interrupt pointer
numbers I1 and I3 while X0 is ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

6.6.1
6.6 Program Execution Control Instructions
When the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU or LCPU is used

DI, EI, IMASK

DI DI

Sequence program

IMASK IMASK S

EI EI

S : Head number of the devices where the interrupt mask data is stored (BIN 16 bits)

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S –– ––

Function
DI
(1) Disables the execution of an interrupt program until the EI instruction has been executed, even if a start cause for the
interrupt program occurs.
(2) A DI state is entered when power is turned ON or when the CPU module is reset.

291
 DI, EI, IMASK

EI
The EI instruction is used to clear the interrupt disable state resulting from the execution of the DI instruction, and to
create a state in which the interrupt program designated by the interrupt pointer number enabled by the IMASK
instruction and the fixed cycle execution type program can be executed.
When the IMASK instruction is not executed, I32 to I47 are disabled.

Sequence program

DI Even if a cause of interrupt occurs during

Sequence program the execution of the sequence program
between the DI and EI instructions,
EI execution of the interrupt program is
FEDN suspended until the processing of the
sequence program is completed.
In Interrupt programs

IMASK
(1) Enables/disables the execution of the interrupt program marked by the designated interrupt pointer by using the bit
pattern of 16 points from the device designated by S .
• 1(ON).......Interrupt program execution enabled
• 0(OFF).....Interrupt program execution disabled
(2) The interrupt pointer numbers corresponding to the individual bits are as shown below:
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
S I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

S +1 I31 I30 I29 I28 I27 I26 I25 I24 I23 I22 I21 I20 I19 I18 I17 I16

S +2 I47 I46 I45 I44 I43 I42 I41 I40 I39 I38 I37 I36 I35 I34 I33 I32

S +3 I63 I62 I61 I60 I59 I58 I57 I56 I55 I54 I53 I52 I51 I50 I49 I48

S +4 I79 I78 I77 I76 I75 I74 I73 I72 I71 I70 I69 I68 I67 I66 I65 I64

S +5 I95 I94 I93 I92 I91 I90 I89 I88 I87 I86 I85 I84 I83 I82 I81 I80

S +6 I111 I110 I109 I108 I107 I106 I105 I104 I103 I102 I101 I100 I99 I98 I97 I96

S +7 I127 I126 I125 I124 I123 I122 I121 I120 I119 I118 I117 I116 I115 I114 I113 I112

S +8 I143 I142 I141 I140 I139 I138 I137 I136 I135 I134 I133 I132 I131 I130 I129 I128

S +9 I159 I158 I157 I156 I155 I154 I153 I152 I151 I150 I149 I148 I147 I146 I145 I144

S +10 I175 I174 I173 I172 I171 I170 I169 I168 I167 I166 I165 I164 I163 I162 I161 I160

S +11 I191 I190 I189 I188 I187 I186 I185 I184 I183 I182 I181 I180 I179 I178 I177 I176

S +12 I207 I206 I205 I204 I203 I202 I201 I200 I199 I198 I197 I196 I195 I194 I193 I192

S +13 I223 I222 I221 I220 I219 I218 I217 I216 I215 I214 I213 I212 I211 I210 I209 I208

S +14 I239 I238 I237 I236 I235 I234 I233 I232 I231 I230 I229 I228 I227 I226 I225 I224

S +15 I255 I254 I253 I252 I251 I250 I249 I248 I247 I246 I245 I244 I243 I242 I241 I240

(3) When the power is turned on or the CPU module is reset, the interrupt programs are as follows.
(a) High Performance model QCPU, Process CPU, and Redundant CPU
Execution of interrupt programs I0 to I31 and I48 to I255 is enabled, and execution of interrupt programs I32 to I47
is disabled.
(b) Universal model QCPU and LCPU
Execution of interrupt programs I0 to I31 and I45 to I255 is enabled, and execution of interrupt programs I32 to I44
is disabled.
(4) The status of devices S , S +1, S +2, and S +3 to S +15 are stored in SD715 to SD717 and SD781 to SD793 (storage
area for the IMASK instruction mask pattern).
(5) Although the special registers are separated as SD715 to SD717 and SD781 to SD793, device numbers should be
designated as S to S +15 successively.

292
 DI, EI, IMASK

1. An interrupt pointer occupies 1 step.

1
T10 X1C
50 Y10
Stored at step 50
X5
53 Y30 2
55 IRET

2. For the information on interrupt conditions, link direct devices, refer to the QnUCPU User's Manual (Function Explanation, 3
Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals)
3. The DI state (interrupt disabled) is active during the execution of an interrupt program. Do not insert the EI instructions in
interrupt programs to attempt the execution of multiple interrupts, with interrupt programs running inside interrupt
programs. 4
4. If there are the EI and DI instructions within a master control, these instructions will be executed regardless of the
execution/non-execution status of the MC instruction.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. 6
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
7
The device specified by S exceeds the range of the corresponding
4101 –– –– –– ––
device.

6.6.1
6.6 Program Execution Control Instructions
DI, EI, IMASK

293
 DI, EI, IMASK

Program Example
(1) The following program creates an execution enabled state for the interrupt program marked by the interrupt pointer
number when X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

294
 IRET

6.6.2 IRET Recovery from interrupt programs

6.6.2 IRET Basic High

performance Process Redundant Universal LCPU
1

I
** 2
IRET IRET

Setting Internal Devices J \

3
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––
4
Function
(1) Indicates the completion of interrupt program processing.
(2) Returns to sequence program processing following the execution of the IRET instruction.

Operation Error 6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0. 7
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4220 There is no pointer corresponding to the interrupt number. 8
After an interrupt occurred, the END, FEND, GOEND, or STOP
4221
instruction was executed prior to the IRET instruction.
The IRET instruction was executed before the interrupt program is
4223
executed.

6.6.2
6.6 Program Execution Control Instructions
The IRET instruction was executed during the fixed scan execution type
4223 –– –– –– ––
program.

IRET
Program Example
(1) The following program adds 1 to D0 if M0 is ON when the number 3 interrupt is generated.
[Ladder Mode] [List Mode]
Step Instruction Device

295
 RFS, RFSP

6.7 I/O Refresh Instructions

6.7.1 RFS, RFSP I/O refresh

6.7.1 RFS, RFSP Basic High

performance Process Redundant Universal LCPU

Command
RFS RFS S n

Command
RFSP RFSP S n

S : Head number of the devices to be refreshed (bits)

n : Number of refreshes (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

S –– ––
(Only X, Y)
n ––

Function
(1) Refreshes only the device being scanned during a scan, and functions to fetch input from external sources or to output
data to an output module.
(2) Fetching of input from or sending output to an external source is conducted in batch only after the execution of the END
instruction, so it is not possible to output a pulse signal to an outside source during the execution of a scan.
When the I/O refresh instruction is executed, the inputs (X) or outputs (Y) of the corresponding device numbers are
refreshed forcibly midway through program execution. Therefore, a pulse signal can be output to an external source
during a scan.
(3) Use direct access inputs (DX) or direct access outputs (DY) to refresh inputs (X) or outputs (Y) in 1-point units.
[Program based on the RFS instruction]
Command
RFS X0 K1 Refreshes X0
X0
Y20
Command
RFS Y20 K1 Refreshes Y20

[Program based on direct access input and direct access output]

DX0
DY20

Direct access input Direct access output

296
 RFS, RFSP

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
4101 The points specified in n exceed those of the proximate I/O. ––
3

Program Example
4
(1) The following program refreshes X100 to X11F and Y200 to Y23F when M0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

6.7.1
6.7 I/O Refresh Instructions
RFS, RFSP

297
 UDCNT1

6.8 Other Convenient Instructions

6.8.1 UDCNT1 Counter 1-phase input up or down

High

6.8.1
Basic performance Process Redundant Universal LCPU
UDCNT1

Command
UDCNT1 UDCNT1 S D n

S : S + 0: Input number for count input (bits)

S + 1: For setting count up/down (bits)
• OFF: Count up (add numbers when counting)
• ON: Count down (subtract numbers when counting)
D : Number of the counter to be enabled to start counting with the UDCNT1 instruction (Device name)
n : Value to set (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S (Only X)*1 –– –– –– ––

D –– (Only C)*2 –– –– ––
n *2 *2 *2 ––
*1: Only the X device can be used for S . However, the X device can be used only in the range of number of I/O points (the
number of accessible points to actual I/O modules).
*2: Local devices and the file registers set for individual programs cannot be used.

Function
(1) When the input designated at S goes from OFF to ON, the present value of the counter designated at D will be updated.
(2) The direction of the count is determined by the ON/OFF status of the input designated by S +1.
• OFF: Count up (counts by adding to the present value)
• ON : Count down (counts by subtracting from the present value)
(3) Count processing is conducted as described below:
• When the count is going up, the counter contact designated at D goes ON when the present value becomes identical
with the setting value designated by n. However, the present value count will continue even when the contact of the
counter designated at D goes ON. (See Program Example (1))
• When the count is going down, the counter for the contact designated at D goes OFF when the present value
reaches the set value -1. (See Program Example (1))
• The counter designated at D is a ring counter. If it is counting up when the present value is 32767, the present value
will become -32768. Further, if it is counting down when the present value is -32768, the present value will become
32767. The count processing performed on the present value is as shown below:
32768 32767 2 1 0 1 2 32766 32767

When counting up

When counting down

(4) The UDCNT1 instruction triggers counting when the execution command is turned OFF ON and suspends counting
when the execution command is turned ON OFF.
When the execution command is turned OFF ON again, the counting resumes from the suspended value.
(5) The RST instruction clears the present value of the counter designated at D and turns the contact OFF.

298
 UDCNT1

1. With the UDCNT1 instruction, the argument device data is registered in the work area of the CPU module and counting
operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the
1
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be counted
must have longer ON and OFF times than the interrupt interval of the CPU module. The interrupt interval of individual
modules is shown below:
CPU Module Type Name Interrupt Interval
2
High Performance model QCPU, Process CPU,
1 ms
Universal model QCPU, LCPU
2. The set value cannot be changed during counting directed by the UDCNT1 instruction (while the execution command is 3
ON). To change the set value, turn OFF the execution command.
3. Counters designated by the UDCNT1 instruction cannot be used by any other instruction. If they are used by other
instructions, they will not be capable of returning an accurate count.
4. The UDCNT1 instruction can be used as many as 6 times within all the programs being executed. The seventh and the
subsequent UDCNT1 instructions are not processed.
4

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/ 6
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

4101
The device specified by S exceeds the range of the corresponding
–– –– 7
device.

Program Example 8
(1) This program uses C0 (Up/Down counter) to count the number of times X0 goes from OFF to ON after X20 has gone
ON.
[Ladder Mode] [List Mode]

6.8.1
6.8 Other Convenient Instructions
Step Instruction Device

UDCNT1
[Operation]

X20

X0

X1 Up Down Up

C0 present value 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0- 1- 2- 3- 2- 1 0 1 1

C0 contact

299
 UDCNT2

6.8.2 UDCNT2 Counter 2-phase input up or down

6.8.2 UDCNT2 Basic High

performance Process Redundant Universal LCPU

Command
UDCNT2 UDCNT2 S D n

S : S + 0: Input number for count input (A phase pulse) (bits)

S + 1: Input number for count input (B phase pulse) (bits)
D : Number of the counter to be enabled to start counting with the UDCNT2 instruction (Device name)
n : Value to set (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S (Only X)*1 –– –– –– ––

D –– (Only C)*2 –– –– ––
n *2 *2 *2 ––
*1: Only the X device can be used for S . However, the X device can be used only in the range of number of I/O points
(the number of accessible points to actual I/O modules).
*2: Local devices and the file registers set for individual programs cannot be used.

Function
(1) The present value of the counter designated by D is updated depending on the status of the input designated by S (A
phase pulse) and the status of the input designated by S +1 (B phase pulse).
(2) Direction of the count is determined in the following manner:
• When S is ON, if S +1 goes from OFF to ON, count up operation is performed (values are added to the present value
of the counter).
• When S is ON, if S +1 goes from ON to OFF, count down operation is performed (values are subtracted from the
present value of the counter).
• No count operation is performed if S is OFF.
(3) Count processing is conducted as described below:
• When the count is going up, the counter contact designated at D goes ON when the present value becomes identical
with the setting value designated by n. However, the present value count will continue even when the contact of the
counter designated at D goes ON. (See Program Example (1))
• When the count is going down, the counter for the contact designated at D goes OFF when the present value
reaches the set value -1. (See Program Example (1))
• The counter designated at D is a ring counter. If it is counting up when the present value is 32767, the present value
will become -32768. Further, if it is counting down when the present value is -32768, the present value will become
32767. The count processing performed on the present value is as shown below:
32768 32767 2 1 0 1 2 32766 32767

When counting up

When counting down

(4) Count processing conducted according to the UDCNT2 instruction begins when the count command goes from OFF to
ON, and is suspended when it goes from ON to OFF.
When the execution command is turned OFF to ON again, the counting resumes from the suspended value.
(5) The RST instruction clears the present value of the counter designated at D and turns the contact OFF.

300
 UDCNT2

1. With the UDCNT2 instruction, the argument device data is registered in the work area of the CPU module and counting
operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the
1
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be counted
must have longer ON and OFF times than the interrupt interval of the CPU module. The interrupt interval of individual
modules is shown below:
CPU Module Type Name Interrupt Interval
2
High Performance model QCPU, Process CPU,
1 ms
Universal model QCPU, LCPU
2. The set value cannot be changed during counting directed by the UDCNT2 instruction (while the execution command is 3
ON). To change the set value, turn OFF the execution command.
3. Counters designated by the UDCNT2 instruction cannot be used by any other instruction. If they are used by other
instructions, they will not be capable of returning an accurate count.
4. The UDCNT2 instruction can be used as many as 5 times within all the programs being executed. The sixth and the
subsequent UDCNT2 instructions are not processed.
4

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/ 6
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

4101
The device specified by S exceeds the range of the corresponding
–– –– 7
device.

Program Example 8
(1) The following program performs a count operation as instructed by C0 (count up or down) on the status of X0 and X1
after X20 has gone ON.
[Ladder Mode] [List Mode]

6.8.2
6.8 Other Convenient Instructions
Step Instruction Device

UDCNT2
[Operation]

X20

X0

X1

COM present value 0 1 2 3 4 5 4 3 2 1 0 1 2 1 1

C0 contact

301
 TTMR

6.8.3 TTMR Teaching timer

6.8.3 TTMR Basic High

performance Process Redundant Universal LCPU

Command
TTMR TTMR D n

D : D + 0: The device where measurement value is stored (BIN 16 bit)

D + 1: For CPU module system use (BIN 16 bit)
n : Measurement value multiplier (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– –– ––
n –– ––

Function
(1) Measures the time while the execution command is ON in units of seconds, and stores the multiplied value of the
measured time by the multiplier specified by n at the device designated by D .
(2) Clears the device designated by D +0 or D +1 when the execution command is turned OFF ON.
(3) The multipliers that can be designated by n are as shown below:
n Multiplier
0 1
1 10
2 100

1. Time measurements are conducted when the TTMR instruction is executed. Using the JMP or similar instruction to jump
the TTMR instruction will make it impossible to get an accurate measurement.
2. Do not change the multiplier designated by n while the TTMR instruction is being executed. Changing this multiplier will
result in an inaccurate value being returned.
3. The TTMR instruction can also be used in low speed execution type programs.
4. The device designated by D +1 is used by the system of the CPU module, so users should not change its value. If users do
change this value, the value stored in the device designated by D will no longer be accurate.

(4) No processing is performed when the value specified by "n" is other than 0 to 2.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified by D exceeds the range of the corresponding
4101 –– ––
device.

302
 STMR

Program Example
1
(1) The following program stores the amount of time that X0 is ON at D0.
[Ladder Mode] [List Mode]

Step Instruction Device 2

3
6.8.4 STMR Special function timer

6.8.4 STMR Basic High

performance Process Redundant Universal LCPU 4

Command
STMR STMR S n D

: Timer number (word)

6
S

n : Value to set (BIN 16 bits).

D : D + 0: Off delay timer output (bits)
D + 1: One shot timer output after OFF (bits)
D + 2: One shot timer output after ON (bits) 7
D + 3: ON delay and Off delay timer output (bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– *1 –– –– ––
8
n ––
D –– –– –– ––
*1: Can be used only by timer (T) data

6.8.4
6.8 Other Convenient Instructions
Function

STMR
(1) The STMR instruction uses the 4 points from the device designated by D to perform four types of timer output.
• OFF delay timer output ( D +0)
Goes ON at the leading edge of the command for the STMR instruction, and after the trailing edge of the command,
goes OFF when the amount of time designated by n has passed.
• One shot timer output after OFF ( D +1)
Goes ON at the trailing edge of the command for the STMR instruction, and goes OFF when the amount of time
designated by n has passed.
• One shot timer output after ON ( D +2)
Goes ON at the leading edge of the command for the STMR instruction, and goes OFF either when the amount of
time designated by n has passed, or when the command for the STMR instruction goes OFF.
• ON delay timer output ( D +3)
Goes ON at the trailing edge of the timer coil, and after the trailing edge of the command for the STMR instruction,
goes OFF when the amount of time designated by n has passed.
(2) The timer coil designated by S turns ON at the leading edge and trailing edge of the command for the STMR instruction,
and starts measurement of the present value.
• The timer coil measures to the point where the value reaches the set value designated by n, then enters a time up
state and goes OFF.
• If the command for the STMR instruction goes OFF before the timer coil reaches the time up state, it will remain ON.
Timer measurement is continued at this time. When the STRM instruction command goes ON once again, the present
value will be cleared to 0 and measurement will begin once again.

303
 STMR

(3) The timer contact goes ON at the leading edge of the command for the STMR instruction, and after the trailing edge is
reached, the timer coil goes OFF at the trailing edge of the STMR instruction command.
The timer contact is used by the CPU module system, and cannot be used by the user.

Command for
STMR instruction

S (Coil)

S (Contact)

D +0 OFF delay timer

D +1 One-shot timer after OFF

D +2 One-shot timer after ON

D +3 ON delay timer + OFF delay timer

Setting value Set value Set value Set value

designated by n designated by n designated by n designated by n

(4) Measurement of the present value of the timer specified by the STMR instruction is executed regardless of the command
ON/OFF status of the STMR instruction.
If the STMR instruction is jumped with the JMP or similar instruction, it will not be possible to get accurate measurement.
(5) Measurement unit for the timer designated by D is identical to the low speed timer.
(6) A value between 0 to 32767 can be set for n.
No operation if n is other than 0 to 32767.
(7) The timer designated by S cannot be used by the OUT instruction.
If the STMR instruction and the OUT instruction use the same timer number, accurate operation will not be conducted.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified by D exceeds the range of the corresponding
4101 –– ––
device.

304
 ROTC

Program Example
1
(1) The following program turns Y0 and Y1 ON and OFF once each second (flicker) when X20 is ON.
(Uses 100 ms timer)
[Ladder Mode] [List Mode] 2
Step Instruction Device

4
[Timing Chart]

X20

M1, Y0

M2, Y1
6
M3

1 sec 1 sec
7

Caution 8
Note that the STMR instruction operates when the instruction is used within the range written data by the online program
change.
For details, refer to the User's Manual (Function Explanation, Program Fundamentals) for the CPU module used.

6.8.5
6.8 Other Convenient Instructions
6.8.5 ROTC Rotary table shortest direction control

6.8.5 ROTC

ROTC
High
Basic performance Process Redundant Universal LCPU

Command
ROTC ROTC S n1 n2 D

S : S + 0: Measures the number of table rotations (for system use) (BIN 16 bits)
S + 1: Call station number (BIN 16 bits)
S + 2: Call item number (BIN 16 bits)
n1 : Number of divisions of table (2 to 32767) (BIN 16 bits)
n2 : Number of low-speed sections (value from 0 to less than n1) (BIN 16 bits)
D : D + 0: A phase input signal (bits)
D + 1: B phase input signal (bits)
D + 2: 0 point detection input signal (bits)
D + 3: High speed forward rotation output signal (for system use) (bits)
D + 4: Low speed forward rotation output signal (for system use) (bits)
D + 5: Stop output signal (for system use) (bits)
D + 6: Low speed reverse rotation output signal (for system use) (bits)
D + 7: High speed reverse rotation output signal (for system use) (bits)

305
 ROTC

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––
n1 ––
n2 ––
D –– –– ––

Function
(1) This control functions to enable shortest direction control of the rotary table to the position of the station number
designated by S +1 in order to remove or deposit an item whose number has been designated by S +2 on a rotary table
with equal divisions of the value designated by n1.
(2) The item number and station number are controlled as items allocated by counterclockwise rotation.
(3) The system uses S +0 as a counter to instruct it as to what item is at which number counting from station number 0. Do
not rewrite the sequence program data.
Accurate controls will not be possible in cases where users have rewritten the data.
(4) The value of n2 should be less than the number of table divisions specified by n1.
(5) D +0 and D +1 are A and B phase input signals that are used to detect whether the direction of the rotary table rotation is
forward or reverse.
The direction of rotation is judged by whether the B phase pulse is at its leading or trailing edge when the A phase pulse
is ON:
• When the B phase is at the leading edge: Forward rotation (clockwise rotation)
• When the B phase is at the trailing edge: Reverse rotation (counterclockwise rotation)
(6) D +2 is the 0 point detection output signal that goes ON when item number 0 has arrived at the No. 0 station.
When the device designated by D +2 goes ON while the ROTC instruction is being executed, S +0 is cleared.
It is best to perform this clear operation first, then to begin shortest direction control with the ROTC instruction.
(7) The data from D +3 to D +7 consists of output signals needed to control the table's operation.
The output signal of one of the devices from D +3 to D +7 will go ON in response to the execution results of the ROTC
instruction.
(8) If the command for the ROTC instruction is OFF, clears all D +3 to D +7 without performing shortest direction control.
(9) The ROTC instruction can be used only one time in all programs where it is executed.
Attempts to use it more than one time will result in inaccurate operations.
(10) No processing is performed when the value of S +0 to S +2, or the value of n2 is greater than n1.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified by S or D exceeds the range of the
4101 –– ––
corresponding device.

306
 RAMP

Program Example
1
(1) The following program deposits the item at section D2 on a 10-division rotary table at the station at section D1, and the
two sections ahead and behind this determine the rotation direction and control speed of the motor when the table is
being rotated at low speed.
2
[Ladder Mode] [List Mode]

Step Instruction Device

3

Station No. 0

0 point detection 6
X002

9 8
0

X000
Part
7
7
6
1 Detection
switch Forward
rotation 5 8
2 X001
4 Rotary table
3
Station No. 1

6.8.6
6.8 Other Convenient Instructions
6.8.6 RAMP Ramp signal

RAMP
6.8.6 RAMP Basic High
performance Process Redundant Universal LCPU

Command
RAMP RAMP n1 n2 D1 n3 D2

n1 : Initial value (BIN 16 bits)

n2 : Final value (BIN 16 bits)
D1 : D1 + 0: Present value (BIN 16 bits)
+ 1: Number of executions (BIN 16 bits)
D1

n3 : Number of shifts (BIN 16 bits)

D2 : D2 + 0: Completion device (bits)
D2 + 1: Bit for selecting data retaining at completion (bit)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n1 ––
n2 ––
D1 –– ––
n3 ––
D2 –– –– ––

307
 RAMP

Function
(1) When the execution command is ON, the following processing is executed.
• Shifts from the value specified by n1 to the value specified by n2 in the number of times specified by n3.
• For n3, designate the number of scans (number of shifts) required for shift from n1 to n2.
No operation if other than 0<n3<32768.
• The system uses D1 +1 to store the number of times the instruction has been executed.
• The value of one variation (one scan) is obtained by the expression below:
(Value specified by n2) (Value specified by n1)
Value of one variation (one scan)
(Value specified by n3)

Example 0 is varied to 350 in seven scans as shown below.

350
Value stored in 300 (7)
D1 + 0 (Present value) 250 (6)
200
150 (5) Value specified by n2 (350)
(4)
Value specified by n1 (0) 100
(3)
50 (2) Value stored in D1 + 1
(1)
(0) (Number of execution times)

Number of shifts (7) specified by n3

When the calculated one variation is indivisible, compensation is made to achieve the value specified in n2 by the
number of shifts specified in n3.
Hence, a linear ramp may not be made.

(2) If the scan is performed for the number of moves specified by n3, the complete device specified by D2 +0 is turned ON.
The ON/OFF status of the completion device and the contents of D1 +0 are determined by the ON/OFF status of the
device designated by D2 +1.

• When D2 +1 is OFF, +0 will go OFF at the next scan, and the RAMP instruction will begin a new move operation from
the value currently at D2 +0.

• When D2 +1 is ON, D2 +0 will remain ON, and the contents of D1 +0 will not change.

(3) When the command is turned OFF during the execution of this instruction, the contents of D1 +0 will not change following
this.
When the command goes ON again, the RAMP instruction will begin a new move from the present value at +0.

(4) Do not change the specified values in n1 and n2 before the completion device specified in D2 +0 turns ON.
Since the same expression is used every scan to calculate the value stored in D1 +1, changing n1/n2 may cause a
sudden variation.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified by D1 or D2 exceeds the range of the
4101 –– ––
corresponding device.

Caution
(1) When the digit specification of bit device is made to D1 , the digit specification of bit device can only be used when the
following condition is met.
• Specification of digits: K8

308
 SPD

Program Example
1
(1) The following program changes the contents of D0 from 10 to 100 in a total of 6 scans, and saves the contents of D0
when the move has been completed.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Timing Chart] 4
ON

X0 OFF

D0 10 25 40 55 70 85 100
D1 0 1 2 3 4 5 6

1 scan 1 scan 1 scan 1 scan 1 scan 1 scan

ON
6
M0 OFF

ON 7
M1 OFF

8
6.8.7 SPD Pulse density measurement

6.8.7 SPD Basic High

performance Process Redundant Universal LCPU

Command
SPD

6.8.7
6.8 Other Convenient Instructions
SPD S n D

SPD
S : Pulse input (bits)
n : Measurement time (unit: ms) (BIN 16 bits)
D : Head number of the devices where the measurement result will be stored (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S (Only X) –– –– ––
n *1 *1 ––

D –– *1 –– ––
*1: Local devices and the file registers set for individual programs cannot be used.

309
 SPD

Function
(1) The number of turning OFF ON input of the device specified by S is counted for just the amount of time specified by n,
and the count results are stored in the device specified by D .
Start of measurement
n [ms] n [ms]

ON
Execution command OFF

ON
S OFF

Measurement result is stored at (D) Measurement result is stored at (D)

(2) When measurement directed by the SPD instruction has been completed, measurement is done again from 0.
Turn OFF the execution command to stop the measurement directed by the SPD instruction.

1. With the SPD instruction, the argument device data is registered in the work area of the CPU module and counting
operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be counted
must have longer ON and OFF times than the interrupt interval of the CPU module. The interrupt interval of individual
modules is shown below:
CPU Module Type Name Interrupt Interval
High Performance model QCPU, Process CPU,
1 ms
Universal model QCPU, LCPU
2. When the High Performance model QCPU or Process CPU is used:
The instruction is not processed when n = 0.
3. The SPD instruction can be used as many as 6 times within all the programs being executed. The seventh and the
subsequent SPD instructions are not processed.
4. While the measurement is in execution (while the command input is ON) by the SPD instruction, the setting value cannot
be changed. Turn OFF the command input before changing the setting value.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified by S exceeds the range of the corresponding
4101 –– ––
device.

Program Example
(1) The following program measures the pulses input to X0 for a period of 500 ms when X10 goes ON, and stores the result
at D0.
[Ladder Mode] [List Mode]

Step Instruction Device

310
 PLSY

6.8.8 PLSY Fixed cycle pulse output

6.8.8 PLSY Basic High

performance Process Redundant Universal LCPU 1

PLSY
Command
PLSY n1 n2 D 2

n1
n2
: Frequency or the number of the device where frequency is stored (BIN 16 bits)
: Outputs count or the number of the device where the outputs count is stored (BIN 16 bits)
3
D : Number of the device to which pulses are output (bits)

Setting Internal Devices J \ Constants

Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other 4
n1 ––
n2 ––
D *1 –– ––
*1: Only output (Y) can be used.

Function 6
(1) Outputs a pulse at a frequency designated by n1 the number of times designated by n2, to the output module with the
output signal (Y) designated by D . 7
(2) Frequencies between 1 to 100 Hz can be designated by n1.
If n1 is other than 1 to 100 Hz, the PLSY instruction will not be executed.
(3) The number of outputs that can be designated by n2 is between 0 to 65535 (0000H to FFFFH). 8
If n2 is set to "0", pulses are continuously output.
(4) Only an output number corresponding to the output module can be designated for pulse output at D .
(5) Pulse output commences with the command leading edge of the PLSY instruction.

6.8.8
6.8 Other Convenient Instructions
Pulse output is suspended when the PLSY instruction command goes OFF.

PLSY
1. With the PLSY instruction, the argument device data is registered in the work area of the CPU module and counting
operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the
execution command OFF, or turning the STOP/RUN switch STOP RUN.) For this reason, the pulses that can be output
must have longer ON and OFF times than the interrupt interval of the CPU module. The interrupt interval of individual
modules is shown below:
CPU Module Type Name Interrupt Interval
High Performance model QCPU, Process CPU,
1 ms
Universal model QCPU, LCPU
2. Do not change the argument for the PLSY instruction during pulse output directed by the PLSY instruction (while the
execution command is ON). To change the argument, turn OFF the execution command.
3. The PLSY instruction can be used only once in all programs executed by the CPU module. The second and the
subsequent PLSY instructions are not processed.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified by D exceeds the range of the corresponding
4101 –– ––
device.

311
 PWM

Program Example
(1) The following program outputs a 10 Hz pulse 5 times to Y20 when X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

6.8.9 PWM Pulse width modulation

6.8.9 PWM Basic High

performance Process Redundant Universal LCPU

Command
PWM PWM n1 n2 D

n1 : ON time or the number of the device where the ON time is stored (BIN 16 bits)
n2 : Frequency or the number of the device where the frequency is stored (BIN 16 bits)
D : Number of the device to which pulses are output (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n1 ––
n2 ––
D *1 –– ––
*1: Only output (Y) can be used.

Function
(1) Outputs the pulse of the cycle set by n2, for the amount of time ON designated by n1, to the output module designated
by D .

n1

n2

(2) The setting ranges for n1 and n2 are shown below:

CPU Module Type Name Setting Range for n1 and n2 [ms] *2
High Performance model QCPU, Process CPU,
1 to 65535 (0001H to FFFFH)
Universal model QCPU, LCPU
*2: The value specified by n1 should be less than the value specified by n2.

312
 MTR

1. With the PWM instruction, the argument device data is registered in the work area of the CPU module and counting
operation is processed as a system interrupt. (The device data registered in the work area is cleared by turning the
1
execution command OFF, or turning the STOP/RUN switch STOP RUN.) The interrupt interval of individual modules is
shown below:
CPU Module Type Name Interrupt Interval of n1, n2
2
High Performance model QCPU, Process CPU,
1 ms
Universal model QCPU, LCPU

For this reason, the PWM instruction can be used only once within all the programs being executed by the CPU module.
2. The instruction is not processed in the following cases:
3
• When both n1 and n2 are 0
• When n1 n2
• When the PWM instruction is executed twice or more.
3. Do not change the argument for the PWM instruction during pulse output directed by the PWM instruction (while the
4
execution command is ON). To change the argument, turn OFF the execution command.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. 6
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified by S exceeds the range of the corresponding
7
4101 –– ––
device.

8
Program Example
(1) The following program outputs a 100 ms pulse once each second to Y20 when X0 is ON.
[Ladder Mode] [List Mode]

6.8.10 MTR
6.8 Other Convenient Instructions
Step Instruction Device

6.8.10 MTR Matrix input

6.8.10 MTR Basic High

performance Process Redundant Universal LCPU

Command
MTR MTR S D1 D2 n

S : Head input device (bits)

D1 : Head output device (bits)
D2 : Head number of the devices where matrix input data will be stored (bits)
n : Number of input rows (BIN 16 bit)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S (Only X) –– ––
D1 (Only Y) –– ––
D2 –– ––
n ––

313
 MTR

Function
(1) It reads the input from 16 points n-rows starting from the input number designated by S , then stores fetched input data
from the device designated by D2 onward.
(2) One row (16 points) can be fetched in 1 scan.
(3) Fetching from the first to the n th row is repeated.
(4) The first through the 16th points store the first row of data and the next 16 points store the second row of data at the
devices following the device designated by D2 .

For this reason, the space of 16 n points from the device designated by D2 are occupied by the MTR instruction.

(5) D1 is the output needed to select the row which will be fetched, and the system automatically turns it ON and OFF.
It uses the n points from the device designated by D1 .

(6) Only device numbers divisible by 16 can be designated for S , D1 and D2 .

(7) For n, a value in the range from 2 to 8 can be assigned.

(8) No processing is performed in the following cases.
• The device number designated by S , D1 , or D2 is not divisible by 16.
• The device designated by S is outside the actual input range.
• The device designated by D1 is outside the actual output range.
• The space 16 n points following the device designated by D2 exceeds the relevant device range.
• The value for n is not between 2 and 8.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device other than the input (X) was specified at S .
4101 –– ––
The device other than the output (Y) was specified at D1 .

Program Example
(1) The following program fetches, when X0 is turned ON, the 16 points 3 matrix starting from X10, and stores the matrix
into the area starting from M0.
[Ladder Mode] [List Mode]
Step Instruction Device

314
 MTR

[Operation]
3rd row

Y20 Y21 Y22

M32
1
M33

M34

M35

M36

M37

M38

M39

M40

M41

M42

M43

M44

M45

M46

M47
X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F 2
2nd row
M16

M17

M18

M19

M20

M21

M22

M23

M24

M25

M26

M27

M28

M29

M30

M31
3
X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F
1st row 4

M10

M11

M12

M13

M14

M15
M0

M1

M2

M3

M4

M5

M6

M7

M8

M9
X010 X011 X012 X013 X014 X015 X016 X017 X018 X019 X01A X01B X01C X01D X01E X01F

6
Caution
(1) Note that the MTR instruction directly operates on actual input and output. 7
The output D1 that had been turned ON by the MTR instruction does not turn OFF when the MTR command turns OFF.
Turn OFF the specified output D1 in the sequence program.
(2) The MTR instruction execution interval must be longer than the total of response time of input and output modules. 8
If the set interval is shorter than the value indicated above, an input cannot be read correctly.
If the scan time in a sequence program is short, select the constant scan and set the scan time longer than the total of
response time.

6.8.10 MTR
6.8 Other Convenient Instructions

315
CHAPTER 7 APPLICATION INSTRUCTIONS

7.1 Logical operation instructions

(1) The logical operation instructions perform logical sum, logical product or other logical operations in 1-bit units.
Example
Category Processing Details Formula for Operation
A B Y
0 0 0
Logical product Becomes 1 only when both input A and 0 1 0
Y A·B
(AND) input B are 1; otherwise, is 0 1 0 0
1 1 1
0 0 0
Logical sum Becomes 0 only when both input A and 0 1 1
Y A+B
(OR) input B are 0; otherwise, is 1 1 0 1
1 1 1
0 0 0
Exclusive OR Becomes 0 if input A and input B are 0 1 1
(XOR) equal; otherwise, is 1 Y A·B+A·B 1 0 1
1 1 0
0 0 1
NON exclusive
Becomes 1 if input A and input B are 0 1 0
logical sum
equal; otherwise, is 0 Y (A + B)(A + B) 1 0 0
(XNR)
1 1 1

316
 WAND, WANDP, DAND, DANDP

7.1.1 WAND, WANDP Logical products with 16-bit data

7.1.1
DAND, DANDP Logical products with 32-bit data

WAND, WANDP, DAND, DANDP High

1
Basic performance Process Redundant Universal LCPU

When two data are set ( D S D , ( D +1, D ) ( S +1, S ) ( D +1, D ))

indicates an instruction symbol of WAND/DAND.

2
Command
WAND,DAND S D

Command
3
P D
WANDP,DANDP S

S : Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits) 4
D : Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––
4
D –– ––

6
Function
WAND 7
(1) A logical product operation is conducted for each bit of the 16-bit data of the device designated at D and the 16-bit data
of the device designated at S , and the results are stored in the device designated at D .

b15 b8 b7 b0 8
D 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1
AND
b15 b8 b7 b0
S 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

b15 b8 b7 b0

7.1.1
7.1 Logical operation instructions
D 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0

(2) When bit devices are designated, the bit devices after the points designated as digits are regarded as "0" in the

WAND, WANDP, DAND, DANDP

operation. (See Program Example (2))

DAND
(1) Conducts a logical product operation on each bit of the 32-bit data for the device designated by S1 and the 32-bit data for
the device designated by S2 , and stores the results at the device designated by D .
D +1 D
b31 b16 b15 b0
D 1 1 1 1 1 1 0 0 1 1 0 0 1 1

AND
S +1 S
b31 b16 b15 b0
S 0 1 0 1 1 0 0 1 0 1 0 0 0 1

D +1 D
b31 b16 b15 b0
D 0 1 0 1 1 0 0 0 0 1 0 0 0 1

(2) When bit devices are designated, the bit devices below the points designated as digits are regarded as "0" in the
operation. (See Program Example (2))

Operation Error
(1) There is no operation error in the WAND(P) or DAND(P) instruction.

317
 WAND, WANDP, DAND, DANDP

Program Example
(1) The following program masks the digit in the 10s place of the 4-digit BCD value at D10 (second digit from the end) to 0
when XA is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 BCD1234 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0
AND
b15 b8 b7 b0
HFF0F 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

b15 b8 b7 b0
D10 BCD1204 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0

(2) The following program performs a logical product operation on the data at D99 and D100, and the 24-bit data between
X30 and X47 when X8 is ON, and stores the results at D99 and D100.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b31 b30b29 b28 b27 b26 b25b24 b23 b22 b3 b2 b1 b0
D100, D99 1 1 1 1 1 1 1 1 1 1 1 1 1 1
AND
X47X46 X33X32X31X30
X47 X30 0 0 0 0 0 0 0 0 1 1 0 1 0 1

Regarded as 0s.

b31 b30 b29 b28 b27b26 b25b24 b23 b22 b3 b2 b1 b0

D100, D99 0 0 0 0 0 0 0 0 1 1 0 1 0 1

When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WAND/DAND.

Command
WAND,DAND S1 S2 D

Command
WANDP,DANDP P S1 S2 D

S1 , S2 : Data for a logical product operation or the head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the logical product operation result will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––

D –– ––

318
 WAND, WANDP, DAND, DANDP

Function
1
WAND
(1) A logical product operation is conducted for each bit of the 16-bit data of the device designated at S1 and the 16-bit data
of the device designated at S2 , and the results are stored in the device designated at D . 2
b15 b8 b7 b0
S1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

3
AND
b15 b8 b7 b0
S2 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0

b15 b8 b7 b0
D 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0
4
(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.
(See Program Examples (1) and (2))

DAND 4
(1) Conducts a logical product operation on each bit of the 32-bit data for the device designated by S1 and the 32-bit data for
the device designated by S2 , and stores the results at the device designated by .
6
D

S1 + 1 S1
b31 b16 b15 b0
S1 1 1 1 1 1 1 0 0 1 1 0 0 1 1

S2 + 1
AND
S2
7
b31 b16 b15 b0
S2 0 1 0 1 1 0 0 1 0 1 0 0 0 1

D+1 D
8
b31 b16 b15 b0
D 0 1 0 1 1 0 0 0 0 1 0 0 0 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation. (See
Program Example (3))

7.1.1
7.1 Logical operation instructions
Operation Error

WAND, WANDP, DAND, DANDP

(1) There is no operation error in the WAND(P) or DAND(P) instruction.

Program Example
(1) The following program performs a logical product operation on the data from X10 to X1B and the data at D33 when XA is
ON, and stores the results at D40.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
X1B X18X17 X13 X10
X1B to X10 0 0 0 0 1 0 0 1 0 0 1 1 1 1 0 0
Regarded as 0s.
AND
b15 b8 b7 b0
D33 0 1 0 1 1 1 0 1 1 1 1 1 0 0 0 0

b15 b8 b7 b0
D40 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0

319
 WAND, WANDP, DAND, DANDP

(2) The following program performs a logical product operation on the data at D10 and at D20 when X1C is ON, and stores
the results from M0 to M11.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
AND
b15 b8 b7 b0
D20 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1

M15 M12 M11 M8 M7 M4 M3 M0

1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0

Not changed
(3) The following program masks the digit in the hundred-thousands place of the 8-digit BCD value at D10 and D11 (sixth
digit from the end) to 0 when XA is ON, and outputs the results to from Y10 to Y2B.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b31 b16b15 b0
D10, D11 (BCD12345678) 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
AND
b31 b16b15 b0
H FF0FFFFF 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

Y2F Y2C Y2B Y28 Y27 Y24 Y23 Y20 Y1F Y1CY1B Y18 Y17 Y14 Y13 Y10
Y2B to Y10 1 1 1 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0
Not changed

320
 BKAND, BKANDP

7.1.2 BKAND, BKANDP Block logical products

7.1.2 BKAND, BKANDP Basic High

performance Process Redundant Universal LCPU
1
Command
BKAND
2
BKAND S1 S2 D n

Command
BKANDP S1 S2 D n
BKANDP
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) 3
S2 *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits)
D *1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
n : Number of operation data blocks (BIN 16 bits)
Setting Internal Devices J \ Constants
4
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 *1 –– –– –– ––
S2
*1 –– –– ––
4
D *1 –– –– –– ––
n ––
*1: The same device number can be specified for S1 and D or S2 and D .
6

Function 7
(1) Performs a logical product operation on the data located in the n points from the device designated by S1 , and the data
located in the n points from the device designated by S2 , and stores the results into the area starting from the device 8
designated by D .
b15 b8 b7 b0 b15 b8 b7 b0
S1 0011001100110011 S2 0011110000111100
S1 + 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 S2 + 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

7.1.2
7.1 Logical operation instructions
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 + 2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
n n
AND

BKAND, BKANDP
S1 +(n 2) 0101010101010101 S2 +(n 2) 1111111111111111
S1 +(n 1) 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S2 +(n 1) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0

b15 b8b7 b0
D 0011000000110000
D +1 1111000000000000
D +2 0000000011111111
n

D +(n 2) 0101010101010101
D +(n 1) 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0

321
 BKAND, BKANDP

(2) The constant designated by S2 can be between -32768 and 32767 (BIN 16-bit data).
b15 b8 b7 b0
S1 0011001100110011
S1 + 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b15 b8b7 b0
n BKAND S2 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1

S1 + (n 2) 0101010101010101
S1 + (n 1) 1111000011110000

b15 b8 b7 b0
D 0011001100000011
D +1 1111000000001111
D +2 0000000000001111
n

D + (n 2) 0101010100000101
D + (n 1) 1111000000000000

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
specified in S1 , S2 , or D .
The ranges of devices starting from the one specified in S1 and D

overlap by n points (except when the same device is specified in S1 and

4101
D ).
The ranges of devices starting from the one specified in S2 and D

overlap by n points (except when the same device is specified in S2 and

D ).

Program Example
(1) The following program performs a logical product operation on the data stored at D100 to D102 and the data stored at R0
to R2 when X20 is turned ON, and stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8 b7 b0 b15 b8b7 b0
D100 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 R0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
BKAND
D101 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 R1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
D102 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1

b15 b8 b7 b0
D200 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D0 3
D201 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
D202 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

322
 WOR, WORP, DOR, DORP

7.1.3 WOR, WORP Logical sums of 16-bit data

7.1.3
DOR, DORP Logical sums of 32-bit data

WOR, WORP, DOR, DORP High

1
Basic performance Process Redundant Universal LCPU

When two data are set ( D S D , ( D +1, D ) ( S +1, S ) ( D +1, D ))

indicates an instruction symbol of WOR/DOR.

2
Command
WOR, DOR S D

Command
3
P S D
WORP, DORP
S : Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits) 4
D : Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––
4
D –– ––

6
Function
WOR 7
(1) Conducts a logical sum operation on each bit of the 16-bit data of the device designated by D and the 16-bit data of the
device designated by S , and stores the results at the device designated by D .

D
b15
0 1 0 1 1 1 1
b8 b7
1 0 0 0 0 0 0 1
b0
1
8
OR
b15 b8 b7 b0
S 1 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0

b15 b8 b7 b0

7.1.3
7.1 Logical operation instructions
D 1 1 0 1 1 1 1 1 1 1 0 0 1 1 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

WOR, WORP, DOR, DORP

DOR
(1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by D and the 32-bit data of the
device designated by S , and stores the results at the device designated by D .
D +1 D
b31 b16 b15 b0
D 1 1 1 1 0 0 0 0 0 0 0 0 1 1

OR
S +1 S
b31 b16 b15 b0
S 1 0 0 1 0 0 0 1 1 1 0 0 1 1

D +1 D
b31 b16 b15 b0
D 1 1 1 1 0 0 0 1 1 1 0 0 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

Operation Error
(1) There is no operation error in the WOR(P) or DOR(P) instruction.

323
 WOR, WORP, DOR, DORP

Program Example
(1) The following program performs a logical sum operation on the data at D10 and D20 when XA is turned ON, and stores
the results at D10.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 1 1 0 0 1 1 0 0 1 1 1 1 0 0 0 0
OR
b15 b8 b7 b0
D20 0 0 0 0 1 0 1 1 1 0 0 1 0 0 0 1

b15 b8 b7 b0
D10 1 1 0 0 1 1 1 1 1 1 1 1 0 0 0 1
(2) The following program performs a logical sum operation on the 32-bit data from X0 to X1F, and on the hexadecimal value
FF00FF00H when XB is turned ON, and stores the results at D66 and D67.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

S +1 S
X1F X1C X10 XF X3 X0
X1F X0 1 0 1 0 0 0 0 0 0 0 1 0 1 0

OR
D +1 D
b31 b16 b15 b0
FF00FF00H 1 1 1 1 0 0 0 1 1 1 0 0 0 0

D +1 D
b31 b16 b15 b0
D67,D66 1 1 1 1 0 0 0 1 1 1 1 0 1 0

324
 WOR, WORP, DOR, DORP

When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WOR/DOR.

1
Command
WOR, DOR S1 S2 D

Command
2
WORP, DORP P S1 S2 D

S1 , S2

D
: Data for a logical sum operation or head number of the devices where the data is stored (BIN 16/32 bits)
: Head number of the devices where the logical sum operation result will be stored (BIN 16/32 bits)
3
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
4
S2 ––

D –– ––
4
Function
6
WOR
(1) Conducts a logical sum operation on each bit of the 16-bit data of the device designated by S1 and the 16-bit data of the
device designated by S2 , and stores the results at the device designated by D . 7
b15 b8 b7 b0
S1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 0 0

b15
OR
b8 b7 b0 8
S2 0 0 0 0 1 1 0 0 1 1 0 0 0 0 1 1

b15 b8 b7 b0
D 1 1 0 0 1 1 0 0 1 1 1 1 0 0 1 1

7.1.3
7.1 Logical operation instructions
(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.
(See Program Example (1))

WOR, WORP, DOR, DORP

DOR
(1) Conducts a logical sum operation on each bit of the 32-bit data of the device designated by S1 and the 32-bit data of the
device designated by S2 , and stores the results at the device designated by D .
S1 + 1 S1

b31 b16 b15 b0

S1 0 0 1 1 0 0 1 1 0 0 1 1 0 0

OR
S2 + 1 S2
b31 b16 b15 b0
S2 0 0 1 0 1 1 0 0 0 0 1 1 1 1

D +1 D
b31 b16 b15 b0
D 0 0 1 1 1 1 1 1 0 0 1 1 1 1
(2) When bit devices are designated, the bit devices below the points designated as digits are regarded as "0" in the
operation. (See Program Example (2))

Operation Error
(1) There is no operation error in the WOR(P) or DOR(P) instruction.

325
 WOR, WORP, DOR, DORP

Program Example
(1) The following program performs a logical sum operation on the data from X10 to X1B, and the data at D33, and stores
the result at Y30 to Y3B when XA is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X1B X18X17 X14X13 X10
X1B to X10 0 0 0 0 1 1 0 0 0 0 1 1 0 0 0 0

Regarded as 0s.
OR
b15 b8 B7 b0
D33 1 1 1 1 1 0 0 1 1 0 0 1 0 0 1 1

Y3B Y38Y37 Y34Y33 Y30

Y3B to Y30 1 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1

Not changed

(2) The following program performs a logical sum operation on the 32-bit data at D0 and D1, and the 24-bit data from X20 to
X37, and stores the results at D23 and D24 when M8 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
S +1 S
b31 b28 b27 b24 b23 b22b21 b3 b2 b1 b0
D1, D0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1
OR
X37X36X35 X23X22X21X20
X37 to X20 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1

Regarded as 0s.

D +1 D
b31 b16 b15 b0
D24, D23 1 1 1 1 0 0 0 0 1 1 0 1 1 1 1

326
 BKOR, BKORP

7.1.4 BKOR, BKORP Block logical sum operations

7.1.4 BKOR, BKORP Basic High

performance Process Redundant Universal LCPU
1
Command
BKOR BKOR S1 S2 D n

Command
2
BKORP S1 S2 D n
BKORP
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) 3
S2 *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits)
D *1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
n : Number of operation data blocks (BIN 16 bits)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other
4
Data Bit Word Bit Word K, H
S1
*1 –– –– –– ––
S2
*1 –– –– –– 4
D *1 –– –– –– ––
n ––
*1: The same device number can be specified for S1 and D or S2 and D . 6

Function
7
(1) Performs a logical sum operation on the data located in the n points from the device designated by S1 , and the data
located in the n points from the device designated by S2 , and stores the results into the area starting from the device
designated by D . 8
b15 b8 b7 b0 b15 b8 b7 b0
S1 0000111100001111 S2 0000111111000011
S1 + 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 S2 + 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1

7.1.4
7.1 Logical operation instructions
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 + 2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
n n
OR

0000111111110000 0011001100110011

BKOR, BKORP
S1 +(n 2) S2 +(n 2)
S1 +(n 1) 1111111100000000 S2 +(n 1) 0011110000001111

b15 b8 b7 b0
D 0000111111001111
D +1 1100110011111111
D +2 0000111111111111
n

D +(n 2) 0011111111110011
D +(n 1) 1111111100001111

327
 BKOR, BKORP

(2) The constant designated by S2 can be between -32768 and 32767 (BIN 16-bit data).
b15 b8 b7 b0
S1 0011110011000011
S1 + 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0
S1 + 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 b15 b8 b7 b0
n OR S2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

S1 +(n 2) 0000111100001111
S1 +(n 1) 1100001111000011

b15 b8 b7 b0
D 0011111111110011
D +1 0000111111111010
D +2 1010111111111010
n

D +(n 2) 0000111111111111
D +(n 1) 1100111111110011

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
specified in S1 , S2 , or D .
The ranges of devices starting from the one specified in S1 and D

overlap by n points (except when the same device is specified in S1 and

4101
D ).
The ranges of devices starting from the one specified in S2 and D

overlap by n points (except when the same device is specified in S2 and

D ).

Program Example
(1) The following program performs a logical sum operation on the data stored at D100 to D102 and the data stored at R0 to
R2 when X20 is turned ON, and stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

b15 b8 b7 b0 b15 b8 b7 b0
D100 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 R0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0
OR
D101 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 R1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
D102 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 R2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

b15 b8 b7 b0
D200 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 0
D201 0 0 1 1 1 1 1 1 1 1 1 1 0 0 1 1
D202 1 1 0 0 1 1 1 1 0 0 1 1 1 1 1 1 D0 3

328
 WXOR, WXORP, DXOR, DXORP

7.1.5 WXOR, WXORP 16-bit exclusive OR operations

7.1.5
DXOR, DXORP 32-bit exclusive OR operations

WXOR, WXORP, DXOR, DXORP High

1
Basic performance Process Redundant Universal LCPU

When two data are set (D S D , ( D +1, D ) ( S +1, S ) ( D +1, D ))

indicates an instruction symbol of WXOR/DXOR.

2
Command
WXOR, DXOR S D

Command
3
P S D
WXORP, DXOR
S : Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits) 4
D : Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––
4
D –– ––

6
Function
WXOR 7
(1) Conducts an exclusive OR operation on each bit of the 16-bit data of the device designated by D and the 16-bit data of
the device designated by S , and stores the results at the device designated by D .

D
b15
1 0 1 0 1 0 1
b8 b7
0 1 0 1 0 1 0 1
b0
0
8
XOR
b15 b8 b7 b0
S 0 0 0 1 1 0 1 1 1 1 1 1 0 0 0 0

b15 b8 b7 b0

7.1.5
7.1 Logical operation instructions
D 1 0 1 1 0 0 0 1 0 1 0 1 1 0 1 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

WXOR, WXORP, DXOR, DXORP

DXOR
(1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated by D and the 32-bit data of
the device designated by S , and stores the results at the device designated by D .
D +1 D
b31 b16 b15 b0
D 0 1 0 1 0 1 0 1 0 1 0 1 0 1

XOR
S +1 S

b31 b16 b15 b0

S 0 1 1 0 0 1 1 0 1 0 0 1 1 0

D +1 D

b31 b16 b15 b0

D 0 0 1 1 0 0 1 1 1 1 0 0 1 1

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

Operation Error
(1) There is no operation error in the WXOR(P) or DXOR(P) instruction.

329
 WXOR, WXORP, DXOR, DXORP

Program Example
(1) The following program performs an exclusive OR operation on the data at D10 and D20 when XA is ON, and stores the
result at D10.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
D10 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XOR
b15 b8 b7 b0
D20 0 0 1 1 1 0 0 1 0 0 1 1 1 0 0 1

b15 b8 b7 b0
D10 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0

(2) The following program compares the bit pattern of the 32-bit data from X20 to X3F with the bit pattern of the data at D9
and D10 when X6 is ON, and stores the number of differing bits at D16.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
S +1 S
X3F X3C X3B X38 X37 X34 X33 X30 X2F X2CX2B X28 X27 X24 X23 X20
X3F to X20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XOR
D +1 D

b31 b16 b15 b0

D10,D9 1 0 1 1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 1 1 0 1 0 1 1 0 1

D +1 D

b31 b16 b15 b0

D10,D9 1 1 1 0 1 1 0 0 1 0 0 1 0 1 0 0 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0

D16 17

Remark
See Page 369, Section 7.5.2 for more information on the DSUMP instruction.

330
 WXOR, WXORP, DXOR, DXORP

When three data are set ( S1 S2 D ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WXOR/DXOR.

1
Command
WXOR, DXOR S1 S2 D

Command
2
WXORP, DXORP P S1 S2 D

S1 , S2

D
: Data for an exclusive OR operation or head number of the devices where the data is stored (BIN 16/32 bits)
: Head number of the devices where the exclusive OR operation result will be stored (BIN 16/32 bits)
3
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
4
S2 ––
–– ––
D
4
Function
WXOR
6
(1) Conducts an exclusive OR operation on each bit of the 16-bit data of the device designated by S1 and the 16-bit data of
the device designated by S2 , and stores the results at the device designated by D . 7
b15 b8 b7 b0
S1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

b15
XOR
b8 b7 b0 8
S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

b15 b8 b7 b0
D 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1

7.1.5
7.1 Logical operation instructions
(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.
(See Program Example (1))

WXOR, WXORP, DXOR, DXORP

DXOR
(1) Conducts an exclusive OR operation on each bit of the 32-bit data of the device designated by S1 and the 32-bit data of
the device designated by S2 , and stores the results at the device designated by D .
S1 + 1 S1
b31 b16 b15 b0
S1 1 1 1 1 0 0 0 0 0 0 1 1 1 1

XOR
S2 + 1 S2
b31 b16 b15 b0
S2 1 1 1 1 1 0 1 0 1 0 1 1 0 0

D +1 D
b31 b16 b15 b0
D 0 0 0 0 1 0 1 0 1 0 0 0 1 1
(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

Operation Error
(1) There is no operation error in the WXOR(P) or DXOR(P) instruction.

331
 WXOR, WXORP, DXOR, DXORP

Program Example
(1) The following program conducts an exclusive OR operation on the data from X10 to X1B and the data at D33 when X10
is ON, and outputs the result to Y30 to Y3B.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
X1B X18X17 X14X13 X10
X1B to X10 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1

Regarded as 0s.
XOR
b15 b8 b7 b0
D33 1 1 1 1 0 0 1 1 0 0 1 1 1 0 0 1

Y3B Y38Y37 Y34Y33 Y30

Y3B to Y30 0 1 1 0 0 1 1 0 0 1 1 0 1 1 0 0
Not changed
(2) The following program conducts an exclusive OR operation on the data at D20 and D21, and the data at D30 and D31
when X10 is turned ON, and stores the results at D40 and D41.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
S1 + 1 S1
b31 b16 b15 b0
D21,D20 1 1 0 0 1 0 1 0 1 1 0 0 1 1

XOR
S2 + 1 S2
b31 b16 b15 b0
D31,D30 0 0 0 0 1 1 0 0 0 1 0 1 0 1

D +1 D
b31 b16 b15 b0
D41,D40 1 1 0 0 0 1 1 0 1 0 0 1 1 0

332
 BKXOR, BKXORP

7.1.6 BKXOR, BKXORP Block exclusive OR operations

7.1.6 BKXOR, BKXORP Basic High

performance Process Redundant Universal LCPU
1
Command
BKXOR BKXOR S1 S2 D n

Command
2
BKXORP S1 S2 D n
BKXORP
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits) 3
S2 *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits)
D *1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
n : Number of operation data blocks (BIN 16 bits)
Setting Internal Devices
R, ZR
J \
Zn
Constants
Other
4
U \G
Data Bit Word Bit Word K, H
S1 *1 –– –– –– ––
S2
*1 –– –– –– 4
D *1 –– –– –– ––
n ––
*1: The same device number can be specified for S1 and D or S2 and D . 6

Function 7
(1) Performs an exclusive OR operation on the data located in the n points from the device designated by S1 , and the data
located in the n points from the device designated by S2 , and stores the results into the area starting from the device
designated by D . 8
b15 b8 b7 b0 b15 b8b7 b0
S1 0011001100000011 S2 0011110000111100
S1 + 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 S2 + 1 0 0 1 1 1 1 0 0 0 0 0 0 1 1 0 0

7.1.6
7.1 Logical operation instructions
S1 + 2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S2 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
n n
XOR

BKXOR, BKXORP
S1 +(n 2) 0000000011111111 S2 +(n 2) 1111111100001111
S1 +(n 1) 0000111111110000 S2 +(n 1) 0000111111111111

b15 b8 b7 b0
D 0000111100111111
D +1 1111000011000000
D +2 1111000000001111
n

D +(n 2) 1111111111110000
D +(n 1) 0000000000001111

333
 BKXOR, BKXORP

(2) The constant designated by S2 can be between -32768 and 32767 (BIN 16-bit data).
b15 b8b7 b0
S1 1111111100000000
S1 + 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
S1 + 2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b15 b8b7 b0
n XOR S2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

S1 +(n 2) 1111111100001111
S1 +(n 1) 0101010101010101

b15 b8b7 b0
D 0101010110101010
D +1 1010010101011010
D +2 1010101001010101
n

D +(n 2) 0101010110100101
D +(n 1) 1111111111111111

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
specified in S1 , S2 , or D .
The ranges of devices starting from the one specified in S1 and D

overlap by n points (except when the same device is specified in S1 and

4101
D ).
The ranges of devices starting from the one specified in S2 and D

overlap by n points (except when the same device is specified in S2 and

D ).

Program Example
(1) The following program performs an exclusive OR operation on the data stored at D100 to D102 and the data stored at R0
to R2 when X20 is turned ON, and stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode]

Step Instruction Device

334
 WXNR, WXNRP, DXNR, DXNRP

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D100 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XOR
R0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
D101 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 R1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
D102 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 1 R2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0

2
b15 b8b7 b0
D200 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
D201 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
D202 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 1
D0 3
3

4
7.1.7 WXNR, WXNRP 16-bit data exclusive NOR operations

7.1.7
DXNR, DXNRP 32-bit data exclusive NOR operations

WXNR, WXNRP, DXNR, DXNRP Basic High

performance Process Redundant Universal LCPU

When two data are set ( D S D , ( D +1, D ) ( S +1, S ) ( D +1, D ))

4
indicates an instruction symbol of WXNR/DXNR.

6
Command
WXNR, DXNR S D

Command
P S D
WXNRP, DXNRP
7
S : Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits)
Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
K, H
Other 8
S ––

D –– ––

7.1.7
7.1 Logical operation instructions
Function
WXNR

WXNR, WXNRP, DXNR, DXNRP

(1) Conducts an exclusive NOR operation on the 16-bit data of the device designated by D and the 16-bit data of the device
designated by S , and stores the results at the device designated by D .
b15 b8 b7 b0
D 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1
XNR
b15 b8 b7 b0
S 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 0

b15 b8 b7 b0
D 1 0 1 0 0 1 0 1 0 1 0 1 0 0 0 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

335
 WXNR, WXNRP, DXNR, DXNRP

DXNR
(1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by D and the 32-bit data of the device
designated by S , and stores the results at the device designated by D .
D +1 D
b31 b16 b15 b0
D 1 1 0 0 0 0 0 0 0 0 0 0 1 1

XNR
S +1 S
b31 b16 b15 b0
S 1 1 1 1 0 0 0 0 1 1 1 1 0 0

D +1 D
b31 b16 b15 b0
D 1 1 0 0 1 1 1 1 0 0 0 0 0 0

(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

Operation Error
(1) There is no operation error in the WXNR(P) or DXNR(P) instruction.

Program Example
(1) The following program compares the bit patterns of the 16-bit data located from X30 to X3F with the bit patterns of the
16-bit data at D99 when XC is ON, and stores the number of identical bit patterns at D7.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
X3F X3CX3B X38X37 X34X33 X30
X3F to X30 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XNR
b15 b8 b7 b0
D99 1 1 0 0 1 0 0 1 1 0 1 0 1 0 1 1

b15 b8 b7 b0
D99 0 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1

D7 5

(2) The following program compares the bit patterns of the 32-bit data located from X20 to X3F with the bit patterns of the
data at D16 and D17 when X6 is ON, and stores the number of identical bit patterns at D18.
[Ladder Mode] [List Mode]

Step Instruction Device

336
 WXNR, WXNRP, DXNR, DXNRP

[Operation]
S +1 S
X3F X3C X3B X38 X37 X34 X33 X30 X2F X2C X2B X28 X27 X24 X23 X20 1
X3F to X20 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XOR
D +1 D

b31 b16 b15 b0

D17,D16 1 1 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 1 1 0 1 1
2

3
D +1 D

b31 b16b15 b0
D17,D16 0 1 1 0 0 0 1 1 1 1 0 0 0 1 1 0 1 0 0 1 0 1 1 0 0 0 1 1 0 0 0 1

D18 15
4

Remark 4
See Page 369, Section 7.5.2 for more information on the SUMP/DSUMP instructions.

6
When three data are set ( S1 S2 D , ( S1 +1, S1 ) ( S2 +1, S2 ) ( D +1, D ))

indicates an instruction symbol of WXNR/DXNR.

Command
7
WXNR, DXNR S1 S2 D

8
Command
WXNRP, DXNRP P S1 S2 D

S1 , S2 : Data for an exclusive NOR operation or head number of the devices where the data is stored (BIN 16/32 bits)
D : Head number of the devices where the exclusive NOR operation result will be stored (BIN 16/32 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other

7.1.7
7.1 Logical operation instructions
Data Bit Word Bit Word K, H
S1 ––

WXNR, WXNRP, DXNR, DXNRP

S2 ––

D –– ––

Function
WXNR
(1) Conducts an exclusive NOR operation on the 16-bit data of the device designated by S1 and the 16-bit data of the device
designated by S2 , and stores the results at the device designated by D .
b15 b8 b7 b0
S1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
XNR
b15 b8 b7 b0
S2 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1

b15 b8 b7 b0
D 0 0 1 1 0 0 1 1 0 0 1 1 1 1 0 0
(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

337
 WXNR, WXNRP, DXNR, DXNRP

DXNR
(1) Conducts an exclusive NOR operation on the 32-bit data of the device designated by S1 and the 32-bit data of the device
designated by S2 , and stores the results at the device designated by D .

S1 + 1 S1
b31 b16 b15 b0
S1 0 0 1 1 0 0 1 1 1 1 0 0 1 1

XNR
S2 + 1 S2
b31 b16 b15 b0
S2 0 1 0 1 0 1 0 1 0 1 0 1 0 1

D +1 D
b31 b16 b15 b0
D 1 0 0 1 1 0 0 1 0 1 1 0 0 1
(2) For bit devices, the bit devices after the points designated by digit specification are regarded as "0" in the operation.

Operation Error
(1) There is no operation error in the WXNR(P) or DXNR(P) instruction.

Program Example
(1) The following program performs an exclusive NOR operation on the 16-bit data from X30 to X3F and the data at D99
when X0 is turned ON, and stores the results to D7.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
X3F X3CX3B X38X37 X34X33 X30
X3F to X30 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
XNR
b15 b8 b7 b0
D99 1 1 0 0 1 0 0 1 1 1 1 1 1 1 0 0

b15 b8 b7 b0
D7 0 1 1 0 0 0 1 1 0 1 0 1 0 1 1 0

(2) The following program performs an exclusive NOR operation on the 32-bit data at D20 and D21 and the data at D10 and
D11 when X10 is turned ON, and stores the result to D40 and D41.
[Ladder Mode] [List Mode]

Step Instruction Device

338
 BKXNR, BKXNRP

[Operation]
S +1 S
b31 b16 b15 b0 1
D21,D20 0 1 0 1 1 0 1 0 1 0 0 1 0 1
XNR

b31
S +1
b16 b15
S
b0
2
D11,D10 0 1 1 0 0 1 0 1 1 0 1 1 0 0

D +1 D
3
b31 b16 b15 b0
D41,D40 1 1 0 0 0 0 0 0 1 1 0 1 1 0
4
7.1.8 BKXNR, BKXNRP Block exclusive NOR operations

7.1.8 BKXNR, BKXNRP Basic High

performance Process Redundant Universal LCPU
4
Command
BKXNR BKXNR S1 S2 D n

Command 6
BKXNRP S1 S2 D n
BKXNRP
S1 *1 : Head number of the devices where data on which a logical operation will be conducted is stored (BIN 16 bits)
S2 *1 : Data for a logical operation or head number of the devices where the data for the logical operation is stored (BIN 16 bits) 7
*1 : Head number of the devices where the operation result will be stored (BIN 16 bits)
D

n : Number of operation data blocks (BIN 16 bits)

Internal Devices
Setting
Data Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
K, H
Other 8
S1
*1 –– –– –– ––
S2
*1 –– –– ––

D *1 –– –– –– ––

7.1.8
7.1 Logical operation instructions
n ––
*1: The same device number can be specified for S1 and D or S2 and D .

BKXNR, BKXNRP
Function
(1) Performs an exclusive NOR operation on the data located in the n points from the device designated by S1 , and the data
located in the n points from the device designated by S2 , and stores the results into the area starting from the device
designated by D .
b15 b8 b7 b0 b15 b8 b7 b0
S1 0000111111110000 S2 0000000011110000
S1 + 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 S2 + 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
S1 + 2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 S2 + 2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
n n
XNR

S1 + (n 2) 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 S2 +(n 2) 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0
S1 + (n 1) 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 S2 +(n 1) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

b15 b8b7 b0
D 1111000011111111
D +1 0000000011111111
D +2 1010101001010101
n

D +(n 2) 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
D +(n 1) 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1

339
 BKXNR, BKXNRP

(2) The constant designated by S2 can be between -32768 and 32767 (BIN 16-bit data).
b15 b8b7 b0
S1 0000111111111111
S1 + 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0
S1 + 2 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 1 b15 b8b7 b0
n XNR S2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0

S1 +(n 2) 1100110011001100
S1 +(n 1) 0000111111110000

b15 b8 b7 b0
D 0000000011110000
D +1 0000000011111111
D +2 1100001100111100
n

D +(n 2) 1100001111000011
D +(n 1) 0000000011111111

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
specified in S1 , S2 , or D .
The ranges of devices starting from the one specified in S1 and D

overlap by n points (except when the same device is specified in S1 and

4101
D ).
The ranges of devices starting from the one specified in S2 and D

overlap by n points (except when the same device is specified in S2 and

D ).

Program Example
(1) The following program performs an exclusive NOR operation on the data stored at D100 to D102 and the data stored at
R0 to R2 when X20 is turned ON, and stores the operation result into the area starting from D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

b15 b8 b7 b0 b15 b8 b7 b0
D100 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 R0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
XNR
D101 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 R1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
D102 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 R2 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0

b15 b8 b7 b0
D200 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1
D201 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 D0 3
D202 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0

340
 ROR, RORP, RCR, RCRP

7.2 Rotation instruction

1
7.2.1 ROR, RORP, RCR, RCRPRight rotation of 16-bit data

7.2.1 ROR, RORP, RCR, RCRP Basic High

performance Process Redundant Universal LCPU

2
indicates an instruction symbol of ROR/RCR.

Command
ROR, RCR D n
3
Command
P D n
RORP, RCRP
D : Head number of the devices to rotate (BIN 16 bits)
4
n : Number of rotations (0 to 15) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H 4
D –– ––
n ––

6
Function
ROR 7
(1) Rotates 16-bit data of the device designated by D , not including the carry flag, n-bits to the right.
The carry flag is ON or OFF depending on the status prior to the execution of the ROR instruction.
Carry flag 8
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

Right rotation (1 bit)

Carry flag

7.2.1
7.2 Rotation instruction
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

ROR, RORP, RCR, RCRP

Right rotation (1 bit)
Value of b0 Value of b0
Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Value of b0 Right rotation (n bits) Value of b0

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D

Value of b(n-1)
Value of b(n-1)

(2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification.
The number of bits by which a rotation is carried out is the remainder of n/(specified number of bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12 1 is "3", and the data is
rotated 3 bits.
(3) Specify any of 0 to 15 as n.
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
For example, when n 18, the contents are rotated two bits to the right since the remainder of 18 / 16 1 is "2".

341
 ROR, RORP, RCR, RCRP

RCR
(1) Rotates 16-bit data of the device designated by D , including the carry flag, n-bits to the right.
The carry flag is ON or OFF depending on the status prior to the execution of the ROR instruction.
Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0

Right rotation (1 bit)

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1

Right rotation (1 bit)

Value of carry flag Value of b0

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Value of carry flag Right rotation (n bits) Value of b0

Carry flag
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D

Value of b(n-1)

(2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12 1 is "3", and the data is
rotated 3 bits.
(3) Specify any of 0 to 15 as n.
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
For example, when n 18, the contents are rotated two bits to the right since the remainder of 18 / 16 1 is "2".

Operation Error
(1) There is no operation error in the ROR(P) or RCR(P) instruction.

Program Example
(1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the right when XC is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0
Carry flag
b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1

Contents of b2 to b0 Contents of b15 to b4

before execution before execution Content of b3 Content of b2
before execution before execution

342
 ROR, RORP, RCR, RCRP

(2) The following program rotates the contents of D0, including the carry flag, 3 bits to the right when XC is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

1

2
[Operation]
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700) 3
D0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 *
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 1 1 * 0 0 0 0 0 0 0 0 0 0 0 0 1
(SM700)
1
4
Contents of b1 and b0 Contents of b15 to b4
Content of b3 Content of b2
4
before execution before execution
Content of carry before execution before execution
flag SM700
* ON/OFF status of the carry flag depends on its status before the execution of ROR.

7.2.1
7.2 Rotation instruction
ROR, RORP, RCR, RCRP

343
 ROL, ROLP, RCL, RCLP

7.2.2 ROL, ROLP, RCL, RCLPLeft rotation of 16-bit data

7.2.2 ROL, ROLP, RCL, RCLP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of ROL/RCL.

Command
ROL, RCL D n

Command
P D n
ROLP, RCLP
D : Head number of the devices to rotate (BIN 16 bits)
n : Number of rotations (0 to 15) (BIN 32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
n ––

Function
ROL
(1) Rotates the 16-bit data of the device designated at D , not including the carry flag, n-bits to the left.
The carry flag turns ON or OFF depending on its status prior to the execution of ROL instruction.
Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D

Left rotation (1 bit)

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D

Value of b15 Left rotation (1 bit) Value of b15

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 D

Value of b15 Left rotation (n bits) Value of b15

Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D

Value of b(16-n)
Value of b(16-n)
(2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12 1 is "3", and the data is
rotated 3 bits.
(3) Specify any of 0 to 15 as n.
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
For example, when n 18, the data is rotated 2 bits to the left since the remainder of 18/16 1 is "2".

344
 ROL, ROLP, RCL, RCLP

RCL
(1) Rotates the 16-bit data of the device designated by , including the carry flag, n-bits to the left.
1
D

The carry flag turns ON or OFF depending on its status prior to the execution of RCL instruction.
Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D 2
Left rotation (1 bit)
Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 3
1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D

Value of b15 Left rotation (1 bit)

Value of carry flag 4
Carry flag
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D
4
Value of b15 Value of carry flag
Left rotation (n bits)

Carry flag 6
(SM700) b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D

7
Value of b(16-n)
(2) When a bit device is designated for , a rotation is performed within the device range specified by digit specification.
8
D

The number of bits by which a rotation is executed is the remainder of n/(specified number of bits).
For example, when n 15 and (specified number of bits) 12 bits, the remainder of 15/12 1 is "3", and the data is
rotated 3 bits.
(3) Specify any of 0 to 15 as n.

7.2.2
7.2 Rotation instruction
If the value specified as n is 16 or greater, the remainder of n / 16 is used for rotation.
For example, when n 18, the data is rotated 2 bits to the left since the remainder of 18/16 1 is "2".

ROL, ROLP, RCL, RCLP

Operation Error
(1) There is no operation error in the ROL(P) or RCL(P) instruction.

Program Example
(1) The following program rotates the contents of D0, not including the carry flag, 3 bits to the left when XC is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D0

Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 D0

Content of b13 Contents of b11 to b0 Contents of b15 to b13

before execution Content of b12 before execution before execution
before execution

345
 DROR, DRORP, DRCR, DRCRP

(2) The following program rotates the contents of D0, including the carry flag, 3 bits to the left when XC is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
* 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 D0

Carry flag
(SM700) b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 1 0 0 0 0 0 0 0 0 0 0 0 0 * 1 1 D0

Content of b12 Contents of b11 to b0 Contents of b15 and b14

Content of b13
before execution before execution before execution
before execution
Content of carry flag SM700

* ON/OFF status of the carry flag depends on its status before the execution of RCL.

7.2.3 DROR, DRORP, DRCR, Right rotation of 32-bit data

7.2.3
DRCRP

DROR, DRORP, DRCR, DRCRP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of DROR/DRCR.

Command
DROR, DRCR D n

Command
DRORP, DRCRP P D n

D : Head number of the devices to rotate (BIN 32 bits)

n : Number of rotations (0 to 31) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
n ––

Function
DROR
(1) The 32-bit data of the device designated at D , not including the carry flag, is rotated n-bits to the right.
The carry flag turns ON or OFF depending on its status prior to the execution of the DROR instruction.
D +1 D Carry flag
b31 b30 b29 b28 b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0 (SM700)

n-bit rotation
(2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of bits).
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24 1 is "7", and the data is
rotated 7 bits.
(3) Specify any of 0 to 31 as n.
If the value specified as n is 32 or greater, the remainder of n / 32 is used for rotation.
For example, when n 34, the contents are rotated two bits to the right since the remainder of 34 / 32 1 is "2".

346
 DROR, DRORP, DRCR, DRCRP

DRCR
(1) Rotates 32-bit data, including carry flag, at device designated by n bits to the right.
1
D

The carry flag goes ON or OFF depending on its status prior to the execution of the DRCR instruction.
D +1 D Carry flag
b31 b30 b29 b28 b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0 (SM700)
2
n-bit rotation
(2) When a bit device is designated for , a rotation is performed within the device range specified by digit specification.
D

The number of bits by which a rotation is executed is the remainder of n /(specified number of bits).
3
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24 1 is "7", and the data is
rotated 7 bits.
4
(3) Specify any of 0 to 31 as n. If the value specified as n is 32 or greater, the remainder of n / 32 is used for rotation. For
example, when n 34, the contents are rotated two bits to the right since the remainder of 34 / 32 1 is "2".
4
Operation Error
(1) There is no operation error in the DROR(P) or DRCR(P) instruction.
6
Program Example
(1) The following program rotates the contents of D0 and D1, not including the carry flag, 4 bits to the right when XC is ON.
7
[Ladder Mode] [List Mode]

Step Instruction Device 8

[Operation]

7.2.3
7.2 Rotation instruction
Carry flag
b31 b28 b27 b24 b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0 (SM700)
D0, D1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0

DROR, DRORP, DRCR, DRCRP

Carry flag
b31 b28 b27 b24b23 b20b19 b16 b15 b12 b11 b8 b7 b4 b3 b0 (SM700)
D0, D1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1

Contents of b3 to b0 Contents of b31 to b4

before execution Content of b3
before execution
before execution
(2) The following program rotates the contents of D0 and D1, including the carry flag, 4 bits to the right when XC is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Carry flag
b31 b28b27 b24b23 b20b19 b16b15 b12b11 b8b7 b4b3 b0 (SM700)
D0, D1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 *

Carry flag
b31 b28b27 b24b23 b20b19 b16b15 b12b11 b8b7 b4b3 b0 (SM700)
D0, D1 1 1 1 * 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1

Before execution
Contents of b2 to b0 Content of b3
before execution Content of carry flag before execution
SM700 before execution

* : ON/OFF status of the carry flag depends on its status before the execution of DRCR.

347
 DROL, DROLP, DRCL, DRCLP

7.2.4 DROL, DROLP, DRCL, Left rotation of 32-bit data

7.2.4
DRCLP

DROL, DROLP, DRCL, DRCLP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of DROL/DRCL.

Command
DROL, DRCL D n

Command
P D n
DROLP, DRCLP
D : Head number of the devices to rotate (BIN 32 bits)
n : Number of rotations (0 to 31) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
n ––

Function
DROL
(1) The 32-bit data of the device designated at D , not including the carry flag, is rotated n-bits to the left. The carry flag turns
ON or OFF depending on its status prior to the execution of the DROL instruction.
D +1 D
Carry flag
(SM700) b31 b30 b29 b28 b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0

n-bit rotation
(2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of bits).
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24 1 is "7", and the data is
rotated 7 bits.
(3) Specify any of 0 to 31 as n. If the value specified as n is 32 or greater, the remainder of n/32 is used for rotation. For
example, when n 34, the data is rotated 2 bits to the left since the remainder of 34/32 1 is "2".

DRCL
(1) Rotates 32-bit data of the device designated by D , including the carry flag, n-bits to the left. The carry flag turns ON or
OFF depending on its status prior to the execution of the DRCL instruction.
D +1 D
Carry flag
(SM700) b31 b30 b29 b28b27 b18 b17 b16 b15b14 b5 b4 b3 b2 b1 b0

n-bit rotation
(2) When a bit device is designated for D , a rotation is performed within the device range specified by digit specification.
The number of bits by which a rotation is executed is the remainder of n/(specified number of bits).
For example, when n 31 and (specified number of bits) 24 bits, the remainder of 31/24 1 is "7", and the data is
rotated 7 bits.
(3) Specify any of 0 to 31 as n. If the value specified as n is 32 or greater, the remainder of n/32 is used for rotation. For
example, when n 34, the data is rotated 2 bits to the left since the remainder of 34/32 1 is "2".

348
 DROL, DROLP, DRCL, DRCLP

Operation Error
1
(1) There is no operation error in the DROL(P) or DRCL(P) instruction.

Program Example 2
(1) The following program rotates the contents of D0 and D1, not including the carry flag, 4 bits to the left when XC is ON.
[Ladder Mode] [List Mode]
3
Step Instruction Device

4
[Operation]
Carry flag 4
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D0, D1

Carry flag 6
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D0, D1

Content of b28
Contents of b27 to b0
before execution
Contents of b31 to b28
before execution
7
before execution
(2) The following program rotates the contents of D0 and D1, including the carry flag, 4 bits to the left when XC is ON.
[Ladder Mode] [List Mode] 8
Step Instruction Device

7.2.4
7.2 Rotation instruction
[Operation]

DROL, DROLP, DRCL, DRCLP

Carry flag
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
* 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 D0, D1

Carry flag
(SM700) b31 b28b27 b24b23 b20 b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 * 1 1 1 D0, D1

Contents of b27 to b0 Contents of b31 to b29

Content of b28 before execution
before execution
before execution Content of carry flag
SM700 before execution
* : ON/OFF status of the carry flag depends on its status before the execution of DRCL.

349
 SFR, SFRP, SFL, SFLP

7.3 Shift instruction

7.3.1 SFR, SFRP n-bit shift to right of 16-bit data

7.3.1
SFL, SFLP n-bit shift to left of 16-bit data

SFR, SFRP, SFL, SFLP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of SFR/SFL.

Command
SFR, SFL D n

Command
P D n
SFRP, SFLP
D : Head number of the devices where shift data is stored (BIN 16 bits)
n : Number of shifts (0 to 15) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
n ––

Function
SFR
(1) Causes a shift to the right by n bits of the 16-bit data from the device designated at D .
The n bits from the upper bit are filled with 0s.
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 0

When n=6:
Carry flag
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 1

Filled with 0s.

(2) When a bit device is designated for D , a right shift is executed within the device range specified by digit specification.
Y1B Y18 Y17 Y14 Y13 Y10
1 0 1 0 1 0 1 0 1 0 1 0

When n = 4:
Carry flag
Y1B Y18 Y17 Y14 Y13 Y10 (SM700)
0 0 0 0 1 0 1 0 1 0 1 0 1

Filled with 0s.

The number of bits by which a shift is executed is the remainder of n/(specified number of bits).
For example, when n 15 and (specified number of bits) 8 bits, the remainder of 15/8 1 is "7", and the data is
shifted 7 bits.
(3) Specify any of 0 to 15 as n. If the value specified as n is 16 or greater, the remainder of n/16 is used for a shift to the
right.
For example, when n 18, the data is shifted 2 bits to the right since the remainder of 18/16 1 is 2.

350
 SFR, SFRP, SFL, SFLP

SFL
(1) Shifts 16-bit data at device designated by n bits to the left.
1
D

Bits starting from the lowest bit to n bit are filled with 0s.
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
1 1 1 1 0 0 1 1 0 0 0 0 1 1 1 1 D
2
When n=8:
Carry flag
(SM700)
1
b15 b14 b13 b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 D 3
Filled with 0s.
(2) When a bit device is designated for D , a left shift is executed within the device range specified by digit specification.
4
X17 X14 X13 X10
0 0 1 1 0 0 1 1

Carry flag
4
(SM700) X17 X14 X13 X12 X10
1 1 0 0 1 1 0 0 0

Filled with 0s. 6

The number of bits by which a shift is executed is the remainder of n/(specified number of bits). For example, when n
15 and (specified number of bits) 8 bits, the remainder of 15/8 1 is "7", and the data is shifted 7 bits.
(3) Specify any of 0 to 15 as n. If the value specified as n is 16 or greater, the remainder of n/16 is used for a shift to the left.
7
For example, when n 18, the data is shifted 2 bits to the left since the remainder of 18/16 1 is "2".

8
Operation Error
(1) There is no operation error in the SFR(P) or SFL(P) instruction.

7.3.1
7.3 Shift instruction
Program Example
(1) The following program shifts the data of D0 to the right by the number of bits designated by D100 when X20 is turned

SFR, SFRP, SFL, SFLP

ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0

D100 3
Carry flag
b15 b14 b13b12 b11b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 (SM700)
D0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0

Filled with 0s.

(2) The following program shifts the contents of X10 to X17 3 bits to the left when X1C is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

351
 BSFR, BSFRP, BSFL, BSFLP
[Operation]
X17 X14 X13 X10
0 0 1 1 0 0 1 1

Carry flag
(SM700) X17 X14 X13 X12 X10
1 1 0 0 1 1 0 0 0

Filled with 0s.

7.3.2 BSFR, BSFRP 1-bit shift to right of n-bit data

7.3.2
BSFL, BSFLP 1-bit shift to left of n-bit data

BSFR, BSFRP, BSFL, BSFLP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of BSFR/BSFL.

Command
BSFR, BSFL D n

Command
P D n
BSFRP, BSFLP
D : Head number of the devices to be shifted (bits)
n : Number of devices to which shift is executed (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
n ––

Function
BSFR
(1) Shifts the data in n points from the device designated by D to the right by one bit.
n
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
1 1 0 1 1 0

Carry flag
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D (SM700)
0 1 1 0 1 1 0

Filled with 0

(2) The device designated by D + (n-1) is filled with 0.

BSFL
(1) Shifts the data in n points from the device designated by D to the left by one bit.
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
1 1 0 0 1 1

Carry flag
(SM700) D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
1 1 0 0 1 1 0

Filled with 0

(2) The device designated by D is filled with 0.

352
 BSFR, BSFRP, BSFL, BSFLP

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
The points specified in n exceed those of the corresponding device
4101
specified in D .
3
Program Example
(1) The following program shifts the data at M668 to M676 to the right when X8F is turned ON. 4
[Ladder Mode] [List Mode]

Step Instruction Device

4

6
[Operation]
Designation range for the
BSFRP instruction
M678M677M676M675M674M673M672M671M670M669M668M667
7
1 1 1 0 1 0 1 1 0 0 1 1

Carry flag 8
M678M677M676M675M674M673M672M671M670M669M668M667 (SM700)
1 1 0 1 0 1 0 1 1 0 0 1 1

Filled with 0s.

(2) The following program shifts the data at Y60 to Y6F to the left when X4 is turned ON.

7.3.2
7.3 Shift instruction
[Ladder Mode] [List Mode]

Step Instruction Device

BSFR, BSFRP, BSFL, BSFLP

[Operation]
Y6FY6EY6DY6CY6BY6AY69Y68Y67Y66Y65Y64Y63Y62Y61Y60
1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1

Carry flag
(SM700) Y6FY6EY6DY6CY6BY6AY69Y68Y67Y66Y65Y64Y63Y62Y61Y60
1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 1 0

Filled with 0

353
 SFTBR, SFTBRP, SFTBL, SFTBLP

7.3.3 SFTBR, SFTBRP n-bit shift to right of n-bit data

SFTBL, SFTBLP n-bit shift to left of n-bit data

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.3.3 SFTBR, SFTBRP, SFTBL, SFTBLP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

indicates an instruction symbol of SFTBR/SFTBL.

Command
SFTBR, SFTBL D n1 n2

Command
SFTBRP, SFTBLP P D n1 n2

D : Head number of the devices to be shifted (bits)

n1 : Number of bits to be shifted (BIN 16 bits)
n2 : Number of shifts (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D *1 –– –– ––
n1 –– ––
n2 –– ––
*1 : T, C, ST, and S devices are not available.

Function
SFTBR(P)
(1) This instruction shifts the n1 bits data in the devices starting from the device specified by D to the right by n2 bits.
n1=10, n2=4
n1
n2

D +9 D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D
0 1 1 1 1 0 0

Carry flag
D +9 D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D (SM700)
0 0 0 0 1 1 1 0 1 1

Filled with 0s

(2) n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is equal to or larger than the value
of n1, the remainder of n2 / n1 (n2 devided by n1) is used for a shift.
(3) This instruction specifies n1 ranged from 1 to 64.
(4) Bits starting from the highest bit to n2th bit are filled with 0s. If the value of n2 is larger than the value of n1, the remainder
of n2 / n1 will be 0.
(5) If the value specified by n1 or n2 is 0, the instruction will be not processed.

354
 SFTBR, SFTBRP, SFTBL, SFTBLP

SFTBL(P)
(1) This instruction shifts the n1 bits data in the devices starting from the device specified by to the left by n2 bits.
1
D

n1=10, n2=4
n1
n2

D +9 D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D 2
0 1 1 0 1 1 1 1 0 1

Carry flag
(SM700)
1
D +9 D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D
3
1 1 1 1 0 1 0 0 0 0

Filled with 0s

(2) n1 and n2 are specified under the condition that n1 is larger than n2. If the value of n2 is equal to or larger than the value
4
of n1, the remainder of n2 / n1 (n2 devided by n1) is used for a shift.
However, if the remainder of n2 / n1 is 0, the instruction will be not processed.
(3) This instruction specifies n1 ranged from 1 to 64.
4
(4) Bits starting from the lowest bit to n2th bit are filled with 0s. If the value of n2 is larger than the value of n1, the remainder
of n2 / n1 will be 0.
6
(5) If the value specified by n1 or n2 is 0, the instruction will be not processed.

Operation Error 7
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
8
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified in n1 is other than 0 to 64.
4100
The value in n2 is negative.

7.3.3
7.3 Shift instruction
4101 The points specified in n1 exceed those of the device specified in D .

SFTBR, SFTBRP, SFTBL, SFTBLP

355
 SFTBR, SFTBRP, SFTBL, SFTBLP

Program Example
(1) The following program shifts the data of Y10 to Y17 (8 bits) specified by D to the right by 2 bits (n2), when M0 is turned
on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10
1 0 1 1 1 0 0 1

Carry flag
Y17 Y16 Y15 Y14 Y13 Y12 Y11 Y10 (SM700)
0 0 1 0 1 1 1 0 0

(2) The following program shifts the data of Y21 to Y2C (12 bits) specified by D to the left by 5 bits (n2), when M0 is turned
on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Y2C Y2B Y2A Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21
1 0 1 1 0 1 0 1 1 0 0 1

Carry flag
(SM700)
0 Y2C Y2B Y2A Y29 Y28 Y27 Y26 Y25 Y24 Y23 Y22 Y21
1 0 1 1 0 0 1 0 0 0 0 0

356
 DSFR, DSFRP, DSFL, DSFLP

7.3.4 DSFR, DSFRP 1-word shift to right of n-word data

7.3.4
DSFL, DSFLP 1-word shift to left of n-word data

DSFR, DSFRP, DSFL, DSFLP High

1
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of DSFR/DSFL.

DSFR, DSFL
Command
D n
2
Command

3
D n
DSFRP, DSFLP P

D : Head number of the devices to be shifted (BIN 16 bits)

n : Number of devices to which shift is executed (BIN 16 bits)
Setting
Data
Internal Devices
R, ZR
J \
U \G Zn
Constants
K, H
Other 4
Bit Word Bit Word
D –– –– ––
n ––
4
Function
6
DSFR
(1) Shifts data n points from device designated by D 1-word to the right.
n 7
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
555 212 325 100 50 40

8
D +(n-1) D +(n-2) D +(n-3) D +(n-4) D +1 D
0 555 212 325 100 50

Filled with 0.
(2) The device designated by D + (n-1) is filled with 0.

7.3.4
7.3 Shift instruction
DSFL

DSFR, DSFRP, DSFL, DSFLP

(1) Shifts data n points from device designated by D 1-word to the left.
n
D +(n-1) D +(n-2) D +(n-3) D +2 D +1 D
555 120 325 100 50 40

D +(n-1) D +(n-2) D +3 D +2 D +1 D
120 325 100 50 40 0

Filled with 0.

(2) The device designated by D is filled with 0.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in D .

357
 DSFR, DSFRP, DSFL, DSFLP

Program Example
(1) The following program shifts the contents of D683 to D689 to the right when XB is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Designation range for the DSFRP instruction
D689 D688 D687 D686 D685 D684 D683
-100 503 600 -336 3802 -32765 5003

D689 D688 D687 D686 D685 D684 D683

0 -100 503 600 -336 3802 -32765

Filled with 0.
(2) The following program shifts the contents of D683 to D689 to the left when XB is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Designation range for the DSFLP instruction
D689 D688 D687 D686 D685 D684 D683
-100 503 600 -336 3802 -32765 5003

D689 D688 D687 D686 D685 D684 D683

503 600 -336 3802 -32765 5003 0

Filled with 0.

358
 SFTWR, SFTWRP, SFTWL, SFTWLP

7.3.5 SFTWR, SFTWRP n-word shift to right of n-word data

SFTWL, SFTWLP n-word shift to left of n-word data

Ver.
Basic High
performance Process Redundant Universal LCPU 1
• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.3.5 SFTWR, SFTWRP, SFTWL, SFTWLP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported
2
indicates an instruction symbol of SFTWR/SFTWL.
Command
SFTWR, SFTWL D n1 n2 3
Command
SFTWRP, SFTWLP P D n1 n2
4
D : Head number of the devices to be shifted (BIN 16 bits)
n1 : Number of words to be shifted (BIN 16 bits)
n2 : Number of shifts (BIN 16 bits)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other
4
Data Bit Word Bit Word K, H
D –– –– ––
n1 –– –– 6
n2 –– ––

Function 7
SFTWR(P)
(1) This instruction shifts n1 words data in the devices starting from the device specified by D to the right by n2 words. 8
n1=9, n2=4
n1
n2

D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D

7.3.5
7.3 Shift instruction
30FH 1EH 100H 0H 1FFH 10 H 1FH 7FFH 2A H

SFTWR, SFTWRP, SFTWL, SFTWLP

D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D
0H 0H 0H 0H 30FH 1EH 100H 0H 1FFH

Filled with 0H
(2) The n2 words data in the devices starting from the highest device are filled with 0s.
(3) If the value specified by n1 or n2 is 0, the instruction will be not processed.
(4) If the value of n2 is equal to or larger than the value of n1, the n1 words data in the devices starting from the device
specified by D will be filled with 0s.

359
 SFTWR, SFTWRP, SFTWL, SFTWLP

SFTWL(P)
(1) This instruction shifts the n1 words data in the devices starting from the device specified by D to the left by n2 words.
n1=9, n2=4
n1
n2

D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D
1FFH 10H 0H 7FFH 3AH 1F H 30 H 0H FFH

D +8 D +7 D +6 D +5 D +4 D +3 D +2 D +1 D
3AH 1F H 30 H 0H FFH 0H 0H 0H 0H

Filled with 0H
(2) The n2 words in the devices starting from the lowest device are filled with 0s.
(3) If the value specified by n1 or n2 is 0, the instruction will be not processed.

(4) If the value of n2 is equal to or greater than the value of n1, the n1 words devices starting from the device specified by D

will be filled with 0s.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value in n1 or n2 is negative. –– –– –– ––
4101 The points specified in n1 exceed those of the device specified in D . –– –– –– ––

360
 SFTWR, SFTWRP, SFTWL, SFTWLP

Program Example
1
(1) The following program shifts the 8 words (n1) data stored in the devices starting from D10 specified by D to the right by
2 words (n2), when M0 is turned on.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation]
D17 D16 D15 D14 D13 D12 D11 D10
4
1FFH 0H 2AH 7FFH 10H 4EH 5FH FFH

4
D17 D16 D15 D14 D13 D12 D11 D10
Filled with 0H 0H 0H 1FFH 0H 2AH 7FFH 10H 4EH
6
(2) The following program shifts the 12 words (n1) data in the devices starting from D21 specified by D to the left by 5 words
(n2), when M0 is turned on. 7
[Ladder Mode] [List Mode]

Instruction Device
8
Step

[Operation]

7.3.5
7.3 Shift instruction
D2C D2B D2A D29 D28 D27 D26 D25 D24 D23 D22 D21
FFH EH 5H 0H 2AH FFH 3AH 1H 0H 0H 10 H 7FFH

SFTWR, SFTWRP, SFTWL, SFTWLP

D2C D2B D2A D29 D28 D27 D26 D25 D24 D23 D22 D21
FFH 3AH 1H 0H 0H 10 H 7FFH 0H 0H 0H 0H 0H Filled with 0H

361
 BSET, BSETP, BRST, BRSTP

7.4 Bit processing instructions

7.4.1 BSET, BSETP Bit set for word devices

7.4.1
BRST, BRSTP Bit reset for word devices

BSET, BSETP, BRST, BRSTP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of BSET/BRST.

Command
BSET, BRST D n

Command
P D n
BSETP, BRSTP
D : Number of the device whose bits are set/reset (BIN 16 bits)
n : Number of the bit to be set/reset (0 to 15) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
n ––

Function
BSET
(1) Sets (sets "1" at) the nth bit in the word device designated at D .
(2) If n exceeds "15", bit set/reset is performed with the lower 4 bits of the data.

BSETP D10 K6

b15 b6 b1b0
Before execution D10 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1

b15 b6 b1b0
After execution D10 1 1 0 0 1 0 1 1 0 1 1 1 1 0 1 1

1 is set

BRST
(1) Resets the nth bit of a word device designated by D to 0.
(2) If n exceeds "15", bit set/reset is performed with the lower 4 bits of the data.

BRSTP D10 K11

b15 b11 b1b0

Before execution D10 1 1 0 0 1 0 1 1 0 0 1 1 1 0 1 1

b15 b11 b1b0

After execution D10 1 1 0 0 0 0 1 1 0 0 1 1 1 0 1 1

0 is set.

Operation Error
(1) There is no operation error in the BSET(P) or BRST(P) instruction.

362
 TEST, TESTP, DTEST, DTESTP

Program Example
1
(1) The following program resets the 8th bit of D8 (b8) to 0 when XB is OFF, and sets the 3rd bit of D8 (b3) to 1 when XB is
ON.
[Ladder Mode] 2
Resets b8 of D8.

Sets b3 of D8. 3

[List Mode] 4
Step Instruction Device

4
[Operation]
b15 b8 b3 b0 6
Before execution D8 0 0 1 1 0 1 0 1 1 1 1 1 0 0 0 1
When XB turns OFF. When XB turns ON.

b15 b8 b3 b0 7
After execution D8 0 0 1 1 0 1 0 0 1 1 1 1 1 0 0 1

Remark 8
Bit set or reset of word devices can also be conducted by bit designation of word devices.
• For the bit specification for word devices, link direct devices, refer to the QnUCPU User's Manual (Function Explanation,
Program Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).
The processing of program example (1) would be conducted as shown below if bit designation of a word device had been
used:

7.4.2
7.4 Bit processing instructions
XB
RST D8.8 Resets b8 of D8.

TEST, TESTP, DTEST, DTESTP

Designation of b8 of D8
XB
SET D8.3 Sets b3 of D8.
Designation of b3 of D8

7.4.2 TEST, TESTP, DTEST, Bit tests

7.4.2
DTESTP

TEST, TESTP, DTEST, DTESTP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of TEST/DTEST.

Command
TEST, DTEST S1 S2 D

Command
TESTP, DTESTP P S1 S2 D

S1 : Number of the device where bit data to be extracted is stored (BIN 16 bits)
S2 : Location of the bit data to be extracted (0 to 15 (TEST)/0 to 31 (DTEST)) (BIN 16/32 bits)
D : Number of the bit device where the extracted data will be stored (bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– ––
S2 ––

D –– –– ––

363
 TEST, TESTP, DTEST, DTESTP

Function
TEST
(1) Fetches bit data at the location designated by S2 within the word device designated by S1 , and writes it to the bit device
designated by D .
(2) The bit device designated by D is OFF when the relevant bit is "0" and ON when it is "1".
(3) The position designated by S2 indicates the position of an individual bit in a 1-word data block (0 to 15). When 16 or
more is designated at S2 , the target is the bit data at the position indicated by the remainder of n / 16. For example, when
n 18, the target is the data at b2 since the remainder of 18 / 16 1 is "2".
S2 bit (When S2 =5)

b15 b5 b0
S1 D

DTEST
(1) Fetches bit data at the location designated by S2 within the 2-word device designated by S1 , or S1 +1, and writes it to the
bit device designated by D .
(2) The bit device designated by D is OFF when the relevant bit is "0" and ON when it is "1".
(3) The position designated by S2 indicates the position of an individual bit in a 2-word data block (0 to 31). When 32 or
more is designated at S2 , the target is the bit data at the position indicated by the remainder of n / 32. For example, when
n 34, the target is the data at b2 since the remainder of 34 / 32 1 is "2".
S2 bit (When S2 =21)

b31 b21 b16 b15 b0

D
S1 +1 S1

Operation Error
(1) There is no operation error in the TEST(P) or DTEST(P) instruction.

Program Example
(1) The following program turns M0 ON or OFF based on the status of the 10th bit in the 1-word data block (D0).
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b10 b0
D0 1 0 1 1 0 0 1 1 0 1 1 0 1 0 1 0

Turns M0 OFF since b10 is "0."

b15 b10 b0
D0 0 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1

Turns M0 ON since b10 is "1."

364
 BKRST, BKRSTP

(2) The following program turns Y40 ON or OFF, depending on the status of the 19th bit of the 2-word data (W0 and W1).
[Ladder Mode] [List Mode]

Step Instruction Device

1

2
[Operation]
b31 b19 b16 b15 b0
10 1 10 0 10 10 1 100 00 10 1 10 1 1 10 1 1 10 110
3
Turns Y40 OFF since b19 is "0."
b31 b19 b16 b15 b0
0 110 110 1110 1 10 0 110 10 110 000 10 1 10 1 4
Turns Y40 ON since b19 is "1."

Remark 4
Programs using the bit test instruction can be rewritten as programs using bit designation of word devices.
If the program in example (1) were changed to use bit designation of a word device, it would appear as follows:
D0.A
M0 turns ON/OFF depending on the ON/OFF
6
M0
status of b10 of D0 (D0.A).
Designation of b10 of D0
7
7.4.3 BKRST, BKRSTP Batch reset of bit devices

7.4.3 BKRST, BKRSTP Basic High

performance Process Redundant Universal LCPU 8
Command
BKRST BKRST D n

Command

7.4.3
7.4 Bit processing instructions
BKRSTP D n
BKRSTP
D : Head number of the devices to be reset (bits)

BKRST, BKRSTP
n : Number of the devices to be reset (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
n ––

Function
(1) Resets bit device n-points from the bit device designated by D .
Device Status
• Turns device n-points from annunciator (F) number designated by D OFF.
Annunciator (F) • Deletes annunciator number turned OFF from SD64 to SD79 and compresses remaining data forward.
• Stores number of annunciators stored from SD64 to SD79 at SD63.
Timer (T) • Sets the current value n-points from timer (T) or counter c designated by (C) to 0, and turns coil contact
Counter (C) OFF.
Bit devices other than the
• Turns OFF coil or contact n-points from the device designated by D .
above

(2) If the designated device is OFF, the device status will not change.

365
 BKRST, BKRSTP

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in D .

Program Example
(1) The following program turns OFF devices from M0 to M7 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
M9M8M7 M4 M3 M0 M9 M8M7 M4M3 M0
1 1100 11100 1100000000

Not changed
(2) The following program sets data from 2nd bit (b2) of D10 to 1st bit (b1) of D11 to 0 when X20 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b2 b1 b0 b15 b8b7 b2 b1b0
D10 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

b15 b8 b7 b1 b0 b15 b8b7 b1 b0

D11 0 0 0 1 0 1 0 0 1 1 1 1 1 1 1 1 D11 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0

366
 SER, SERP, DSER, DSERP

7.5 Data processing instructions

1
7.5.1 SER, SERP 16-bit data search

7.5.1
DSER, DSERP 32-bit data search

SER, SERP, DSER, DSERP Basic High

Process Redundant Universal LCPU
performance
2
Command
SER, DSER S1 S2 D n

Command
3
SERP, DSERP P S1 S2 D n

S1

S2
: Search data or head number of the devices where the search data is stored (BIN 16/32 bits)
: Data to be searched or head number of the devices where the data to be searched is stored (BIN 16 bits)
4
D : Head number of the devices where the search result will be stored (BIN 16 bits)
n : Number of searches (BIN 16 bits)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other 4
Data Bit Word Bit Word K, H
S1 ––
S2 –– –– –– –– ––
6
D –– –– –– ––
n ––

7
Function
SER 8
(1) Searches n points from the 16-bit data of the device designated by S2 , regarding 16-bit data of the device designated by
S1 as a keyword. Then, the number of matches with the keyword is stored at the device designated by D +1, and the first
matched device number (in the relative number from S2 ) is stored at the device designated by D .

7.5.1
7.5 Data processing instructions
Head number to be
Search data searched
S1 123 123
S2 10

SER, SERP, DSER, DSERP

S2 +1 500 Match data Search results
S2 +2 123 Search range D 3 Position of match
Relative value (n points) D +1 2 Number of matches
-123
S2 +(n-2) 20
S2 +(n-1) 123
123

(2) No processing is conducted if n is 0 or a negative value.

(3) If no matches are found in the search, the devices designated at D and D +1 become "0".

367
 SER, SERP, DSER, DSERP

DSER
(1) Searches n points from the device designated by S2 in 32-bit units (2 n points in 16-bit units) regarding 32-bit data of
the device designated by S1 +1 and S1 as a keyword. Then, the number of matches with the keyword is stored at the
device designated by D +1, and the first matched device number (in the relative number from S2 ) is stored at the device
designated by D .
Head number to be
Search data searched
S1 +1. S1 5678901 5678901
S2 +1, S2 5678901 Match data
S2 +3, S2 +2 123456 Search results
S2 +5, S2 -1 Search range D 1 Position of match
(2 n points) D +1 2 Number of matches
Relative value
S2 +(n-3), S2 +(n-4) 5678901
S2 +(n-1), S2 +(n-2) 0
5678901

(2) No processing is conducted if n is 0 or a negative value.

(3) If no matches are found in the search, the devices designated at D and D +1 become "0".

If the data to be searched using the SER/DSER instruction is sorted in the ascending order, searches can be accelerated
by the use of the binary search method, which is activated by turning SM702 *1 ON. However, correct search results are
not obtained if SM702 is turned ON when the data to be searched is not sorted in the ascending order.

*1: SM702 is the special relay for setting the search method.
• SM702 OFF: Sequential search method (linear search method) (Comparison with the search data starts from the beginning
of the data to be searched.)
• SM702 ON: Binary search method (Obtains the center value of the sorted array and decides if the obtained value is larger
or smaller than the search value, then, chooses the area for search between the larger and smaller value divisions. By
repeating this process, the area for search is narrowed down.)
Search order

Search data Data to be searched Data to be searched Data to be searched

500 100 100 100
200 200 200
300 300 300
Search range Compared with the
400 400 400
search data
500 500 Search range 500 Compared with the
600 Search range 600 Compared with the 600 search data
700 700 search data 700

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The range of n exceeds that of the device specified in S2

4101 The device range specified in D exceeds the range of the

–– –– –– ––
corresponding device.

368
 SUM, SUMP, DSUM, DSUMP

Program Example
1
(1) The following program searches D100 to D105 for the contents of D0 when X20 is ON, and stores the search results at
W0 and W1.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
[Operation]
Search data Data to be searched
4
D0 123 D100 500
D101 123 Search results
D102 300 W0 2 Position of match 4
D103 123 W1 2 Number of matches
D104 32000
D105 122

(2) The following program searches D100 to D111 for the contents of D11 and D10 when X20 is ON, and stores the search
6
results at W0 and W1.
[Ladder Mode] [List Mode]
7
Step Instruction Device

[Operation]
Search data Data to be searched

7.5.2
7.5 Data processing instructions
D11, D10 56789051 D101, D100 200000
D103, D102 56789051 Search results
D105, D104 56789051 W0 2 Position of match

SUM, SUMP, DSUM, DSUMP

D107, D106 -30000 W1 3 Number of matches
D109, D108 56789051
D111, D110 30000

7.5.2 SUM, SUMP 16-bit data check

7.5.2
DSUM, DSUMP 32-bit data check

SUM, SUMP, DSUM, DSUMP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of SUM/DSUM.

Command
SUM, DSUM S D

Command
SUMP, DSUMP P S D

S : Head number of the devices where the total number of bits of "1" is counted (BIN 16/32 bits)
D : Head number of the devices where the total number of the bits will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––
D –– ––

369
 SUM, SUMP, DSUM, DSUMP

Function
SUM
From the 16-bit data in the device designated by S , stores the total number of bits where 1 is set, in the device
designated by D .
b15 b8 b7 b0
S 1 10 0 10 1 100 1 100 0 1

Total number of bits where 1 is set

b15 b8 b7 b0
D 0 00 00 00 000 00 10 00

Stores the total number of bits where 1 is set in BIN.

(There are 8 bits where 1 is set in the example.)

DSUM
From the 32-bit data in the device designated by S , stores the total number of bits where 1 is set, in the device
designated by D .
S +1 S

b31 b16b15 b0
100 1110 0 10 10 0 1 110 00 100 0 0 111 10 1 10

Total number of bits where 1 is set

b15 b8 b7 b0
D 00000000000 10000

Stores the total number of bits where 1 is set in BIN.

(There are 16 bits where 1 is set in the example.)

Operation Error
(1) There is no operation error in the SUM(P) or DSUM(P) instruction.

Program Example
(1) The following program stores the number of bits which are ON from X8 to X17 into D0 when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X17 X8
0 0 10 10 1 100 00 0 1 11

Stores the total number of bits

where 1 is set at D0.

D0 7

(2) The following program stores the number of bits which are ON in D100 and D101 into D0 when X10 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

370
 DECO, DECOP

[Operation]
b31 b16 b15 b0
D100, D101 0 1 0 1 0 0 0 0 1 1 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1
Stores the total number of bits where 1 is set into D0.

D0 15 2
7.5.3 DECO, DECOP Decoding from 8 to 256 bits

7.5.3 DECO, DECOP Basic High

performance Process Redundant Universal LCPU 3
Command

DECO DECO S D n
4
Command
DECOP S D n
DECOP
S : Data to be decoded or the number of the device where the data to be decoded is stored (BIN 16 bits) 4
D : Head number of the devices where the decoding result will be stored (Device name)
n : Valid bit length (1 to 8), 0: No processing (BIN 16 bits)
Setting
Data
Internal Devices
Bit Word
R, ZR
Bit
J \
Word
U \G Zn
Constants
K, H
Other 6
S ––

D –– –– ––
7
n ––

Function 8
(1) Turns ON the bit position of D , which corresponds to the binary value designated by the lower n bits at S .
n=3

S 1 1 0 (Binary value = 6)

7.5.3
7.5 Data processing instructions
7 6 5 4 3 2 1 0
D 0 1 0 0 0 0 0 0

DECO, DECOP
ON
(2) The value of n can be designated between 1 and 8.
(3) No processing is conducted if n 0, and there are no changes in the details of the device designated at D .
(4) Bit devices are treated as 1 bit, and word devices as 16 bits.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value of n is other than 0 to 8.
The range 2n bits from D exceeds the range of the corresponding
4101
device.

371
 ENCO, ENCOP

Program Example
(1) The following program decodes the 3 bits from X0 and stores the results at M10 when X20 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
X2 X1 X0
0 1 1 0 When 6 is designated at X0 to X2

M17 M10
0 0 0 0 0 1 0 0 0 0 0 0 Decoding result

If 3 bits are designated as significant bits, 8 points are occupied.

7.5.4 ENCO, ENCOP Encoding from 256 to 8 bits

7.5.4 ENCO, ENCOP Basic High

performance Process Redundant Universal LCPU

Command
ENCO S D n
ENCO
Command
ENCOP S D n
ENCOP
S : Head number of the device where the data to be encoded is stored (Device name)
D : Number of the device where the encoding result will be stored (BIN 16 bits)
n : Valid bit length (1 to 8), 0: No processing (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– ––
n ––

Function
(1) Stores the binary value corresponding to the bits which are "1" included in the 2n-bit data of S to D .
8 7 6 5 4 3 2 1 0
S 0 0 1 0 0 0 0 0 0

D 1 1 0 (Binary value = 6)

(2) The value of n can be designated at between 1 and 8.

(3) If n 0, there will be no operation, and the contents of D will not change.
(4) Bit devices are treated as 1 bit, and word devices as 16 bits.
(5) If more than 1 bit is at 1, processing will be conducted at the upper bit location.

372
 SEG, SEGP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The vaue of n is other than 0 to 8.
4100
All data 2n bits from S is "0". 3
n
The range 2 bits from S exceeds the range of the corresponding
4101
device.
4
Program Example
(1) The following program encodes the 3 bits from M10 when X20 is ON, and stores the results at D8. 4
[Ladder Mode] [List Mode]

Step Instruction Device

6

[Operation]
7
M17 M10
0 0 0 0 0 0 0 0 1 0 0 0
8
If 3 bits are designated as significant bits, 8 points are occupied.

Storage device D8
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Encoding result

The location of the ON bit, counted from M10, is stored in BIN.

7.5.5
7.5 Data processing instructions
7.5.5 SEG, SEGP 7-segment decode

7.5.5

SEG, SEGP
SEG, SEGP Basic High
performance Process Redundant Universal LCPU

Command
SEG S D
SEG
Command
SEGP SEGP S D

S : Data to be decoded or head number of the devices where the data to be decoded is stored (BIN 16 bits)
D : Head number of the devices where the decoding result will be stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

Function
(1) Decodes the data from 0 to F designated by the lower 4 bits of S to 7-segment display data, and stores at D .

373
 SEG, SEGP

(2) If D is a bit device, indicates the head number of the devices storing the 7-segment display data; if it is a word device,
indicates the number of the device storing the data.
Before execution After execution
Y4F Y48
Bit device SEG K7 K2Y48 0 0 100 111

8 points

D8
b15 b8b7 b0
Word device SEG K7 D8 0 00000000 0 100 111

Upper 8 bits are 7-segment display data is

always filled with 0s. stored in lower 8 bits.

Operation Error
(1) There is no operation error in the SEG(P) instruction.
7-segment decode display
S Configuration of 7 D
Display Data
Hexadecimal Bit Pattern Segments B7 B6 B5 B4 B3 B2 B1 B0

0 0000 0 0 1 1 1 1 1 1

1 0001 0 0 0 0 0 1 1 0

2 0010 0 1 0 1 1 0 1 1

3 0011 0 1 0 0 1 1 1 1

4 0100 0 1 1 0 0 1 1 0

5 0101 B0 0 1 1 0 1 1 0 1

6 0110 0 1 1 1 1 1 0 1
B5 B1
7 0111 B6 0 0 1 0 0 1 1 1

8 1000 0 1 1 1 1 1 1 1
B4 B2
9 1001 0 1 1 0 1 1 1 1

A 1010 B3 0 1 1 1 0 1 1 1

B 1011 0 1 1 1 1 1 0 0

C 1100 0 0 1 1 1 0 0 1

D 1101 0 1 0 1 1 1 1 0

E 1110 0 1 1 1 1 0 0 1

F 1111 0 1 1 1 0 0 0 1

Head number of bit device

Lowest bit of word device

374
 DIS, DISP

Program Example
1
(1) The following program converts the data from XC to XF to 7-segment display data and outputs it to Y38 to Y3F when X0
is turned ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
[Timing Chart]
4
X0

*1
Y38 to Y3F 4
*1: The data Y38 to Y3F will not change until the next data is output.

7.5.6 DIS, DISP 4-bit dissociation of 16-bit data

6
7.5.6 DIS, DISP Basic High
performance Process Redundant Universal LCPU

Command 7
DIS S D n
DIS
Command
DISP DISP S D n 8
S : Head number of the devices where data to be dissociated is stored (BIN 16 bits)
D : Head number of the devices where the dissociated data will be stored (BIN 16 bits)
n : Number of dissociations (1 to 4), 0: No processing (BIN 16 bits)
Setting Internal Devices J \ Constants

7.5.6
7.5 Data processing instructions
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

DIS, DISP
D –– –– ––
n ––

Function
(1) Stores the lower n-digits (1 digit is 4 bits) of the 16-bit data designated by S at the lower 4 bits n-points from the device
designated by D .
b15 b12b11 b8 b7 b4 b3 b0 b15 b4 b3 b0
S D
D +1
n
D +2
D +3
Filled with 0s. Storage area
(2) The upper 12 bits n-points from the device designated by S become 0.
(3) The value of n can be designated at between 1 and 4.
(4) If n 0, there will be no processing, and the contents n-points from D will not change.

375
 UNI, UNIP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value of n is other than 0 to 4.
The range n-points from D exceeds the range of the corresponding
4101
device.

Program Example
(1) The following program dissociates the 16-bit data from D0 into 4-bit groups, and stores from D10 to D13 when X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b12 b11 b8 b7 b4 b3 b0 b15 b4 b3 b2 b1 b0
D0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 0 1 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
D11 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
D12 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
D13 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0

Filled with 0s. Storage area

7.5.7 UNI, UNIP 4-bit linking of 16-bit data

7.5.7 UNI, UNIP Basic High

performance Process Redundant Universal LCPU

Command
UNI S D n
UNI
Command
S D n
UNIP UNIP

S : Head number of the devices where data to be linked is stored (BIN 16 bits)
D : Head number of the devices where the linked data will be stored (BIN 16 bits)
n : Number of links (1 to 4), 0: No processing (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– –– ––
D –– ––
n ––

376
 UNI, UNIP

Function
1
(1) Links lower 4 bits of 16-bit data n-points from device designated by S to 16-bit device designated by D .
b15 b4b3 b0
S
S +1
2
S +2 b15 b12 b11 b8 b7 b4 b3 b0
S +3 D

Ignored Linked data 3

(2) The bits of the upper (4-n) digits of the device designated by D become 0.
(3) The value of n can be designated at between 1 and 4.
4
(4) If n 0, there will be no processing, and the contents of device D will not change.

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
6
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value of n is other than 0 to 4. 7
The range n-points from S exceeds the range of the corresponding
4101
device.
8
Program Example
(1) The following program links the lower 4 bits of D0 to D2 when X0 is ON, and stores them at D10.
[Ladder Mode] [List Mode]

7.5.7
7.5 Data processing instructions
Step Instruction Device

UNI, UNIP
[Operation]
b15 b4 b3 b2 b1 b0 b15 b8 b7 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 D10 0 0 0 0 1 0 0 1 0 1 0 1 0 0 0 1
D1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1
D2 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1

Linked data

377
 NDIS, NDISP, NUNI, NUNIP

7.5.8 NDIS, NDISP Dissociation of random data

7.5.8
NUNI, NUNIP Linking of random data

NDIS, NDISP, NUNI, NUNIP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of NDIS/NUNI.

Command
NDIS, NUNI S1 D S2

Command
NDISP, NUNIP P S1 D S2

S1 : Head number of the devices where data to be dissociated/linked is stored (BIN 16 bits)
D : Head number of the devices where the dissociated/linked data will be stored (BIN 16 bits)
S2 : Head number of the devices where the units of dissociation/linking will be stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S1 –– ––

D –– ––
S2 –– ––

Function
NDIS
(1) Dissociates data stored in device numbers starting from that designated at S1 into the number of individual bits
designated at S2 , and stores this data in device numbers starting from that designated at D .
Designation of the number of dissociated bits
S2 6
S2 +1 8
S2 6
S2 +3 4
S2 +4 8
S2 +5 10
S2 +6 3
S2 +7 0 Designation of the end of setting
b15b14b13 b6b5 b0 b5 b0
S1 Number of bits D
designated at S2
b7 b0
Number of bits D +1
designated at S2 +1
b15 b8b7 b4b3 b0 b5 b0
S1 +1 Number of bits D +2
designated at S2 +2
b3 b0
Number of bits D +3
designated at S2 +3
b7 b0
Number of bits D +4
designated at S2 +4
b12 b10b9 b0 b9 b0
S1 +2 Number of bits D +5
designated at S2 +5
b2 b0
Number of bits D +6
designated at S2 +6

(2) The number of dissociated bits designated at S2 can be designated within a range of 1 to 16 bits.
(3) Bits from the device number designated at S2 to the device number where "0" is stored are processed as dissociated bits.
(4) Do not overlap the device range for data to be dissociated ( S1 to end range of S1 ) with the device range which stores the
dissociated data ( D to end range of D ). If overlapped, the correct operation result may not be obtained.
(5) Do not specify the same device number for S1 , S2 , and D . If the same device is specified for S1 , S2 , and D , the operation
does not work correctly.

378
 NDIS, NDISP, NUNI, NUNIP

NUNI
(1) Links individual bits of data stored into the area starting from the device number designated by in the number of bits
1
S1

specified by S2 , and stores them following the device number designated by D .

Designation of the number of linked bits
6
2
S2
S2 +1 8
S2 +2 6
S2 +3 4
S2
S2
+4
+5
8
10
3
S2 +6 3
S2 +7 0 Designation of the end of setting
b5 b0 b15b14b13 b6 b5 b0 4
S1 Number of bits D
designated at S2
b7 b0
S1 +1
Number of bits
designated at S2 +1 4
b5 b0 b15 b8 b7 b4 b3 b0
S1 +2 Number of bits D
designated at S2 +2 6
b4 b0
S1 +3 Number of bits
designated at S2 +3

S1 +4
b7 b0 7
Number of bits
designated at S2 +4
b9 b0 b12 b10 b0
S1 +5 Number of bits
designated at S2 +5
D 8
b2 b0
S1 +6 Number of bits
designated at S2 +6

(2) The number of bits to be linked as designated by S2 can be within a range of from 1 to 16.

7.5.8
7.5 Data processing instructions
(3) Processing will be performed on the number of bits to be linked from the device number designated by S2 to the device
number storing "0".

NDIS, NDISP, NUNI, NUNIP

(4) Do not overlap the device range for data to be linked ( S1 to end range of S1 ) with the device range which stores the linked
data ( D to end range of D ). If overlapped, the correct operation result may not be obtained.
(5) Do not overlap the device numbers to be designated at S1 , S2 , and D . If overlapped, correct operation is not possible.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The number of bits dissociated or linked specified by S2 has not been
4100
set within the range from 1 to 16 bits.
The device number of the device specified by S1 or D based on the
4101 number of bits dissociated or linked specified by S2 is greater than the
final device number of each device.

379
 NDIS, NDISP, NUNI, NUNIP

Program Example
(1) The following program dissociates data of 4, 3, and 6 bits respectively from the lower bits of D0, and stores them from
D10 to D12.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b12 b7 b6 b4b3 b0
1 1 0 1 0 1 1 0 0 0 1 1 1 1 0 0 D0
4 bits b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 D10
Filled with 0s.
3 bits b2 b0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D11
Filled with 0s.
The data in these
6 bits b5 b0
bits is ignored.
0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 D12
Filled with 0s.

(2) The following program links the lower 4 bits of data from D10, the lower 3 bits of data from D11, and the lower 6 bits of
data from D12, and stores at D0.
[Ladder Mode] [List Mode]

Step Instruction Device

380
 WTOB, WTOBP, BTOW, BTOWP

[Operation]
b3 b0
D10 0 0 0 1 0 1 1 0 0 1 1 0 1 1 0 0
4 bits
1
b2 b0
D11 0 1 0 1 1 1 1 0 1 0 0 0 1 1 0 1
3 bits 2
b5 b0
D12 0 0 1 1 1 0 1 1 0 0 1 0 1 1 0 0
6 bits
3
The data in these bits is ignored. D0 0 0 0 1 0 1 1 0 0 1 0 1 1 1 0 0
b12 b7b6 b4b3 b0
Filled with 0s. 4
7.5.9 WTOB, WTOBP Data dissociation in byte units

7.5.9
BTOW, BTOWP Data linking in byte units

WTOB, WTOBP, BTOW, BTOWP Basic High

performance Process Redundant Universal LCPU
4
indicates an instruction symbol of WTOB/BTOW.

Command
S D n
6
WTOB, BTOW
Command
WTOBP, BTOWP P S D n
7
S : Head number of the devices where data to be dissociated/linked in byte units is stored (BIN 16 bits)
D : Head number of the devices where the result of dissociated/linking in byte units will be stored (BIN 16 bits)
n : Number of byte data to be dissociated/linked (BIN 16 bits)
8
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– –– ––

7.5.9
7.5 Data processing instructions
n ––

WTOB, WTOBP, BTOW, BTOWP

Function
WTOB
(1) Dissociates n-bytes of the 16-bit data stored into the area starting from the device number designated by S , and stores
them following the device designated by D .
b15 b8b7 b0 b15 b8 b7 b0
S Upper byte Lower byte D 00H Data of lower byte
S +1 Upper byte Lower byte D +1 00H Data of upper byte
D +2 00H Data of lower byte
n n bytes
S +( -1) *1 Upper byte Lower byte D +3 00H Data of upper byte
2
*1: Fractions that follow the decimal
point are rounded up. D +(n-2) 00H Data of lower byte
D +(n-1) 00H Data of upper byte
For example, if n 5, data through the lower 8 bits of S to ( S +2) would be stored from ( D to D +4).
b15 b8b7 b0 b15 b8 b7 b0
S 12H 39H D 00H 39H
S +1 56H 78H D +1 00H 12H
When n=5
S +2 FEH DCH D +2 00H 78H
bytes
D +3 00H 56H
Ignored when n=5 D +4 00H DCH

381
 WTOB, WTOBP, BTOW, BTOWP

(2) Setting the number of bytes with n automatically determines the range of the 16-bit data designated by S and the range
of the devices to store the byte data designated by D .
(3) No processing will be conducted when the number of bytes designated by n is "0".
(4) The "00H" code will automatically be stored at the upper 8 bits of the byte storage device designated by D .
b15 b8 b7 b0 b15 b8 b7 b0
D12 32H 31H 00H 31H
D11
D13 34H 33H 00H 32H
D12
D14 36H 35H 00H 33H
D13
D14 00H 34H
00H 35H
D15
D16 00H 36H

Stores 00H.

(5) Even though the range of the device with the data to be devided ( S to S +( n -1)) is the same as the range of the device
2
with the devided data ( D to D +(n-1)), the instruction operates correctly.

BTOW
(1) Links the lower 8 bits of the 16-bit data in n words stored in the area starting from the device designated by S in 1-word
units and stores it into the area starting from the device designated by D . The upper 8 bits of n-word data stored in the
area starting from the device designated by S will be ignored. Further, if n is an odd number, 0 is stored at the upper 8
bits of the device where the nth byte data is stored.
b15 b8b7 b0 b15 b8 b7 b0
S Data of the 1st byte D Data of the 2nd byte Data of the 1st byte
S +1 Data of the 2nd byte D Data of the 4th byte Data of the 3rd byte
n bytes S +2 Data of the 3rd byte
n *1
S +3 Data of the 4th byte D +( -1) Data of the nth byte Data of the (n-1) byte
2
*1: Figures after the decimal point are rounded up.
S +(n-1) Data of the nth byte

Upper bytes are ignored.

For example, if n 5, the lower 8 bits of data from S to ( S +4) are linked and stored at D to ( D +2).
b15 b8b7 b0 b15 b8 b7 b0
S 00H 12H D 34H 12H
S +1 00H 34H D +1 78H 56H
If n = 5 S +2 00H 56H D +2 00H FEH
S +3 00H 78H
+4 00H is set.
S 00H FEH

(2) Setting the number of bytes with n automatically determines the range of the byte data designated by S and the range of
the devices to store the linked data designated by D .
(3) No processing will be conducted when the number of bytes designated by n is "0".
(4) The upper 8 bits of the byte storage device designated by S are ignored, and the lower 8 bits are used.
(5) Linking is correctly processed even when the device range ( S to S +(n-1)) where the data to be linked is stored overlaps

with the device range ( D to D +( n -1)) where the linked data will be stored.
2
For example, the following will take place in a case where the lower 8 bits of D11 to D16 are to be stored at D12 to D14:
b15 b8 b7 b0 b15 b8 b7 b0
D11 00H 31H D11 00H 31H
D12 00H 32H D12 32H 31H
D13 00H 33H D13 34H 33H
D14 00H 34H D14 36H 35H
D15 00H 35H D15 00H 35H
D16 00H 36H D16 00H 36H

382
 WTOB, WTOBP, BTOW, BTOWP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The range of the values in n exceeds that of the device specified by S .
4101
The range of the values in n exceeds that of the device specified by D . 3

Program Example 4
(1) The following program dissociates the data at D10 to D12 in byte units and stores it at D20 to D25 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

4

6
[Operation]
b15 b8 b7 b0 b15 b8 b7 b0 7
D10 FDH 58H D20 00H 58H
D11 57H E2H D21 00H FDH
D12 34H 44 H D22 00H E2H
D23 00H 57H 6 bytes 8
D24 00H 44H
D25 00H 34H

(2) The following program links the lower 8 bits of data from D20 through D25 and stores the result at D10 to D12 when X0
is turned ON.

7.5.9
7.5 Data processing instructions
[Ladder Mode] [List Mode]

Step Instruction Device

WTOB, WTOBP, BTOW, BTOWP

[Operation]
b15 b8 b7 b0 b15 b8 b7 b0
D20 00H 78H D10 12H 78H
D21 31H 12H D11 55H 49H
D22 36H 49H D12 31H 67H
6 bytes 44H 55H
D23
D24 48H 67H
D25 49H 31H

Upper byte is ignored.

383
 MAX, MAXP, DMAX, DMAXP

7.5.10 MAX, MAXP Maximum value search for 16-bit data

7.5.10
DMAX, DMAXP Maximum value search for 32-bit data

MAX, MAXP, DMAX, DMAXP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of MAX/DMAX.

Command
MAX, DMAX S D n

Command
P S D n
MAXP ,DMAXP
S : Head number of the devices where a maximum value is searched (BIN 16/32 bits)
D : Head number of the devices where the maximum value search result will be stored (BIN 16/32 bits)
n : Number of data blocks to be searched (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– –– ––
n ––

Function
MAX
(1) Searches in the n points of 16-bit BIN data, from the device designated by S , for the maximum value and stores the
searched maximum value at the device designated by D . Starts the search from the device designated by S and stores
the location, specified in the number of points counted from S , of the device where the maximum value is found first at
D +1 and stores the number of the found minimum values at D +2.
S 1234 (BIN)
S +1 5678 (BIN)
D 5678 (BIN) Maximum value
S +2 5678 (BIN)
n D +1 2 Location
D +2 2 Quantity
S +(n-2) -5214 (BIN)
S +(n-1) 5555 (BIN)

DMAX
(1) Searches in the n points of 32-bit BIN data, from the device designated by S , for the maximum value and stores the
searched maximum value at the device designated by D and D +1.
Starts the search from the device designated by S and stores the location, specified in the number of points counted
from S , of the device where the maximum value is found first at D +2 and stores the number of the found minimum
values at D +3.

S +1, S 54321000 (BIN)

S +3, S +2 4321000 (BIN) D +1, D 54321000 (BIN) Maximum value
S +5, S +4 3254000 (BIN) n D +2 1 Location
S +7, S +6 54321000 (BIN) D +3 2 Quantity
S +9, S +8 12345678 (BIN)

384
 MAX, MAXP, DMAX, DMAXP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in S . 3
The device specified by in D exceeds the range of the corresponding
4101 –– –– –– ––
device.

4
Program Example
(1) The following program subtracts, when X1C is turned ON, the data stored at D100 to D103 from the data stored at R0 to 4
R3, and searches in the results of subtraction for the maximum value, then, stores it at D200 to D202.
[Ladder Mode] [List Mode]

Step Instruction Device

6

[Operation] 8
b15 b0 b15 b0 b15 b0
D100 4321 (BIN) R0 5000 (BIN) D150 -679 (BIN)
D101 5432 (BIN) R1 4000 (BIN) D151 1432 (BIN)
D102 4444 (BIN) R2 4000 (BIN) D152 444 (BIN)

7.5.10 MAX, MAXP, DMAX, DMAXP

7.5 Data processing instructions
D103 5000 (BIN) R3 6000 (BIN) D153 -1000 (BIN)
D200 1432 Maximum value
D201 2 Location
D0 4 D202 1 Quantity

(2) The following program searches for the maximum value from the32-bit data at D0 to D7, and stores it at D100 to D103
when X20 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

D1, D0 3786213 (BIN) D101, D100 8744740

D3, D2 -3235 (BIN) D102 3
D5, D4 8744740 (BIN) D103 1
D7, D6 7141821 (BIN)

385
 MIN, MINP, DMIN, DMINP

7.5.11 MIN, MINP Minimum value search for 16-bit data

7.5.11
DMIN, DMINP Minimum value search for 32-bit data

MIN, MINP, DMIN, DMINP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of MIN/DMIN.

Command
MIN, DMIN S D n

Command
P S D n
MINP, DMINP
S : Head number of the devices where a minimum value is searched (BIN 16/32 bits)
D : Head number of the devices where the minimum value search result will be stored (BIN 16/32 bits)
n : Number of data blocks to be searched (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– –– ––
n ––

Function
MIN
(1) Searches in the n points of 16-bit BIN data, from the device designated by S , for the minimum value and stores
searched minimum value at the device designated by D .
Starts the search from the device designated by S and stores the location, specified in the number of points counted
from S , of the device where the minimum value is found first at D +1 and stores the number of the found minimum
values at D +2.

S 5015 (BIN)
S +1 6192 (BIN)
D 5015 (BIN) Minimum value
S +2 5571 (BIN) n D +1 1 Location
D +2 2 Quantity
S +(n-2) 5015 (BIN)
S +(n-1) 5571 (BIN)

DMIN
(1) Searches in the n points of 32-bit BIN data, from the device designated by S , for the minimum value and stores
searched minimum value at the devices designated by D and D +1.
Starts the search from the device designated by S and stores the location, specified in the number of points counted
from S , of the device where the minimum value is found first at D +2 and stores the number of the found minimum
values at D +3.
S 22342001 (BIN)
D +1, D 22342001 (BIN) Minimum value
S +2 37282010 (BIN)
D +2 1 Location
S +4 22342001 (BIN)
D +3 2 Quantity
S +6 59872019 (BIN)

386
 MIN, MINP, DMIN, DMINP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in S .
–– –– –– ––
3
The device specified in D exceeds the range of the corresponding
4101 –– –– –– ––
device.

4
Program Example
(1) The following program adds, when X1C is turned ON, the data stored at D100 to D103 and the data stored at R0 to R3, 4
and searches in the results of addition for the minimum value, then, stores it at D200 to D202.
[Ladder Mode] [List Mode]

Step Instruction Device

6

[Operation]
8
b15 b0 b15 b0 b15 b0
D100 5542 (BIN) R0 5500 (BIN) D150 11042 (BIN)
D101 5857 (BIN) R1 4000 (BIN) D151 9857 (BIN)
+
D102 4590 (BIN) R2 4500 (BIN) D152 9090 (BIN)

7.5.11 MIN, MINP, DMIN, DMINP

7.5 Data processing instructions
D103 4450 (BIN) R3 6000 (BIN) D153 10450 (BIN)
D200 9090 Minimum value
D201 3 Location
D0 4 D202 1 Quantity
(2) The following program, when X20 is turned ON, searches for the minimum value from the 32-bit data contained from D0
to D7, and stores it from D100 to D103.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D1,D0 57020175 (BIN) D101,D100 69386
D3,D2 2070166 (BIN) D102 4
D5,D4 3596045 (BIN) D103 1
D7,D6 69386 (BIN)

387
 SORT, DSORT

7.5.12 SORT BIN 16 bit-data sort operations

7.5.12
DSORT BIN 32 bit-data sort operations

SORT, DSORT Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of SORT/DSORT.

Command
SORT, DSORT S1 n S2 D1 D2

S1 : Head device number in the table to be sorted (BIN 16/32 bits)

n : Number of data blocks to be sorted (BIN 16 bits)
S2 : Number of data blocks to be compared in one sort operation (BIN 16 bits)
D1 : Number of the bit device to be turned ON at the completion of the sort operation (bits)
D2 : Device reserved for the system (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– –– ––
n ––
S2 ––
D1 –– –– ––

D2 –– –– ––

Function
SORT
(1) Sorts (rearranges data) BIN 16-bit data n points from S1 in ascending or descending order.
Sort order is designated by the ON/OFF status of SM703:
• When SM703 is OFF: Ascending order sort
• When SM703 is ON : Descending order sort
S -124
Data before sort When SM703 = OFF S +1 -10
Sort in the ascending order
S 35 S +2 35
S +1 -10 S +3 500
S +2 500
S +3 -124
S 500
S +1 35
Sort in the descending order
When SM703 = ON S +2 -10
S +3 -124

(2) Several scans are required for sorts performed by the SORT instruction. The number of scans executed until completion
is the value obtained by dividing the maximum number of times executed until the completion of the sort by the number
of data blocks compared at one execution designated by S2 . (Decimal fractions are rounded up.) When the value of S2 is
increased, the number of scans until completion of the sort is reduced, but the amount of time per scan is lengthened.
(3) The maximum number of executions until completion of the sort should be calculated according to the following
equation:
The maximum number of executions until completion (n) (n - 1) / 2 [times executed]

Example

When n 10, the number of executions is obtained as 10 (10 - 1) / 2 45 [times executed]. If S2 2, then the number
of scans until the completion of sort is calculated as 45/2 22.5 23 [scans].

(4) The device designated by D1 (the completion device) is turned OFF by the execution of the SORT instruction, and turned
ON when the sort is completed. Because the device designated by D1 is maintained in the ON state after the completion
of the sort, the user must turn it OFF if required.

388
 SORT, DSORT

(5) The 2 points from the device designated by D2 are used by the system during the execution of the SORT instruction.
These 2 points from the device designated by D2 should therefore not be used by the user.
Changing these points may cause an error code to be returned (Error code: 4100). 1
(6) If the value of n is changed during the execution of the SORT instruction, the sort will be conducted in accordance with
the number of sort data blocks after the change.
(7) If the execution command is turned OFF during the execution of the SORT instruction, the sort is suspended. The sort
2
resumes from the beginning when the execution command is turned ON again.
(8) To execute another sort operation immediately after the completion of the previous sort, turn OFF the execution
command once, then turn it ON.
3
DSORT
(1) Sorts (rearranges data) BIN 32-bit data n points from S1 in ascending or descending order. 4
Sort order is designated by the ON/OFF status of SM703:
• When SM703 is OFF : Ascending order sort
• When SM703 is ON : Descending order sort 4
S1 +1 , S1 -1000
Data before sort When SM703 = OFF S1 +3 , S1 +2 -124
S1 +1 , S1 35000 S1 +5 , S1 +4 500
Sort in the ascending order
6
S1 +3 , S1 +2 -1000 S1 +7 , S1 +6 35000
S1 +5 , S1 +4 500
+7 , S1 +6 -124
7
S1
S1 +1 , S1 35000
S1 +3 , S1 +2 500
When SM703 = ON Sort in the descending order
S1 +5 , S1 +4 -124
S1 +7 , S1 +6 -1000

(2) Several scans are required for sorts performed by the DSORT instruction. The number of scans executed until 8
completion is the value obtained by dividing the maximum number of times executed until the completion of the sort by
the number of data blocks compared at one execution designated by S2 . (Decimal fractions are rounded up.) When the
value of S2 is increased, the number of scans until completion of the sort is reduced, but the amount of time per scan is
lengthened.

7.5.12 SORT, DSORT

7.5 Data processing instructions
(3) The maximum number of executions until completion of the sort should be calculated according to the following
equation:
The maximum number of executions until completion (n) (n-1)/2 [times executed]

Example

When n 10, the number of executions is obtained as 10 (10-1)/2 45 [times executed]. If S2 2, then the number of
scans until the completion of sort is calculated as 45/2 22.5 23 [scans].

(4) The device designated by D1 (the completion device) is turned OFF by the execution of the SORT instruction, and turned
ON when the sort is completed. Because the device designated by D1 is maintained in the ON state after the completion
of the sort, the user must turn it OFF if required.

(5) The 2 points from the device designated by D2 are used by the system during the execution of a DSORT instruction.
These 2 points from the device designated by D2 should therefore not be used by the user.
Changing these points may cause an error code to be returned (Error code: 4100).
(6) If the value of n is changed during the execution of the SORT instruction, the sort will be conducted in accordance with
the number of sort data blocks after the change.
(7) If the execution command is turned OFF during the execution of the SORT instruction, the sort is suspended. The sort
resumes from the beginning when the execution command is turned ON again.
(8) To execute another sort operation immediately after the completion of the previous sort, turn OFF the execution
command once, then turn it ON.

389
 SORT, DSORT

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 S2 is 0 or a negative value.
The range from S1 to (S1 + n/2 n) (including S1) overlaps the range
4101
from D2 to D2 +1.
For the SORT(P) instruction, the range of the device specified by S1
4101
exceeds the range from S1 to S1 + n (including S1).
For the DSORT(P) instruction, the range of the device specified by S1
4101
exceeds the range from S1 to S1 + (2 n) (including S1).

Program Example
(1) The following program sorts the BIN 16-bit data from D0 to D3 in the ascending/descending order when X10 is turned
ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data after sort
D0 -999
Data before sort D1 -1
X0 OFF
D0 100 D2 100
D1 -1 D3 12345
D2 12345
D3 -999
D0 12345
X0 ON D1 100
D2 -1
D3 -999

(2) The following program sorts the BIN 32-bit data from D0 to D9 in ascending/descending order when X10 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

390
 WSUM, WSUMP

[Operation]
Data after sort
D1, D0 -99999 1
D3, D2 -1111
Data before sort
X0 OFF D5, D4 1
D1, D0 456789
D7, D6 5000
D3, D2
D5, D4
-1111
5000
D9, D8 456789 2
D7, D6 -1 D1, D0 456789
D9, D8 -99999 D3, D2 5000
X0 ON
D5, D4 1 3
D7, D6 -1111
D9, D8 -99999

7.5.13 WSUM, WSUMP Calculation of totals for 16-bit data 4

7.5.13 WSUM, WSUMP Basic High
performance Process Redundant Universal LCPU

Command
4
WSUM S D n
WSUM

WSUMP
Command
WSUMP S D n 6
S : Head number of the devices where data to be summed are stored (BIN 16 bits)

n
D : Head number of the devices where the sum will be stored (BIN 32 bits)
: Number of data blocks (BIN 16 bits)
7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– –– –– 8
D –– ––
n ––

Function

7.5.13 WSUM, WSUMP

7.5 Data processing instructions
(1) Adds all 16-bit BIN data for n blocks from the device designated at S , and stores it in the device designated at D .

S 4444 (BIN)
S +1 3333 (BIN)
S +2 1234 (BIN) n D + 1, D 13914 (BIN)
S +3 5426 (BIN)
S +4 329 (BIN)
S +5 10000 (BIN)

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in S .

391
 DWSUM, DWSUMP

Program Example
(1) The following program adds the 16-bit BIN data from D10 to D14, and stores it in D100 and D101 when X1C is turned
ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

D10 4500 (BIN)

D11 2500 (BIN)
D12 3276 (BIN) D101,D100 14948 (BIN)
D13 6780 (BIN)
D14 4444 (BIN)

7.5.14 DWSUM, DWSUMP Calculation of totals for 32-bit data

7.5.14 DWSUM, DWSUMP Basic High

performance Process Redundant Universal LCPU

Command
DWSUM S D n
DWSUM
Command
S D n
DWSUMP DWSUMP

S : Head number of the devices where data to be summed are stored (BIN 32 bits)
D : Head number of the devices where the sum will be stored (BIN 64 bits)
n : Number of data blocks (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– –– ––

D –– –– ––
n ––

Function
(1) Adds all 32-bit BIN data stored in n points of devices starting from the one designated by S , and stores the result to 4
points of devices (4 words) starting from the one designated by D .
S + 1, S 32767000 (BIN)
S + 3, S +2 6000 (BIN)
S + 5, S +4 35392000 (BIN) n D + 3 to D 68640000 (BIN)
S + 7, S +6 11870000 (BIN)
S + 9, S +8 12345000 (BIN)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The points specified in n exceed those of the corresponding device
4101
specified in S .
The device specified in D exceeds the range of the corresponding
4101 –– –– –– ––
device.

392
 MEAN, MEANP, DMEAN, DMEANP

Program Example
1
(1) The following program adds the 32-bit BIN data at D100 to D107, and stores the result at D10 and D13 when X20 is
turned ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation]
D101,D100 11245600 (BIN)
4
D103,D102 27543200 (BIN)
D13 to D10 23672600 (BIN)
D105,D104 558800 (BIN)
D107,D106 15675000 (BIN) 4
7.5.15 MEAN, MEANP Calculation of averages for 16-bit data
DMEAN, DMEANP Calculation of averages for 32-bit data

6
Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.5.15 MEAN, MEANP, DMEAN, DMEANP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported 7
indicates an instruction symbol of MEAN/DMEAN.

MEAN, DMEAN
Command
S D n
8
Command
MEANP, DMEANP P S D n

S : Head number of the devices where the data to be averaged are stored (BIN16/32 bits)

7.5.15 MEAN, MEANP, DMEAN, DMEANP

7.5 Data processing instructions
D : Head number of the devices where the average will be stored (BIN 16/32 bits)
n : Number of data or number of the devices where the number of data are stored (Setting range: 1 to 32767) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– –– ––

D –– –– –– ––
n –– ––

Function
MEAN(P)
(1) This instruction calculates the mean of 16-bit BIN data stored in n-point devices starting from the device specified by S ,
and then stores the result into the device specified by D.

S
S +1 Average value D
S +2 n

S +n 1
(2) If the value calculated is not integer, this instruction will drop the number of decimal places.
(3) If the value specified by n is 0, the instruction will be not processed.

393
 MEAN, MEANP, DMEAN, DMEANP

DMEAN(P)
(1) This instruction calculates the mean of 32-bit BIN data stored in n-point devices starting from the device specified by S ,
and then stores the result into the device specified by D.

S +1, S D +1, D
Average value
S +3, S +2
n

S +2n 1, S +2n 2
(2) If the value calculated is not integer, this instruction will drop the number of decimal places.
(3) If the value specified by n is 0, the instruction will be not processed.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value specified in n is other than 0 to 32767. –– –– –– ––
The points specified in n exceed those of the corresponding device
4101 –– –– –– ––
specified in S .

Program Example
(1) The following program stores the average value of 16-bit data stored from D0 to D2 into D10, when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D0 105 (BIN)
D1 555 (BIN) D10 550 (BIN)
D2 990 (BIN)

(2) The following program stores the average value of 32-bit data stored from D0 to D5 into D10 and D11, when M0 is turned
on.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D1,D0 623541 (BIN)
D3,D2 4753647 (BIN) D11,D10 2101176 (BIN)
D5,D4 926342 (BIN)

394
 FOR, NEXT

7.6 Structure creation instructions

1
7.6.1 FOR, NEXT FOR to NEXT instruction loop

7.6.1 FOR, NEXT Basic High

performance Process Redundant Universal LCPU
2
FOR n
FOR
Repeat program 3
NEXT NEXT

n : Number of repetitions of FOR to NEXT loop (1 to 32767) (BIN 16 bits)

Setting Internal Devices J \ Constants
4
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n ––
4
Function
(1) When the processing in the FOR to NEXT loop is executed n-times without conditions, the step following the NEXT 6
instruction will be executed.
(2) The value of n can be designated at between 1 and 32767. If it is designated from -32768 to 0, the processing which is
executed when n=1 will be performed. 7
(3) If you do not desire to execute the processing called for within the FOR to NEXT loop, use the CJ or SCJ instruction to
jump.
(4) FOR instructions can be nested up to 16 deep.
8

FOR K5
X

7.6.1
7.6 Structure creation instructions
FOR, NEXT
FOR K3
X1

FOR instructions can be

FOR K100 nested up to 16 deep.
X2

NEXT

NEXT

NEXT

395
 FOR, NEXT

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
After the FOR instruction was executed, the END, FEND, or GOEND
instruction was executed prior to the NEXT instruction.
4200
The STOP instruction is in process between the FOR and the NEXT
instructions.
4201 The NEXT instruction was executed prior to the FOR instruction.
The 17th FOR instruction was executed when the FOR instruction has
4202
been nested.

Program Example
(1) The following program executes the FOR to NEXT loop when X8 is OFF, and does not execute it when X8 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

Remark
1. To force an end to the repetitious execution of the FOR to NEXT loop during the execution of the loop, insert a BREAK
instruction. See Page 397, Section 7.6.2 for details concerning the use of the BREAK instruction.
2. Use the EGP/EGF instruction to perform the pulse operation of an index-modified program between the FOR and NEXT
instructions. Note, however, that rise and fall instructions are not available on the operation output side. Refer to Page 145,
Section 5.2.5 for details of the EGP/EGF instruction. The program samples are shown below:

3. Branching into a FOR to NEXT loop using a JMP or other branch instruction from the outside of the FOR to NEXT loop
is not possible.

396
 BREAK, BREAKP

7.6.2 BREAK, BREAKP Forced end of FOR to NEXT instruction loop

7.6.2 BREAK, BREAKP Basic High

performance Process Redundant Universal LCPU
1
Command
BREAK D Pn
BREAK
Command
2
BREAKP BREAKP D Pn

Pn
D : Number of the device where the remaining number of loops will be stored (BIN 16 bits)
: Number of the pointer (device name (pointer)) where the program is branched at the forced end of a loop.
3
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word P
D –– ––
4
Pn –– ––

4
Function
(1) Forces an end to a FOR to NEXT instruction loop and shifts the operation to the pointer specified by Pn. Only a pointer
within the same program file can be assigned to Pn. If a pointer of the other program file is used, an operation error will
6
be returned.

FOR K ** 7
If the BREAK instruction is not executed,
Forced end condition program returns to the FOR instruction
BREAK D Pn
When forced end condition is satisfied
as many times as the number specified
with the FOR instruction.
8
NEXT

Pn

7.6.2
7.6 Structure creation instructions
(2) The remaining number of the FOR to NEXT instruction loop times is stored at D .
Note that the remaining number includes the operation when the BREAK instruction is executed.

BREAK, BREAKP
(3) The BREAK instruction can be used only during the execution of a FOR to NEXT instruction loop.
(4) The BREAK instruction can be used only when there is only one level of nesting. When an end is forced to the multiple
nesting levels, execute the same number of BREAK instructions for the nesting levels.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The BREAK instruction is used in a case other than with the FOR to
4203
NEXT instruction loop.
The jump destination for the pointer specified by Pn does not exist.
4210
The pointer of another program file is specified for Pn.

397
 CALL, CALLP

Program Example
(1) The following program forces the FOR to NEXT loop to end when the value of D0 reaches 30 (when the FOR to NEXT
loop has been executed 30 times).
[Ladder Mode] [List Mode]

Step Instruction Device

Remark
The value 71 is stored at D1 when the BREAK instruction is executed.

7.6.3 CALL, CALLP Subroutine program calls

7.6.3 CALL, CALLP Basic High

performance Process Redundant Universal LCPU

Command
CALL CALL Pn

Command
CALLP CALLP Pn

Command
CALL CALL Pn S1 to S5

Command
CALLP CALLP Pn S1 to S5

Pn : Head pointer number of a subroutine program (Device name)

S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H P
Pn –– –– ––
(Other
S1 to S5 ––
than F)

398
 CALL, CALLP

Function
1
(1) When the CALL (P) instruction is executed, executes the subroutine program of the program specified by Pn.

The CALL (P) instruction can execute subroutine programs specified by a pointer
within the same program file and subroutine programs specified by a common pointer.
2
Main routine Subroutine
program
Pn
program
3

CALL Pn RET 4

END 4
(2) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with S1 to S5 corresponding to
the function device. The contents to the devices specified by to are as indicated below.
6
S1 S5

(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
(b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding

7.6.3
7.6 Structure creation instructions
devices.
(c) The processing units for the function devices are as follows:

CALL, CALLP
• FX, FY : Bits
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the argument. The device
specified as a function device should be secured for the data size. An error will occur if it cannot be secured for the
data size.
Function devices Device Data Size Remark
• FX Bit device 1 point
––
• FY When bit designation is made for word device 1 bit
When digit designation of a bit device is used *1 4 words The data size varies depending on
• FD
Word device 4 words the instruction to be used.

*1: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit designation of the
bit device.
[Main routine program]

X0
CALL P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(3) S1 to S5 can be used with the CALL (P) instruction.

399
 CALL, CALLP

(4) The number of function devices to be used by a subroutine program must be identical to the number of arguments in the
CALL (P) instruction.
Also, the types of the function device and CALL (P) argument used should be identical.
(5) Device numbers specified by the CALL (P) instruction should not overlap.
If they do overlap, it will not be possible to obtain accurate calculations.
(6) The device used in the argument of the CALL (P) instruction should not be used in a subroutine program. If used, it will
not be possible to obtain accurate calculations. (Refer to the following program example.)
(7) When the device, either timer or counter, is used in the argument of the CALL(P) instruction, only the current value is
transmitted/received.
Incorrect operation example
The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D1 is
used in the subroutine program.
[Program example]

[Operation performed after subroutine program execution]

Before the execution Immediately after the At the time of

of subroutine program execution of CALL subroutine program After the execution
instruction execution of RET instruction
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 110 *1 D1 110 *3
D2 100 D2 100 D2 100 D2 100 *2
Transfer Transfer
D3 1000 D3 1000 D3 1000 D3 1000 *2

Indefinite 0 33 *1 Indefinite
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite
*1: Stores the execution result of the subroutine program.
*2: Replaced by the value of the function device.
*3: D1 does not reflect the value of the function device.
Correct operation example
The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is
used in the subroutine program.
[Program example]

400
 CALL, CALLP

[Operation performed after subroutine program execution]

Immediately after the At the time of
Before the execution
of subroutine program
execution of CALL
instruction
subroutine program
execution
After the execution
of RET instruction
1
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 10 D1 1 *2
D2 100 Transfer D2 100 D2 100 D2 100 *2 2
D3 1000 D3 1000 D3 1000 Transfer D3 1000 *2
D4 0 D4 0 D4 100 *1 D4 100

Indefinite 0 33 *1 Indefinite
3
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite
4
*1: Stores the execution result of the subroutine program.
*2: Replaced by the value of the function device.
(8) Up to 16 nesting levels are possible with the CALL(P) instruction. However, this 16 levels is the total number of levels in 4
the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions.

CALL P0 P0 P10 P20

6
CALL P10 CALL P20

FEND RET RET RET 7

END
(9) Devices which are turned ON within subroutine programs will be latched even if the subroutine program is not executed.
Devices which are turned ON during the execution of a subroutine program can be turned OFF by the execution of the
8
FCALL(P) instruction.

Operation Error

7.6.3
7.6 Structure creation instructions
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

CALL, CALLP
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified for the argument cannot be secured for the data
4101
size.
There is no subroutine program for the pointer specified in the CALL (P)
4210
instruction.
After the CALL (P) instruction was executed, the END, FEND, GOEND,
4211
or STOP instruction was executed prior to the RET instruction.
4212 The RET instruction was executed prior to the CALL (P) instruction.
4213 The 17th nesting level was executed.

401
 RET

Program Example
(1) The following program executes a subroutine program with argument when X20 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7.6.4 RET Return from subroutine programs

7.6.4 RET Basic High

performance Process Redundant Universal LCPU

RET RET

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
(1) Indicates end of subroutine program
(2) When the RET instruction is executed, returns to the step following the CALL (P), FCALL (P), ECALL (P), EFCALL (P) or
XCALL instruction which called the subroutine program.
Main routine Subroutine
program program
Pn

CALL Pn RET

END

402
 FCALL, FCALLP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
After the CALL(P), FCALL (P), ECALL (P), EFCALL (P) or XCALL
4211 instruction was executed, an END, FEND, GOEND, or STOP 3
instruction was excected prior to the RET instruction.
The RET instruction was executed prior to the CALL (P), FCALL (P),
4212
ECALL (P), EFCALL (P) or XCALL instruction.
4
7.6.5 FCALL, FCALLP Subroutine program output OFF calls

7.6.5 FCALL, FCALLP Basic High

performance Process Redundant Universal LCPU
4
Command
FCALL FCALL Pn

Command
6
FCALLP FCALLP Pn

7
Command
FCALL FCALL Pn S1 to S5

Command
FCALLP FCALLP Pn S1 to S5
8
Pn : Head pointer number of a subroutine program (Device name)
S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)
Setting Internal Devices J \ Other
R, ZR U \G Zn Constants
Data Bit Word Bit Word P
Pn –– –– ––

7.6.5
7.6 Structure creation instructions
(Other
S1 to S5 ––
than F)

FCALL, FCALLP
Function
(1) When FCALL(P) is executed, the non-execution processing of the subroutine program of the pointer designated by Pn is
performed.

The FCALL (P) instruction can execute subroutine programs designated by a pointer
within the same program file, and subroutine programs designated by common pointers.

(a) Non-execution processing is identical to the processing that is conducted when the condition contacts for the
individual coil instructions are in the OFF state.
Main routine Subroutine
program program
Pn Non-execution processing is
executed when the command
for the FCALL(P) instruction is
FCALL Pn RET turned from ON to OFF.

END

403
 FCALL, FCALLP

(b) The operation results for the individual coil instructions following non-execution processing will be as follows,
regardless of the ON/OFF status of the individual contacts:
OUT instruction........................................................ Forced OFF
SET instruction
RST instruction
SFT instruction ................ Maintains status
Basic instructions
Application instructions
PLS instruction
Pulse generation ................ Processing identical to when condition contacts are OFF
instruction ( P)
Present value of low speed/high speed timers......... 0
Present value of retentive timer
................ Preserves
Present value of counter

(2) The FCALL (P) instruction is used in conjunction with the CALL(P) instruction.
(3) If the FCALL (P) instruction is used in conjunction with the CALL(P) instruction, non-execution processing of a subroutine
program is performed when the execution command is turned OFF, enabling forcible turning OFF of the OUT instruction
and the PLS instruction (including P instructions).
In case the FCALL (P) instruction is not used in conjunction with the CALL(P) instruction, non-execution processing of a
subroutine program is not performed even if the execution command is turned OFF. Therefore, output status of the
individual coil instructions remains unchanged.
X0
CALL P0 When FCALL instruction is used

FCALL P0 X0

X1

FEND Y10
X1
P0 Y10 Y11

SET Y11 M0

Forced OFF by FCALL instruction

PLS M0

RET

X0 When FCALL instruction is not used

CALL P0
X0

X1
FEND
X1 Y10
P0 Y10
Y11
SET Y11
M0
PLS M0

RET

404
 FCALL, FCALLP

(4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with S1 to S5 corresponding to
the function device. The contents to the devices specified by S1 to S5 are as indicated below.
1

4
(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
(b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding
4
devices.
(c) The processing units for the function devices are as follows:
• FX, FY: Bits
6
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the argument. The device
specified as a function device should be secured for the data size. An error will occur if it cannot be secured for the
7
data size.
Function devices Device Data Size Remark
• FX Bit device 1 point
• FY When Bit Designation has been Made for Word Device 1 bit
–––– 8
When digit designation of a bit device is used*1 4 words The upper 2 words of FD become 0.
• FD
Word device 4 words ––––

*1: An error will not occur if the device number specified by S1 to S5 is not a multiple of 16 at the digit designation of the bit device.
[Main routine program]

7.6.5
7.6 Structure creation instructions
X0
FCALL P0 M0 D0 D30

FCALL, FCALLP
Occupies from D30 to D33 (Transfer to FD2).
Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(5) The FCALL (P) instruction can use from S1 to S5 .

(6) Up to 16 nesting levels are possible with the FCALL(P) instruction. However, this 16 levels is the total number of levels in
the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions.
CALL P0

FCALL P0 P0 P10 P20

CALL P10 CALL P20

FCALL P10 FCALL P20

FEND RET RET RET

END

405
 FCALL, FCALLP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device specified for the argument cannot be secured for the data
4101
size.
The subroutine program of the pointer designated by the FCALL (P)
4210
instruction does not exist.
After the CALL (P) instruction was executed, the END, FEND, GOEND,
4211
or STOP instruction was executed prior to the RET instruction.
4212 The RET instruction was executed prior to the FCALL (P) instruction.
4213 The 17th nesting level is executed.

Program Example
(1) The following program executes a subroutine program with argument when X20 is turned ON, and forces non-execution
processing when X20 is turned from ON to OFF.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

X20

M0

Y1

Forced OFF by FCALL instruction

406
 ECALL, ECALLP

7.6.6 ECALL, ECALLP Subroutine calls between program files

7.6.6 ECALL, ECALLP Basic High

performance Process Redundant Universal LCPU 1
Command
ECALL ECALL File name Pn
2
Command
ECALLP ECALLP File name Pn

Command 3
ECALL ECALL File name Pn S1 to S5

Command

4
ECALLP ECALLP File name Pn S1 to S5

File name: Name of the program file to be called (character string)

Pn : Head pointer number of a subroutine program (Device name)
S1 to
Setting
S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)
Internal Devices J \ Constants Other
4
R, ZR U \G Zn
Data Bit Word Bit Word K, H $ P
File name –– –– ––
Pn –– –– –– –– 6
(Other
S1 to S5 –– ––
than F)
7
Function
(1) Executes the subroutine program of the pointer designated by Pn in the designated program file name when the ECALL 8
(P) instruction is executed. The ECALL(P) instruction can be used to call a subroutine program that uses a local pointer
from a different program file.

[File name: MAIN] [File name: ABC]

7.6.6
7.6 Structure creation instructions
Main routine Subroutine
program program
Pn

ECALL, ECALLP
ECALLABCPn RET

END
(2) Only the file name of a program file stored in the drive 0 (program memory/internal RAM) can be designated for a file
name.
(3) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

407
 ECALL, ECALLP

(4) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function
device with S1 to S5 . The contents of the devices specified by S1 to S5 are as indicated below.

[MAIN]

[ABC]

(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
(b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding
devices.
(c) The processing units for the function devices are as follows:
• FX, FY: Bits
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the argument. The device
specified as a function device should be secured for the data size. An error will occur if it cannot be secured for the
data size.
Function devices Device Data Size Remark
• FX Bit device 1 point
––––
• FY When Bit Designation has been Made for Word Device 1 bit
When digit designation of a bit device is used*1 4 words The data size varies depending
• FD
Word device 4 words on the instruction to be used.

*1: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit designation of the
bit device.
[Main routine program]
X0
ECALL "A-LINE" P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(5) From S1 to S5 can be used by the ECALL instruction.

(6) The device used in the argument of the ECALL instruction should not be used in a subroutine program.
If used, it will not be possible to obtain accurate calculations. (Refer to the following program example.)

408
 ECALL, ECALLP

Incorrect operation example

The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D1 is
used in the subroutine program. 1
[Program example]

[Operation performed after subroutine program execution]

6
Before the execution Immediately after the At the time of
of subroutine program execution of ECALL subroutine program After the execution
instruction execution of RET instruction 7
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 110 *1 D1 110 *3
D2
D3
100
1000
D2
Transfer
D3
100
1000
D2
D3
100
1000
Transfer D2
D3
100 *2
1000 *2
8
Indefinite 0 33 *1 Indefinite
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite

7.6.6
7.6 Structure creation instructions
Indefinite 1000 1000 Indefinite
*1: Stores the execution result of the subroutine program.
*2: Replaced by the value of the function device.

ECALL, ECALLP
*3: D1 does not reflect the value of the function device.
Correct operation example
The following example shows the operation performed when D0 is specified for FD0 in the subroutine program and D4 is
used in the subroutine program.
[Program example]
[MAIN]

[ABC]

409
 ECALL, ECALLP

[Operation performed after subroutine program execution]

Immediately after the At the time of
Before the execution
execution of ECALL subroutine program After the execution of
of subroutine program
instruction execution RET instruction
D0 0 D0 0 D0 0 D0 33 *2
D1 10 D1 10 D1 10 D1 1 *2
D2 100 D2 100 D2 100 Transfer D2 100 *2
Transfer
D3 1000 D3 1000 D3 1000 D3 1000 *2
D4 0 D4 0 D4 100 *1 D4 100

Indefinite 0 33 *1 Indefinite
Indefinite 10 1 *1 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite
*1: Stores the execution result of the subroutine program.
*2: Replaced by the value of the function device.
(7) The numbers of the devices designated by the arguments in the ECALL(P) instruction should not overlap. If they do
overlap, it will not be possible to obtain accurate calculations.
(8) Up to 16 levels of nesting can be used with the ECALL(P) instruction. However, this 16 levels is the total number of
levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions.

ECALL "ABC" P0 P0 P10 P20

ECALL "DEF" P10 ECALL "GHI" P20

FEND RET RET RET

END
(9) Devices which are turned ON within subroutine programs will be latched even if the subroutine program is not executed.
Devices turned ON during the execution of a subroutine program can be turned OFF by the EFCALL(P) instruction.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The specified file does not exist.
2411 The specified file cannot be executed.
The device specified for the argument cannot be secured for the data
4101
size.
The subroutine program of the pointer specified by the ECALL (P)
4210
instruction does not exist.
After the ECALL (P) instruction was executed, the END, FEND,
4211
GOEND, or STOP instruction was executed prior to the RET instruction.
4212 The RET instruction was executed prior to the ECALL (P) instruction.
4213 The 17th nesting level is executed.

410
 EFCALL, EFCALLP

Program Example
1
(1) The following program executes program block P0 of the program A-LINE when X20 is turned ON.
[Ladder Mode] [List Mode]

[MAIN] Step Instruction Device 2

[A-LINE] Step Instruction Device

4

6
7.6.7 EFCALL, EFCALLP Subroutine output OFF calls between program files

7.6.7 EFCALL, EFCALLP High

7
Basic performance Process Redundant Universal LCPU

EFCALL
Command
EFCALL File name Pn 8
Command
EFCALLP EFCALLP File name Pn

Command
EFCALL

7.6.7
7.6 Structure creation instructions
EFCALL File name Pn S1 to S5

Command
EFCALLP EFCALLP File name Pn S1 to S5

EFCALL, EFCALLP
File name: Name of the program file to be called (character string)
Pn : Head pointer number of a subroutine program (Device name)
S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H $ P
File name –– –– ––
Pn –– –– –– ––
(Other
S1 to S5 –– ––
than F)

411
 EFCALL, EFCALLP

Function
(1) When the EFCALL(P) instruction is executed, the non-execution processing of the subroutine program of the pointer
designated by Pn is performed.

The EFCALL (P) can also be used to call a subroutine program that uses a local
pointer from a different program file.

(a) Non-execution processing is identical to the processing that is conducted when the condition contacts for the
individual coil instructions are in the OFF state.
[File name: MAIN] [File name: ABC]
Main routine Subroutine
program program
Pn Non-execution processing
is executed when the
command for the
EFCALL(P) instruction is
EFCALL "ABC" Pn RET turned from ON to OFF.

END
(b) The operation results for the individual coil instructions following non-execution processing will be as follows,
regardless of the ON/OFF status of the individual contacts:
OUT instruction........................................................ Forced OFF
SET instruction
RST instruction
SFT instruction ................ Maintains status
Basic instructions
Application instructions
PLS instruction
Pulse generation ................ Processing identical to when condition contacts are OFF
instruction ( P)
Present value of low speed/high speed timers......... 0
Present value of retentive timer
................ Preserves
Present value of counter

(2) The EFCALL (P) instruction is used in combination with the ECALL (P) instruction.

412
 EFCALL, EFCALLP

(3) If the EFCALL(P) instruction is used in conjunction with the ECALL(P) instruction, non-execution processing of a
subroutine program is performed when the execution command is turned OFF, enabling forcible turning OFF of the OUT
instruction and the PLS instruction (including P instructions). 1
In case the EFCALL(P) instruction is not used in conjunction with the ECALL(P) instruction, non-execution processing of
a subroutine program is not performed even if the execution command is turned OFF. Therefore, output status of the
individual coil instructions remains unchanged. 2
When EFCALL instruction is used

[File Name: ABC.QPG]

4

4
Forced OFF by FCALL instruction

7
When EFCALL instruction is not used

[File Name: ABC.QPG]

8

7.6.7
7.6 Structure creation instructions
EFCALL, EFCALLP
(4) Only the file name of a program file stored in the drive 0 (program memory/internal RAM) can be designated for a file
name.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

413
 EFCALL, EFCALLP

(6) When function devices (FX, FY, FD) are used by a subroutine program, specify a device corresponding to the function
device with S1 to S5 .

[MAIN]

[ABC]

(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
(b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding
devices.
(c) The processing units for the function devices are as follows:
• FX, FY: Bits
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the argument. The device
specified as a function device should be secured for the data size. An error will occur if it cannot be secured for the
data size.
Function devices Device Data Size Remark
• FX Bit device 1 point
––
• FY When Bit Designation has been Made for Word Device 1 bit
When digit designation of a bit device is used*1 4 words The upper 2 words of FD become 0.
• FD
Word device 4 words ––

*1: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit designation of the
bit device.
[Main routine program]
X0
EFCALL "ABC" P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(7) S1 to S5 can be used with the EFCALL (P) instruction.

(8) The number of function devices used by subroutine programs must be identical to the number of arguments used by the
EFCALL (P) instruction. Further, the function devices should be identical to the types of arguments used by the EFCALL
(P) instruction.

414
 EFCALL, EFCALLP

(9) Up to 16 levels of nesting can be used with the EFCALL (P) instruction. However, this 16 levels is the total number of
levels in the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions.
ECALL "ABC" P0 1
EFCALL "ABC" P0 P0 P10 P20

ECALL "DEF" P10 ECALL "GHI" P20 2

EFCALL"DEF" P10 EFCALL "GHI" P20
FEND

END
RET RET RET 3

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

Error
Q00J/ 4
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2411 The specified file cannot be executed. 6
The device specified for the argument cannot be secured for the data
4101
size.
The subroutine program of the pointer specified by the ECALL (P)
4210
instruction does not exist. 7
After the EFCALL (P) instruction was executed, the END, FEND,
4211
GOEND, or STOP instruction was executed prior to the RET instruction.
4212 The RET instruction was executed prior to the EFCALL (P) instruction. 8
4213 The 17th nesting level is executed.

Program Example

7.6.7
7.6 Structure creation instructions
(1) The following program executes a subroutine program with argument when X0 is ON, and forces non-execution
processing when X20 is turned from ON to OFF.

EFCALL, EFCALLP
[Ladder Mode] [List Mode]
Step Instruction Device

415
 XCALL
7.6.8 XCALL Subroutine program calls

Ver.
High
Basic performance Process Redundant Universal LCPU

7.6.8 XCALL • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
XCALL XCALL Pn S1 to S5

Pn : Head pointer number of a subroutine program (Device name)

S1 to S5 : Number of the device to be passed as an argument to a subroutine program (bits, BIN 16 bits, BIN 32 bits)
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H P
P –– –– ––
(Other
S1 to S5 ––
than F)

Function
(1) XCALL instruction executes the subroutine program and performs non-execution processing of the subroutine program.
(a) Execution of subroutine program
Executes each coil instruction according to ON/OFF status of the condition contacts.
(b) Non-execution of subroutine program
Performs the same processing for each coil instruction as when the condition contacts are OFF status. The
operation results for the individual coil instructions following non-execution processing will be as follows, regardless
of the ON/OFF status of the individual contacts:
OUT instruction........................................................ Forced OFF
SET instruction
RST instruction
SFT instruction ................ Maintains status
Basic instructions
Application instructions
PLS instruction
Pulse generation ................ Processing identical to when condition contacts are OFF
instruction ( P)
Present value of low speed/high speed timers......... 0
Present value of retentive timer
................ Preserves
Present value of counter

(2) Operation of XCALL instruction varies according to the CPU module type. The following program example shows the
operation of XCALL instruction for each CPU module.
[Program example]

Subroutine program (P1)

call by XCALL instruction

P1 subroutine program

416
 XCALL

[ON/OFF timing of X0]

(1) Turning X0 ON (3) Turning X0 OFF
(OFF ON) (2) During X0 is ON *2 (ON OFF)
1
ON
OFF
X0
*2: Time during X0 is ON (2) does not include the time when turning X0 ON (1). 2
Component Operation of XCALL instruction
• Process CPU 1) When X0 is turned ON: Without process (Do not execute subroutine program of "P1".)
(serial No. of first 5 digits: 07031 or earlier) 2) During X0 is ON: Execute subroutine program of "P1". 3
• High performance model QCPU 3) When X0 is turned OFF: Perform "Non-execution processing" of subroutine program of
(serial No. of first 5 digits: 06081 or earlier) "P1".
1) Using SM734 (XCALL instruction executing condition designation) to select operation
when X0 is turned ON. 4
• High performance model QCPU
• When SM734 is OFF: Without process (Do not execute subroutine program of "P1".)
(serial No. of first 5 digits: 06082 or later)
• When SM734 is ON: Execute subroutine program of "P1".
• Process CPU
(serial No. of first 5 digits: 07032 or later)
2) During X0 is ON: Execute subroutine program of "P1". 4
3) When X0 is turned OFF: Perform "Non-execution processing" of subroutine program of
"P1".
• Redundant CPU 1) When X0 is turned ON: Execute subroutine program of "P1".
• Basic model QCPU 2) During X0 is ON: Execute subroutine program of "P1". 6
• Universal model QCPU 3) When X0 is turned OFF: Perform "Non-execution processing" of subroutine program of
• LCPU "P1".

(3) When function devices (FX, FY, FD) are used by a subroutine program, specify a device with S1 to S5 corresponding to 7
the function device. The contents to the devices specified by S1 to S5 are as indicated below.

7.6.8
7.6 Structure creation instructions
XCALL
(a) Prior to execution of the subroutine program, bit data is transmitted to FX, and word data is transmitted to FD.
(b) After the execution of the subroutine program, the contents of FY and FD are transmitted to the corresponding
devices.
(c) The processing units for the function devices are as follows:
• FX, FY: Bits
• FD : 4-word units
The size of the data to be dealt with will differ depending on the device specified in the argument. The device
specified as a function device should be secured for the data size. An error will occur if it cannot be secured for the
data size.
Function devices Device Data Size Remark
• FX Bit device 1 point
––––
• FY When Bit Designation has been Made for Word Device 1 bit
When digit designation of a bit device is used*3 4 words The data size varies depending
• FD
Word device 4 words on the instruction to be used.

*3: An error will not occur even when the device number specified by S1 to S5 is not a multiple of 16 at the digit specification of the
bit device.

417
 XCALL

[Main routine program]

X0
XCALL P0 M0 D0 D30

Occupies from D30 to D33 (Transfer to FD2).

Occupies from D0 to D3 (Transfer to FD1).
Occupies M0 (Transfer to FX0).

(4) S1 to S5 can be used by the XCALL instruction.

(5) The number of function devices used by a subroutine program must be identical to the number of arguments in the
XCALL instruction. Also, the function device and the type of XCALL argument should be identical.
(6) Device numbers specified in the argument of the XCALL instruction should not overlap.
If they do overlap, it will not be possible to obtain accurate calculations.
(7) Up to 16 nesting levels can be used with the XCALL instruction. However, this 16 levels is the total number of levels in
the CALL(P), FCALL(P), ECALL(P), EFCALL(P), and XCALL instructions.

XCALL P0 X0 P0 P20

XCALL P10 X10 XCALL P20 X20

FEND RET RET RET

END

(8) The device used for the argument of the XCALL instruction must not be used in a subroutine program.
If used, it will not be possible to perform correct calculations.
(Refer to the following program example.)
The processing to be executed when D1 is used in a subroutine program with D0 designated for FD0 in a subroutine
program is shown below.
[Program example]

[Operation performed after subroutine program execution]

Immediately after the At the time of
Before the execution After the execution
execution of subroutine program
of subroutine program of RET instruction
XCALL instruction execution
D0 0 D0 0 D0 0 D0 1 *2
D1 10 D1 10 D1 110 *1 D1 10 *2
D2 100 D2 100 D2 100 Transfer D2 100 *2
Transfer
D3 1000 D3 1000 D3 1000 D3 1000 *2

Indefinite 0 1 *1 Indefinite
Indefinite 10 10 Indefinite
FD0 FD0 FD0 FD0
Indefinite 100 100 Indefinite
Indefinite 1000 1000 Indefinite
*1: Stores the execution result of the subroutine program.
*2: Replaced by the value of the function device. D1 does not reflect the operation result in the subroutine program.

418
 COM

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The device specified for the argument cannot be secured for the data
4101
size. 3
There is no subroutine program for the pointer specified in the XCALL
4210
(P) instruction.

4211
After the XCALL (P) instruction was executed, the END, FEND,
GOEND, or STOP instruction was executed prior to the RET instruction.
4
4212 The RET instruction was executed prior the XCALL (P) instruction.
4213 The 17th nesting level is executed.
4
Program Example
(1) The following program executes a subroutine program with argument when X20 is turned ON.
6
[Ladder Mode] [List Mode]

Step Instruction Device

7

7.6.9
7.6 Structure creation instructions
COM
7.6.9 COM Refresh

7.6.9 COM Basic High

performance Process Redundant Universal LCPU

Refer to Page 421, Section 7.6.10 for the COM instruction of the following CPU modules.
• Basic model QCPU of serial No. 04122 or later
• High Performance model QCPU of serial No. 04012 or later
• Process CPU of serial No. 07032 or later
• Redundant CPU
• Universal model QCPU
• LCPU

COM
COM

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

419
 COM

Function
(1) Use the COM instruction for the following purposes.
(a) To reduce the time required to send/receive data to/from the remote I/O stations.
(b) To ensure data communication with a CPU module on another station when two CPU modules perform operations
using different scan times.
(2) The processing of the COM instruction differs depending on the status (ON or OFF) of the special relay SM775.
• SM775 is OFF: Performs both auto refresh and communication with external devices. *1 *2
• SM775 is ON: Performs only communication with external devices.*1
*1: The following processing is performed in communication with external devices.
• Monitor processing of other stations
• Read processing by the serial communications module of the buffer memory of another intelligent function module
*2: The auto refresh includes the following processing:
• Refresh of MELSECNET/10H
• CC-Link refresh
• Auto refresh of intelligent function modules
(3) At the point of the execution of the COM instruction, the CPU module temporarily stops the processing of the sequence
program, and performs the same operation as ordinary data processing as well as auto refresh of intelligent function
modules (including link refreshes) at the END processing. However, the low speed cyclic refresh of MELSECNET/10 or
MELSECNET/H is not performed.
Execution of COM instruction Execution of COM instruction

0 END 0 END 0

General data processing and auto refresh

(including link refresh) of intelligent function module
(4) The COM instruction can be used in a sequence program any number of times. Note, however, that the scan time of the
sequence program will increase by the time taken for communication with external devices and auto refresh (including
link refresh) of intelligent function modules.
(5) Data communications using the COM instruction
(a) Example of data communications when COM instruction is not used

Host station program 0 END 0 END 0 END 0 END 0 END 0 END 0

Data communications

Program at other station 0 END 0 END 0 END 0 END 0

I/O refresh at remote I/O station

(b) Example of data communications when COM instruction has been used
COM COM COM COM COM COM
Host station program 0 END 0 END 0 END 0 END 0 END 0

Data communications

COMCOM COM COM COM

Program at other station 0 0 0 END 0 0

END END COM COM COM END

I/O refresh at remote I/O station

1) When the COM instruction is used at the host station, it is possible to increase the number of data
communication repetitions with the remote I/O station unconditionally, as shown in (b) above, and thus to speed
up data communications.

420
 COM

2) In cases where the remote station scan time is longer than the scan time of the host station, the COM instruction
used at the remote station side can avoid the occurrence of timing failure in which the data cannot be fetched,
as shown in (a). 1
3) When the COM instruction has been used at the other station, a link refresh will be performed each time that
station receives a command from the host station.
Step 0 COM instruction Link refresh can be performed 2
COM instruction COM instruction once in each of these intervals.
COM instruction END instruction
(6) If the scan time from the linked station is longer than the sequence program scan time at the host station, designating the
COM instruction at the host station will not increase the speed of data communications.
3
END

Sequence program 0 COM END 0 COM END 0 COM 0 COM END 4

Link scan
4
The programs in which the COM instruction cannot be used are shown below:
• Low-speed execution type programs
• Interrupt programs
6
• Fixed scan execution type programs

7
Operation Error
(1) There is no operation error in the COM instruction. 8
7.6.10 COM Select refresh

Ver. Ver. Ver.

High
Basic performance Process Redundant Universal LCPU
• Basic model QCPU: The serial number (first five digits) is

7.6.10 COM
7.6 Structure creation instructions
"04122" or later.
• High Performance model QCPU: The serial number (first five
digits) is "04012" or later.

7.6.10 COM • Process CPU: The serial number (first five digits) is "07032" or
later.

Refer to Page 419, Section 7.6.9. for the COM instruction of the following CPU modules.
• Basic model QCPU of serial No. 04121 or later
• High Performance model QCPU of serial No. 04011 or later
• Process CPU of serial No. 07031 or later

COM
COM

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

421
 COM

(1) The COM instruction is used to perform I/O refresh at any timing during execution of a sequence program.

(2) The following processing can be performed with the COM instruction.
Processing item QCPU LCPU
I/O refresh
CC-Link refresh
CC-Link IE Controller Network refresh
CC-Link IE Field Network refresh *1 *2

MELSECNET/H refresh
Auto refresh of intelligent function modules
Auto refresh using QCPU standard area of multiple CPU system
Reading input/output data of all modules other than the multiple CPU system group
Auto refresh using the multiple CPU high speed transmission area of multiple CPU system
Communication with display unit
Service processing (communication with programming tool, GOT, or other external devices)
*1: Products with the first 5 digits of the serial No. "12012" or higher are applicable.
*2: Products with the first 5 digits of the serial No. "13012" or higher are applicable.

Remark
The following processing is also performed during service processing.
• Monitor processing of other station
• Read of another intelligent function module buffer memory by the serial communication module

(3) All the processing items except I/O refresh are performed when SM775 is turned OFF.
(4) Selecting a processing item
(a) Select a processing item in SD778 and turn ON SM775.
The following table shows processing that can be specified in SD778 when SM775 is turned ON.
QCPU LCPU
Processing item When SM775 is When SM775 is When SM775 is When SM775 is
OFF ON OFF ON
I/O refresh Not executed Not executed Whether to be
executed or not
CC-Link refresh Executed
can be selected.
CC-Link IE Controller Network refresh - -
Whether to be
CC-Link IE Field Network refresh Executed executed or not
can be selected.
MELSECNET/H refresh Whether to be - -
executed or not Whether to be
Executed
Auto refresh of intelligent function modules can be selected. Executed executed or not
can be selected.
Auto refresh using QCPU standard area of multiple CPU
- -
system
Reading input/output data of all modules other than the
- -
multiple CPU system group
Auto refresh using the multiple CPU high speed
- -
transmission area of multiple CPU system
Communication with display unit - -
Whether to be
Whether to be
Service processing (communication with programming Executed executed or not
Executed executed or not
tool, GOT, or other external devices) can be selected.
can be selected.

422
 COM

(b) Set an execution status for each processing in SD778.

Set an execution status for each bit of SD778 as shown below.
[QCPU] 1
Bit of SD778 Executed Not Executed
b0 to b6 1 0
b15 0 1
2
b15 b14 to b6 b5 b4 b3 b2 b1 b0
SD778 1/0 0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
I/O refresh
CC-Link refresh 3
CC-Link IE Controller Network,
MELSECNET/H refresh
Auto refresh of
intelligent function module 4
Auto refresh using QCPU standard
area of multiple CPU system
Reading inputs/outputs from the outside
of the multiple CPU system group
Auto refresh using the multiple CPU high speed
4
transmission area of multiple CPU system
CC-Link IE Field Network refresh
Service processing
(communication with programming tool, 6
GOT, or other external devices)

Example

To make only the send/receive processing with the remote I/O station faster, designate MELSECNET/H refresh
7
only.
(Set only b2 and b15 of SD778 to 1 (SD778: 8004H).)
8

Refresh between the multiple CPUs by the COM instruction is performed under the following condition.
• Receiving operation from other CPUs: When b4 of SD778 (auto refresh in the CPU shared memory) is 1.
• Sending operation from host CPU: When b15 of SD778 (execution status of service processing) is 0.

7.6.10 COM
7.6 Structure creation instructions
[LCPU]
Bit of SD778 Executed Not Executed
b0, b1, b3, b6, b14 1 0
b15 0 1

b15 b14b13 to b6 b5 b4 b3 b2 b1 b0
SD778 1/0 1/0 0 1/0 0 0 1/0 0 1/0 1/0
I/O refresh
Refresh via CC-Link

Auto refresh by intelligent function module

Refresh via CC-Link IE Field Network

Communication with display unit

Service processing (communication with
programming tool, GOT, or external devices)

Example

To speed up processing of the display unit only, specify communication with the display unit only. (Write "1" to bits
b14 and b15 of SD778 (SD778:C000H).)

423
 CCOM, CCOMP

(5) At the point of the execution of the COM instruction, the CPU module temporarily stops the processing of the sequence
program, and performs specified processing.
Execution of COM Execution of COM
instruction instruction

0 END 0 END 0

Specified processing Specified processing

(6) The COM instruction can be used in a sequence program any number of times.
However, note that the scan time of the sequence program will be lengthened by the time taken for the processing
selected in SD778.
(7) Only with the Universal model QCPU and LCPU, interruption is enabled during the execution of the COM instruction.
However, note that the data can be separated if the refresh data is used by an interrupt program etc.
(8) With the Built-in Ethernet port QCPU and Built-in Ethernet port LCPU, processing time may be increased if the service
process was executed by the COM instruction while the built-in Ethernet ports are in Ethernet connection.

1. The programs in which the COM instruction cannot be used are shown below:
• Low-speed execution type programs
• Interrupt programs
• Fixed scan execution type programs
2. For the redundant CPU, there are restrictions on use of the COM instruction. Refer to the manual below for details.
• QnPRHCPU User's Manual (Redundant System)

Operation Error
(1) There is no operation error in the COM instruction.

7.6.11 CCOM, CCOMP Select refresh

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.6.11 CCOM, CCOMP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

Command
CCOM CCOM

Command
CCOMP CCOMP

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––

Function
See Page 421, Section 7.6.10 for details about function.

424
 CCOM, CCOMP

Operation Error
1
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
When the CCOM(P) instruction was executed in the QnUD(H)CPU
4100 whose serial number (first five digits) is "10101" or earlier, an error –– –– –– –– ––
occurs.
3
Program Example
(1) Turning on M0 enables the program to execute the select refresh, while turning off M0 disables the program to execute 4
the select refresh.
[Ladder Mode] [List Mode]

Step Instruction Device

4

7.6.11 CCOM, CCOMP

7.6 Structure creation instructions

425
 IX, IXEND

7.6.12 IX, IXEND Index modification of entire ladder

7.6.12 IX, IXEND Basic High

performance Process Redundant Universal LCPU

IX IX S

Ladder where index modification is performed

IXEND I X END

S : Head number of the devices where index modification data is stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S –– ––

Function
(1) Performs index modification on all devices in the ladder up to the IXEND instruction after the IX instruction, using the
index modification value specified in the index modification table. Refer to Page 429, Section 7.6.13 for how to configure
an index modification table.
The configuration of the index modification table and the corresponding index register numbers are as shown below:
Index register Index register
Device name Device name
number number
Modification value of timer Modification value of
S Z0 S +8 data register (D)
Z8
(T)

S +1 Modification value of counter S +9 Modification value of

(C)
Z1 link register (W)
Z9
Modification value of input S + 10 Modification value of
S +2 Z2 file register (R) Z10
(X)
Modification value of output Modification value of
S +3 (Y)
Z3 S + 11 buffer register I/O No. (U) Z11
Modification value of Modification value of
S +4 internal relay (M) Z4 S + 12 buffer register (G) Z12
Modification value of *1
S +5 Modification value of
latch relay (L)
Z5 S + 13 link direct device Z13
network No. (J)
Modification value of Modification value of
S +6 link relay (B)
Z6 S + 14 file register (ZR)
Z14

S +7 Modification value of Modification value of pointer

edge relay (V) Z7 S + 15 (P) Z15

*1: When using a basic model QCPU, index registers with numbers from Z10 onward cannot be used.

426
 IX, IXEND

(2) Index modification for device numbers is accomplished in the manner as below: By setting a modification value to each
of the devices, the set modification values are added to the all device numbers of the devices used in the ladder between
the IX and IXEND instructions. The program is executed using the index modified device numbers. 1
IX D100 Modification value
D100 8 T (Z0)
X1Z2 M62Z4 Y24 Z3
SET M6Z4
D101
D102
5
2
C
X
(Z1)
(Z2)
2
D103 10 Y (Z3)
T495Z0 C270Z1B20Z6 D104 10 M (Z4)
MOV K0 D0Z8 D105
D106
20
16
L
B
(Z5)
(Z6)
3
X19Z2
D107 20 V (Z7)
Y40Z3
D108 1 D (Z8)

IXEND
4
X3 M72 Y2E
SET M16 Value "2" is added to X1 and X9.
Value "10 (AH)" is added to Y24 and Y40.
Processed as X3 and X1B, respectively.
Processed as Y2E and Y4A, respectively. 4
Value "10" is added to M6 and M62. Processed as M16 and M72, respectively.
T498 C275 B30
MOV K0 D1 Value "16 (10H)" is added to B20. Processed as B30.
Value "8" is added to T495. Processed as T498.
X1B Value "5" is added to C270. Processed as C275. 6
Y4A Value "1" is added to D0. Processed as D1.

(3) Instructions such as the PLS, PLF, and P instructions, which are executed only once when input conditions have
been established, cannot be index modified by using the IX to IXEND instruction loop.
7
(4) In cases where adding the modification value causes the device number to exceed the device range, accurate
processing will not be conducted.
8
(5) Do not execute the IX or IXEND instructions during online program changes of sequence programs (write during RUN).
Accurate processing will not be conducted if this happens.
(6) Modification values are preset for random word devices as BIN values, and the initial device number for which
modification values have been set is designated by S .

7.6.12 IX, IXEND

7.6 Structure creation instructions
(7) Do not execute a scan execution type program and an interrupt program simultaneously between the IX and IXEND
instructions.
(8) Whether the program will be expanded or a user needs to create the program is depending on your GPP function
software package.
The index register should be added to the index modification ladder established with the IX and IXEND instructions. *2

IX D100
X1Z2 M62Z4 Y24Z3
SET M6Z4
T495Z0 C270Z1 B20Z6
MOV K0 D0Z8
X19Z2
Y40Z3

IXEND

*2: The value of Zn is returned to the previous Zn value before the execution of the IX instruction after the IXEND instruction has
been executed.

1. When using the IX and IXEND instructions in both a normal sequence program and an interrupt sequence program,
establish the interlock to avoid simultaneous execution. The interlock assumes the area between the IX and IXEND
instructions in the normal sequence program as DI, disabling the interruption.
2. The IXDEV and IXSET instructions can be used to specify modification values. Refer to Page 429, Section 7.6.13 for
details.

427
 IX, IXEND

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The IX and IXEND instructions are not used as a pair.
4231 After the IX instruction was executed, the END, FEND, GOEND, or
STOP instruction was executed prior to the IXEND instruction.

Program Example
(1) The following program executes the same ladder 10 times, while changing device numbers.

[Ladder Mode] [List Mode]

Sets modification Step Instruction Device

value

Ladder which
executes index
modification

Changes
modification
value

[Operation]

Modification value 1st time 2nd time 3rd time 10th time
B0 B1 B2 B9
D100 Modification value of T
X10 X11 X12 X19
D101 Modification value of C Y30 Y31 Y32 Y39
D102 Modification value of X M0 M1 M2 M9
D103 Modification value of Y D0 D1 D2 D9
D104 Modification value of M D10 D11 D12 D19
T3 T4 T5 T12
D105 Modification value of L
C4 C5 C6 C13
D106 Modification value of B D40 D41 D42 D49
D107 Modification value of V
D108 Modification value of D

428
 IXDEV, IXSET

7.6.13 IXDEV, IXSET Designation of modification values in index modification

of entire ladders

7.6.13 IXDEV, IXSET Basic High

performance Process Redundant Universal LCPU 1

IXDEV IXDEV
2
IXSET IXSET S D

Dummy contact
3

Offset designation sections 4

S : Head number of the devices where index modification data is stored (pointer only) P (Pointer)
D : Head number of the devices where index modification data will be stored (except a pointer) (BIN 16 bits)
Setting Internal Devices
R, ZR
J \
U \G Zn Constants
Other 4
Data Bit Word Bit Word P
S –– –– ––

D –– –– –– 6

Function
7
(1) The IXDEV and IXSET instructions are used to configure an index modification table used in the IX and IXEND
instructions.
(2) The device offset value designated at the offset designation area is set at the index modification table designated by D . 8
(3) The value 0 will be entered if no designation is made.
(4) Word devices are also indicated by contact (word device bit designation). Data register 10 (D10) is designated with
D10.0.
(Any value from 0 to F can be used for the bit number.)

7.6.13 IXDEV, IXSET

7.6 Structure creation instructions
(5) Designation is made according to the method described below. *1 (The symbol is where the offset value will be. The
notation XX indicates random selection.)
Device T C X Y M L V B
Designation T C X Y M L V B
method
Device D W R U/G J ZR

Designation D .XX W .XX R .XX U \G .XX *2

J \B
method

Device P
Designation *3
IXSET S D
method

*1: When using a basic model QCPU, the devices R, U/G, J, ZR and P cannot be used.
*2: Devices following J \ designate B, W, X, or Y, and the offset value is also set in correspondence with this.
*3: When using a basic model QCPU, specify a dummy device number. S is P .
(6) If two offsets for two identical types of device have been set in the offset designation area, the last value set will be valid.
(7) The IXDEV and IXSET instructions should be treated as a pair.
(8) Any value from 0 to 32767 is valid for ZR. (The offset value will be the remainder of the quotient of the designated device
number divided by 32768.)

429
 IXDEV, IXSET

(9) The dummy contacts in the offset specifying part are valid for only LD and AND located within the range of the IXDEV-
IXSET instructions. The IXDEV-IXSET instructions will not be executed if other instructions are described.

Example

IXDEV
Non-execution processing (outputs OFF)

Non-execution processing (ignored)

Valid dummy contacts INC D50

IXSET P3 D0

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4231 The IXDEV and IXSET instructions are not used as a pair.

Program Example
(1) The following program changes the modification values for input (X), output (Y), data register (D) and pointer (P).
When using a basic model QCPU, the devices R, U/G, J, ZR and P cannot be used.
[Ladder Mode] [List Mode]

Step Instruction Device

Index modification ladder

*

Index modification
table
D0 4 T
0 C
5 X
3 Y
0 M
0 L
0 B
0 V
8 D
0 W
0

0
D15 0 P
*4: Refer to Page 426, Section 7.6.12 for index modification using the IX to IXEND instructions.

430
 FIFW, FIFWP

7.7 Data Table Operation Instructions

1
7.7.1 FIFW, FIFWP Writing data to the data table

7.7.1 FIFW, FIFWP Basic High

performance Process Redundant Universal LCPU
2
Command
FIFW FIFW S D

Command
3
FIFWP FIFWP S D

S : Data to be written into the table or the number of the device where the data is stored (BIN 16 bits) 4
D : Head number of the table (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data K, H
S
Bit Word Bit Word
––
4
D –– –– –– ––

6
Function
(1) Stores the 16-bit data designated by S in the data table designated by D .
7
The number of data blocks stored in the table is stored at D , and the data designated by S is stored in sequence from
D +1.
Data table Data table 8
D 2 Number of stored data blocks D 3
D +1 5432 D +1 5432
D +2 1234 D +2 1234
D +3 0 Data table range D +3 4321
D +4 0 (controlled by the user) D +4 0

7.7.1
7.7 Data Table Operation Instructions
0 0

FIFW, FIFWP
S 4321
(2) The first time the FIFW instruction is executed, any values designated by D device should be cleared.
(3) The number of data blocks to be written in the data table and the data table range should be controlled by the user.
[See Program Example (2)]

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The data table range exceeds the range of the corresponding device at
4101
the execution of the FIFW instruction.

431
 FIFR, FIFRP

Program Example
(1) The following program stores the data at D0 to the data table following R0 when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Table Table
R0 4 Number of stored data blocks R0 5
R1 123 R1 123
R2 55 R2 55
R3 4321 R3 4321
Data table range
R4 11 R4 11
R5 0 R5 257

D0 257
(2) The following program stores the data at X20 to X2F to data table of D38 to D44 table when X1B is turned ON, and, if
there are more than 6 data blocks to be stored, turns Y60 ON and disables the FIFW instruction.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Table Table
D38 5 Number of stored data blocks D38 6
D39 1000 D39 1000
D40 8100 D40 8100
D41 4321 D41 4321
Data table range
D42 1234 D42 1234
D43 123 D43 123
D44 0 D44 4444
D45 0 D45 0

X20 to X2F 4444

7.7.2 FIFR, FIFRP Reading oldest data from tables

7.7.2 FIFR, FIFRP Basic High

performance Process Redundant Universal LCPU

Command
FIFR FIFR S D

Command
FIFRP FIFRP S D

S : Head number of the devices where the data read from the table will be stored (BIN 16 bits)
D : Head number of the table (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S ––

D –– –– ––

432
 FIFR, FIFRP

Function
1
(1) Stores the oldest data ( D +1) input to the table designated by D at the device designated by S .
After the execution of the FIFR instruction, the data in the table is all compressed up by one block.
Data table Data table 2
D 3 Number of stored D 2
5432 data blocks 1234
D +1 D +1
D +2 1234 4321
3
D +2
D +3 4321 D +3 0 Stores 0.
D +4 0 D +4 0

0 0
4
S 5432

(2) Users should attempt to avoid executing the FIFR instruction if the value stored at D is 0. [See Program Example (1)] 4
Operation Error
6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

Error
Error details
Q00J/
Q00/ QnH QnPH QnPRH QnU LCPU
7
code
Q01
4100 The FIFR instruction was executed when the value of was 0.
8
D

The data table range exceeded the range of the corresponding device
4101
at the execution of the FIFR instruction.

Program Example

7.7.2
7.7 Data Table Operation Instructions
(1) The following program stores the R1 data from the table R0 to R7 at D0 when X10 is turned ON.
[Ladder Mode] [List Mode]

FIFR, FIFRP
Step Instruction Device

[Operation]
Data table Data table
R0 5 Number of stored data blocks R0 4 Number of stored data blocks
R1 123 R1 55
R2 55 R2 4321
R3 4321 R3 123
R4 123 R4 234 Data table
R5 234 R5 0
R6 0 R6 0
R7 0 R7 0

D0 123

433
 FPOP, FPOPP

(2) The following program stores the data at D0 in the data table D38 to D43, and, when the table stores 5 data, stores the
data at D39 of the data table in R0, when X1C is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data table Data table Data table
Number of Number of Number of
D38 4 stored D38 5 stored D38 4 stored
data tables data tables data tables
D39 1234 D39 1234 D39 55
D40 55 D40 55 D40 1000 Executes the FIFWP
D41 1000 D41 1000 D41 123 instruction when X1C
Data turns ON again.
D42 123 D42 123 D42 4444
table
D43 0 D43 4444 D43 0
D44 0 D44 0 D44 0
D45 0 D45 0 D45 0

Executes the FIFRP

D0 4444 R0 1234
instruction when D38=5.

7.7.3 FPOP, FPOPP Reading newest data from data tables

7.7.3 FPOP, FPOPP Basic High

performance Process Redundant Universal LCPU

Command
FPOP FPOP S D

Command
FPOPP FPOPP S D

S : Head number of the devices where the data read from the table will be stored (BIN 16 bits)
D : Head number of the table (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S ––

D –– –– ––

Function
(1) Stores the newest data input to the table designated by D at the device designated by S . After the execution of the
FPOP instruction, the device storing the data read by the FPOP instruction is reset to 0.
Data table Data table
D 7 Number of stored D 6
D +1 1234 data blocks D +1 1234
D +2 5432 D +2 5432

-1000 -1000
D +7 -4321 D +7 0 Stores 0.
0 0

S -4321
(2) Perform interlock to avoid executing the FPOP instruction when the value stored at D is 0. [See Program Example (1)]

434
 FPOP, FPOPP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
4100 The FPOP instruction was executed when the value of D was 0.

4101
The data table range exceeded the range of the corresponding device 3
at the execution of the FPOP instruction.

Program Example 4
(1) The following program stores the data stored last in the data table R0 to R7 at D0 when X10 is turned ON.
[Ladder Mode] [List Mode] 4
Step Instruction Device

6
[Operation]
Data table Data table
7
R0 5 R0 4
R1 -123 R1 -123
R2 1400 R2 1400 8
R3 1234 R3 1234
R4 5432 R4 5432
R5 3000 R5 0 Stores 0.
R6 0 R6 0
R7 0 R7 0

7.7.3
7.7 Data Table Operation Instructions
D0 3000

FPOP, FPOPP
(2) The following program stores the data at D0 in the data table D38 to D43 when X1C is turned ON, and when the number
of data stores in the table reaches 5, turns X1D ON, and stores the data stored last in the data table to R0.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data table Data table Data table
D38 4 D38 5 D38 4 Since the number of
D39 1234 D39 1234 D39 1234 stored data block is 4, the
D40 55 X1C: ON D40 55 X1D: ON D40 55 FIFWP instruction is
Data table
D41 1000 D41 1000 D41 1000 executed when XIC turns ON.
range
D42 123 D42 123 D42 123
D43 0 D43 4444 D43 0
D44 0 D44 0 D44 0
D45 0 D45 0 D45 0

Executes the FPOPP

D0 4444 R0 4444
instruction when D38=5.

435
 FDEL, FDELP, FINS, FINSP

7.7.4 FDEL, FDELP Deletion of data from data tables

7.7.4
FINS, FINSP Insertion of data in data tables

FDEL, FDELP, FINS, FINSP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of FDEL/FINS.

Command
FDEL, FINS S D n

Command
FDELP, FINSP P S D n

S : Head number of the devices where data to be inserted is stored (BIN 16 bits)
Head number of the devices where the data to be deleted will be stored (BIN 16 bits)
D : Head number of the table (BIN 16 bits)
n : Location on the table where data is inserted/deleted (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– ––

D –– –– –– ––
n ––

Function
FDEL
(1) Deletes the nth block of data from the data table designated by D , and stores it at the device designated by S .
After the execution of the FDEL instruction, the data in the table following the deleted block is compressed forward by
one block.
Data table Data table
D 4 D 3
D +1 5432 D +1 5432
D +2 3333 D +2 3333
D +3 4444 D +3 1234
D +4 1234 D +4 0 Stores 0.
D +5 0 D +5 0

0 0

If n=3, data
at D +3 is deleted. S 4444

FINS
(1) Inserts the 16-bit data designated by S at the nth block of the data table designated by D .
After the execution of the FINS instruction, the data in the table following the inserted block is all dropped one position.
Data table Data table
D 3 Number of stored D 4
D +1 5432 data blocks D +1 5432
D +2 1234 D +2 4444 Data table range
D +3 123 D +3 1234
D +4 0 D +4 123
D +5 0 D +5 0

0 0

If n=2, data is inserted to D +2.

S 4444

436
 FDEL, FDELP, FINS, FINSP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The FDEL or FINS instruction was executed when n = 0.
4100
The FDEL instruction was executed when the value of D was 0. 3
The Nth position from D is larger than the number of data storage at
the execution of the FDEL instruction.
The Nth position from D is larger than the "number of data storage + 1" 4
at the execution of the FINS instruction.
4101
The value of n in the case of the FDEL, FINS instruction exceeds the
device range of the table .
4
D

The data table range exceededs the range of the corresponding device
at execution of the FDEL or FINS instruction.

6
Program Example
(1) The following program deletes the second data from the table R0 to R7 and stores the deleted data at D0 when X10 is
turned ON. 7
[Ladder Mode] [List Mode]

Step Instruction Device

8

[Operation]

7.7.4
7.7 Data Table Operation Instructions
Data table Data table
R0 5 R0 4
X10: ON
R1 -123 R1 -123

FDEL, FDELP, FINS, FINSP

R2 4444 R2 3210 Data table
Data table R3 R3 range
3210 1234
range
R4 1234 R4 5432
R5 5432 R5 0
R6 0 R6 0
R7 0 R7 0

D0 4444

437
 FDEL, FDELP, FINS, FINSP

(2) The following program inserts the data at D0 into the third position at the table R0 to R7 when X10 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Data table Data table
R0 4 R0 5
X10: ON
R1 1234 R1 1234
R2 4444 R2 4444
R3 -123 R3 -3210
Data table
R4 5000 R4 -123
range
R5 0 R5 5000
R6 0 R6 0
R7 0 R7 0

D0 -3210

438
 FROM, FROMP, DFRO, DFROP

7.8 Buffer memory access instruction

1
7.8.1 FROM, FROMP Reading 1-word data from the intelligent function module
DFRO, DFROP Reading 2-word data from the intelligent function module

7.8.1 FROM, FROMP, DFRO, DFROP Basic High

performance Process Redundant Universal LCPU
2
indicates an instruction symbol of FROM/DFRO.

FROM, DFRO
Command
n1 n2 D n3
3
Command
FROMP, DFROP
4
P n1 n2 D n3

n1 : Head I/O number of an intelligent function module (BIN 16 bits) *1

n2 : Head address of the buffer memory where data to be read is stored (BIN 16 bits)

n3
D : Head number of the devices where the read data will be stored (BIN 16/32 bits)
: Number of data blocks to be read (BIN 16 bits)
4
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H U
n1 6
n2 ––
D –– ––
n3 –– 7
*1: Specified with the upper three digits when the head I/O number is expressed in 4 hexadecimal digits.

8
Function
FROM
(1) Reads the data in n3 words from the buffer memory address designated by n2 of the intelligent function module

7.8.1
7.8 Buffer memory access instruction
designated by n1, and stores the data into the area starting from the device designated by D .

Intelligent function module

FROM, FROMP, DFRO, DFROP

buffer memory Device designated CPU module
by D
n2
n3 words n3 points

DFRO
(1) Reads the data in (n3 2) words from the buffer memory address designated by n2 of the the intelligent function module
designated by n1, and stores the data into the area starting from the device designated by D .

Intelligent function module

buffer memory Device designated CPU module
by D
n2
n2+1
(n3 2) words (n3 2) points

Data read from intelligent function modules is also possible with the use of an intelligent function module device.
For the intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program
Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).

439
 FROM, FROMP, DFRO, DFROP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
An error has been detected in an intelligent function module at the
1402
execution of the instruction.
There has been no exchange of signals with an intelligent function
1412
module at the execution of the instruction.
2110 The I/O number specified in n1 is not for the intelligent function module.
The range of n3 points (2 n3 points for the DFRO) from the device
4101 specified in D exceeds the specified device range.
The address specified in n2 is outside the buffer memory range.

Program Example
(1) The following program reads CH1 digital output value of the Q68ADV at I/O numbers 040 to 04F to D0 when X0 is turned
on (reads data by one word from the buffer memory address 11).
[Ladder Mode] [List Mode]
Step Instruction Device

(2) The following program reads the current feed value of axis 1 of the QD75P4 at I/O numbers 040 to 05F to D0 and D1
when X0 is turned on (reads data by two words from the buffer memory address 800).
[Ladder Mode] [List Mode]
Step Instruction Device

440
 TO, TOP, DTO, DTOP

Remark
1. The value of n1 is specified by the upper 3 digits of hexadecimal 4 digits which represent the head I/O number of an 1
intelligent function module.

QCPU
2
Power
Q68 QY41
supply CPU QX10 QX10 QX10 QX10 QY10 QY10
ADV P
module
3
0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Head I/O number configured in
the I/O assignment setting

Specify K4 or H4 as the head I/O number to be read.

4
LCPU
CPU module
(L26CPU-BT) 4
Power
supply
module
CPU Built-in Built-in LX40
I/0 CC-Link C6
LX40
C6
LX40
C6
L60
AD4
LY41
NT1P
LY10
R2
LY10 LY10
R2 R2 6
0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Head I/O number configured in
the I/O assignment setting
7
Specify K6 or H6 as the head I/O number to be read.

8
2. QCPU and LCPU establishe the automatic interlock of the FROM/DFRO instructions.

7.8.2 TO, TOP Writing 1-word data to the intelligent function module

7.8.2
DTO, DTOP Writing 2-word data to the intelligent function module

TO, TOP, DTO, DTOP High

7.8.2
7.8 Buffer memory access instruction
Basic performance Process Redundant Universal LCPU

TO, TOP, DTO, DTOP

indicates an instruction symbol of TO/DTO.

Command
TO, DTO n1 n2 S n3

Command
TOP, DTOP P n1 n2 S n3

n1 : Head I/O number of an intelligent function module (BIN 16 bits) *1

n2 : Head address of the area where data is written (BIN 16 bits)
S : Data to be written or head number of the devices where the data to be written is stored (BIN 16/32 bits)
n3 : Number of data blocks to be written (BIN 16 bits)
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H U
n1
n2 ––
S –– ––
n3 ––

*1: Specified with the upper three digits when the head I/O number is expressed in 4 hexadecimal digits.

441
 TO, TOP, DTO, DTOP

Function
TO
Writes the data stored in n3 points starting from the device designated by S into the area starting from buffer memory address
designated by n2 of the intelligent function module designated by n1.
Intelligent function module
CPU module buffer memory
Device designated
0
by S

...
n2
n3 points n3 words

When a constant is designated to S , writes the same data (value designated to S ) to the area of n3 words starting from the
specified buffer memory. ( S can be designated in the following range: -32768 to 32767 or 0H to FFFFH.)

Intelligent function module

buffer memory
CPU module 0
S 5
...

(When 5 is designated to S ) n2 5
5 n3 words
5 (The same data is written)

DTO
Writes the data stored in n3 2 points starting from the device designated by S into the area starting from buffer memory
address designated by n2 of the intelligent function module designated by n1.

Intelligent function module

CPU module buffer memory
Device designated
0
by S
...

n2
n2+1
(n3 2) (n3 2)
points words

When a constant is designated to S , writes the same data (value designated to S ) to the area of n3 2 words starting from
the specified buffer memory. ( S can be designated in the following range: -2147483648 to 2147483647 or 0H to
FFFFFFFFH.)

Intelligent function module

buffer memory
CPU module
0
S
...

70000
n2 70000
(When 70000 is designated to S ) n2+1
70000 (n3 2) words
(The same data is written)
70000

Data write to intelligent function modules is also possible with the use of an intelligent function module device.
For the intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program
Fundamentals) or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).

442
 TO, TOP, DTO, DTOP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
An error has been detected in an intelligent function module at the
1402
execution of the instruction. 3
There has been no exchange of signals with an intelligent function
1412
module at the execution of the instruction.
2110 The I/O number specified in n1 is not for the intelligent function module.
The range of n3 points (2 n3 points for the DTO) from the device
4
4101
specified in S exceeds the specified device range.

4
Program Example
(1) The following program sets "A/D conversion disabled" to the CH1 and CH2 of the Q68ADV at I/O numbers 040 to 04F
when X0 is turned on (writes "3" to the buffer memory address 0).
6
[Ladder Mode] [List Mode]

Step Instruction Device 7

(2) The following program zeroes the positioning address/movement amount of axis 1 of the QD75P4 at I/O numbers 040 to
8
05F when X0 is turned on (writes 0 to the buffer memory addresses 2006 and 2007).
[Ladder Mode] [List Mode]
Step Instruction Device

7.8.2
7.8 Buffer memory access instruction
TO, TOP, DTO, DTOP

443
 TO, TOP, DTO, DTOP

Remark
1. The value of n1 is specified by the upper 3 digits of hexadecimal 4 digits which represent the head I/O number of an
intelligent function module.

QCPU

Power
Q68 QY41
supply CPU QX10 QX10 QX10 QX10 QY10 QY10
ADV P
module

0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Head I/O number configured in
the I/O assignment setting
Specify K4 or H4 as the head I/O number to be written.

LCPU
CPU module
(L26CPU-BT)

Power
supply CPU Built-in Built-in LX40 LX40 LX40 L60 LY41 LY10 LY10 LY10
module I/0 CC-Link C6 C6 C6 AD4 NT1P R2 R2 R2

0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Head I/O number configured in
the I/O assignment setting

Specify K6 or H6 as the head I/O number to be written.

2. QCPU and LCPU establishe the automatic interlock of the TO/DTO instructions.

444
 PR

7.9 Display instructions

1
7.9.1 PR Print ASCII code

7.9.1 PR Basic High

performance Process Redundant Universal LCPU 2
Command
PR PR S D
3
S : ASCII code or head number of the devices where the ASCII code is stored (character string)
D : Head number of the output module to which the ASCII code will be output (bits)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other
4
Data Bit Word Bit Word $

S –– *1 –– ––

D (Only Y) –– –– –– –– 4
*1: Local devices and the file registers set for individual programs cannot be used.

Function 6
(1) Outputs ASCII code stored in the device specified by S or ASCII code stored in the area startings from the device
number to an output module specified by D . 7
The number of characters output differs according to the ON/OFF status of SM701
(number of output characters selection).
(a) If SM701 is ON, characters 8 points (16 characters) from the device designated by S will be the target of the 8
operation.
Device where ASCII code is stored

Upper 8 bits Lower 8 bits

7.9.1
7.9 Display instructions
b15 b8 b7 b0 Output Y
S +0 42 H (B) 41 H (A) Head of output D
S +1 44 H (D) 43 H (C)

PR
50 H
4F H
4EH
4DH
4CH
4BH
4AH
49 H
48 H
47 H
46 H
45 H
44 H
43 H
42 H
41 H

S +2 46 H (F) 45 H (E)
S +3 48 H (H) 47 H (G)
S +4 4A H (J) 49 H (I)
S +5 ASCII code output
4CH (L) 4B H (K)
Printer or
S +6 4E H (N) 4DH (M)
S +7 display device
50 H (P) 4F H (O) D +7
D +8
Strobe signal output
Sequence D +9
Flag indicating PR
program instruction in execution

Used as interlock

445
 PR

(b) If SM701 is OFF, everything from the device designated by S to the 00H code will be the target of the operation.

Device where ASCII code is stored

Upper 8 bits Lower 8 bits

b15 b8 b7 b0 Output Y
S +0 42 H (B) 41 H (A) Head of output D
S +1 44 H (D) 43 H (C)

4CH
4B H
4A H
49 H
48 H
47 H
46 H
45 H
44 H
43 H
42 H
41 H
S +2 46 H (F) 45 H (E)
S +3 48 H (H) 47 H (G)
S +4 4A H (J) 49 H (I)
ASCII code output
S +5 4C H (L) 4B H (K)
Scheduled Printer or
S +6 4E H (N) 00 H (NULL) completion display device
S +7 50 H (P) 4F H (O) D +7
D +8
Sequence program Strobe signal output
D +9
Flag indicating PR
instruction in execution
Used as interlock

(2) The number of points used by the output module is 10 points from the Y address designated by D .
(3) Output signals from the output module are transmitted at the rate of 30 ms per character.
For this reason, the time required to the completion of the transmission of the designated number of characters (n) will be
30 ms n (ms).
At 10 ms interrupt intervals, the PR instruction executes data output, strobe signal ON, and strobe signal OFF. The other
instructions are executed continuously during a period between the above processings.
Execution of sequence program PR instruction processing

Data output

ON
OFF
Strobe signal

10 ms 10 ms 10 ms 10 ms 10 ms

30 ms

(4) In addition to the ASCII code, the output module also outputs a strobe signal (10 ms ON, 20 ms OFF) from the D +8
device.
(5) Following the execution of the PR instruction, the PR instruction execution flag ( D + 9 device) remains ON until the
completion of the transmission of the designated number of characters.
(6) The PR and PRC instructions can be used multiple times, but it is preferable to establish an interlock with the PR
instruction execution flag ( D + 9 device) so that they will not be ON simultaneously.
(7) If the contents of the device in which ASCII codes are stored changes during the ASCII code output, the modified data
after change will be output.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When SM701 is OFF, there is no 00H code within the device range
4101 –– –– –– ––
specified in S .

446
 PR

Program Example
1
(1) The following program converts the string "ABCDEFGHIJKLMNOP" to ASCII code when X0 is turned ON and stores it
from D0 to D7, and then outputs the ASCII code at D0 to D7 to Y14 to Y1D when X3 is turned ON (when SM701 is OFF).
[Ladder Mode] 2

When X0 turns ON, converts "ABCDEFGHIJKLMOP"

to the ASCII code and stores it to D to D7. 3

4
When X3 turns ON, outputs the ASCII code in D0 to D7
to Y14 to Y1D. (Y1C is used for a strobe signal, and Y1D
is used for the PR instruction execution flag.)
4
[List Mode]
6

[Timing Chart] 8
ON
OFF
X0
$MOV "ABCDEFGH" D0

7.9.1
7.9 Display instructions
Stores the ASCII
code for "A" to "H"
$MOV "IJKLMNOP" D4 to D0 to D3.

PR
Stores the ASCII code for
"I" to "P" to D4 to D7.
X3

A B P
Y14
ASCII code 41H 42H 50H
Y1B
10 10
10 ms ms ms
10 ms
PR instruction
OFF
Strobe signal Y1C
ON
OFF
PR instruction in PR instruction in execution 480 ms
execution flag Y1D

447
 PRC

7.9.2 PRC Print comment

7.9.2 PRC Basic High

performance Process Redundant Universal LCPU

Command
PRC PRC S D

S : Head number of the device which prints the comment (Device name)
D : Head number of the output module which outputs the comment (bits)

Setting Internal Devices J \ Other

R, ZR U \G Zn Constants
Data Bit Word Bit Word P, I, J, U
S –– ––
D (Only Y) –– –– –– –– ––

Function
(1) Outputs comment (ASCII code) at device designated by S to output module designated by D .
The number of characters output differs according to the ON/OFF status of SM701.
• When SM701 is OFF: Comment is 32 characters
• When SM701 is ON : Comment is the upper 16 characters
The number of points used by the output module is 10 points from the Y address designated by D .

PRC X1 Y30

Comment at X1
Output Y
A B C D E F G H I K K L M n O
Y30
Head of output

ASCII code output

Printer or
display device
Y37
Y38
Strobe signal output
Sequence Y39
program Flag indicating PRC
instruction in execution
Used as interlock

448
 PRC

[Timing Chart]
A B C n O
Y30 to Y37 Preprocessing 41H 42H 43H 4EH 4FH 1
(several scans) 30 ms
ON

PRC
OFF
2
ON
Y38 OFF
(Strobe signal) 10 10 10 3
ms ms ms
ON
Y39 OFF
(Flag indicating strobe
signal is being output)
30ms x 16 = 480 ms
4
ON
SM721 OFF
(File access in
progress flag)
ON PRC instruction cannot be executed again. 4
SM720 OFF
(File access
completion flag) None of
instructions can
Instructions other than PRC instruction (SP.FREAD,
SP.FWRITE, PUNROAD, PLOAD, PSWAPP) can be executed.
6
be executed.

(2) Output signals from the output module are transmitted at the rate of 30 ms per character.
For this reason, the time required to the completion of the transmission of the designated number of characters will be 30
7
ms n (ms).
At 10ms interrupt intervals, the PRC instruction executes data output, strobe signal ON, and strobe signal OFF. The
other instructions are executed continuously during a period between the above processings.
8
Execution of sequence program Processing of PRC instruction

7.9.2
7.9 Display instructions
Data output

PRC
ON
OFF
Strobe signal

10 ms 10 ms 10 ms 10 ms 10 ms

30 ms

(3) In addition to the ASCII code, the output module also outputs a strobe signal (10 ms ON, 20 ms OFF) from the D +8
device.
(4) Following the execution of the PRC instruction, the PRC instruction execution flag ( D + 9 device) remains ON until the
completion of the transmission of the designated number of characters.
(5) The PRC instruction can be used multiple times, but it is preferable to establish an interlock with the PRC instruction
execution flag ( D + 9 device) so that they will not be ON simultaneously.
(6) If no comments have been registered at the device designated by S , processing will not be performed.

449
 PRC

(7) When a comment is read, SM720 turns ON for one scan after the instruction is completed.
SM721 turns ON during the execution of the instruction.
The PRC instruction cannot be executed while SM721 is ON. If the attempt is made, no processing is performed.

1. For device comments used with the PRC instruction, use comment files stored in the standard ROM or memory card.
Comment files stored in the program memory cannot be used.
2. The comment file used by the PRC instruction is set at the "PLC File Setting" option in the PLC parameter dialog box.
If no comment file has been set for use by the PLC file setting, it will not be possible to output device comments with the
PRC instruction.
3. Do not execute the PRC instruction during an interrupt program.
Otherwise, malfunction may occur.
4. If a device which is not set a comment is specified, an error occurs. However, when the comment range for the device is
set in the "Device Comment Detail Setting" of the "Online Data Operation" window using a programming tool, the error
does not occur even if the comment is not set within the setting range.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The PRC instruction is executed while a comment is written during
–– –– –– ––
RUN.
4100
A device which is not set a comment is specified and the PRC
–– –– –– ––
instruction is executed.

Program Example
(1) Program which outputs the comment of Y60 to Y30 to Y39 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

450
 LEDR

7.9.3 LEDR Error display and annunciator reset

7.9.3 LEDR Basic High

performance Process Redundant Universal LCPU 1
Command
LEDR LEDR
2
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data
––
Bit Word Bit Word
––
3

Function 4
Resets the self-diagnosis error display so that annunciator display or operation can be continued.
With one execution of this instruction, either error display or annunciator is reset.
(1) Operation when self-diagnosis error is generated 4
(a) If the self-diagnosis error is one which allows continued operation.
If there is an indication of the self-diagnosis error which the CPU module can continue the operation, reset the
"ERR." LED in front of the CPU module. It will be necessary to reset SM0, SM1, and SD0 at the user program, 6
because they are not reset automatically.
Since the cause of the error displayed at this time has a higher priority over annunciator, no action for resetting the
annunciator is taken. 7
(b) When a battery error is generated.
If the LEDR instruction is executed after the battery is changed, the "BAT." LED in front of the CPU module is reset.
SM51 is also turned OFF at this time. 8
(2) Operations when an annunciator (F) is ON.
When the LEDR instruction is executed, the following operations are performed.
1) "USER" LED flickers, and is turned OFF

7.9.3
7.9 Display instructions
2) The annunciators (F) stored in SD62 and SD64 are reset, and the F numbers for SD65 to SD79 are moved up.
3) The data newly stored at SD64 is transmitted to SD62.

LEDR
4) The data at SD63 is decremented by -1. However, if SD63 is 0, it remains 0.
Before execution After execution
SD62 200 SD62 99
Decrements 1.
SD63 15 SD63 14 Number of registered F numbers
SD64 200 SD64 99
SD65 99 SD65 5
SD66 5 SD66 255
SD67 255
F number storage area

SD77 83
SD78 83 SD78 0
SD79 0 SD79 0

451
 LEDR

Remark
1. The defaults for the error item numbers set in special registers SD207 to SD209 and order of priority are given in the table
below:
Factor number
Priority Meaning Remarks
(Hexadecimal)
AC DOWN Power supply cut
1 1 SINGLE PS.DOWN Redundant base unit power supply voltage drop (QCPU only)
SINGLE PS.ERROR Redundant power supply module fault (QCPU only)
I/O module verify error (QCPU only)
UNIT VERIFY ERR.
Blown fuse (QCPU only)
FUSE BREAK OFF
2 2 Special function module verify error (QCPU only)
SP. UNIT ERROR
Intelligent function module verification error
SP. UNIT DOWN
Intelligent function module error (LCPU only)
OPERATION ERROR [Operation Errors]
LINK PARA.ERROR Link parameter error (QCPU only)
SFCP OPE. ERROR SFC instruction operation error (QCPU only)
3 3
SFCP EXE. ERROR SFC program execution error (QCPU only)
REMOTE PASS.FAIL Remote password error (LCPU only)
SNTP OPE.ERROR SNTP error (LCPU only)
ICM.OPE ERROR Memory card operation error
FILE OPE. ERROR File access error
EXTEND INST. ERROR Extend instruction error (QCPU only)
OPE. MODE DIFF. Operation status, switch mismatch (QCPU only)
4 4 CAN'T EXE.MODE Current mode-time function execution disabled (QCPU only)
TRK.TRANS.ERR. Tracking data transmission error (QCPU only)
TRK.SIZE ERROR Tracking capacity excess error (QCPU only)
TRK.DISCONNECT Tracking cable not connected, failure (QCPU only)
FLASH ROM ERROR Flash ROM access count exceeded error (LCPU only)
Constant scan setting time over error
5 5 PRG.TIME OVER
Low speed execution monitoring tome over error (QCPU only)
6 6 CHK instruction ––
7 7 Annunciators ––
8 8 LED instruction ––
9 9 BATTERY ERR. ––
10 A Clock data ––
CAN'T SWITCH System switching error (QCPU only)
11 B STANDBY SYS.DOWN Standby system not started/stop error (QCPU only)
MEM.COPY EXE. Memory copy function executed (QCPU only)
12 C DISPLAY ERROR Display unit error (LCPU only)

2. If the highest priority is given to the annunciator, it can be reset with priority by the LEDR instruction. (Basic model QCPU,
High Performance model QCPU, Process CPU, and Redundant CPU)

452
 CHKST, CHK

7.10 Debugging and failure diagnosis instructions

1
7.10.1 CHKST, CHK Special format failure check

7.10.1 CHKST, CHK Basic High

performance Process Redundant Universal LCPU 2
Command
CHKST CHKST
3
X X X X
CHK CHK

Check condition (Only a contact is valid; b contact is ignored)

Only input (X) can be used 4
Up to 150 contacts can be connected

Setting Internal Devices

R, ZR
J \
U \G Zn Constants Other
4
Data Bit Word Bit Word
–– ––

6
Function
CHKST 7
(1) The CHKST instruction is the instruction that starts the CHK instruction.
If the command for the CHKST instruction is OFF, execution jumps from the CHK instruction to the next instruction.
If the command for the CHKST instruction is ON, the CHK instruction is executed. 8
TO
CHKST

X0 X2
When T0 is OFF,
CHK

7.10.1 CHKST, CHK

7.10 Debugging and failure diagnosis instructions
program jumps to the
instruction next to the
CHK instruction. Y10

CHK
(1) The CHK instruction is the instruction used for the bidirectional operation as shown on the following page to confirm the
nature of the system failure.
(a) When the CHK instruction is executed, a failure diagnosis check is conducted with the designated check conditions,
and if a failure is detected, SM80 is turned ON, and the failure number is stored at SD80 as a BCD value.
The error code "9010" will be returned if a failure is detected.
The contact number where the failure was discovered is stored at the upper 3 digits of SD80 (see Page 455,
Section 7.10.1 (3)), and the coil number where the failure was detected (see Page 455, Section 7.10.1 (2)) is stored
at the lower 1 digit of SD80.
At the detection of failure of
Contact No.: 62, Coil No.: 3
Before the detection of failure After the detection of failure
SM80 OFF SM80 ON
SD80 0 0 0 0 SD80 0 6 2 3

453
 CHKST, CHK

(b) The contact instruction prior to the CHK instruction does not control the execution of the CHK instruction, but rather
sets the check conditions.
Advance command (X4)
Advance operation
(Y50)
Advance

M Retract operation
(Y51)
Retract
Advance end sensor (X0) Retract end sensor (X1)
turns ON at the detection turns ON at the detection
Retract command (X5)
(c) A ladder such as the one shown below can be created to perform a cycle time over check for the system shown
above:
T0 When T0 is OFF, program jumps to the instruction
CHKST next to the CHK instruction.
X000 Executes CHK instruction when T0 is ON.
CHK
X004 X005 X000
Y050 Advances conveyor 1.
Y050
SET Y000 Turns ON the internal relay used for failure detection.
X005 X004 X001
Y051 Retracts conveyor 1.
Y051
RST Y000 Turns OFF the internal relay used for failure detection.
Y050 X000 K100
T0 Cycle time
Y051 X001 check timer

(d) The following points should be taken into consideration when creating a ladder for use with the CHK instruction:
1) The contact numbers for the advance edge detection sensor and the retract edge detection sensor (X ) must
always be continuous. Further, the contact number (X ) for the advance edge detection sensor should be
lower than that for the retract edge.
2) Controls for the advance edge detection sensor contact number (X ) and output with the identical number
(Y ) *1 are as follows:
When advance operation is in progress.....turn ON
When retract operation is in progress.........turn OFF
*1: Output (Y ) is treated as an internal relay, and cannot be output to an external device.

454
 CHKST, CHK

(2) Depending on the designated contact, the CHK instruction undergoes processing identical to that shown for the ladder
below:
TO
CHKST
1
X X
CHK (Detection by both advance and retraction end sensors
Max. 150 contacts
X
during advance operation of the conveyor)
X +1 Y
2
Coil No. 1 SET SM80

MOV Failure No. 1 SD80

(Detection by both advance and retraction end sensors
during retract operation of the conveyor)
3
Example X X0
X +1 X1 X X +1 Y
Y Y0 Coil No. 2 SET SM80

Executes the same processing MOV Failure No. 2 SD80 4

as the ladder indicated above (Advance operation of the conveyor at the detection
by the advance end sensor)
X Y
SET SM80
4
Coil No. 3

MOV Failure No. 3 SD80

(Retract operation of the conveyor at the detection
by the retraction end sensor)

Coil No. 4
Y X +1
SET SM80 6
MOV Failure No. 4 SD80
(Advance operation of the conveyor during no detection
Y
by the retraction end sensor)
X +1
7
Coil No. 5 SET SM80

MOV Failure No. 5 SD80

(Retract operation of the conveyer at the detection
by the advance end sensor)
8
Y X
Coil No. 6 SET SM80

MOV Failure No. 6 SD80

7.10.1 CHKST, CHK

7.10 Debugging and failure diagnosis instructions
(3) Numbers 1 to 150 from the vertical bus on the left side have been allocated as contact numbers during failure detection.
X5 X7 X9 X1A X1C
CHK

Contact No. 1 2 3 149 150

(4) Reset SM80 and SD80 prior to forcing the execution of the CHK instruction.
After the execution of the CHK instruction, it cannot be performed once again until SM80 and SD80 have been reset.
(The contents of SM80 and SD80 will be preserved until reset by user.)
(5) A CHKST instruction must be placed before the CHK instruction.
An error will be returned if an instruction other than the LD, LDI, AND or ANI instruction is used between the CHK
instruction and the CHKST instruction.
(Error code: 4235)
(6) The CHK instruction can be written at any step of the program.
However, there is a limit in the number of uses of the CHK instruction.
• Can be used up to two places in all program files being executed.
• Can be used only one place in a single program file.
An error will be returned if the CHK instruction is used exceeding the number of uses specified above.
(Error code: 4235)

455
 CHKST, CHK

(7) Place LD and AND instructions prior to the CHK instruction to establish a check condition.
Check conditions cannot be set using other contact instructions.
If a check condition has been set with LDI or ANI, the processing for the check condition they specify will not be
conducted.
However, contact numbers during failure detection can also be allocated to the LDI and ANI instructions.
Does not execute check

X5 X7 X9 XA X1A X1C
CHK

Contact No. 1 2 3 4
Contact numbers are allocated
(8) The failure detection method differs according to whether SM710 is ON or OFF.
(a) If SM710 is OFF, checks will be conducted of coil numbers 1 to 6 for each contact successively.
When the CHK instruction is executed, checks will be in order from coil No. 1 of contact No. 1, through coil No. 6,
then move on to contact No. 2 and check the coils in order from No. 1.
The CHK instruction will be completed when coil No. 6 from contact No. n has been checked.
(b) If SM710 is ON, checks will be conducted of contact numbers 1 through n, in coil number order.
When the CHK instruction is executed, checks will begin with the ladder for coil No. 1, in order from contact No. 1
until contact No. n, then move on to the coil No. 2 ladder and begin from contact No. 1.
The CHK instruction will be completed when a check has been made through contact No. n of coil No. 6.
(9) If more than one failure is detected, the number of the first failure detected will be stored.
Failure numbers detected after this will be ignored.
(10) The CHK instruction cannot be used by a low speed execution type program.
If a low speed execution type program has been set in a program file containing the CHK instruction, an operation error
will be returned, and the CPU module operation will be suspended.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
There is a parallel ladder.
There is an NOP instruction.
There are more than 150 contact instructions.
A CHK instruction is not executed after the CHKST instruction.
The CHK instruction is executed when no CHKST instruction has been
executed.
4235 The CHKST and CHK instruction are used in a low speed execution –– –– ––
type program.
There is an instruction other than the LD, LDI, AND or ANI instruction
between the CHK instruction and the CHKST instruction.
The CHK instruction is used on three or more points in all of the
program files being executed.
The CHK instruction is used on two more points a single program file.

456
 CHKCIR, CHKEND

7.10.2 CHKCIR, CHKEND Changing check format of CHK

7.10.2 CHKCIR, CHKEND Basic High

performance Process Redundant Universal LCPU 1
When the GX Developer is used (High Performance model QCPU/Process CPU/Redundant CPU)
2
Command
CHKST CHKST Refer to
Page 453,
X X X X Section 7.10.1. 3
CHK CHK

SM400
CHKCIR CHKCIR
4
Fn

Ladder pattern to be checked Fn Max. 9 coils

4

Fn
6
SM400
CHKEND CHKEND

7
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– ––
8
Function
CHKCIR, CHKEND
(1) The check ladder pattern that will be used in the CHK instruction can be updated to any format desired.

7.10.2 CHKCIR, CHKEND

7.10 Debugging and failure diagnosis instructions
The actual failure checks are conducted with the CHKST and CHK instructions.
(2) Failure checks are conducted according to the check conditions designated by the CHK instruction and the ladder
pattern described between the CHKCIR and CHKEND instructions.

Remark
Refer to Page 453, Section 7.10.1 for more information on the CHKST and CHK instructions.

To change the check format of the CHK instruction using the CHKCIR to CHKEND instructions, the user should create a
ladder with index modification (Z0).

(a) The device numbers indicated at check conditions (X2 and X8 in the figure below) will assume index modification
values for the individual device numbers (with the exception of annunciators (F)) described in the ladder patterns.
Example X10 in the in the figure below would be as follows:

When corresponding to check condition X2 Processing performed by.....X12

When corresponding to check condition X8 Processing performed by.....X18

However, the order in which failure detection is executed differs depending on whether SM710 is ON or OFF.

457
 CHKCIR, CHKEND

1) If SM710 is OFF, checks will be conducted of coil numbers 1 through the end for each contact successively.
[Ladder designated by CHKCIR to CHKEND] [Order of check by CPU module]
X12 X14 Y42 X8
CHKST F0

X2 X8 XA
CHK F1
Ladder
SM400 Y60 X23 Y48 X1C equivalent to X2
CHKCIR F2

X10Z0 X12Z0 Y40Z0 X6Z0 Y61 X24

F0

X8Z0 X18 X1A Y48 XE

F1 F0

Y5EZ0 X21Z0 Y46Z0 X1AZ0 X10

F2 F1
Ladder
Y5FZ0 X22Z0 Y66 X29 Y4E X22 equivalent to X8
F2

SM400 Y67 X2A

CHKEND

2) If SM710 is ON, checks will be conducted of contact numbers 1 through the end, in coil number order.
[Ladder designated by CHKCIR to CHKEND] [Order of check by CPU module]
X12 X14 Y42 X8
CHKST F0

X2 X8 X18 X1A Y48 XE

CHK F0

SM400 X12 X14 XA

CHKCIR F1

X10Z0 X12Z0 Y40Z0 X6Z0 Y18 X1A X10

F0 F1

X8Z0 Y60 X23 Y48 X1C

F1 F2

Y5EZ0 X21 Z0 Y46Z0 X1AZ0 X61 X24

F2

Y5FZ0 X22Z0 Y66 X29 Y4E X22

F2

SM400 Y67 X2A

CHKEND

(b) Failure checks check the ON/OFF status of OUT F by using the ladder pattern in the various check conditions.

In all check conditions, SM80 will be turned ON if even one of the OUT F is ON in a ladder pattern.

Further, the error numbers (contact numbers and coil numbers) corresponding to the OUT F which were found to
be ON will be stored from SD80 in BCD order.
(c) The instructions that can be used in ladder patterns are as follows:
Contacts......LD, LDI, AND, ANI, OR, ORI, ANB, ORB, MPS, MPP, MRD, and comparative operation instructions

Coil..............OUT F
(d) The following devices can be used for ladder pattern contacts:
Input (X), Output (Y)
(e) Only annunciators (F) can be used in ladder pattern coils.
However, since annunciators (F) are used as a dummy, any value can be set for an annunciator (F).
Further, they can overlap with no difficulties.
(f) ON/OFF controls can be performed without error if an annunciator (F) used during the execution of the CHK
instruction has the same number as an annunciator (F) used in some other context than the CHK instruction. They
will be treated differently during the CHK instruction than they are in the different context.

458
 CHKCIR, CHKEND

(g) The annunciators (F) used in the CHK instruction do not actually turn ON/OFF. Even when they are monitored from
an external device, the ON/OFF status cannot be checked.
(h) A ladder pattern can be created up to 256 steps. 1
Further, OUT F can use up to 9 coils.
(3) Coil numbers for ladders designated with the CHKCIR through CHKEND instructions are allocated coil numbers from 1
to 9, from top to bottom. 2
SM400
CHKCIR
3
F
Coil No. 1
4
F
Coil No. 2

F
to 4
Coil No. 8

F 6
Coil No. 9
SM400
CHKEND

(4) The CHKCIR and CHKEND instructions can be written at any step in the program desired. 7
It can be used in up to two locations in all program files being executed.
However, the CHKCIR and CHKEND instructions cannot be used in more than 1 location in a single program file.
(5) The CHKCIR and CHKEND instructions cannot be used in low speed execution type programs.
8
If a program file in which the CHKCIR or CHKEND instruction is described is set as a low speed execution type program,
an operation error will occur, and the High Performance model QCPU/Process CPU/Redundant CPU operation will be
suspended.

7.10.2 CHKCIR, CHKEND

7.10 Debugging and failure diagnosis instructions
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The CHKEND instruction is not executed after the CHKCIR instruction.
4230 The CHKEND instruction is executed when no CHKCIR instruction has –– –– ––
been executed.
The CHKCIR or CHKEND instruction appears three or more times in all
program files.
The CHKCIR or CHKEND instruction appears two or more times in a
single program file.
The CHKST and CHK instruction are used in a low speed execution
4235 type program. –– –– ––
There are 10 or more F instances in a ladder pattern.
The ladder pattern has 257 or more steps.
The device has been encountered which cannot be used in a ladder
pattern.
Index modification has been conducted on the ladder pattern device.

459
 BINDA, BINDAP, DBINDA, DBINDAP

7.11 Character string processing instructions

7.11.1 BINDA, BINDAP Conversion from BIN 16-bit data to decimal ASCII
DBINDA, DBINDAP Conversion from BIN 32-bit data to decimal ASCII

7.11.1 BINDA, BINDAP, DBINDA, DBINDAP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of BINDA/DBINDA.

Command
BINDA, DBINDA S D

Command
BINDAP, DBINDAP P S D

S : BIN data to be converted to ASCII (BIN 16/32 bits)

D : Head number of the devices where the conversion result will be stored (character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– –– ––

Function
BINDA
(1) Converts the individual digit numbers of decimal notation of the BIN 16-bit data designated by S into ASCII codes, and
stores the results into the area starting from the device designated by D .
b15 b8 b7 b0
D ASCII code for ten-thousands place Sign
b15 b0
D +1 ASCII code for hundreds place ASCII code for thousands place
S
D +2 ASCII code for units place ASCII code for tens place
BIN 16-bit data D +3 0 Only when
SM701 is OFF

For example, if -12345 has been designated at S , the following will be stored from D onward:
b15 b8 b7 b0
D 31H (1) 2DH ( )
b15 b0
D +1 33H (3) 32H (2)
S 1 2 3 4 5
D +2 35H (5) 34H (4)
D +3 00H

(2) The BIN data designated at S can be in the range from -32768 to 32767.
(3) The operation results stored at D are as follows:
(a) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored if it is negative.
(b) The sign "20H" will be stored for the leading zeros of effective digits. (Zero suppression is conducted.)
00325
Number of significant digits
20H is set
(c) The storage of data at devices specified by D +3 differs depending on the ON/OFF status of SM701 (output number
of characters conversion signal).
When SM701 is OFF.....Stores "0"
When SM701 is ON ......Does not change

460
 BINDA, BINDAP, DBINDA, DBINDAP

DBINDA
(1) Converts the individual digit numbers of decimal notation of the BIN 32-bit data designated by into ASCII codes, and
1
S

stores the results into the area starting from the device designated by D .
b15 b8b7 b0
D ASCII code for billions place Sign
S +1 S
D +1 ASCII code for ten-millions place ASCII code for hundred-mil ions place 2
D +2 ASCII code for hundred-thousands place ASCII code for millions place
Upper 16 bits Lower 16 bits
D +3 ASCII code for thousands place ASCII code for ten-thousands place
BIN 32-bit data D
D
+4 ASCII code for tens place
+5 0 or 20 H
ASCII code for hundreds place
ASCII code for units place
3
When SM701 is OFF 0
When SM701 is ON 20 H
For example, if the value -12345678 has been designated by S , the following would be stored into the area starting from 4
D :
b15 b8b7 b0
D 20H (space) 2D H ( ) 4
D +1 31H (1) 20 H (space)
S +1 S
D +2 33H (3) 32 H (2)
12 3 4 5 6 7 8
D
D
+3
+4
35H (5)
37H (7)
34 H (4)
36 H (6)
6
D +4 0 or 20 H 38 H (8)

(2) BIN data designated by can be between -2147483648 to 2147483647.

7
S

(3) The operations results stored at D will be stored in the following way:
(a) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored if it is negative.
(b) The sign "20H" will be stored for the leading zeros of effective digits. (Zero suppression is conducted.) 8
0012034560
20H Number of significant digits

(c) The data stored at the upper 8 bits of the device designated by D +5 differs depending on the ON/OFF status of
SM701 (number of characters to output select signal).

7.11.1 BINDA, BINDAP, DBINDA, DBINDAP

7.11 Character string processing instructions
When SM701 is OFF.....Stores "0"
When SM701 is ON..... Stores "20H"

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The range of the device specified in D exceeds the range of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following example program uses the PR instruction to output the 16-bit BIN data W0 value by decimal to Y40 to Y48
as ASCII.
[Ladder Mode] [List Mode]

Step Instruction Device

461
 BINHA, BINHAP, DBINHA, DBINHAP

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, the PR instruction will output ASCII code until 00H is encountered.

b15 b8 b7 b0
D0 20 H(space) 20 H(space)
W0 PR
D1 31 H (1) 35 H (5)
5126 Y40 to Y48
D2 36 H (6) 32 H (2)
BIN value
D3 00 H is output.
(2) The following program uses the PR instruction to output the decimal value of the 32-bit BIN data at W10 and W11 in
ASCII code to Y40 to Y48.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, the PR instruction will output ASCII code until 00H is encountered.

b15 b8 b7 b0
D0 20 H (space) 2D H ( )
PR
D1 20 H (space) 20 H (space)
W11 W10 Y40 to Y48
D2 38 H (8) 33 H (3) - 3842563
3 8 4 2 5 6 3
D3 32 H (2) 34 H (4) is output.
BIN value
D4 36 H (6) 35 H (5)
D5 00 H 33 H (3)

7.11.2 BINHA, BINHAP Conversion from BIN 16-bit data to hexadecimal ASCII
DBINHA, DBINHAP Conversion from BIN 32-bit data to hexadecimal ASCII

7.11.2 BINHA, BINHAP, DBINHA, DBINHAP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of BINHA/DBINHA.

Command
BINHA, DBINHA S D

Command
BINHAP, DBINHAP P S D

S : BIN data to be converted to ASCII (BIN 16/32 bits)

D : Head number of the devices where the conversion result will be stored (character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––
D –– –– ––

462
 BINHA, BINHAP, DBINHA, DBINHAP

Function
1
BINHA
(1) Converts the individual digit numbers of hexadecimal notation of the BIN 16-bit data designated by S into ASCII codes,
and stores the results into the area starting from the device designated by D . 2
b15 b8b7 b0
b15 b0 D ASCII code for the 3rd digit ASCII code for the 4th digit
S D +1 ASCII code for the 1st digit ASCII code for the 2nd digit
D +2 0 Only when 3
BIN 16-bit data SM701 is OFF
For example, if 02A6H has been designated by S , it will be stored as follows: D
b15 b8 b7 b0 4
b15 b0 D 32H (2) 30H (0)
S 02A6H D +1 36H (6) 41H (A)
D +2 00H
4
(2) The BIN data designated by S can be in the range from 0H to FFFFH.

(3) The operation results stored at D are processed as 4-digit hexadecimal values.
For this reason, zeros which are significant digits on the left side of the value are processed as "0". (No zero suppression 6
is conducted.)
(4) The data to be stored at the device designated by D +2 differs depending on the ON/OFF status of SM701 (number of
characters to output select signal). 7
When SM701 is OFF.....Stores "0"
When SM701 is ON......Does not change
8
DBINHA
(1) Converts the individual digit numbers of hexadecimal notation of the BIN 32-bit data designated by S into ASCII codes,
and stores the results into the area starting from the device designated by D .
b15 b8b7 b0

7.11.2 BINHA, BINHAP, DBINHA, DBINHAP

7.11 Character string processing instructions
D ASCII code for the 7th digit ASCII code for the 8th digit
S +1 S D +1 ASCII code for the 5th digit ASCII code for the 6th digit
D +2 ASCII code for the 3rd digit ASCII code for the 4th digit
Upper 16 bits Lower 16 bits
D +3 ASCII code for the 1st digit ASCII code for the 2nd digit
BIN 32-bit data D +4 0 (Only when
SM701 is OFF)
For example, if the value 03AC625EH has been designated by S , it would be stored following D in the following manner:
b15 b8 b7 b0
D 33H (3) 30H (0)
D +1 43H (C) 41H (A)
S +1 S
D +2 32H (2) 36H (6)
0 3 A C 6 2 5EH
D +3 45H (E) 35H (5)
D +4 00H

(2) The BIN data designated by S can be in the range from 0H to FFFFFFFFH.

(3) The operation results stored at D are processed as 8-digit hexadecimal values.
For this reason, zeros which are significant digits on the left side of the value are processed as "0". (No zero suppression
is conducted.)
(4) The data to be stored at the device designated by D +2 differs depending on the ON/OFF status of SM701 (number of
characters to output select signal).
When SM701 is OFF.....Stores "0"
When SM701 is ON......Does not change

463
 BINHA, BINHAP, DBINHA, DBINHAP

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The range of the device specified in D exceeds the range of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program uses the PR instruction to output the hexadecimal value of the 16-bit BIN data at W0 in ASCII
code to Y40 to Y48.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.

b15 b8b7 b0
W0 D0 43H (C) 39H (9) PR
9C06 H D1 36H (6) 30H (0) Y40 to Y48
BIN value D2 00H Outputs "9C06"

(2) The following program uses the PR instruction to output the hexadecimal value of the 32-bit BIN data at W10 and W11 to
Y40 to Y48.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.

b15 b8b7 b0
D0 42H (B) 37H (7)
W11 W10 D1 43H (C) 33H (3) PR
7 B 3 C 5 8 1 FH D2 38H (8) 35H (5) Y40 to Y48
D3 46H (F) 31H (1) Outputs "7B3C581F"
D4 00H

464
 BCDDA, BCDDAP, DBCDDA, DBCDDAP
7.11.3 BCDDA, BCDDAP Conversion from BCD 4-digit data to decimal ASCII data

7.11.3
DBCDDA, DBCDDAP Conversion from BCD 8-digit data to decimal ASCII data

BCDDA, BCDDAP, DBCDDA,

DBCDDAP 1
High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of BCDDA/DBCDDA.

BCDDA, DBCDDA
Command
S D
2
Command
BCDDAP, DBCDDAP P S D
3
S : BCD data to be converted to ASCII (BCD 4 digits/8 digits)
D : Head number of the devices where the conversion result will be stored (character string)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other 4
Data Bit Word Bit Word K, H
S ––

D –– –– ––
4
Function
6
BCDDA
(1) Converts the individual digit numbers of hexadecimal notation of the BCD 4-digit data designated by S into ASCII codes,
and stores the results into the area starting from the device designated by D . 7
b15 b8 b7 b0
b15 b12 b11 b8 b7 b4 b3 b0 D ASCII code for hundreds place ASCII code for thousands place

S D +1 ASCII code for units place ASCII code for tens place
D +2 0
8
Thousands Hundreds Tens Units
place place place place Only when SM701 is OFF

For example, when "9105" is designated for S , the results of the operation are stored into the area starting from D in the
following manner:

7.11.3 BCDDA, BCDDAP, DBCDDA, DBCDDAP

7.11 Character string processing instructions
b15 b8b7 b0
b15 b12b11 b8 b7 b4b3 b0 D 31H (1) 39H (9)
S 9 1 0 5 D +1 35H (5) 30H (0)
D +2 00H

(2) The BCD data designated by S can be in the range of from 0 to 9999.
(3) The results of calculation stored in the device D . All zeros on the left side of the "Number of significant digits" are zero-
suppressed.
0050
Number of significant digits
20H

(4) The data to be stored at the device designated by D +2 differs depending on the ON/OFF status of SM701 (number of
characters to output select signal).
When SM701 is OFF.....Stores "0"
When SM701 is ON......Does not change

465
 BCDDA, BCDDAP, DBCDDA, DBCDDAP

DBCDDA
(1) Converts the individual digit numbers of hexadecimal notation of the BCD 8-digit data designated by S into ASCII codes,
and stores the results into the area starting from the device designated by D .
b15 b8b7 b0
S +1 S D ASCII code for millions place ASCII code for ten-millions place

b31 b28b27 b24b23 b20b19 b16 b15 b12b11 b8 b7 b4 b3 b0 D +1 ASCII code for ten-thousands place ASCII code for hundred-thousands place
D +2 ASCII code for hundreds place ASCII code for thousands place

D +3 ASCII code for unit place ASCII code for tens place
Ten Millions Hundred Ten Thou- Hundreds Tens Units
millions place thou- thou- sands place place place 0 (Only when
place sands sands place SM701 is OFF)
place place

For example, if the value 01234056 is designated by S , the operation result would be stored following D in the following
manner:
b15 b8b7 b0
D 31H (1) 20H
b31 b28b27 b24b23 b20b19 b16 b15 b12 b11 b8b7 b4 b3 b0 D +1 33H (3) 32H (2)
0 1 2 3 4 0 5 6 D +2 30H (0) 34H (4)
D +3 36H (6) 35H (5)
S +1 S
D +4 00H

(2) The BCD data designated by S can be in the range of 0 to 99999999.

(3) The results of calculation stored in the device D . All zeros on the left side of the "Number of significant digits" are zero-
suppressed.
00012098
Number of significant digits
20H

(4) The data to be stored at the device designated by D +4 differs depending on the ON/OFF status of SM701 (number of
characters to output select signal).
When SM701 is OFF.....Stores "0"
When SM701 is ON......Does not change

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
During the operation of the BCDDA instruction, the data of S is other
than 0 to 9999.
4100 ––
During the operation of the DBCDDA instruction, the data of S is other
than 0 to 99999999.
The range of the device specified in D exceeds the range of the
4101 –– –– –– ––
corresponding device.

466
 BCDDA, BCDDAP, DBCDDA, DBCDDAP

Program Example
1
(1) The following program uses the PR instruction to convert BCD 4-digit data (the value at W0) to decimal, and outputs it in
ASCII format to Y40 to Y48.
[Ladder Mode] [List Mode] 2
Step Instruction Device

4
[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.
4
b15 b8b7 b0
W0 D0 32H (2) 31H (1)
6
PR
1 2 9 5 D1 35H (5) 39H (9) Y40 to Y48
BCD value D2 00H Outputs "1295"
(2) The following program uses the PR instruction to convert BCD 8-digit data (the values at W10 and W11) to decimal, and
outputs it in ASCII format to Y40 to 48. 7
[Ladder Mode] [List Mode]

Step Instruction Device

8

7.11.3 BCDDA, BCDDAP, DBCDDA, DBCDDAP

7.11 Character string processing instructions
[Operation]
Conducts ASCII output of Y40 to Y48 by using the PR instruction when X0 goes ON.
Because SM701 is OFF, The PR instruction will output ASCII code until 00H is encountered.

b15 b8b7 b0
D0 35H (5) 33H (3)
W11 W10 D1 37H (7) 34H (4) PR
3 5 4 7 8 3 5 2 D2 33H (3) 38H (8) Y40 to Y48
BCD value D3 32H (2) 35H (5) Outputs "35478352"
D4 00H

467
 DABIN, DABINP, DDABIN, DDABINP
7.11.4 DABIN, DABINP Conversion from decimal ASCII to BIN 16-bit data
DDABIN, DDABINP Conversion from decimal ASCII to BIN 32-bit data

7.11.4 DABIN, DABINP, DDABIN, DDABINP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of DABIN/DDABIN.

Command
S D
DABIN, DDABIN
Command
P S D
DABINP, DDABINP
S : ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored (character string)
D : Head number of the devices where the conversion result will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

D –– ––

Function
DABIN
(1) Converts decimal ASCII data stored into the area starting from the device number designated by S into BIN 16-bit data,
and stores it in the device number designated by D .
b15 b8b7 b0
S ASCII code for ten-thousands place Sign data b15 b0
S +1 ASCII code for hundreds place ASCII code for thousands place D
S +2 ASCII code for units place ASCII code for tens place
BIN 16 bits
For example, if the ASCII code "-25108H" is specified for the area starting from S , the conversion result is stored at D as
shown below:
b15 b8b7 b0
S 32H (2) 2DH ( ) b15 b0
S +1 31H (1) 35H (5) D 2 5 1 0 8
S +2 38H (8) 30H (0)

(2) The ASCII data designated by from S to S +2 can be in the range of from -32768 to 32767
(3) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored if it is negative.
(If other than "20H " and "2DH" is set, it will be processed as positive data.)
(4) ASCII code can be set for each position within the range from "30H" to "39H".
(5) If the ASCII code set for individual positions is "20H" or "00H," it will be processed as "30H".

DDABIN
(1) Converts decimal ASCII data stored into the area starting from the device number designated by S into BIN 32-bit data,
and stores it in the device number designated by D .
b15 b8b7 b0
S ASCII code for billions place Sign data
S +1 ASCII code for ten-millions place ASCII code for hundred-millions place D +1 D
b31 b16b15 b0
S +2 ASCII code for hundred-thousands place ASCII code for millions place
Upper 16 bits Lower 16 bits
S +3 ASCII code for thousands place ASCII code for ten-thousands place
S +4 ASCII code for tens place ASCII code for hundreds place BIN 32 bits
S +5 (Ignored) ASCII code for units place

468
 DABIN, DABINP, DDABIN, DDABINP

For example, if the ASCII code of -1234543210H is designated for the area starting from S , the operation result would be
stored at D +1 and D in the following manner:
b15 b8b7 b0 1
S 31H (1) 2DH ( )
S +1 33H (3) 32H (2)
D +1 D
S
S
+2
+3
35H
33H
(5)
(3)
34H
34H
(4)
(4)
12 34 5 4 3 2 1 0 2
S +4 31H (1) 32H (2)
S +5 30H (0)

(2) The ASCII data designated by S to S +5 can be in the range of from -2147483648 to 2147483647. 3
Further, data stored at the upper bytes of S +5 will be ignored.
(3) The sign "20H" will be stored if the BIN data is positive, and the sign "2DH" will be stored if it is negative.
4
(If other than "20H " and "2DH" is set, it will be processed as positive data.)
(4) ASCII code can be set for each position within the range from "30H" to "39H".
(5) If the ASCII code set for individual positions is "20H" or "00H," it will be processed as "30H". 4

Operation Error 6
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

Error
Q00J/ 7
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The ASCII codes specified in S to S +5 other than "30H" to "39H",
8
"20H", or "00H".
4100 The ASCII data specified in S to S +5 is outside the following ranges: ––
When the DABIN instruction is used……-32768 to 32767
When the DDABIN instruction is used…-2147483648 to 2147483647

7.11.4 DABIN, DABINP, DDABIN, DDABINP

7.11 Character string processing instructions
The device specified in S exceeds the range of the corresponding
4101 –– –– –– ––
device.

Program Example
(1) The following program converts the decimal, 5-digit ASCII data and sign set at D20 through D22 to BIN values, and
stores the result at D0.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8b7 b0
D0
D20 20H (space) 2DH ( )
276
D21 32H (2) 20H (space)
(Regarded as -00276) BIN value
D22 36H (6) 37H (7)
- 276

469
 HABIN, HABINP, DHABIN, DHABINP

(2) The following program converts the decimal, 10-digit ASCII data and sign set at D20 through D25 to BIN values and
stores the result at D10 and D11.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8b7 b0
D20 20H (space) 20H (space)
D21 20H (space) 20H (space)
D11 D10
D22 39H (9) 33H (3)
3 9 6 8 3 7 0
D23 38H (8) 36H (6)
(Regarded as +0003968370) BIN value
D24 37H (7) 33H (3)
D25 30H (0)
3968370

7.11.5 HABIN, HABINP Conversion from hexadecimal ASCII to BIN 16-bit data
DHABIN, DHABINP Conversion from hexadecimal ASCII to BIN 32-bit data

7.11.5 HABIN, HABINP, DHABIN, DHABINP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of HABIN/DHABIN.

Command
HABIN, DHABIN S D

Command
HABINP, DHABINP P S D

S : ASCII data to be converted to BIN value or head number of the devices where the ASCII data is stored (character string)
D : Head number of the devices where the conversion result will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

D –– ––

Function
HABIN
(1) Converts hexadecimal ASCII data stored in the area starting from the device number designated by S into BIN 16-bit
data, and stores it in the device number designated by D .
b15 b8b7 b0
b15 b0
S ASCII code for the 3rd digit ASCII code for the 4th digit
D
S +1 ASCII code for the 1st digit ASCII code for the 2nd digit
BIN 16 bits
For example, if the ASCII code of 5A8DH is designated for the area starting from S , the operation result would be stored
at D in the following manner:
b15 b8 b7 b0
b15 b0
S 41H (A) 35H (5)
D 5A8DH
S +1 44H (D) 38H (8)
(2) The ASCII data designated by S to S +1 can be in the range of from 0000H to FFFFH.
(3) The ASCII codes can be in the range of "30H" to "39H" and from "41H" to "46H".

470
 HABIN, HABINP, DHABIN, DHABINP

DHABIN
(1) Converts hexadecimal ASCII data stored in the area starting from the device number designated by into BIN 32-bit
1
S

data, and stores it in the device number designated by D .

b15 b8b7 b0
S ASCII code for the 7th digit ASCII code for the 8th digit
S +1 ASCII code for the 5th digit ASCII code for the 6th digit
b31
D +1
b16 b15
D
b0 2
Upper 16 bits Lower 16 bits
S +2 ASCII code for the 3rd digit ASCII code for the 4th digit
S +3 ASCII code for the 1st digit ASCII code for the 2nd digit BIN 32 bits

For example, if the ASCII code of 5CB807E1H is designated for the area starting from S , the operation result would be 3
stored at D +1 and D in the following manner:

S
b15
43H (C)
b8b7
35H (5)
b0
D +1 D
4
b31 b16 b15 b0
S +1 38H (8) 42H (B)
5CB8H 07E1H
S +2 37H (7) 30H (0)
S +3 31H (1) 45H (E) 4
(2) The ASCII data designated by S to S +3 can be in the range of from 00000000H to FFFFFFFFH.
(3) The ASCII codes can be in the range of "30H" to "39H" and from "41H" to "46H".
6
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
7
SD0.
Q00J/
Error
code
Error details Q00/ QnH QnPH QnPRH QnU LCPU 8
Q01
The ASCII codes specified in S to S +3 are other than "30H" to "39H"
4100 ––
and from "41H" to "46H".
The range of the device specified in S exceeds the range of the

7.11.5 HABIN, HABINP, DHABIN, DHABINP

7.11 Character string processing instructions
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program converts the hexadecimal, 4-digit ASCII data set at D20 and D21 to BIN data, and stores the
result at D0.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8b7 b0
D0
D20 36H (6) 41H (A)
22977
D21 46H (F) 33H (3)
Regarded as A63FH BIN value
A63F (-22977 in decimal
value)

471
 DABCD, DABCDP, DDABCD, DDABCDP

(2) The following program converts the hexadecimal, 8-digit ASCII data set at D20 to D23 to BIN values, and stores the
result at D10 and D11.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8b7 b0
D20 46H (F) 34H (4)
D11 D10
D21 32H (2) 44H (D)
1339 1 97264
D22 37H (7) 38H (8)
Regarded as 4FD28750H BIN value
D23 30H (0) 35H (5) (1339197264 in decimal
4FD28750 value)

7.11.6 DABCD, DABCDP Conversion from decimal ASCII to BCD 4-digit data

7.11.6
DDABCD, DDABCDP Conversion from decimal ASCII to BCD 8-digit data

DABCD, DABCDP, DDABCD,

DDABCDP
High
Basic performance Process Redundant Universal LCPU

indicates an instruction symbol of DABCD/DDABCD.

Command
DABCD, DDABCD S D

Command
DABCDP, DDABCDP P S D

S : ASCII data to be converted to BCD value or head number of the devices where the ASCII data is stored (character string)
D : Head number of the devices where the conversion result will be stored (BCD 4 digits/8 digits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

D –– ––

Function
DABCD
(1) Converts decimal ASCII data stored in the area starting from device number designated by S into 4-digit BCD data, and
stores at device number designated by D .
b15 b8b7 b0
S ASCII code for hundreds place ASCII code for thousands place
b15 b12b11 b8b7 b4b3 b0
D
S +1 ASCII code for units place ASCII code for tens place
Thousands Hundreds Tens Units
place place place place

For example, if the ASCII code of 8765H is designated for the area starting from S , the operation results would be stored
at D in the following manner:
b15 b8b7 b0
b15 b12 b11 b8 b7 b4 b3 b0
S 37H (7) 38H (8)
D 8 7 6 5
S +1 35H (5) 36H (6)

(2) The ASCII data designated by S to S +1 can be in the range of from 0 to 9999.
(3) The ASCII code set at each digit can be in the range of from "30H" to "39H".
(4) If ASCII code for individual digits is "20H" or "00H", it is processed as "30H".

472
 DABCD, DABCDP, DDABCD, DDABCDP

DDABCD
(1) Converts decimal ASCII data stored in the area starting from the device designated by to 8-digit BCD data, and stores
1
S

it into the area starting from the device designated by D .

b15 b8b7 b0
S
S +1
ASCII code for millions place ASCII code for ten-millions place
ASCII code for ten-thousands place ASCII code for hundred-thousands place
D +1 D
2
b31 b28b27 b24 b23 b20b19 b16 b15 b12b11 b8b7 b4 b3 b0
S +2 ASCII code for hundreds place ASCII code for thousands place
S +3 ASCII code for units place ASCII code for tens place
Ten Milli- Hundred
milli- ons thou-
Ten
thou-
Thou- Hund- Tens Units
sands reds place place 3
ons place sands sands place place
place place place

For example, if the ASCII code of 87654321H is designated for the area starting from S , the operation results would be
4
stored at D +1 and D in the following manner:
b15 b8 b7 b0
S 37H (7) 38H (8) 4
S +1 35H (5) 36H (6) b31 b28b27 b24b23 b20b19 b16 b15 b12 b11 b8 b7 b4 b3 b0
S +2 33H (3) 34H (4) 8 7 6 5 4 3 2 1
S +3 31H (1) 32H (2)
D +1 D 6
(2) The ASCII data designated at S to S +3 can be in the range of from 0 to 99999999.
(3) The ASCII code set at each digit can be in the range of from "30H" to "39H".
7
(4) If ASCII code for individual digits is from "20H" to "00H", it is processed as "30H".

Operation Error 8
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error

7.11.6 DABCD, DABCDP, DDABCD, DDABCDP

7.11 Character string processing instructions
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 A character other than 0 to 9 is put in the data of S . ––
The range of the device specified in S exceeds the range of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program converts the decimal ASCII data set from D20 to D22 to BCD 4-digit data, and outputs the results
to Y40 to Y4F.
[Ladder Mode]

Outputs the converted

BCD value to a display device.

[List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
Y4F Y40
D20 34H (4) 20H (space)
0 4 9 4
D21 34H (4) 39H (9) Regarded BCD value
494 as 0494

473
 COMRD, COMRDP

(2) The following program converts the decimal ASCII data set at D20 to D23 into 8-digit BCD data, stores the result at D10
and D11, and also outputs it to from Y40 to Y5F.
[Ladder Mode]

Outputs the converted

BCD value to a display device.

[List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
D20 34H (4) 20H (space)
D11 D10 DMOV Y5F Y50 Y4F Y40
D21 37H (7) 39H (9)
0 4 9 7 2 9 4 9 0 4 9 7 2 9 4 9
D22 39H (9) 32H (2)
Regarded BCD value BCD value
D23 39H (9) 34H (4) as 04972949
4972949

7.11.7 COMRD, COMRDP Reading device comment data

7.11.7 COMRD, COMRDP Basic High

performance Process Redundant Universal LCPU

Command
COMRD COMRD S D

Command
COMRDP COMRDP S D

S : Head number of the devices where a comment to be read is stored (Device name)
D : Head number of the devices where the read comment will be stored (character string)
Internal Devices J \ Other
Setting BL\S, BL,
R, ZR U \G Zn Constants
Data Bit Word Bit Word BL\TR, P, I,
J, U
S ––

D –– –– –– ––

Function
(1) Reads the comment at the device number designated by S , and stores it as ASCII code in the area starting from the
device number designated by D .
b15 b8b7 b0
D ASCII code for the 2nd character ASCII code for the 1st character
D +1 ASCII code for the 4th character ASCII code for the 3rd character
Comment at device number designated by S D +2 ASCII code for the 6th character ASCII code for the 5th character
D +3 ASCII code for the 8th character ASCII code for the 7th character Stores up to 32
characters
ASCII code for the 30th character ASCII code for the 29th character
D +15 ASCII code for the 32nd character ASCII code for the 31st character
00H

474
 COMRD, COMRDP

For example, if the comment for the device designated by S were "NO. 1 LINE START," the operation results
would be stored following D as follows:
b15 b8b7 b0 1
D 4FH (O) 4EH (N)
D +1 31H (1) 2EH (.)
Comment at S
2
D +2 4CH (L) 20 H (space)
NO.1 LINE START D +3 4EH (N) 49H (I)
D +4 20H (space) 45H (E)
D +5 54H (T) 53H (S)
D
D
+6
+7
52H (R)
20 H (space)
41H (A)
54H (T)
3

D +15 20H (space)

00H
20H (space)
4
(2) If no comment has been registered for the device specified by S despite the fact that the comment range setting is
made, all of the characters for the comment are processed as "20H" (space). 4
(3) The device number plus 1 where the final character of D is stored differs depending on the ON/OFF status of SM701
(number of characters to output select signal).
When SM701 is OFF.....Does not change 6
When SM701 is ON......Stores "0"
(4) When a comment is read, SM720 turns ON for one scan after the instruction is completed.
SM721 turns ON during the execution of the instruction. 7
While SM721 is ON, the COMRD(P) instruction cannot be executed. If the attempt is made, no processing is performed.

8
1. For device comments used with the COMRD(P) instruction, use comment files stored in the standard RAM, standard
ROM, memory card, or SD memory card.
Comment files stored in the program memory cannot be used.
2. Set the comment file used for the COMRD(P) instruction in "PLC file setting" in the PLC parameter dialog box. If the
comment file to be used is not set in the PLC file setting, device comments cannot be output with the COMRD(P)

7.11.7 COMRD, COMRDP

7.11 Character string processing instructions
instruction.
When a comment file is set in the "PLC File" tab of the PLC Parameter dialog box, but the file does not exist at power-on
or reset, "FILESET ERROR" (error code: 2400) will occur.
3. The COMRD(P) instruction cannot be executed during the interrupt program.
No operation if executed.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The comment is not registered to the device number specified by S . ––
The device number specified by D is not a word device. ––
4101 The range of the device specified by D exceeds the range of the
–– –– –– ––
corresponding device.

475
 LEN, LENP

Program Example
(1) The following program stores the comments set at D100 into the area starting from W0 as ASCII when X1C is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b8 b7 b0
W0 49H (I) 4CH (L)
W1 45H (E) 4EH (N)
Comment at D100 W2 41H (A) 20H (space)
LINE A TARGET W3 54H (T) 20H (space)
W4 52 H (R) 41H (A)
W5 45H (E) 47H (G)
W6 20H (space) 54H (T)
W7 20H (space) 20H (space)

W15 20H (space) 20H (space)

W16 00H

Caution
(1) The processing completes after several scans.
(2) The COMRD(P)/PRC instruction is not executed if the start signal (execution command) of the COMRD(P)/PRC
instruction is turned ON before completion of the instruction (while SM721 is ON). Execute the COMRD(P)/PRC
instruction when SM721 is OFF.
(3) Two or more file comments cannot be accessed simultaneously.
(4) The following instructions cannot be executed simultaneously because they use SM721 in common.
Instruction Name ON During Execution ON for One Scan After Completion ON after Abnormal Completion
SP. FREAD
Designated by instruction. (Device designated by instruction) + 1
SP. FWRITE
SM721
PRC
SM720 None
COMRD

(5) For the High-speed Universal model QCPU and LCPU, when a comment file stored on an SD memory card is used, this
instruction cannot be executed while SM606 (SD memory card forced disable instruction) is ON. If the instruction is
executed, the command will be ignored.

7.11.8 LEN, LENP Character string length detection

7.11.8 LEN, LENP Basic High

performance Process Redundant Universal LCPU

Command
LEN LEN S D

Command
LENP LENP S D

S : Character string or head number of the devices where the character string is stored (character string)
D : Number of the device where the length of detected character string will be stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

D –– ––

476
 LEN, LENP

Function
(1) Detects length of character string designated by S and stores in the area starting from the device number designated by
1
D .
Processes the data from the device number designated by S to the device number storing "00H" as a character string. 2
b15 b8b7 b0
S 2nd character 1st character
S
S
4th character
6th character
3rd character
5th character
b15 b0 3
D Length of character string

S 00H nth character

4
Indicates the end of character string
For example, when the value "ABCDEFGHI" is stored in the area starting from , the value 9 is stored at .
4
S D

b15 b8b7 b0
S 42H (B) 41H (A)
S +1 44H (D) 43H (C) b15 b0
"ABCDEFGHI"
S +2 46H (F) 45H (E) D 9 6
S +3 48H (H) 47H (G)
S +4 00H 49H (I)

7
Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/ 8
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
There is no "00H" set within the range of the corresponding device after
4101 ––
the device number specified in S .

7.11.8 LEN, LENP

7.11 Character string processing instructions
Program Example
(1) The following program outputs the length of the character string from D0 to Y40 to Y4F as BCD 4-digit values.
[Ladder Mode]

Outputs the length of character

string to a display device.

[List Mode]

Step Instruction Device

[Operation]

b15 b8b7 b0
D0 49 H (I) 4DH (M)
D10 BCD conversion Y4F Y40
D1 53 H (S) 54 H (T)
10 0 0 1 0
D2 42 H (B) 55 H (U) BCD
"MITSUBISHI" BCD value
D3 53 H (S) 49 H (I)
(Characters "ABC"
D4 49 H (I) 48 H (H) that follow 00H are ignored)
D5 41 H (A) 00 H
D6 42 H (C) 43 H (B)

477
 STR, STRP, DSTR, DSTRP

7.11.9 STR, STRP Conversion from BIN 16-bit data to character string
DSTR, DSTRP Conversion from BIN 32-bit data to character string

Ver.
High
Basic Process Redundant Universal LCPU

7.11.9
performance

STR, STRP, DSTR, DSTRP • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

indicates an instruction symbol of STR/DSTR.

Command
STR, DSTR S1 S2 D

Command
STRP, DSTRP P S1 S2 D

S1 : Head number of the devices where the digits numbers for the numerical value to be converted are stored (BIN 16 bits)
S2 : BIN data to be converted (BIN 16/32 bits)
D : Head number of the devices where the converted character string will be stored (character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– ––
D2 ––

D –– –– –– ––

Function
STR
(1) Adds a decimal point to the BIN 16-bit data designated by S2 at the location designated by S1 , converts the data to
character string data, and stores it in the area starting from the device number designated by D .
b15 b8b7 b0
S1 Total number of digits ASCII code for the
(total number of digits -1) ASCII code for the sign
S1 Number of digits in decimal fraction D th digit
ASCII code for the ASCII code for the
(total number of digits -3) (total number of digits -2)
D th digit th digit
. ASCII code for the ASCII code for the
D (total number of digits -5) (total number of digits -4) Designated total
th digit th digit number of digits
Sign
ASCII code for the ASCII code for the
D (total number of digits -7) (total number of digits -6)
th digit th digit
S2 BIN data
D 00H

Automatically stored at
the end of the character string

S1 5
S1 +1 1
b15 b8 b7 b0
D 31 H (1) 2D ( )
1 2 . 3 D +1 2EH (.) 32H (2)
D +2 00H 33H (3)

S2 123

(2) The total number of digits that can be designated by S1 is from 2 to 8.

(3) The number of digits that can be designated by S1 +1 as a part of the decimal fraction is from 0 to 5.
However, the number of digits following the decimal point must be smaller than or equal to the total number of digits
minus 3.
(4) BIN data in the range between -32768 and 32767 can be designated at S2 .

(5) After conversion, character string data is stored at the device number D or later device number as indicated below:
(a) The sign "20H" (space) will be stored if the BIN data is positive, and the sign "2DH" (minus sign) will be stored if it is
negative.

478
 STR, STRP, DSTR, DSTRP

(b) If the setting for the number of digits after the decimal fraction is anything other than "0", "2EH" (.) will automatically
be stored at the position before the first of the specified number of digits.
Total number of digits 6 1
Number of digits 2
in decimal fraction 1 2. 34
BIN data 1 2 3 4 Number of digits in decimal fraction
Automatically added 2
If the number of digits in the decimal fraction part of the number is "0", the ASCII code "2EH" (.) will not be stored.
(c) If the total number of digits following the decimal fraction is greater than the number of BIN data digits, a zero will be
added automatically and the number converted by shifting to the right, so that it would become "0. ".
3
Total number of digits 6
Number of digits
in decimal fraction 3 0 . 012
4
BIN data 1 2
Automatically added
(d) If the total number of digits excluding the sign and the decimal point is greater than the number of BIN data digits,
"20H" (space) will be stored between the sign and the numeric value.
4
Total number of digits 8
Number of digits
in decimal fraction 1 12 . 3
6
BIN data 1 2 3 Filled with 20H (space)
If the number of BIN digits is greater, an error will be returned.
(e) The value "00H" is automatically stored at the end of the converted character string. 7
DSTR
(1) Adds a decimal point to the BIN 32-bit data designated by S2 at the location designated by S1 , converts the data to 8
character string data, and stores it following the device number designated by D .
S1 Total number of digits
S1 +1 Number of digits in decimal fraction b15 b8 b7 b0
ASCII code for the
D (total number of digits -1) ASCII code for the sign

7.11.9 STR, STRP, DSTR, DSTRP

7.11 Character string processing instructions
th digit
ASCII code for the ASCII code for the
. D +1 (total number of digits -3) (total number of digits -2)
th digit th digit
ASCII code for the ASCII code for the
Sign D +2 (total number of digits -5) (total number of digits -4)
th digit th digit Designated total
S2 +1 S2 ASCII code for the ASCII code for the number of digits
b31 b16 b15 b0 (total number of digits -7) (total number of digits -6)
D +3
Upper 16 bits Lower 16 bits th digit th digit
ASCII code for the ASCII code for the
BIN 32 bits D +4 (total number of digits -9) (total number of digits -8)
th digit th digit
ASCII code for the
D +5 00H (total number of digits -10)
th digit

Automatically stored at the

S1 8 end of the character string
S1 +1 3
b15 b8 b7 b0
D 36H (6) 2DH ( )
D +1 34H (4) 35H (5)
6 5 4 . 3 2 1 D +2 33H (3) 2EH (.)
D +3 31H (1) 32H (2)
S2 +1 S2 +4 00H
D
BIN data 6 5 4 3 2 1

(2) The total number of digits that can be designated by S1 is from 2 to 13.
(3) The number of digits that can be designated by S1 +1 as a part of the decimal fraction is from 0 to 10.
However, the number of digits following the decimal point must be smaller than or equal to the total number of digits
minus 3.
(4) The BIN data that can be designated by S1 and S2 +1 is within the range of from -2147483648 to 2147483647.

479
 STR, STRP, DSTR, DSTRP

(5) After conversion, character string data is stored at the device number following D as indicated below:
(a) The sign "20H" (space) will be stored if the BIN data is positive, and the sign "2DH" (minus sign) will be stored if it is
negative.
(b) If the setting for the number of digits after the decimal fraction is anything other than "0", "2EH" (.) will automatically
be stored at the position before the first of the specified number of digits.
Total number of digits 10
Number of digits 3
in decimal fraction 12345 . 678
BIN data 12 3 4 5 6 7 8
Number of digits in decimal fraction
Automatically added
If the number of digits in the decimal fraction part of the number is "0", the ASCII code "2EH" (.) will not be stored.
(c) If the total number of digits following the decimal fraction is greater than the number of BIN data digits, a zero will be
added automatically and the number converted by shifting to the right, so that it would become "0. ".
Total number of digits 13
Number of digits 10
in decimal fraction 0 . 0000054321
BIN data 5 4 3 2 1
Automatically added

(d) If the total number of digits excluding the sign and the decimal point is greater than the number of BIN data digits,
"20H" (space) will be stored between the sign and the numeric value.
Total number of digits 13
Number of digits 2
in decimal fraction 5432 . 10
BIN data 5 4 3 2 1 0 Filled with 20H (space) codes
If the number of BIN digits is greater, an error will be returned.
(e) The value "00H" is automatically stored at the end of the converted character string.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The total number of digits specified by S1 is outside the following
ranges:
When the STR instruction is in use......2 to 8
When the DSTR instruction is in use....2 to 13
The number of digits for a part of the decimal fraction specified by S

+1 is outside the following ranges:

When the STR instruction is in use......0 to 5
When the DSTR instruction is in use...0 to 10
4100 The relationship between the total number of digits specified by S1 and
the number of digits in the decimal fraction specified by S1 +1 is not as
follows :
Total number of digits -3 Number of digits in the decimal fraction
The number of digits specified by S1 is smaller than the number of
digits of the BIN data + 2 specified by S2

((Number of digits of S1 < Number of digits of the BIN data at S2 without

a sign + number of digits of a sign (+ or -) + number of digits of decimal
point (.))
The range of the devices that store the character string specified in D
4101
exceeds the range of the corresponding device.

480
 STR, STRP, DSTR, DSTRP

Program Example
1
(1) The following program converts the BIN 16-bit data stored at D10 when X0 is turned ON in accordance with the digit
designation of D0 and D1, and stores the result from D20 to D23.
[Ladder Mode] 2
Sets the data.

Sets the total number of digits. 3

Sets the number of digits in decimal fraction.

[List Mode] 4
Step Instruction Device

6
[Operation]
7
b15 b8b7 b0
D10 12672 D20 31H (1) 20H (space)
D21 36H (6) 32H (2)
D0 7 D22 2E H (.) 37H (7)
1267.2
8
D1 1 D23 00H 32H (2)

(2) The following program converts the BIN 32-bit data stored at D10 and D11 when X0 is turned ON in accordance with the
digit designation of D0 and D1, and stores the result at from D20 to D26.
[Ladder Mode]

7.11.9 STR, STRP, DSTR, DSTRP

7.11 Character string processing instructions
Sets the data.

Sets the total number of digits.

Sets the number of digits in decimal fraction.

[List Mode]

Step Instruction Device

[Operation]
D11 D10 b15 b8b7 b0
D10 12345678 D20 30 H (0) 20 H (space)
D21 30 H (0) 2EH (.)
D0 12 0.012345678
D22 32 H (2) 31 H (1)
D1 9 D23 34 H (4) 33 H (3)
D24 36 H (6) 35 H (5)
D25 38 H (8) 37 H (7)
D26 00 H

481
 VAL, VALP, DVAL, DVALP
7.11.10 VAL, VALP Conversion from character string to BIN 16-bit data
DVAL, DVALP Conversion from character string to BIN 32-bit data

Ver.
High
Basic performance Process Redundant Universal LCPU
• Basic model QCPU: The serial number (first five digits) is

7.11.10 VAL, VALP, DVAL, DVALP "04122" or later.

(Compatible GX Developer: Version 8.00A or later)

indicates an instruction symbol of VAL/DVAL.

Command
VAL, DVAL S D1 D2

Command
VALP, DVALP P S D1 D2

S : Character string to be converted to BIN data or head number of the devices where the character string is stored (character string)
D1 : Head number of the devices where the number of digits of the converted BIN data will be stored (BIN 16 bits)
D2 : Head number of the devices where the converted BIN data will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––
D1 –– –– ––

D2 –– ––

Function
VAL
(1) Converts character strings stored in the device numbers starting from that designated at S to BIN 16-bit data, and stores
the number of digits and BIN data in D1 and D2 .

For conversions from character strings to BIN, all data from the device number designated by S to the device number
where "00H" is stored will be processed as character strings.

Total number
D1 of digits
b15 b8b7 b0
S ASCII code for the 1st character ASCII code for the sign D1 +1 Number of digits
in decimal fraction
S +1 ASCII code for the 3rd character ASCII code for the 2nd character Integer value
S +2 ASCII code for the 5th character ASCII code for the 4th character . D2 ignoring decimal
point
S +3 ASCII code for the 7th character ASCII code for the 6th character
Sign 1st 2nd 7th
S +4 00H char- char- char- BIN 16 bits
acter acter acter
Indicates the end of character string
For example, if the character string "-123.45" is designated for the area starting from S , the operation result would be
stored at D1 and D2 in the following manner:
D1 7
b15 b8 b7 b0 D1 +1 2
S 31H (1) 2DH ( )
S +1 33H (3) 32 H (2)
1 2 3 . 4 5 D2 12345
S +2 34H (4) 2EH (.)
S +3 00H 35 H (5)

(2) The total number of characters that can be designated as a character string at S is from 2 to 8.
(3) From 0 to 5 characters from the character string designated at S can become the decimal fraction part.
However, this number must not exceed the total number of digits minus 3.
(4) The range of the numerical character string that can be converted to BIN value is from -32768 to 32767, ignoring a
decimal point.
Numerical value character strings, excluding the sign and the decimal point, can be designated only within the range
from "30H" to "39H".
The value ignoring a decimal point means:
Example : "-12345.6" "-123456"

482
 VAL, VALP, DVAL, DVALP

(5) The sign "20H" will be stored if the numerical value is positive, and the sign "2DH" will be stored if it is negative.
(6) "2EH" is set for the decimal point.

(7) The total number of digits stored at D1 amounts to all characters expressing numerical values (including signs and
1
decimal points).
The characters following the decimal point stored at D1 +1 include the number of characters from "2EH" (.) onward.
2
The BIN data stored at D2 is the character string ignoring the decimal point that has been converted to BIN data.
(8) In cases where the character string designated by S contains "20H" (space) or "30H" (0) between the sign and the first
numerical value other than "0", these "20H" and "30H" are ignored in the conversion into a BIN value. 3
Total number of digits 8 Total number of digits 7
Number of digits 2 Number of digits 4
123 . 45 in decimal fraction
12345
0 . 0012 in decimal fraction
12
4
BIN data BIN data
Ignored Sign Ignored

DVAL 4
(1) Converts the character string stored in the area starting from the device designated by S to BIN 32-bit data, and stores
the digits numbers and BIN data in D1 and D2 .

For conversions from character strings to BIN, all data from the device number designated by S to the device number
6
where "00H" is stored will be processed as character strings.

S
b15 b8 b7
ASCII code for the 1st character ASCII code for the sign
b0 D1 Total number of digits 7
D1 +1 Number of digits
in decimal fraction
S +1 ASCII code for the 3rd character ASCII code for the 2nd character
S +2 ASCII code for the 5th character ASCII code for the 4th character D2 +1 D2
S +3 ASCII code for the 7th character ASCII code for the 6th character . Integer value ignoring decimal point 8
S +4 ASCII code for the 9th character ASCII code for the 8th character
ASCII code for the 11th character ASCII code for the 10th character
Sign 1st 2nd 12th BIN 32 bits
S +5 char- char- char-
S +6 00H ASCII code for the 12th character acter acter acter

Indicates the end of character string

7.11.10 VAL, VALP, DVAL, DVALP

7.11 Character string processing instructions
b15 b8 b7 b0 D1 10
S 31H (1) 2D H ( ) D1 +1 3
S +1 33H (3) 32H (2)
S +2 35H (5) 34H (4)
S +3 36H (6) 2EH (.) 1 2 3 4 5 . 6 7 8 12 34 5 678
S +4 38H (8) 37H (7) D2 +1 D2
S +5 00H

(2) The total number of characters in the character string indicated by S is from 2 to 13.
(3) From 0 to 10 characters in the character string indicated by S can be the decimal fraction part.
However, this number must not exceed the total number of digits minus 3.
(4) The range of the numerical character string that can be converted to BIN value is from -2147483648 to 2147483647,
excluding the decimal point.
Numerical value character strings, excluding the sign and the decimal point, can be designated only within the range
from "30H" to "39H".
(5) The sign "20H" will be stored if the numerical value is positive, and the sign "2DH" will be stored if it is negative.
(6) "2EH" is set for the decimal point.
(7) The total number of digits stored at D1 amounts to all characters expressing numerical values (including signs and
decimal points).
The characters following the decimal point stored at D1 +1 include the number of characters from "2EH" (.) onward.

The BIN data stored at D2 is the character string ignoring the decimal point that has been converted to BIN data.

483
 VAL, VALP, DVAL, DVALP

(8) In cases where the character string designated by S contains "20H" (space) or "30H" (0) between the sign and the first
numerical value other than "0", these "20H" and "30H" are ignored in the conversion into a BIN value.
Total number of digits 12
Number of digits 2
6543 . 21 in decimal fraction
BIN data 6 5 4 3 2 1
Ignored

Total number of digits 11

Number of digits 8
0 . 00054321 in decimal fraction
BIN data 5 4 3 2 1
Sign Ignored

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The number of characters in the character string specified by S1 is
outside the following ranges:
When VAL instruction is in use........2 to 8
When DVAL instruction is in use.....2 to 13
The number of characters in the decimal fraction portion of the
character string specified by S is outside the following ranges:
When VAL instruction is in use........0 to 5
When DVAL instruction is in use.....0 to 10
The total number of characters in the character string specified by S

and the number of characters in the decimal fraction part stand in a

4100
relationship that is outside the following ranges:
Total number of characters -3 Number of characters in the decimal
fraction part
An ASCII code other than "20H" or "2DH" has been set for the sign.
An ASCII code other than "30H" to "39H" or "2EH" (decimal point) has
been set as a digit for one of the individual numbers.
There has been more than one decimal points set in the value.
The converted BIN value exceeds the following ranges:
When the VAL instruction is in use........-32768 to 32767
When the DVAL instruction is in use.....-2147483648 to 2147483647
No "00H" is set within the range from the device number specified by S
4101
to the last device number of the corresponding device.

Program Example
(1) The following program reads the character string data stored from D20 to D22 as an integer, converts it to a BIN value,
and stores it at D0 when X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

484
 ESTR, ESTRP

[Operation]
b15 b8b7 b0
D20
D21
31H (1)
2E H (.)
2DH ( )
36H (6)
D0 1654
1
D22 34H (4) 35H (5) D10 6 Total number of digits
D23 00H D11 2 Number of digits in decimal fraction

Set 00H
2
(2) The following program reads the character string data stored from D20 to D24 as an integer, converts it to a BIN value,
and stores it at D0 when X0 is ON.
3
[Ladder Mode] [List Mode]

Step Instruction Device

4

[Operation]
4
b15 b8 b7 b0 D1 D0

6
D20 37H (7) 20 H (space) 7 9 1 0 0 6 1 1
D21 31H (1) 39H (9)
D22 30H (0) 30H (0) D10 10 Total number of digits
D23 36H (6) 2EH (.) D11 3 Number of digits in decimal fraction
D24
D25
31H (1)
00H
31H (1)
7
Set 00H

7.11.11
data
ESTR, ESTRP Conversion from floating-point data to character string
8
Ver.
High
Basic Process Redundant Universal LCPU

7.11.11 ESTR, ESTRP

performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

7.11.11 ESTR, ESTRP

7.11 Character string processing instructions
Command
ESTR ESTR S S2 D

Command
ESTRP ESTRP S1 S2 D

S1 : 32-bit floating decimal point data to be converted or head number of the devices where the data is stored (real number)
S2 : Head number of the devices where display designation for the numerical value to be converted is stored (BIN 16 bits)
D : Head number of the devices where the converted character string will be stored (character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S1 –– –– *1 ––
D2 –– –– –– –– –– ––

D –– –– –– –– –– ––
*1: Available only in multiple Universal model QCPU and LCPU

Function
(1) Converts the 32-bit floating decimal point data designated by S1 to a character string according to the display designation
specified by S2 , and stores the result into the area starting from the device number designated by D .
(2) The post-conversion data differs depending on the display designation designated by S2 .

0: Decimal point format The converted data differs depending

S2 on the format selected at S2 .
1: Exponent format
S2 +1 Total number of digits Setting is possible in the range from 2 to 24.
S2 +2 Number of digits in decimal fraction

485
 ESTR, ESTRP

When using decimal point format

b15 b8 b7 b0
S2 Decimal point format ASCII code for the
S2 +1 Total number of digits D (total number of digits -1) ASCII code for the sign
th digit
S2 +2 Number of digits in decimal fraction
ASCII code for the ASCII code for the
D +1 (total number of digits -3) (total number of digits -2)
th digit th digit
. ASCII code for the ASCII code for
D +2 (total number of digits -5) decimal point (.)
Sign th digit (2E H)

ASCII code for the ASCII code for the

S1+1 S1 D +3 (total number of digits -7) (total number of digits -6)
th digit th digit
D +4 00 H
32-bit floating-point real number Automatically stored at the
end of character sting
For example, in a case where there are 8 digits in total, with 3 digits in the decimal fraction part, and the value designated
is -1.23456, the operation result would be stored in the area starting from D in the following manner:

S2 0
S2 +1 8
S2 +2 b15 b8 b7 b0
3
D 20H (space) 2DH(-)
D +1 31H (1) 20H (space)
- 1 . 2 3 5 D +2 32H (2) 2EH (.)
D +3 35H (5) 33H (3)
Sign D +4 00H

S1 +1 S1 Automatically stored at the end of character sting

-1. 2 3 4 5 6

32-bit floating-point real number

(a) The total number of digits that can be designated by S2 +1 is as shown below:
When the number of decimal fraction digits is "0"
.........................Number of digits (max.: 24) 2
When the number of decimal fraction digits is other than "0"
.........................Number of digits (max.: 24) (Number of decimal fraction digits + 3)
(b) The number of digits of decimal fraction part that can be designated by S2 +2 is from 0 to 7.
However, the number of digits following the decimal point must be smaller than or equal to the total number of digits
minus 3.
(c) The converted character string data is stored at the area starting from the device number D as indicated below:
1) The sign "20H" (space) will be stored if the 32-bit floating decimal point type real number is positive, and the sign
"2DH" (minus sign) will be stored if it is negative.
2) If the decimal fraction part of a 32-bit floating point real number data is out of the range of the digits of decimal
fraction part, the lower decimal values will be rounded off.

S2 0: Decimal point format

S2 +1 8 (Total number of digits) Total number of digits
S2 +2 2 (Number of digits in decimal fraction)
- 1 . 2 3 4 5 6
S1 +1 S1 Number of digits in Rounded off
-1. 2 3 4 5 6 decimal fraction

486
 ESTR, ESTRP

3) If the number of digits following the decimal point has been set at any value other than "0", "2EH" (.) will
automatically be stored at the position before the first of the specified number of digits.

S2 0: Decimal point format

1
S2 +1 8 (Total number of digits) Total number of digits
S2 +2 2 (Number of digits in decimal fraction)
- 1 . 2 3
2
S1 +1 S1 Number of digits
-1 . 2 3 4 5 6 in decimal fraction
Automatically added
If the number of digits in the decimal fraction part is "0", the ASCII code "2EH" (.) will not be stored. 3
4) If the total number of digits, excluding the sign, the decimal point and the decimal fraction part, is greater than
the integer part of the 32-bit floating point type real number data, "20H (space)" will be stored between the sign
and the integer part.
4
S2 0
S2 +1 8 Total number of digits 4
S2 +2 2
- 1 . 2 3
S1+1 S1
-1 . 2 3 4 5 6
Number of digits
in decimal fraction 6
Filled with 20H
(space) codes
5) The value "00H" is automatically stored at the end of the converted character string. 7
When using exponent format

b15 b8b7 b0
8
S2 Exponent format ASCII code for the
D (total number of digits-1)th ASCII code for the sign
S2 +1 Total number of digits digit
S2 +2 Number of digits in decimal fraction ASCII code for decimal
ASCII code for the
D +1 point (.) (2EH)
(total number of digits-2)th
digit

7.11.11 ESTR, ESTRP

7.11 Character string processing instructions
ASCII code for the ASCII code for the

E D +2 (total number of digits-5)th (total number of digits-4)th

. digit digit
ASCII code for the ASCII code for the
Sign (for integer) Sign (for exponent) D +3 (total number of digits-7)th (total number of digits-6)th
digit digit

S1 +1 S1 ASCII code for the sign

D +4 (for exponent)
45H (E)
Automatically added
ASCII code for the ASCII code for the
D +5 (total number of digits-11)th (total number of digits-10)th
digit digit
32-bit floating-point real number
D +6 00H

Automatically stored at
the end of character sting
For example, in a case where there are 12 digits is total, with 4 digits in the decimal fraction portion, and the value
designated is -12.34567, the operation results would be stored in the area starting from D in the following manner:

S2 1
S2 +1 12
b15 b8 b7 b0
S2 +2 4
D 20H (space) 2DH (-)
D +1 2EH (.) 31H (1)
- 1 . 2 3 4 6E + 0 1 D +2 33H (3) 32H (2)
D +3 36H (6) 34H (4)
Sign (for integer) Sign (for exponent) D +4 2CH (+) 45H (E)
D +5 31H (1) 30H (0)
S1 +1 S1 00H
D +6
- 1 2 . 3 4 567
Automatically added
32-bit floating-point real number

487
 ESTR, ESTRP

(a) The total number of digits that can be designated by S2 +1 is as shown below:
When the number of decimal fraction digits is "0"
.........................Number of digits (max.: 24) 2
When the number of decimal fraction digits is other than "0"
.........................Number of digits (max.: 24) (Number of decimal fraction digits + 7)
(b) The number of digits of dicimal fraction part that can be designated by S2 +2 is from 0 to 7.
However, the number of digits in the decimal fraction portion should be equal to or less than the total number of
digits minus 7.
(c) The converted character string data is stored at the area starting from the device number D as indicated below:
1) If the 32-bit floating decimal point type real number data is positive in value, the sign before the integer will be
stored as ASCII code "20H" (space), and if it is a negative value, the sign will be stored as "2DH" (-).
2) The integer portion is fixed to one digit.
20H (space) will be stored between the integer and the sign.

1 Total number of digits (12)

S2
S2 +1 12 Fixed to 1 digit
S2 +2 4
- 1 . 2 3 4 6 E+ 0 1
S1+1 S1
-1 2. 3 4567
Filled with 20H (space) codes
3) If the decimal fraction part of the 32-bit floating point type real number is out of the range of the digits of the
decimal fraction part, the lower decimal values will be rounded off.

S2 1
S2 +1 12 Total number of digits (12)
S2 +2 4
- 1 . 2 3 4 6 6 7 E+ 0 1
S1+1 S1
Number of digits These are cut
-1 2. 3 4 5 6 7 in decimal fraction (4)

4) If the number of digits of the decimal fraction part has been set at any value other than "0", "2EH" (.) will
automatically be stored at the position before the first of the specified number of digits.

S2 1
S2 +1 12 Total number of digits (12)
S2 +2 4
- 1 . 2 3 4 6 E+ 0 1
S1 +1 S1 Number of digits
-1 2. 3 4 5 6 7 in decimal fraction (4)
Automatically added
If the number of digits in the decimal fraction part of the number is "0", the ASCII code "2EH" (.) will not be
stored.
5) The ASCII code "2CH" (+) will be stored as the sign for the exponent portion of the value if the exponent is
positive in value, and the code "2DH" (-) will be stored if the exponent is a negative value.
6) The exponent portion is fixed at 2 digits.
If the exponent portion is only 1 digit, the ASCII code "30H" (0) will be stored between the sign and the exponent
portion of the number.

S2 1 Total number of digits (12)

S2 +1 12 Fixed to 2 digits
S2 +2 4
- 1 . 2 3 4 6 E+ 0 1
S1 +1 S1
-1 2 . 3 4567 Filled with
30H (0) code
7) The value "00H" is automatically stored at the end of the converted character string.
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3)

488
 ESTR, ESTRP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The S1 value is not within the following range:
0, 2-126 | S1 | < 2128 3
The format specified by S2 is other than 0 and 1.
The total number of digits specified by S2 + 1 is outside the following
ranges: 4
When using decimal point format
When the number of decimal fraction digits is "0"
.....Total number of digits 2
When the number of decimal fraction digits is not "0"
4
.....Total number of digits (Number of decimal fraction digits + 3)
When using exponent format
4100 When the number of decimal fraction digits is "0" 6
.....Total number of digits 6
When the number of decimal fraction digits is not "0"
.....Total number of digits (Number of decimal fraction digits + 7) 7
The number of digits for the decimal fraction portion specified by S2 +2
is outside the following ranges:
When using the decimal point format 8
.....Number of decimal fraction digits (Total number of digits -3)
When using the exponent format
.....Number of decimal fraction digits (Total number of digits -7)
The value in more than 24 digits was specified.

7.11.11 ESTR, ESTRP

7.11 Character string processing instructions
The range of the devices that store the character string specified in D

exceeds the range of the corresponding device.

4101
The range of the device specified by S2 exceeds the range of the
–– –– –– ––
corresponding device.
The specified device value is -0, unnormalized number, nonnumeric, or
4140
± .

Program Example
(1) The following program converts the 32-bit floating point type real number data which had been stored at R0 and R1 in
accordance with the conversion designation that is being stored at R10 to R12, and stores the result following D0 when
X0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

R10 0 Conversion format b15 b8 b7 b0

R11 7 20H (space)
D0 20H (space)
Total number of digits Total number of digits
R12 D1 2EH (.) 30H (0)
3 Number of digits
in decimal fraction 0 . 0 3 3 D2 33H (3) 30H (0)
00H 33H (3)
R1 R0 Space Number of digits
0 . 0327 457 in decimal fraction Automatically stored

489
 EVAL, EVALP

(2) The following program converts the 32-bit floating decimal point type real number data which had been stored at D0 and
D1 in accordance with the conversion designation that is being stored at R10 to R12, and stores the result following D10
when X1C goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

R10 1 (exponent format) Conversion format

R11 12 Total number of digits Total number of digits
R12 4 Number of digits
in decimal fraction 3 . 2 7 4 6 E- 0 2

D1 D0 Space Number of digits

0 . 0 327 4578 in decimal fraction
b15 b8 b7 b0
D10 20H (space) 20H (space)
D11 2EH (.) 33H (3)
D12 37H (7) 32H (2)
D13 36H (6) 34H (4)
D14 2DH(-) 45H (E)
D15 32H (2) 30H (0)
D16 00H

Automatically stored

7.11.12 EVAL, EVALP Conversion from character string to floating-point data

Ver.
High
Basic Process Redundant Universal LCPU

7.11.12 EVAL, EVALP

performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
EVAL EVAL S D

Command
EVALP EVALP S D

S : Character string data to be converted to 32-bit floating decimal point real number data or head number of the devices where the character string data is
stored (character string)
D : Head number of the devices where the converted 32-bit floating decimal point real number data will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– –– –– ––
D –– –– *1 –– –– ––
*1: Available on Universal model QCPU and LCPU

Function
(1) Converts character string stored in the area starting from the device number designated by S to 32-bit floating point type
real number, and stores result at device designated by D .

490
 EVAL, EVALP

(2) The designated character string can be converted to 32-bit floating point type real number data either in the decimal point
format or the exponent format.
b15 b8 b7 b0 1
S ASCII code for the 1st character ASCII code for the sign
S +1 ASCII code for the 3rd character ASCII code for the 2nd character D +1 D
S +2 ASCII code for the 5th character ASCII code for the 4th character
S +3 ASCII code for the 7th character ASCII code for the 6th character 2
32-bit floating-point
S +4 00H real number

3
Indicates the end
of character string
(a) When using decimal point format
b15 b8b7 b0
S 31H (1) 2DH(-)
D +1 D
4
S +1 30H (0) 2EH (.)
S +2 38H (8) 37H (7) -1 . 0 7 8 12
S +3 32H (2) 31H (1)
S +4 00H
32-bit floating-point
real number
4
- 1 . 0 7 8 1 2

(b) When using exponent format 6

b15 b8b7 b0
S 20H (space) 2DH (-)
S +1
7
2EH (.) 31H (1)
S +2 32H (2) 33H (3) D +1 D
S +3 31H (1) 30H (0) -1. 320 1E + 10
S +4 2BH (+) 45H (E)
32-bit floating-point
S +5
S +6
30H (0)
00H
31H (1) real number 8
1 1 . 3 2 0 1 E+ 1 0

(3) Excluding the sign, decimal point, and exponent portion of the result, 6 digits of the character string designated by S to
be converted to a 32-bit floating decimal point type real number will be effective; the 7th digit on later digit will be cut from

7.11.12 EVAL, EVALP

7.11 Character string processing instructions
the result.
(a) When using decimal point format
b15 b8b7 b0
S 20H (space) 2DH (-)
S +1 31H (1) 20H (space)
S +2 33H (3) 2EH (.) D +1 D
S +3 31H (1) 30H (0) -1. 3 0 1 5 6
S +4 36H (6) 35H (5)
S +5 32-bit floating-point real number
31H (1) 38H (8)
S +6 00H 32H (2)

- 1 . 3 0 1 5 6 8 1 2

These are cut

491
 EVAL, EVALP

(b) When using exponent format

b15 b8b7 b0
S 20H (space) 2DH (-)
S +1 2EH (.) 31H (1)
S +2 35H (5) 33H (3) D +1 D
S +3 33H (3) 30H (0) -1 . 350 34 E- 2
S +4 31H (1) 34H (4)
S +5 45H (E) 32H (2) 32-bit floating-point
real number
S +6 30H (0) 2DH (-)
S +7 00H 32H (2)

- 1 . 3 5 0 3 4 1 2 E- 0 2

These are cut

(4) In the decimal point format, if "2BH" (+) is specified for the sign or if the designation of sign is omitted, conversion is made
assuming a positive value.
If "2DH" (-) is specified for the sign, the character string is converted assuming a negative value.
(5) In the exponent format, if "2BH" (+) is specified for the sign in the exponent portion or if the designation of sign is omitted,
conversion is made assuming a positive value.
If "2DH" (-) is specified for the sign in the exponent portion, the character string is converted assuming a negative value.
(6) In a case where the ASCII code "20H (space)" or "30H" (0) exists between numbers not including the initial zero in a
character string specified by S , it will be ignored when the conversion is done.
b15 b8b7 b0
S 20H (space) 2DH (-)
S +1 31H (1) 30H (0) D +1 D
S +2 32H (2) 2EH (.) -1 . 2 3 1
S +3 31H (1) 33H (3)
32-bit floating-point
S +4 00 real number

- 0 1 . 2 3 1

Ignored
(7) In a case where the ASCII code "30H (0) " exists between the character "E" and a number in an exponent format
character string, the "30H" would be ignored when the conversion is performed.

b15 b8b7 b0
20H (space) 2DH (-)
2EH (.) 31H (1)
34H (4) 30H (0) D +1 D
33H (3) 35H (5) -1 . 0 4 5 3 E + 3
2BH (+) 45H (E)
33H (3) 30H (0)
00H

- 1 . 0 4 5 3 E+ 0 3

Ignored
(8) If the "20H" (space) code is contained in the character string, the code is ignored in the conversion.
(9) Up to 24 characters can be set for a character string.
The codes "20H" (space) and "30H" (0) contained in the character string are also counted as a character.

492
 EVAL, EVALP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The integer portion or the decimal fraction portion contains a character
other than one in the range from "30H" (0) to "39H" (9). 3
There are two or more "2EH" (.) in the character string specified in D .
The exponent portion contains the code (character) other than "45H"(E),

4100
"2BH"(+), "45H"(E) or "2DH"( ), or the string contains more than one 4
exponent portion.
Data after conversion is not within the following range.
0, 2-126 | Data after conversion | 2128
4
The number of characters in the character string following S is either 0
or more than 24.

4101
The code "00H" does not appear in the range from
device.
S to the relevant
6

Program Example 7
(1) The following program converts the character string stored in the area starting from R0 to a 32-bit floating decimal point
type real number, and stores the result at D0 and D1 when X20 is turned ON.
[Ladder Mode] [List Mode]
8
Step Instruction Device

7.11.12 EVAL, EVALP

7.11 Character string processing instructions
[Operation]
b15 b8b7 b0
R0 20H (space) 2DH (-)
R1 31H (1) 30H (0)
D1 D0
R2 32H (2) 2EH (.)
-1 . 234 5 2
R3 34H (4) 33H (3)
R4 32H (2) 35H (5)
R5 00H 31H (1)

- 0 1 . 2 3 4 5 2 1

Ignored These are cut

(2) The following program converts the character string stored in the area starting from D10 to a 32-bit floating decimal point
type real number, and stores the result at D100 and D101 when X20 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

493
 ASC, ASCP

[Operation]
b15 b8b7 b0
D10 20H (space) 20H (space)
D11 2EH (.) 31H (1)
D12 33H (3) 32H (2) D101 D100
D13 35H (5) 34H (4) 1 . 2 3 4 5 E -2
D14 2DH (-) 45H (E)
D15 32H (2) 30H (0)
D16 00

1 . 2 3 4 5 E - 0 2

Ignored Ignored

7.11.13 ASC, ASCP Conversion from hexadecimal BIN to ASCII

7.11.13 ASC, ASCP Basic High

performance Process Redundant Universal LCPU

Command
ASC ASC S D n

Command
ASCP ASCP S D n

S : Head number of the devices where BIN data to be converted to a character string is stored (BIN 16 bits)
D : Head number of the devices where the converted character string will be stored (character string)
n : Number of characters to be stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– –– ––
n ––

Function
(1) Converts the BIN 16-bit data stored in the area starting from the device designated by S to ASCII by treating the BIN
data in hexadecimal representation. Then, stores the converted data into the area starting from the device designated by
D , for the number of characters specified by n.
b15 b12b11 b8b7 b4b3 b0 b15 b8b7 b0
S 4th digit 3rd digit 2nd digit 1st digit D ASCII code for the 2nd digit ASCII code for the 1st digit
S +1 4th digit 3rd digit 2nd digit 1st digit D +1 ASCII code for the 4th digit ASCII code for the 3rd digit
D +2 ASCII code for the 2nd digit ASCII code for the 1st digit Number of
D +3 ASCII code for the 4th digit ASCII code for the 3rd digit characters
4th digit 3rd digit 2nd digit 1st digit designated by n

BIN data ASCII code for the 2nd digit ASCII code for the 1st digit

b15 b12b11 b8b7 b4b3 b0 b15 b8b7 b0

S 1H 2H 3H 4H D 33H (3) 34H (4)
S +1 5H 6H 7H 8H D +1 31H (1) 32H (2)
S +2 FH EH DH CH D +2 37H (7) 38H (8)
S +3 AH 9H BH 6H D +3 35H (5) 36H (6) When "15" is
D +4 44H (D) 43H (C) set for n
D +5 46H (F) 45H (E)
D +6 42H (B) 36H (6)
D +7 00H 39H (9)

(2) The use of n to set the number of characters causes the BIN data range designated by S and the character string
storage device range designated by D to be set automatically.

494
 ASC, ASCP

(3) Processing will be performed accurately even if the device range where BIN data to be converted is being stored
overlaps with the device range where the converted ASCII data will be stored.
b15 b12 b11 b8 b7 b4b3 b0 b15 b8b7 b0 1
D11 4H 3H 2H 1H D10 32H 31H
D12 8H 7H 6H 5H D11 34H 33H
D12
2
D13 AH 9H 36H 35H
D13 38H 37H
D14 41H 39H
(4) If an odd number of characters has been designated by n, the ASCII code "00H" will be automatically stored in the upper
8 bits of the final device in the range where the character string is to be stored. 3
When 5 characters have been designated by n.
b15 b12b11 b8b7 b4b3 b0
4
b15 b8b7 b0
S 1 A 2 B S D 32H(2) 42H(B)
S +1 B S D +1 31H(1) 41H(A)
S D +2 00H 42H(B)

4
Stored automatically
(5) If the number of characters designated by n is "0", conversion processing will not be conducted.

6
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
7
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 8
The range for the number of characters designated by n following the
device number designated by S exceeds the relevant device range.
4101 ––
The range for the number of characters designated by n following the
device number designated by D exceeds the relevant device range.

7.11.13 ASC, ASCP

7.11 Character string processing instructions
Program Example
(1) The following program reads the BIN data being stored at D0 as hexadecimal values, converts them to a character
string, and stores the result from D10 to D14 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
b15 b12b11 b8 b7 b4b3 b0 b15 b8b7 b0
D0 CH 7H 2H 9H D10 32H (2) 39H (9)
D1 0H 5H AH FH D11 43H (C) 37H (7)
D2 0H 0H 2H 2H D12 41H (A) 46H (F)
D13 30H (0) 35H (5)
D14 32H (2) 32H (2)

495
 HEX, HEXP
7.11.14 HEX, HEXP Conversion from ASCII to hexadecimal BIN

7.11.14 HEX, HEXP Basic High

performance Process Redundant Universal LCPU

Command
HEX HEX S D n

Command
HEXP HEXP S D n

S : Head number of the devices where a character string to be converted to BIN data is stored (character string)
D : Head number of the devices where the converted BIN data will be stored (BIN 16 bits)
n : Number of characters to be stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– ––

D –– –– ––
n ––

Function
(1) Converts the number of characters of hexadecimal ASCII data designated by n stored in the area starting from the
device number designated by S into BIN values and stores them in the area starting from the device number designated
by D .
b15 b8b7 b0 b15 b12b11 b8b7 b4b3 b0
S ASCII code for the 2nd digit ASCII code for the 1th digit D 4th digit 3rd digit 2nd digit 1st digit
S +1 ASCII code for the 4nd digit ASCII code for the 3th digit D +1 4th digit 3rd digit 2nd digit 1st digit
Number of S +2 ASCII code for the 2st digit ASCII code for the 1rd digit
characters
designated S +3 ASCII code for the 4st digit ASCII code for the 3rd digit
by n

BIN data

For example, if the number 9 has been designated by n, the operation would be as follows:
b15 b8b7 b0
S 33H (3) 34H (4)
When "9" S +1 31H (1) 32H (2) b15 b12b11 b8b7 b4b3 b0
is set S +2 42H (B) 36H (6) D 1H 2H 3H 4H
for n
S +3 41H (A) 39H (9) D +1 AH 9H BH 6H
S +4 38H (8) 45H (E) D +2 0H 0H 0H EH

Code "38H" remains unchanged since the designated number of characters is "9".

(2) When the number of characters is specified for n, the range of characters designated by S as well as the device range
designated by D in which the BIN data will be stored are automatically decided.
(3) Accurate processing will be conducted even in cases where the range of devices where the ASCII code to be converted
is being stored overlaps with the range of devices that will store the converted BIN data.
b15 b8b7 b0 b15 b12 b11 b8 b7 b4b3 b0
D10 32H (2) 31H (1) D11 4H 3H 2H 1H
D11 34H (4) 33H (3) D12 8H 7H 6H 5H
D12 36H (6) 35H (5) D13 0H 0H AH 9H
D13 38H (8) 37H (7)
D14 41H (A) 39H (9)

496
 HEX, HEXP

(4) If the number of characters designated by n is not divisible by 4, "0" will be automatically stored after the designated
number of characters in the final device number of the devices which are storing the converted BIN values.
b15 b8b7 b0 b15 b12 b11 b8b7 b4b3 b0 1
S 32H (2) 42H (B) D 1 A 2 B
S +1 31H (1) 41H (A) D +1 0 0 0 8
S +2 43H (C) 38H (8)
Value "0" is automatically stored in
the area outside the range of the
2
designated number of characters.
(5) If the number of characters designated by n is "0", conversion processing will not be conducted.
(6) ASCII code that can be designated by S includes from "30H" to "39H" and from "41H" to "46H".
3

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
4
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
Characters other than those outside the hexadecimal character string 6
4100 (characters that are not in the range between "30H" to "39H" and "41H" ––
to "46H") have been set in the device specified by S .
The range of the device specified by S exceeds the range from S to S 7
+ the number of characters specified in n (including S ).
4101 The range of the device specified by D exceeds the range from D to D ––
+ the number of characters specified in n (including D ). 8
n is negative.

Program Example

7.11.14 HEX, HEXP

7.11 Character string processing instructions
(1) The following program converts the character string being stored from D0 to D4 to BIN data and stores the result from
D10 to D14 when X0 goes ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0 b15 b12b11 b8 b7 b4b3 b0
D0 42H (B) 36H (6) 2H 5H BH 6H
D1 32H (2) 35H (5) 3H 1H 7H AH
D2 37H (7) 41H (A) 0H 0H 9H 7H
D3 33H (3) 31H (1)
D4 39H (9) 37H (7)

497
 RIGHT, RIGHTP, LEFT, LEFTP
7.11.15 RIGHT, RIGHTP Extracting character string data from the right
LEFT, LEFTP Extracting character string data from the left

7.11.15 RIGHT, RIGHTP, LEFT, LEFTP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of RIGHT/LEFT.

Command
RIGHT, LEFT S D n

Command
RIGHTP, LEFTP P S D n

S : Character string or head number of the devices where the character string is stored (character string)
D : Head number of the devices where the character string consisting of n characters starting from the right or left of S will be stored (character string)
n : Number of characters to be extracted (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $
S –– –– –– ––
D –– –– –– –– ––
n –– ––

Function
RIGHT
(1) Stores n number of characters from the right side of the character string (the end of the character string) being stored in
devices starting from that whose number is designated by S , in devices starting from that whose number is designated
by D .
b15 b8b7 b0
S b15 b8b7 b0
ASCII code for the 2nd character ASCII code for the 1st character
D ASCII code for the (last - n + 2)th character ASCII code for the (last - n + 1)th character
S +1 ASCII code for the 4th character ASCII code for the 3rd character
D +1 ASCII code for the (last - n + 4)th character ASCII code for the (last - n + 3)th character

ASCII code for the (last - n + 2)th character ASCII code for the (last - n + 1)th character
ASCII code for the (last - 1)th character ASCII code for the (last - 2)th character
ASCII code for the (last - n + 4)th character ASCII code for the (last - n + 3)th character
00H ASCII code for the last character

ASCII code for the (last - 1)th character ASCII code for the (last - 2)th character
00H ASCII code for the last character

When n 5
b15 b8b7 b0
b15 b8b7 b0
S 42 H (B) 41H (A)
D 32 H (2) 31 H (1)
S +1 44 H (D) 43H (C)
D +1 34 H (4) 33 H (3)
S +2 46 H (F) 45H (E)
D +2 00 H 35 H (5)
S +3 32 H (2) 31H (1)
S +4 "12345"
34 H (4) 33H (3)
S +5 00H 35H (5) ASCII code for the 5th character

"ABCDEF12345"
(2) The NULL code (00H) indicating the end of the character string is automatically appended at the end of the character
string. Refer to Page 97, Section 3.2.5 for the format of the character string data.
(3) If the number of characters designated by n is "0", the NULL code (00H) will be stored at D .

498
 RIGHT, RIGHTP, LEFT, LEFTP

LEFT
(1) Stores n number of characters from the left side of the character string (the beginning of the character string) being
stored in devices starting from that whose number is designated by S , in devices starting from that whose number
1
designated by D .

S
b15 b8b7 b0
ASCII code for the 2nd character ASCII code for the 1st character
b15 b8b7 b0 2
D ASCII code for the 2nd character ASCII code for the 1st character
S +1 ASCII code for the 4th character ASCII code for the 3rd character
D +1 ASCII code for the 4th character ASCII code for the 3rd character

ASCII code for the (n - 1)th character ASCII code for the (n - 2)th character
ASCII code for the (n - 1)th character ASCII code for the (n - 2)th character 3
ASCII code for the (n + 1)th character ASCII code for the nth character
00H ASCII code for the nth character

00H ASCII code for the last character

4
When n 7

b15 b8b7 b0
S 42 H (B) 41H (A)
D
b15
42 H (B)
b8b7
41H (A)
b0
4
S +1 44 H (D) 43H (C)
D +1 44 H (D) 43H (C)
S +2 46 H (F) 45H (E)
D +2 46 H (F) 45H (E)
S +3 32 H (2) 31H (1)
S +4 34 H (4) 33H (3)
D +3
ASCII code for the
00 H
"ABCDEF1"
31H (1)
6
S +5 00 H 35H (5) 7th character
"ABCDEF12345"

(2) The NULL code (00H) indicating the end of the character string is automatically added to the end of the character string. 7
Refer to Page 97, Section 3.2.5 for the format of the character string data.
(3) If the number of characters designated by n is "0", the NULL code (00H) will be stored at .
8
D

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into

7.11.15 RIGHT, RIGHTP, LEFT, LEFTP

7.11 Character string processing instructions
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value of n exceeds the number of characters specified by S .
4101 The range of the device specified by D exceeds the range from D to D ––
+ the number of characters specified in n (including D ).

Program Example
(1) The following program stores 4 characters of data from the rightmost of the character string stored in the area starting
from R0, and stores it into the area starting from D0 when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
b15 b8b7 b0
b15 b8b7 b0
R0 41H (A) 42H (B)
D0 45H (E) 30H (0)
R1 31H (1) 32H (2)
D1 41H (A) 46H (F)
R2 45H (E) 30H (0)
D2 00H
R3 41H (A) 46H (F)
"0EFA"
R4 00H
"BA210EFA" ASCII code for the 4th character

499
 MIDR, MIDRP, MIDW, MIDWP

(2) The following program stores the number of characters corresponding to the value being stored in D0 from the left of the
character string data being stored at D100 to the area starting from R10 when X1C is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

b15 b8b7 b0
b15 b8b7 b0
D100 51 H (Q) 53H (S)
R10 51 H (Q) 53H (S)
D101 4EH (N) 4FH (O)
R11 4EH (N) 4FH (O)
D102 44 H (D) 48H (H)
R12 44 H (D) 48H (H)
D103 42 H (B) 41H (A)
R13 00H
D104 00H
"SQONHD"
"SQONHDAB"
D0 6
ASCII code for the 6th character

7.11.16 MIDR, MIDRP Random selection from character strings

MIDW, MIDWP Random replacement in character strings

7.11.16 MIDR, MIDRP, MIDW, MIDWP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol MIDR/MIDW.

Command
MIDR, MIDW S1 D S2

Command
MIDRP, MIDWP P S1 D S2

S1 : Character string or head number of the devices where the character string is stored (character string)
D : Head number of the devices where a character string data obtained as the result of operation will be stored (character string)
S2 : Head number of the devices where the location of the first character and the number of characters will be stored (BIN 16 bits)
• S2 : Position of first character
• S2 +1: Number of characters
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S1 –– –– ––
D –– –– –– ––
D2 –– ––

Function
MIDR
(1) Extracts the character string data of S2 +1 characters, starting from the position designated by S2 , counted from the left
end of the character string data designated by S1 , and stores the extracted data into the area starting from the device
designated by D .
b15 b8b7 b0
b15 b8b7 b0
S1 42 H (B) 41H (A)
D 46 H (F) 45 H (E)
S1 +1 44 H (D) 43H (C)
D +1 48 H (H) 47 H (G)
S1+2 46 H (F) 45H (E)
Position of the 5th D +2 00 H 49 H (I)
S1+3 48 H (H) 47H (G)
S1+4 character S2 "EFGHI"
4AH (J) 49H (I)
S1+5 00 H 4BH (K) ASCII code for the 5th character S2 +1
"ABCDEFGHIJK"
S2 5
S2 +1 5

500
 MIDR, MIDRP, MIDW, MIDWP

(2) The NULL code (00H) indicating the end of the character string is automatically added to the end of the character string.
Refer to Page 97, Section 3.2.5 for the format of the character string data.
(3) If the number of characters designated by S2 + 1 is "0", the NULL code (00H) is stored at the start of D . 1
(4) If the number of characters designated by S2 +1 is "-1", stores the data up to the final character designated by S starting
from the device designated by D .
2
b15 b8b7 b0
S1 b15 b8b7 b0
42 H (B) 41 H (A)
D 46H (F) 45 H (E)
S1 +1
S1 +2
44 H (D)
46 H (F)
43 H (C)
45 H (E)
D +1 48H (H) 47 H (G) 3
Position of D +2 4AH (J) 49 H (I)
S1 +3 48 H (H) 47 H (G)
the 5th D +3 00 H 4B H (K)
S1 +4 4A H (J) 49 H (I) character S2
S1 +5 00 H 4B H (K) "EFGHIJK"
4
"ABCDEFGHIJK"

S2 5
S2 +1 1
4
MIDW
(1) Extracts the character string data of S2 +1 characters, starting from the left end of the character string data designated by
S1 ,
6
and stores the extracted data to the character string data designated by D in the area starting from the position
designated by S2 from the left end.
Before execution 7
b15 b8b7 b0
b15 b8b7 b0 D 42H (B) 41 H (A)
S1 D +1
8
31H (1) 30H (0) 44H (D) 43 H (C)
S1 +1 33H (3) 32H (2) D +2 46H (H) 45 H (E)
S1 +2 35H (5) 34H (4) D +3 48H (H) 47 H (G)
S1 +3 37H (7) 36H (6) D +4 00H 49 H (I)
S1 +4 00H 38H (8) "ABCDEFGHI"
After execution
"012345678"
b15 b8b7 b0

7.11.16 MIDR, MIDRP, MIDW, MIDWP

7.11 Character string processing instructions
3 Position counted from the left D
S2 end of character string data 42H (B) 41H (A)
S2 +1 6 designated by D D +1 31H (1) 30H (0)
Number of characters counted D +2 33H (3) 32H (2)
from the left end of the character
string data designated by S1 D +3 35H (5) 34H (4)
D +4 00H 49H (I)
"AB012345I"
(2) The NULL code (00H) indicating the end of the character string is automatically added to the end of the character string.
Refer to Page 97, Section 3.2.5 for the format of the character string data.
(3) If the number of characters designated by S2 + 1 is "0", the NULL code (00H) is stored at the start of D .

501
 MIDR, MIDRP, MIDW, MIDWP

(4) If the number of characters designated by S2 +1 exceeds the final character from the character string data designated by
D , data will be stored up to the final character.
Before execution
b15 b8b7 b0
b15 b8b7 b0 D 42H (B) 41H (A)
S1 31H (1) 30H (0) D +1 44H (D) 43H (C)
S1 +1 33H (3) 32H (2) D +2 46H (F) 45H (E)
S1 +2 35H (5) 34H (4) D +3 48H (H) 47H (G)
S1 +3 37H (7) 36H (6) D +4 00H 49H (I)
S1 +4 00H 38H (8) "ABCDEFGHI"
"012345678" After execution
b15 b8b7 b0
Position counted from the left
S2 5 end of character string data D 42H (B) 41H (A)
S2 +1 8 designated by D D +1 44H (D) 43H (C)
Number of characters counted D +2
from the left end of character 31H (1) 30H (0)
string data designated by S1 D +3 33H (3) 32H (2)
D +4 00H 34H (4)
"ABCD01234"
Characters "35H" (5) to "37H" (7)
are not stored.

(5) If the number of characters designated by S2 +1 is "-1", stores the data up to the final character designated by S1 to the
area starting from the device designated by D .

Before execution
b15 b8b7 b0
b15 b8b7 b0 D 42H (B) 41H (A)
S1 31H (1) 30 H (0) D +1 44H (D) 43H (C)
S1 +1 33H (3) 32 H (2) D +2 46H (F) 45H (E)
S1 +2 35H (5) 34 H (4) D +3 48H (H) 47H (G)
S1 +3 00 H D +4 4AH (J) 49H (I)
"012345" D +5 00H 4B H (K)
"ABCDEFGHIJK"
Position counted from the left After execution
S2 2 end of character string data b15 b8b7 b0
S2 +1 1 designated by D
D 30H (0) 41H (A)
Number of characters counted
from the left end of character D +1 32H (2) 31H (1)
string data designated by S1 D +2 34H (4) 33H (3)
D +3 48H (H) 35H (5)
D +4 4AH (J) 49H (I)
D +5 00H 4B H (K)
"A012345HIJK"

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
For MIDR instruction
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value of S2 exceeds the number of characters specified by S1 .

The S2 +1 number of characters from position D exceeds the D device

4101 range. ––
The S2 + 0 value is 0.
"00H" does not exist in the devices specifed by S1 .

502
 MIDR, MIDRP, MIDW, MIDWP

For MIDW instruction

Q00J/
Error
code
Error details Q00/
Q01
QnH QnPH QnPRH QnU LCPU
1
The value of S2 exceeds the number of characters specified by D .

4101
The
The
S2

S2
+1 value exceeds the number of characters for
+0 value is 0.
S1 .
–– 2
"00H" does not exist in the devices specifed by S1 .

3
Program Example
(1) The following program stores the 3rd character through the 6th character from the left of the character string stored in the
area starting from D10 at devices starting from D0 when X0 is turned ON.
4
[Ladder Mode] [List Mode]

Step Instruction Device 4

6
[Operation]

D10
b15
41 H (A)
b8b7
42 H (B)
b0
D0
b15
31 H (1)
b8b7
32 H (2)
b0
7
D11 31 H (1) 32 H (2) D1 46 H (E) 33 H (3)
D12 46 H (E) 33 H (3) D2 00 H
D13 00 H 45 H (D) "213E" 8
"BA213ED"

R0 3
R1 4
(2) The following program stores 4 characters of the character string data stored in the area starting from D0 into the area

7.11.16 MIDR, MIDRP, MIDW, MIDWP

7.11 Character string processing instructions
starting from the 3rd character from the left of the character string data in the area starting from D100 when X0 is turned
ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Before execution
b15 b8b7 b0 b15 b8b7 b0
D0 31H (3) 32H (2) D100 53H (S) 55H (U)
D1 45H (E) 46H (F) D101 59H (Y) 43H (C)
D2 33H (3) 30H (0) D102 31H (1) 5AH (Z)
D3 00H D103 42H (B) 30H (0)
"21FE03" D104 00H
"USCYZ10B"
R0 3
After execution
R1 4 b15 b8b7 b0
D100 53H (S) 55H (U)
D101 31H (1) 32H (2)
D102 45H (E) 46H (F)
D103 42H (B) 30H (0)
D104 00H
"US21FE0B"

503
 INSTR, INSTRP
7.11.17 INSTR, INSTRP Character string search

7.11.17 INSTR, INSTRP Basic High

performance Process Redundant Universal LCPU

Command
INSTR INSTR S1 S2 D n

Command
INSTRP INSTRP S1 S2 D n

S1 : Character string to be searched or head number of the devices where the character string to be searched is stored (character string)
S2 : Character string in which a search is performed or head number of the devices where the character string is stored (character string)
D : Head number of the devices where the result of search will be stored (BIN 16 bits)
n : Location to start the search (BIN 16 bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $
S1 –– –– –– ––
D2 –– –– –– ––

D –– –– ––
n –– ––

Function
(1) Searches for the character string data designated by S1 in the area starting from the nth character from the left of the
character string data designated by S2 and stores the result of search at the device designated by D .
As the result of search, the location of match, counted in the number of characters from the first character of the
character string data designated by S2 , is stored.
When n 3
b15 b8b7 b0 b15 b8b7 b0
S2 42H (B) 41 H (A) Searches from the S1 46 H (F) 45 H (E)
S2 +1 44H (D) 43 H (C) 3rd character S1 +1 48 H (H) 47 H (G)
S2 +2 46H (F) 45 H (E) 5th character from S1 +2 00H
S2 +3 48H (H) 47H (G) the first character
"EFGH"
S2 +4 4AH (J) 49 H (I)
S2 +5 00 H 4B H (K)
"ABCDEFGHIJK"
D 5 Stores the position of the
found character, counted
by the number of characters
from the 1st character in
the character string data
designated by S2 .

(2) If there is no matching character string data, stores "0" at D .

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value of n exceeds the number of characters for S2 .
00H (NULL) does not exist within the corresponding device range after
4100 ––
the device specified by S1 and S2 .
n is negative or 0.

504
 INSTR, INSTRP

Program Example
1
(1) The following program searches from the 5th character from the left of the character string data stored in devices starting
from R0 for the character string data in devices starting from D0, and stores the results at D100 when X0 goes ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
[Operation]
b15 b8b7 b0
Not searched since
b15 b8b7 b0 4
R0 49H (I) 43 H (C) the search start D0 49H (I) 43H (C)
R1 33H (3) 32 H (2) position is 5 D1 33H (3) 32H (2)
R2 32H (2) 31 H (1) Searches from D2 00 H
R3 49H (I) 43 H (C) the 5th character
"CI23" 4
R4 00H 4DH (M)
"CI2312CIM"

D100 0 6
Stores "0" because there are no matches.

(2) The following program searches from the 3rd character from the left of the character string data being stored in devices
starting from D0 for the character string data "AB", and stores the results of the search at D100 when X1C goes ON. 7
[Ladder Mode] [List Mode]

8
Step Instruction Device

[Operation]

7.11.17 INSTR, INSTRP

7.11 Character string processing instructions
b15 b8b7 b0
D0 32H (2) 31H (1) Searches from the
D1 34H (4) 33H (3) 3rd character "AB" D100 5
D2 42H (B) 41H (A) 5th character from
the first character
D3 36H (6) 35H (5)
D4 42H (B) 41H (A)
D5 00H

505
 STRINS, STRINSP

7.11.18 STRINS, STRINSP Insertion of character string

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.11.18 STRINS, STRINSP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

Command
STRINS STRINS S D n

Command
STRINSP STRINSP S D n

S : Character string to be inserted or head number (character string) of the devices where insert character strings are stored
D : Head number (character string) of the devices where insert character strings are stored
n : Insert position (Setting range: 1 n 16383) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $
S –– –– –– ––

D –– –– –– –– ––
n –– –– ––

Function
(1) This instruction inserts the character string data specified by S to the nth device (insert position) from the initial character
string data stored in the devices specified by D.

Insert position: n 3
b15 b8b7 b0 Shifts the third character
S 31 H (1) 30 H (0) and up by the number of
b15 b8b7 b0
S +1 33 H (3) 32 H (2) characters specified by
S to the left and inserts D 42 H (B) 41H (A)
S +2 00 H 34 H (4) D +1 ( S )
the character string data 31 H (1) 30H (0)
specified by S . D +2 33 H (3) 32H (2) ( S +1)
D +3 43 H (C) 34H (4) ( S +2)
b15 b8b7 b0
D D +4 45 H (E) 44H (D)
42 H (B) 41H (A)
D +1 D +5 47 H (G) 46H (F)
44 H (D) 43H (C) Third character insertion
D +2 position D +6 00 H 48H (H)
46 H (F) 45H (E)
D +3 D +7 66 H (f) 65H (e)
48 H (H) 47H (G)
D +4 00 H
D +5 The character data stored after
62 H (b) 61H (a)
D +4 will be written over in
D +6 64 H (d) 63H (c) accordance with the number of
D +7 66 H (f) 65H (e) characters to be inserted.

(2) This instruction stores the NULL code (00H) into the device (1 word) that positions after the last device where the
character string data are stored, if the character string ( S + D ) value is even after the insertion.
(3) This instruction stores the NULL code (00H) into the last device (high 8 bits) where the character string data are stored, if
the character string ( S + D ) value is odd after the insertion.
(4) This instruction links the device, where the character string data are stored, specified by S with the last device specified
by D , if n is specified by the number of devices specified by D plus one.

506
 STRINS, STRINSP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The number of characters in the devices specified by S , D , or the
devices specified by ( S + D ) after the insertion exceeds 16383 3
characters.
4100 The value specified in n is not within the specified range. –– –– –– ––
(1 n 16383) 4
The value specified in n exceeds the number of characters of the
character string D + 1.
The devices, that store character strings, specified by S overlaps with
4
even one of the devices specified by D .
The range of the devices specified by ( S + D ) in which character strings
data have been inserted exceeds the specified device range.
4101
The NULL code (00H) does not exist within the specified device range
–– –– –– –– 6
after the device specified by S or D .
The device where the character has been inserted is the same as the
device storing the character strings. 7

Program Example 8
(1) The following program inserts the character string data stored in the device D0 and up to the fourth device from the initial
character string data stored in D20 and up, when M0 is turned on.
[Ladder Mode] [List Mode]

7.11.18 STRINS, STRINSP

7.11 Character string processing instructions
Step Instruction Device

[Operation]

Before insertion
D0 38 H (8) 35 H (5) D20 52 H (R) 50H (P)
D1 00 H 34 H (4) D21 47 H (G) 4FH (O)
D22 41 H (A) 52H (R)
D0 character string 584
D23 41 H (A) 4DH (M)
D24 43 H (C) 42H (B)
D25 00 H 44H (D)

D20 character string D20 character string PROGRAMABCD

Inserted between "O" and "G" Fourth character from
the left (Insert position)

After insertion
D20 52 H (R) 50H (P)
D21 35 H (5) 4FH (O)
D22 34 H (4) 38H (8)
D23 52 H (R) 47H (G)
D24 4DH (M) 41H (A)
D25 42 H (B) 41H (A)
D26 44 H (D) 43H (C)
D27 00 H

D20 character string P R O 5 8 4 G R A M A B C D

507
 STRDEL, STRDELP

7.11.19 STRDEL, STRDELP Deletion of character string

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.11.19 STRDEL, STRDELP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

Command
STRDEL STRDEL D n1 n2

Command
STRDELP STRDELP D n1 n2

D : Head number (character string) of the devices where character strings to be deleted are stored
n1 : Deletion start position (Setting range 1 n1 16383) (BIN 16 bits)
n2 : Number of characters to be deleted (Setting range 1 n2 16384-n1) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H

D –– –– –– ––
n1 –– ––
n2 –– ––

Function
(1) This instruction deletes n2 characters data in the devices specified by D starting from the device (insert position)
specified by n1.
Device position where character string data to be deleted: n1 3
Number of characters to be deleted: n2 5
Shifts the n1+n2th characters and up,
which are stored after the devices whose characters Stores the NULL code (00H) into
were deleted, by n2 characters to the right the empty devices after shifting.
b15 b8b7 b0 b15 b8b7 b0 b15 b8b7 b0
D 42 H (B) 41H (A) D 42 H (B) 41H (A) D 42 H (B) 41H (A)
Deletes n2 characters from
D +1 44 H (D) 43H (C) the n1th device and up D +1 D +1 49 H (I) 48H (H)
D +2 46 H (F) 45H (E) D +2 D +2 4BH (K) 4AH (J)
D +3 48 H (H) 47H (G) D +3 48 H (H) D +3 00 H 4CH (L)
D +4 4AH (J) 49H (I) D +4 4AH (J) 49H (I) D +4 00 H
D +5 4CH (L) 4BH (K) D +5 4CH (L) 4BH (K) D +5 00 H
D +6 00 H D +6 00 H D +6 00 H
D +7 31 H (1) 30H (0) D +7 31 H (1) 30H (0) D +7 31 H (1) 30H (0)
D +8 33 H (3) 32H (2) D +8 33 H (3) 32H (2) D +8 33 H (3) 32H (2)
D +9 35 H (5) 34H (4) n1th character D +9 35 H (5) 34H (4) D +9 35 H (5) 34H (4)
to be deleted
D The characters of the devices other than
the shifted devices do not change.

(2) This instruction stores the NULL code (00H) into the device (one word) that positions after the last device that stores the
character string data when the character string data specified by D is even, after the characters are deleted.
(3) This instruction stores the NULL code (00H) into the last device (high 8 bits) that stores the character string data when
the character string data specified by D is odd, after the characters are deleted.
(4) This instruction shifts the characters stored in the devices that position after the deleted devices by n2 characters to the
right, and then stores the NULL code (00H) into the empty device.

508
 STRDEL, STRDELP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The number of characters in the devices specified by D exceeds
16383. 3
The value specified by n1 is not within the range. (1 n1 16383)
The value specified by n1 exceeds the number of characters in the
4100 –– –– –– ––
devices specified by D . 4
The value specified in n2 exceeds the number of characters between
n1 and the last character in D .
The value specified in n2 is negative.
4
Program Example
(1) The following program deletes the fourth to the seventh characters in the character string data stored in the devices D0
6
and up, when M0 is turned on.
[Ladder Mode] [List Mode]
7
Step Instruction Device

[Operation]
D0 52 H (R) 50H (P) D0 52 H (R) 50H (P) D0 52 H (R) 50H (P)

7.11.19 STRDEL, STRDELP

7.11 Character string processing instructions
D1 47 H (G) 4FH (O) D1 47 H (G) 4FH (O) D1 44H (D) 4FH (O)
D2 41 H (A) 52H (R) D2 41 H (A) 52H (R) D2 00 H
D3 41 H (A) 4DH (M) D3 41 H (A) 4DH (M)
D0 character string PROD
D4 43 H (C) 42H (B) D4 43 H (C) 42H (B)
D5 00 H 44H (D) D5 00 H 44H (D)

D0 character string PROGRAMABCD D0 character string PROGRAMABCD

Fourth character Seven characters to be deleted
to be deleted

509
 EMOD, EMODP

7.11.20 EMOD, EMODP Floating-point data to BCD

7.11.20 EMOD, EMODP Basic High

performance Process Redundant Universal LCPU

Command
EMOD EMOD S1 S2 D

Command
EMODP EMODP S1 S2 D

S1 :32-bit floating decimal point real number data or head number of the devices where the floating decimal point real number data is stored (real number)
S2 :Decimal fraction digits data (BIN 16 bits)
D :Head number of the devices where the data after break down into BCD will be stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H E
S1 –– –– *1 –– ––
D2 –– ––

D –– –– –– –– –– –– ––

*1: Available only in multiple Universal model QCPU and LCPU

Function
(1) Dissociate the 32-bit floating decimal point data designated by S1 into BCD type floating point format based on the
decimal fraction digits specified by S2 , and stores the result into the area starting from the device designated by D .
S1 +1 S1 D Sign Positive: 0
D +1 Negative: 1
BCD
7 BCD digits
32-bit floating-point D +2 Positive: 0 floating-point
real number D +3 Sign (for exponent) format
Negative: 1
S2 Number of digits in decimal fraction
D +4 BCD exponent (0 to 38)

S1 +1 S1 D 0
3.254 27 D +1 4270H
3254270H
32-bit floating-point
D +2 0325H
real number D +3 1
S2 3 D +4 3

S2 specifies the decimal fraction digits of the 32-bit floating decimal point real number data of S1 .

In the example above, a decimal fraction digit is designated as shown below:

3.25427

S2 =3
S1 +1 S1 D 1
0 . 03542768 D +1
D 3542770H
+2
D +3 1
S2 4 D +4 4

S1 +1 S1 D 1
1 . 5 4 3 2 1E + 2 D +1
D +2 1543210H
D +3 1
S2 3 D +4 1

510
 EMOD, EMODP

(2) The 7th digit of the significant digits being stored at D +1 and D +2 is rounded off to make a 6-digit number.
S1 +1 S1 D 0
1 . 2 3456789 D +1
1234570H
1
D +2
D +3 1 123456789
S2 3 +4 Rounded off
2
D 3

1234570
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).
3
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
4
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU 4
code
Q01
The decimal fraction digit specified by S2 is not within the range
between 0 and 7. 6
4100 The 32-bit floating point real number specified by S1 is not within the ––
following range:
0. 2-126 | Device | 2128 7
The range of the device specified by D exceeds that of the
––
corresponding device.
4101
The range of the device specified by
corresponding device.
D exceeds that of the
–– –– –– –– 8
The specified device value is -0, unnormalized number, nonnumeric, or
4140 –– –– –– ––
± .

7.11.20 EMOD, EMODP

7.11 Character string processing instructions
Program Example
(1) The following program breaks down the 32-bit floating decimal point type real number data stored at D0 and D1 into BCD
according to the decimal fraction digits as designated by R10, and stores the results into the area starting from D100
when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]

D1 D0 D100 1
0.987654 D101
9876540H
D102
D103 1
R10 3 D104 4

511
 EREXP, EREXPP
7.11.21 EREXP, EREXPP From BCD format data to floating-point data

7.11.21 EREXP, EREXPP Basic High

performance Process Redundant Universal LCPU

Command
EREXP EREXP S1 S2 D

Command
EREXPP S1 S2 D
EREXPP
S1 : Head number of the devices where BCD type floating point format data is stored (BIN 16 bits)
S2 : Decimal fraction digits data (BIN 16 bits)
D : The device where the converted 32-bit floating point real number data will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– –– –– –– –– ––
D2 ––

D –– –– *1 –– ––
*1: Available only in multiple Universal model QCPU and LCPU

Function
(1) Converts the BCD type floating point data designated by S1 to the 32-bit floating decimal point real number data
according to the decimal fraction digits specified by S2 , and stores the result into the area starting from the device
designated by D .

S1 Sign Positive: 0
BCD S1 +1 Negative: 1 D +1 D
BCD 7 digits
floating-point S1 +2 Positive: 0
format S1 +3 Sign (for exponent)
Negative: 1
S1 +4 BCD exponent 32-bit floating-point
(0 to 38) real number
S2 Number of digits in decimal fraction (0 to 7)

(2) The sign at S1 and the sign for the exponent at S1 +3 is set at 0 for a positive value and at 1 for a negative value.
(3) 0 to 38 can be set for the BCD exponent of S1 +4.

(4) 0 to 7 can be set for the decimal fraction digits of S2 .

S1 1 (Sign)
BCD S1 +1 5423H D +1 D
floating-point S1 +2 3215423H (BCD 7 digits)
0321H -3.215 423E+2
format S1 +3 0 (Sign (for exponent))
S1 +4 2 (BCD exponent)

S2 6 (Number of digits in decimal fraction)

512
 EREXP, EREXPP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The data format in the device specified by S1 is not 0 or 1.
A value other than 0 to 9 exists in the each digit of S1 + 1 and S1 + 2. 3
The format designation made by S1 + 3 is not 0 or 1.
The data format in the device specified by S1 + 3 is not 0 or 1.
4100 ––
The exponent data in the device specified by S1 + 4 is not within the 4
range from 0 to 38.
The decimal fraction digit designated in S2 is not within the range from 0
to 7.
4
The range of the device specified by S1 exceeds that of the
4101 –– –– –– ––
corresponding device.

6
Program Example
(1) The following program converts the BCD type floating decimal point format data being stored in devices starting from D0
to 32-bit floating decimal point type real number data based on the decimal fraction digit being stored at D10, and stores
7
the result at D100 and D101 when X0 goes ON.
[Ladder Mode] [List Mode]
8
Step Instruction Device

7.11.21 EREXP, EREXPP

7.11 Character string processing instructions
[Operation]
D0 1
D1 4567H D101 D100
D2 1234567H (BCD 7 digits)
0123H 1. 2 3 4 5 6 7
D3 1
D4 3

D10 3

513
 SIN, SINP

7.12 Special function instructions

7.12.1 SIN, SINP SIN operation on floating-point data (Single precision)

Ver.
High
Basic performance Process Redundant Universal LCPU

7.12.1 SIN, SINP • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
SIN SIN S D

Command
SINP S D
SINP
S : Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Returns the SIN (sine) value of the angle designated at S and stores the operation result in the device number
designated at D .
S +1 S D +1 D
SIN ( )

32-bit floating-point 32-bit floating-point

real number real number
(2) Angles designated at S are set in radian units (degrees / 180).
For conversion between degrees and radian values, see the RAD and DEG instructions.
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The specified device value is -0.*2 –– ––
The specified device value is -0, unnormalized number, nonnumeric,
4140 –– –– –– ––
and ± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

514
 SIND, SINDP

Program Example
1
(1) The following program conducts a SIN operation on the angles stored in the four BCD digits from X20 to X2F and stores
the results at D0 and D1 as 32-bit floating decimal point type real numbers.
[Ladder Mode] 2
Inputs an angle used for SIN
operation ( 1 ).
Converts the input angle into
a 32-bit floating-point real 3
number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).
Executes SIN operation
using the converted radian value ( 4 ).
4

[List Mode] 4
Step Instruction Device

[Operations involved when X20 to X2F designate a value of 150]

7
D30
X2F X20 Conversion to BIN b15 b0
0 1 5 0 150
BCD value BIN BIN value 8
Conversion to floating-point
FLT

D21 D20 Conversion to radian D11 D10 SIN operation D1 D0

150 2 . 6 17994 0 . 500000

7.12.2 SIND, SINDP

7.12 Special function instructions
32-bit floating-point RAD 32-bit floating-point SIN 32-bit floating-point
real number real number real number

7.12.2 SIND, SINDP SIN operation on floating-point data (Double precision)

7.12.2 SIND, SINDP Basic High

performance Process Redundant Universal LCPU

Command
SIND SIND S D

Command
SINDP S D
SINDP
S : Angle data of which the SIN (sine) value is obtained or head number of the devices where the angle data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

Function
(1) The SIN (sine) value of the angle specified by S is calculated and its result is stored into the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
SIN ( )

64-bit floating-point 64-bit floating-point

real number real number

515
 SIND, SINDP

(2) Angles designated at S are set in radian units (degrees / 180).

For conversion between degrees and radian values, see the RADD and DEGD instructions.
(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example
(1) The following program conducts a SIN operation on the angles stored in the four BCD digits from X20 to X2F and stores
the results at D0 to D3 as 64-bit floating decimal point type real numbers.
[Ladder Mode]

Inputs an angle used for

SIN operation ( 1 ).
Converts the input angle into a
64-bit floating-point real number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).
Executes SIN operation using the
converted radian value ( 4 ).

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 150]

1 Conversion D30 2 Conversion to

X2F X20 to BIN b15 b0 floating-point D23 D22 D21 D20
0 1 5 0 150 150
BCD value BIN BIN value FLTD 64-bit floating-point
real number
3 Conversion to radian
RADD

D13 D12 D11 D10 4 SIN operation D3 D2 D1 D0

2.617994 0.500000
64-bit floating-point SIND 64-bit floating-point
real number real number

516
 COS, COSP
7.12.3 COS, COSP COS operation on floating-point data (Single precision)

Ver.
High
Basic Process Redundant Universal LCPU
1
performance

7.12.3 COS, COSP • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
COS COS S D
2
Command
COS
P S D
COSP
S : Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data is stored (real number)
3
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
Data Bit Word
R, ZR
Bit Word
U \G Zn
E
Other
4
S –– –– *1 ––

D –– –– *1 –– ––
*1: Applicable for the Universal model QCPU, LCPU. 4

Function
6
(1) Returns the COS (cosine) value of the angle designated by S and stores operation result at device number designated
by D .
S +1 S D +1 D 7
COS ( )

32-bit floating-point
real number
32-bit floating-point
real number 8
(2) Angles designated at S are set in radian units (degrees / 180).
For conversion between degrees and radian values, see the RAD and DEG instructions.
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

7.12.3 COS, COSP

7.12 Special function instructions
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The specified device value is -0.*2 –– ––
The specified device value is -0, unnormalized number, nonnumeric,
4140 –– –– –– ––
and ± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

517
 COSD, COSDP

Program Example
(1) The following program performs a COS operation on the angle data designated by the 4 BCD digits from X20 to X2F, and
stores results as 32-bit floating decimal point type real numbers at D0 and D1.
[Ladder Mode]

Inputs an angle used for COS

operation ( 1 ).
Converts the input angle into
a 32-bit floating-point real
number ( 2 ).
Converts the converted angle into
a radian value ( 3 ).
Executes COS operation
using the converted radian value ( 4 ).

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 60]

D30
X2F X20 Conversion to BIN b15 b0
0 0 6 0 60
BCD value BIN BIN value
Conversion to floating-point
FLT

D21 D20 Conversion to radian D11 D10 COS operation D1 D0

60 1 . 04 7 198 0 . 500000
32-bit floating-point RAD 32-bit floating-point COS 32-bit floating-point
real number real number real number

7.12.4 COSD, COSDP COS operation on floating-point data (Double precision)

7.12.4 COSD, COSDP Basic High

performance Process Redundant Universal LCPU

Command
COSD COSD S D

Command
COSDP S D
COSDP
S : Angle data of which the COS (cosine) value is obtained or head number of the devices where the angle data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

518
 COSD, COSDP

Function
1
(1) The COS (cosine) value of the angle specified by S is calculated and its result is stored into the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
COS ( ) 2
64-bit floating-point 64-bit floating-point
real number real number
(2) Angles designated at S are set in radian units (degrees / 180). 3
For conversion between degrees and radian values, see the RADD and DEGD instructions.
(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur. 4
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0. 6
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range: 7
4140 -102 1024 –– –– –– ––
0, 2 | Specified device value | < 2
The specified device value is -0.
The operation result exceeds the following range (when an overflow 8
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example

7.12.4 COSD, COSDP

7.12 Special function instructions
(1) The following program performs a COS operation on the angle data designated by the 4 BCD digits from X20 to X2F, and
stores results as 64-bit floating decimal point type real numbers at D0 to D3.
[Ladder Mode]

Inputs an angle used for

COS operation ( 1 ).
Converts the input angle into a
64-bit floating-point real number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).
Executes COS operation using the
converted radian value ( 4 ).

[List Mode]

Step Instruction Device

519
 TAN, TANP

[Operations involved when X20 to X2F designate a value of 60]

1 Conversion D30 2 Conversion to

X2F X20 to BIN b15 b0 floating-point D23 D22 D21 D20
0 0 6 0 60 60
BCD value BIN BIN value FLTD 64-bit floating-point
real number
3 Conversion to radian
RADD

D13 D12 D11 D10 4 SIN operation D3 D2 D1 D0

1.047198 0.500000
64-bit floating-point COSD 64-bit floating-point
real number real number

7.12.5 TAN, TANP TAN operation on floating-point data (Single precision)

Ver.
High
Basic Process Redundant Universal LCPU

7.12.5
performance

TAN, TANP • Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
TAN TAN S D

Command
TANP S D
TANP
S : Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––
D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Returns the tangent (TAN) value of the angle data designated by S , and stores operation result in device designated by
D .
S +1 S D +1 D
TAN ( )

32-bit floating-point 32-bit floating-point

real number real number
(2) Angles designated at S are set in radian units (degrees / 180).
For conversion between degrees and radian values, see the RAD and DEG instructions.
(3) When angles designated by S are /2 radians, or (3/2) radians, an operation error will be generated in the calculation
of the radian value, so care must be taken to avoid such errors.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

520
 TAN, TANP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The specified device value is not within the following range:
4100 0, 2-126 | Specified device value | < 2128 –– –– 3
*2
The specified device value is -0.
The specified device value is -0, unnormalized number, nonnumeric,
4140 –– –– –– ––
and ± . 4
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
4
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

6
Program Example
(1) The following program performs a TAN operation on the angle data set by the 4 BCD digits from X20 to X2F, and stores
the results as 32-bit floating decimal point type real numbers at D0 and D1. 7
[Ladder Mode]

Inputs an angle used for TAN 8

operation ( 1 ).
Converts the input angle into a 32-bit
floating-point real number ( 2 ).
Converts the converted angle
into a radian value ( 3 ).

7.12.5 TAN, TANP

7.12 Special function instructions
Executes TAN operation using
the converted radian value ( 4 ).

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 135]

D30
X2F X20 Conversion to BIN b15 b0
0 1 3 5 135
BCD value BIN BCD value
Conversion to floating-point
FLT

D21 D20 Conversion to radian D11 D10 TAN operation D1 D0

135 2 . 356 194 1 . 000000
32-bit floating-point RAD 32-bit floating-point TAN 32-bit floating-point
real number real number real number

521
 TAND, TANDP
7.12.6 TAND, TANDP TAN operation on floating-point data (Double precision)

7.12.6 TAND, TANDP Basic High

performance Process Redundant Universal LCPU

Command
TAND TAND S D

Command
TANDP S D
TANDP
S : Angle data of which the TAN (tangent) value is obtained or head number of the devices where the angle data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

Function
(1) The TAN (tangent) value of the angle specified by S is calculated and its result is stored into the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
TAN ( )
64-bit floating-point 64-bit floating-point
real number real number
(2) Angles designated at S are set in radian units (degrees / 180).
For conversion between degrees and radian values, see the RADD and DEGD instructions.
(3) When angles designated by S are /2 radians, or (3/2) radians, an operation error will be generated in the calculation
of the radian value, so care must be taken to avoid such errors.
(4) When the operation results in -0 or an underflow, the result is processed as 0.
(5) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

522
 ASIN, ASINP

Program Example
1
(1) The following program performs a TAN operation on the angle data set by the 4 BCD digits from X20 to X2F, and stores
the results as 64-bit floating decimal point type real numbers at D0 to D3.
[Ladder Mode] 2
Inputs an angle used for TAN
operation ( 1 ).
Converts the input angle into a 3
64-bit floating-point real number ( 2 ).
Converts the converted angle into a
radian value ( 3 ).
Executes TAN operation using the 4
converted radian value ( 4 ).

[List Mode] 4
Step Instruction Device

[Operations involved when X20 to X2F designate a value of 135] 7

1 Conversion D30 2 Conversion to
X2F X20 to BIN b15 b0 floating-point D23 D22 D21 D20
0 1 3 5
BCD value BIN
135
BIN value FLTD
135
64-bit floating-point 8
real number
3 Conversion to radian
RADD

7.12.7 ASIN, ASINP

7.12 Special function instructions
D23 D22 D21 D20 4 TAN operation D23 D22 D21 D20
2.356194 -1.000000
64-bit floating-point TAND 64-bit floating-point
real number real number

7.12.7 ASIN, ASINP Arc sine operation on floating-point data (Single

precision)

7.12.7 ASIN, ASINP Basic High

performance Process Redundant Universal LCPU

Command
ASIN ASIN S D

Command
ASINP S D
ASINP
S : SIN value of which the SIN-1 (inverse sine) value is obtained or head number of the devices where the SIN value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
–– –– *1 ––
S

–– –– *1 –– ––
D
*1: Applicable for the Universal model QCPU, LCPU.

523
 ASIN, ASINP

Function
(1) Returns the SIN-1 angle of the SIN value designated by S , and stores operation results at word device designated by D .
S +1 S D +1 D
-1
SIN ( )

32-bit floating-point 32-bit floating-point

real number real number
(2) The SIN value designated by S can be in the range from -1.0 to 1.0.
(3) The angle (operation result) stored at D is stored in radian units.
For more information on the conversion between radian and angle data, see description of RAD and DEG instructions.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified by S is not within the range between -1.0 and 1.0. ––
4100
*2 –– –– ––
The specified device value is -0.
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .
The result exceeds the following range (when an overflow occurs):
4141 –– –– –– ––
2128 | Operation result |
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

Program Example
(1) The following program seeks the inverse sine of the 32-bit floating decimal point real number at D0 and D1, and outputs
the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode]

Calculates an angle (radian value)

by SIN-1 operation ( 1 )
Converts the radian value
into an angle ( 2 )
Converts the angle in
32-bit floating-point real
number into an integer ( 3 )
Outputs the integer-converted
angle to a display device ( 4 )

[List Mode]

Step Instruction Device

524
 ASIND, ASINDP

[Operations involved when the D0 and D1 value is 0.5]

D1 D0 SIN-1 operation D11 D10

0.5 0 . 5235988 1
32-bit floating-point ASIN 32-bit floating-point
real number real number
Conversion to angle
DEG 2
Conversion D30
D21 D20 b15 b0 BCD operation Y4F Y40
to BIN
30 30 0 0 3 0
32-bit floating-point INT BIN value BCD BCD value 3
real number

4
7.12.8 ASIND, ASINDP Arc sine operation on floating-point data (Double
precision)

7.12.8 ASIND, ASINDP Basic High

performance Process Redundant Universal LCPU

Command 4
ASIND ASIND S D

Command
ASINDP ASINDP S D
6
S : SIN value of which the SIN-1 (inverse sine) value is obtained or head number of the devices where the SIN value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other
7
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– –– 8

Function
(1) The angle is calculated from the SIN (sine) value specified by S is and its result is stored into the device specified by D .

7.12.8 ASIND, ASINDP

7.12 Special function instructions
S +3 S +2 S +1 S D +3 D +2 D +1 D
1
SIN ( )
64-bit floating-point 64-bit floating-point
real number real number

(2) The SIN value designated by S can be in the range from -1.0 to 1.0.
(3) The angle (operation result) stored at D is stored in radian units.
For more information on the conversion between radian and angle data, see description of RADD and DEGD
instructions.
(4) When the operation results in -0 or an underflow, the result is processed as 0.
(5) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

525
 ASIND, ASINDP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified by S is within the double-precision floating-point
4100 –– –– –– ––
range and not within the range between -1.0 and 1.0.
The specified device value is not within in the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example
(1) The following program seeks the inverse sine of the 64-bit floating decimal point real number at D0 to D3, and outputs
the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode]

Calculates an angle (radian value)

by SIN 1 operation ( 1 ).
Converts the radian value into
an angle ( 2 ).
Converts the angle in 64-bit floating-point
real number into an integer ( 3 ).
Outputs the integer-converted angle to a
display device ( 4 ).

[List Mode]

Step Instruction Device

[Operations involved when the D0 to D3 value is 0.5]

D3 D2 D1 D0 1 SIN 1 operation D13 D12 D11 D10

0.5 0.5235988
64-bit floating-point ASIND 64-bit floating-point
real number real number
2 Conversion to angle
DEGD

3 Conversion D30
D23 D22 D21 D20 to BIN b15 b0 4 BCD operation Y4F Y40
30 30 0 0 3 0
64-bit floating-point INTD BIN value BCD BCD value
real number

526
 ACOS, ACOSP
7.12.9 ACOS, ACOSP Arc cosine operation on floating-point data (Single
precision)

7.12.9 ACOS, ACOSP Basic High

Process Redundant Universal LCPU
1
performance

Command
ACOS ACOS S D

Command
ACOSP S D
2
ACOSP
S : COS value of which the COS-1 (inverse cosine) value is obtained or head number of the devices where the COS value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number) 3
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 –– 4
D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

4
Function
(1) Returns the COS-1 angle of the COS value designated by S , and stores operation result at word device designated by 6
D .
S +1 S D +1 D
COS -1 ) 7
32-bit floating-point 32-bit floating-point
real number real number
(2) The COS value designated by S can be in the range of from -1.0 to 1.0. 8
(3) The angle (operation result) stored at D is stored in radian units.
For more information on the conversion between radian and angle data, see description of RAD and DEG instructions.
(4) When an input value is set using a programming tool, a rounding error may occur.

7.12.9 ACOS, ACOSP

7.12 Special function instructions
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified in S is not within the range between -1.0 and 1.0. ––
4100
*2 –– –– ––
The specified device value is -0.
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

527
 ACOSD, ACOSDP

Program Example
(1) The following program seeks the inverse cosine of the 32-bit floating decimal point real number at D0 and D1, and
outputs the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode]

Calculates an angle (radian value)

by COS-1 operation ( 1 )
Converts the radian value into an angle ( 2 )

Converts the angle in 32-bit floating-point

real number into an integer ( 3 )
Outputs the integer-converted angle
to a display device ( 4 )

[List Mode]

Step Instruction Device

[Operations involved when the D0 and D1 value is 0.5]

D1 D0 COS-1 operation D11 D10
0.5 1 . 04 7 198
32-bit floating-point ACOS 32-bit floating-point
real number real number
Conversion to angle
DEG

Conversion D30
D21 D20 to BIN b15 b0 BCD operation Y4F Y40
60 60 0 0 6 0
32-bit floating-point INT BIN value BCD BCD value
real number

7.12.10 ACOSD, ACOSDP Arc cosine operation on floating-point data (Double

precision)

7.12.10 ACOSD, ACOSDP Basic High

performance Process Redundant Universal LCPU

Command
ACOSD ACOSD S D

Command
ACOSDP S D
ACOSDP
S : COS value of which the COS-1 (inverse cosine) value is obtained or head number of the devices where the COS value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

528
 ACOSD, ACOSDP

Function
1
(1) The angle is calculated from the COS (cosine) value specified by S is and its result is stored into the device specified by
D .

1
S +3 S +2 S +1 S D +3 D +2 D +1 D 2
COS ( )
64-bit floating-point 64-bit floating-point
real number real number
3
(2) The COS value designated by S can be in the range of from -1.0 to 1.0.
(3) The angle (operation result) stored at D is stored in radian units.
For more information on the conversion between radian and angle data, see description of RADD and DEGD 4
instructions.
(4) When the operation results in -0 or an underflow, the result is processed as 0.
(5) When an input value is set using a programming tool, a rounding error may occur. 4
For precautions, refer to Page 95, Section 3.2.4 (3).

6
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0. 7
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
8
The value specified in S is within the double-precision floating-point
4100 –– –– –– ––
range and not within the range from -1.0 to 1.0.
The specified device value is not in the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.

7.12.10 ACOSD, ACOSDP

7.12 Special function instructions
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example
(1) The following program seeks the inverse cosine of the 64-bit floating decimal point real number at D0 to D3, and outputs
the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode]

1
Calculates an angle (radian value) by COS
operation ( 1 ).
Converts the radian value into an angle ( 2 ).

Converts the angle in 64-bit floating-point

real number into an integer ( 3 ).
Outputs the integer-converted angle to a
display device ( 4 ).

[List Mode]

Step Instruction Device

529
 ATAN, ATANP

[Operations involved when the D0 to D3 value is 0.5]

D3 D2 D1 D0 1 COS 1 operation D13 D12 D11 D10

0.5 1.047198
64-bit floating-point ACOSD 64-bit floating-point
real number real number
2 Conversion to angle
DEGD

3 Conversion D30
D23 D22 D21 D20 to BIN b15 b0 4 BCD operation Y4F Y40
60 60 0 0 6 0
64-bit floating-point INTD BIN value BCD BCD value
real number

7.12.11 ATAN, ATANP Arc tangent operation on floating-point data (Single

precision)

7.12.11 ATAN, ATANP Basic High

performance Process Redundant Universal LCPU

Command
ATAN ATAN S D

Command
ATANP S D
ATANP
S : TAN value of which the TAN-1 (inverse tangent) value is obtained or head number of the devices where the TAN value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Returns the TAN-1 angle of the TAN value designated by S , and stores operation results at word device designated by
D .
S +1 S D +1 D
-1
TAN ( )

32-bit floating-point 32-bit floating-point

real number real number
(2) The angle (operation result) stored at D is stored in radian units.
For more information on the conversion between radian and angle data, see description of RAD and DEG instructions.
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

530
 ATAN, ATANP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
4100 The specified device value is -0.*2 –– –– ––
The specified device value is not within the following range: 3
0, 2-126 | Specified device value | < 2 128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± . 4
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
4
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

6
Program Example
(1) The following program seeks the inverse tangent of the 32-bit floating decimal point real number at D0 and D1, and
outputs the angle to the 4 BCD digits at Y40 to Y4F. 7
[Ladder Mode]

Calculates an angle (radian value)

by TAN-1 operation ( 1 )
8
Converts the radian value
into an angle ( 2 )
Converts the angle in
32-bit floating-point real
number into an integer ( 3 )

7.12.11 ATAN, ATANP

7.12 Special function instructions
Outputs the integer-converted
angle to a display device ( 4 )

[List Mode]

Step Instruction Device

[Operations involved when D0 and D1 value is 1]

D1 D0 -1
TAN operation D11 D10
1 0 . 785398
32-bit floating-point ATAN 32-bit floating-point
real number real number
Conversion to angle
DEG

D30
D21 D20 Conversion to BIN b15 b0 BCD operation Y4F Y40
45 45 0 0 4 5
32-bit floating-point INT BIN value BCD BCD value
real number

531
 ATAND, ATANDP
7.12.12 ATAND, ATANDP Arc tangent operation on floating-point data
(Double precision)

7.12.12 ATAND, ATANDP Basic High

performance Process Redundant Universal LCPU

Command
ATAND ATAND S D

Command
ATANDP S D
ATANDP
S : TAN value of which the TAN-1 (inverse tangent) value is obtained or head number of the devices where the TAN value is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

Function
(1) The angle is calculated from the TAN (tangent) value specified by S is and its result is stored into the device specified by
D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
1
TAN ( )
64-bit floating-point 64-bit floating-point
real number real number
(2) The angle (operation result) stored at D is stored in radian units.
For more information on the conversion between radian and angle data, see description of RADD and DEGD
instructions.
(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

532
 RAD, RADP

Program Example
1
(1) The following program seeks the inverse tangent of the 64-bit floating decimal point real number at D0 to D3, and outputs
the angle to the 4 BCD digits at Y40 to Y4F.
[Ladder Mode] 2
1
Calculates an angle (radian value) by TAN
operation ( 1 ).
Converts the radian value into 3
an angle ( 2 ).
Converts the angle in 64-bit floating-point
real number into an integer ( 3 ).
Outputs the integer-converted angle 4
to a display device ( 4 ).

[List Mode] 4
Step Instruction Device

[Operations involved when D0 to D3 value is 1] 7

D3 D2 D1 D0 1 TAN 1 operation D13 D12 D11 D10
1 0.785398
64-bit floating-point ATAND 64-bit floating-point 8
real number real number
2 Conversion to angle
DEGD

3 Conversion D30
D23 D22 D21 D20 to BIN b15 b0 4 BCD operation Y4F Y40

7.12.13 RAD, RADP

7.12 Special function instructions
45 45 0 0 4 5
64-bit floating-point INTD BIN value BCD BCD value
real number

7.12.13 RAD, RADP Conversion from floating-point angle to radian

(Single precision)

Ver.
High
Basic Process Redundant Universal LCPU

7.12.13 RAD, RADP

performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
RAD RAD S D

Command
RADP S D
RADP
S : Angle to be converted to radian units or head number of the devices where the angle is stored (real number)
D : Head number of the devices where the value converted in radian units will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

533
 RAD, RADP

Function
(1) Converts units of angle size from angle units designated by S to radian units, and stores result at device number
designated by D .
S +1 S D +1 D
( ) ( )rad

32-bit floating-point 32-bit floating-point

real number real number
(2) Conversion from degree to radian units is performed according to the following equation:

Radian unit = Degree unit

180
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The specified device value is -0.*2 –– ––
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
*2: There are CPU modules that will not result in an operation error if 0 is specified.
For details, refer to Page 93, Section 3.2.4.

Program Example
(1) The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians, and stores results as 32-bit
floating decimal point type real number at D20 and D21.
[Ladder Mode]

Inputs an angle to be converted

into a radian value ( 1 )
Converts the input a 32-bit
floating-point real number ( 2 )
Converts the converted angle into
a radian value ( 3 )

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 120]

Conversion D0 Conversion to Conversion
X2F X20 to BIN b15 b0 floating-point D11 D10 to radian D21 D20
0 1 2 0 120 120 2 . 094395
BCD value BIN BIN value FLT RAD

534
 RADD, RADDP
7.12.14 RADD, RADDP Conversion from floating-point angle to radian
(Double precision)

7.12.14 RADD, RADDP Basic High

Process Redundant Universal LCPU
1
performance

Command
RADD RADD S D

RADDP
Command
RADDP S D 2
S : Angle to be converted to radian units or head number of the devices where the angle is stored (real number)
D : Head number of the devices where the value converted in radian units will be stored (real number) 3
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––
4
D –– –– –– ––

Function 4
(1) The unit expressing the size of an angle is converted into the radian unit from the degree unit specified by S , and its
result is stored into the device specified by D . 6
S +3 S +2 S +1 S D +3 D +2 D +1 D
( ) ( )rad

64-bit floating-point 64-bit floating-point 7

real number real number
(2) Conversion from degree to radian units is performed according to the following equation:

Radian unit = Degree unit 8

180
(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

7.12.14 RADD, RADDP

7.12 Special function instructions
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

535
 DEG, DEGP

Program Example
(1) The following program converts the angle set by the 4 BCD digits at X20 to X2F to radians, and stores results as 64-bit
floating decimal point type real number at D20 to D23.
[Ladder Mode]

Inputs an angle to be converted into a

radian value ( 1 ).
Converts the input angle into a 64-bit
floating-point real number ( 2 ).
Converts the converted angle into a
radian value ( 3 ).

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2F designate a value of 120]

1 Conversion D0 2 Conversion to 3 Conversion
X2F X20 to BIN b15 b0 floating-point D13 D12 D11 D10 to radian D23 D22 D21 D20
0 1 2 0 120 120 2.094395···
BCD value BIN BIN value FLTD RADD

7.12.15 DEG, DEGP Conversion from floating-point radian to angle

(Single precision)

Ver.
High
Basic Process Redundant Universal LCPU

7.12.15 DEG, DEGP

performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
DEG DEG S D

Command
DEGP S D
DEGP
S : Radian angle to be converted to degrees or head number of the devices where the radian angle is stored (real number)
D : Head number of the devices where the value converted in degrees will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––

D –– –– *1 –– ––
*1: Applicable for the Universal model QCPU, LCPU.

Function
(1) Converts units of angle size from radian units designated by S to angles, and stores result at device number designated
by D .
S +1 S D +1 D
( )rad (

32-bit floating-point 32-bit floating-point

real number real number
(2) The conversion from radians to angles is performed according to the following equation:

Degree unit = Radian unit 180

(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

536
 DEGD, DEGDP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
4100 The specified device value is -0.*2 –– ––

4140
The specified device value is -0, unnormalized number, nonnumeric,
–– –– –– ––
3
and ± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– –– 4
2128 | Operation result |
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.
4
Program Example
(1) The following program converts the radian value set with 32-bit floating decimal point type real number at D20 and D21 6
to angles, and stores the result as a BCD value at Y40 to Y4F.
[Ladder Mode]
7
Converts a radian value into
an angle ( 1 )
Converts the angle in
32-bit floating-point real 8
number into an integer ( 2 )
Outputs the converted integer
to a display device ( 3 )

[List Mode]

7.12.16 DEGD, DEGDP

7.12 Special function instructions
Step Instruction Device

[Operations involved when the values at D20 and D21 are 1.435792]
Conversion Conversion D0
D21 D20 to angle D11 D10 to BIN b15 b0 BCD operation Y4F Y40
1 . 435792 82 . 26482 82 0 0 8 2
32-bit floating-point DEG 32-bit floating-point BIN BIN value BCD BCD value
real number real number
7.12.16 DEGD, DEGDP Conversion from floating-point radian to angle
(Double precision)

7.12.16 DEGD, DEGDP Basic High

performance Process Redundant Universal LCPU

Command
DEGD DEGD S D

Command
DEGDP S D
DEGDP
S : Radian angle to be converted to degrees or head number of the devices where the radian angle is stored (real number)
D : Head number of the devices where the value converted in degrees will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

537
 DEGD, DEGDP

Function
(1) The unit expressing the size of an angle is converted into the degree unit from the radian unit specified by S , and its
result is stored into the device specified by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
( )rad ( )

64-bit floating-point 64-bit floating-point

real number real number
(2) The conversion from radians to angles is performed according to the following equation:

Degree unit = Radian unit 180

(3) When the operation results in -0 or an underflow, the result is processed as 0.

(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example
(1) The following program converts the radian value set with 64-bit floating decimal point type real number at D20 to D23 to
angles, and stores the result as a BCD value at Y40 to Y4F.
[Ladder Mode]

Converts a radian value into an angle ( 1 ).

Converts the angle in 64-bit floating-point

real number into an integer ( 2 ).
Outputs the converted integer to a display
device ( 3 ).

[List Mode]

Step Instruction Device

[Operations involved when the values at D20 to D23 are 1.435792]

1 Conversion 2 Conversion D0
D23 D22 D21 D20 to angle D13 D12 D11 D10 to BIN b15 b0 3 BCD operation Y4F Y40
1.435792 82.26482 82 0 0 8 2
64-bit floating-point DEGD 64-bit floating-point INTD BIN value BCD BCD value
real number real number

538
 POW, POWP
7.12.17 POW, POWP Exponentiation operation on floating-point data
(Single precision)

Ver.
High
Basic Process Redundant Universal LCPU
1
performance

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.12.17 POW, POWP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

Command 2
POW POW S1 S2 D

Command
POWP POWP S1 S2 D
3
S1 : Exponentiation recipient data or head number of the devices where the exponentiation recipient data are stored (real number)
: Exponentiation data or head number of the devices where the data are stored (real number)
4
S2

D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S1 –– –– *1 –– 4
S2 –– –– *1 ––

D –– –– –– ––

*1: Available only for real number

6

Function 7
(1) This instruction raises the 32-bit floating-point data type real number specified by S1 to the number nth specified by S2

power, and then stores the operation result into the device specified by D .
Exponentiation data
8
S2 +1 S2

S1 +1 S1 D +1 D

Exponentiation recipient data

7.12.17 POW, POWP

7.12 Special function instructions
S1 +1 S1 S1 +1 S1 S1 +1 S1 S1 +1 S1

The instruction raises S1 +1 S1 to S2 +1 S2 th power.

32-bit floating-point 32-bit floating-point

data type real number data type real number

(2) The following shows the values to be specified by and stored into S1 or S2 .

0, 2-126 | Set values (Storage values) | < 2128

(3) If the value resulted from the operation is -0 or an underflow occurs, the result will be processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

539
 POW, POWP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The values specified by S1 or S2 is not within the following range:
4140 0, 2-126 |Specified value (storage value)| < 2128 –– –– –– ––
The value of S1 or S2 is -0.
The operation result is within the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |

Program Example
(1) The following program raises the 32-bit floating-point data type real number data specified by D0 and D1 to the data
specified by (D10 and D11)th power, when X10 is turned on. Then the program stores the operation result into D20 and
D21.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]

D11 D10
1.2
D1 D0 Exponentiation D21 D20
operation
0.22 0.163

540
 POWD, POWDP

7.12.18 POWD, POWDP Exponentiation operation on floating-point data

(Double precision)

Ver.
Basic High
performance Process Redundant Universal LCPU 1
• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.12.18 POWD, POWDP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported
2
Command
POWD POWD S1 S2 D

Command
3
POWDP POWDP S1 S2 D

S1

S2
: Exponentiation recipient data or head number of the devices where the exponentiation recipient data are stored (real number)
: Exponentiation data or head number of the devices where the data are stored (real number)
4
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
Data Bit Word
R, ZR
Bit Word
U \G Zn
E
Other
4
S1 –– –– *1 ––
S2 –– –– *1 ––

D –– –– –– –– 6
*1: Available only for real number

Function 7
(1) This instruction raises the 64-bit floating-point data type real number specified by S1 to the number nth specified by S2

power, and then stores the operation result into the device specified by D . 8
Exponentiation data
S2 +3 S2 +2 S2 +1 S2

S1 +3 S1 +2 S1 +1 S1 D +3 D +2 D +1 D

Exponentiation recipient data

7.12.18 POWD, POWDP

7.12 Special function instructions
S1 +3 S1 +2 S1 +1 S1 S1 +3 S1 +2 S1 +1 S1 S1 +3 S1 +2 S1 +1 S1

S1 +3 S1 +2 S1 +1 S1 raised to the power of S2 +3 S2 +2 S2 +1 S2 is carried out.

64-bit floating-point data type real number 64-bit floating-point data type real number

(2) The following shows the values to be specified by and stored into S1 or S2

-1022 1024
0, 2 | Set values (Storage values) | < 2
(3) If the value resulted from the operation is -0 or an underflow occurs, the result will be processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

541
 SQR, SQRP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified by S1 or S2 is out of the range shown below.
4140 0, 2-1022 | Set value (storage value) | < 21024 –– –– –– ––
The value of S1 or S2 is -0.
The operation result is within the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example
(1) The following program raises the 64-bit floating-point data type real number specified by D200 to D203 to the number nth
specified by D0 to D3 power, when X10 is turned on. Then the program stores the operation result into D100 to D103.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D3 D2 D1 D0
Exponentiation
3
operation
D203 D202 D201 D200 D103 D102 D101 D100

15.6 3796.416

7.12.19 SQR, SQRP Square root operation for floating-point data

(Single precision)

Ver.
High
Basic Process Redundant Universal LCPU

7.12.19 SQR, SQRP

performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
SQR SQR S D

Command
SQRP S D
SQRP
S : Data of which the square root is obtained or head number of the devices where the data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

542
 SQR, SQRP

Function
(1) Returns the square root of the value designated at S , and stores the operation result in the device number designated at
1
D .

S +1 S D +1 D 2
( )

32-bit floating-point 32-bit floating-point

real number real number 3
(2) Only positive values can be designated by S . (Operation cannot be performed on negative numbers.)
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3). 4

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

Error
Q00J/ 6
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified in is negative. ––
7
S
4100
The specified device value is -0.*2 –– ––
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140
The specified device value is -0, unnormalized number, nonnumeric, or
–– –– –– –– 8
± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |

7.12.19 SQR, SQRP

7.12 Special function instructions
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

Program Example
(1) The following program seeks the square root of the value set by the 4 BCD digits from X20 to X2F, and stores the result
as a 32-bit floating decimal point type real number at D0 and D1.
[Ladder Mode]

Inputs data used for

square root operation ( 1 )
Converts the input data into a
32-bit floating-point real number ( 2 )
Executes square root
operation ( 3 )

[List Mode]

Step Instruction Device

[Operations involved when value designated by X20 to X2F is 650]

1 Conversion D20 2 Conversion to
X2F X20 to BIN b15 b0 floating-point D11 D10 3 SQR operation D1 D0
0 6 5 0 650 650 25 . 4951
BCD value BIN BIN value FLT SQR

543
 SQRD, SQRDP
7.12.20 SQRD, SQRDP Square root operation for floating-point data
(Double precision)

7.12.20 SQRD, SQRDP Basic High

performance Process Redundant Universal LCPU

Command
SQRD SQRD S D

Command
SQRDP S D
SQRDP
S : Data of which the square root is obtained or head number of the devices where the data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

Function
(1) Returns the square root of the value designated at S , and stores the operation result in the device number designated at D .

S +3 S +2 S +1 S D +3 D +2 D +1 D
( )

64-bit floating-point 64-bit floating-point

real number real number

(2) Only positive values can be designated by S . (Operation cannot be performed on negative numbers.)
(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value specified in S is negative. –– –– –– ––
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
1024
2 | Operation result |

Program Example
(1) The following program seeks the square root of the value set by the 4 BCD digits from X20 to X2F, and stores the result
as a 64-bit floating decimal point type real number at D0 to D3.
[Ladder Mode]

Inputs data used for square root

operation ( 1 ).
Converts the input data into a 64-bit
floating-point real number ( 2 ).
Executes square root operation ( 3 ).

544
 EXP, EXPP

[List Mode]

Step Instruction Device

1

[Operations involved when value designated by X20 to X2F is 650] 2

1 Conversion D20 2 Conversion to
X2F X20 to BIN b15 b0 floating-point D13 D12 D11 D10 3 SQR operation D3 D2 D1 D0
0 6 5 0
BCD value BIN
650
BIN value FLTD
650
SQRD
25.4951
3
7.12.21 EXP, EXPP Exponent operation on floating-point data
(Single precision)

Ver.
Basic High
Process Redundant Universal LCPU
4
7.12.21 EXP, EXPP
performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

4
Command
EXP EXP S D

Command
EXPP S D
6
EXPP
S : Data of which the exponential value is obtained or head number of the devices where the data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number) 7
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– *1 –– 8
D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

Function

7.12.21 EXP, EXPP

7.12 Special function instructions
(1) Returns the exponent of the value designated by S , and stores the results of the operation at the device designated by
D .
S +1 S D +1 D

e ( )

32-bit floating-point 32-bit floating-point

real number real number
(2) Exponent operations are calculated taking the base (e) to be "2.71828".
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

545
 EXP, EXPP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The operation result is not within the following range:
–– –– –– –– ––
2-126 | Operation result | < 2128
4100 The operation result is not within the following range:
–– –– ––
2-126 | Operation result | < 2128
The specified device value is -0.*2 –– ––
The specified device value is -0, unnormalized number, nonnumeric, or
4140 –– –– –– ––
± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
128
2 | Operation result |
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

Program Example
(1) The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X27, and stores
the results as a 32-bit floating decimal point real number at D0 and D1.
[Ladder Mode]

Inputs the data used for

exponent operation ( 1 ).

Checks the range of the

value for operation. *4

Converts the input data into

a 32-bit floating-point real number ( 2 ).
Executes exponent operation ( 3 ).

[List Mode]

Step Instruction Device

[Operations involved when value designated by X20 to X27 is 13]

1 Conversion D20 2 Conversion to
X27 X20 to BIN b15 b0 floating-point D11 D10 3 EXP operation D1 D0
1 3 13 13 4 4 24 13 . 4
BCD value BIN BIN value FLT 32-bit floating-point EXP 32-bit floating-point
real number real number

*4: The operation result will be under 2129 if the BCD value of X20 to X27 is less than 89, from the calculation loge 2129 = 89.4.
Because setting a value of over 90 will return an operation error, turn M1 ON if a value of over 90 has been set to avoid the
error.

546
 EXPD, EXPDP

Conversion from natural logarithm to common logarithm

In the CPU module, calculation is made using a natural logarithm. 1
To obtain a common logarithm value, enter in, S a common logarithm value divided by 0.43429.

2
7.12.22 EXPD, EXPDP Exponent operation on floating-point data
(Double precision)

7.12.22 EXPD, EXPDP Basic High

performance Process Redundant Universal LCPU
3
Command
EXPD EXPD S D 4
Command
EXPDP S D
EXPDP
4
S : Data of which the exponential value is obtained or head number of the devices where the data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
Data Bit Word
R, ZR
Bit Word
U \G Zn
E
Other 6
S –– –– ––
–– –– –– ––
7
D

Function
(1) Returns the exponent of the value designated by S , and stores the results of the operation at the device designated by
8
D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
e ( ) ( )

7.12.22 EXPD, EXPDP

7.12 Special function instructions
64-bit floating-point 64-bit floating-point
real number real number
(2) Exponent operations are calculated taking the base (e) to be "2.71828".
(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0.
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

547
 EXPD, EXPDP

Program Example
(1) The following program performs an exponent operation on the value set by the 2 BCD digits at X20 to X31, and stores
the results as a 64-bit floating decimal point real number at D0 to D3.
[Ladder Mode]

Inputs data used for exponent

operation ( 1 ).
Checks the range of the value used
for operation. *1
Converts the input data into a 64-bit
floating-point real number ( 2 ).
Executes exponent operation ( 3 ).

[List Mode]

Step Instruction Device

[Operations involved when value designated by X20 to X31 is 13]

1 Conversion D20 2 Conversion to
X31 X20 to BIN b15 b0 floating-point D13 D12 D11 D10 3 EXP operation D3 D2 D1 D0
0 1 3 13 13 442413.4
BCD value BIN BIN value FLTD 64-bit floating-point EXPD 64-bit floating-point
real number real number
*1: The operation result will be under 21024 if the BCD value of X20 to X31 is less than 709, from the calculation
loge 21024 = 709.7832.
Because setting a value of over 710 will return an operation error, turn M0 ON if a value of over 710 has been set to avoid the
error.

Conversion from natural logarithm to common logarithm

In the CPU module, calculation is made using a natural logarithm.
To obtain a common logarithm value, enter in, S a common logarithm value divided by 0.43429.

548
 LOG, LOGP
7.12.23 LOG, LOGP Natural logarithm operation on floating-point data
(Single precision)

Ver.
High
Basic Process Redundant Universal LCPU

7.12.23 LOG, LOGP 1

performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
LOG LOG S D
2
Command
LOGP S D
LOGP
S : Data of which the natural logarithm is obtained or head number of the devices where the data is stored (real number)
3
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
Data Bit Word
R, ZR
Bit Word
U \G Zn
E
Other
4
S –– –– *1 ––

D –– –– *1 –– ––

*1: Applicable for the Universal model QCPU, LCPU.

4

Function 6
(1) Returns the natural logarithm of the value designated by S taking (e) as base, and stores operation results at device
designated by D .
S +1 S D +1 D
7
log ( )

32-bit floating-point
real number
32-bit floating-point
real number
8
(2) Only positive values can be designated by S . (Operation cannot be performed on negative numbers.)
(3) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

7.12.23 LOG, LOGP

7.12 Special function instructions
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified in S is negative.
––
4100 The value specified in S is 0.
The specified device value is -0.*2 –– ––
The specified device value is not within the following range:
0, 2-126 | Specified device value | < 2128
4140 –– –– –– ––
The specified device value is -0, unnormalized number, nonnumeric,
and ± .
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |
*2: There are CPU modules that will not result in an operation error if -0 is specified.
For details, refer to Page 93, Section 3.2.4.

549
 LOGD, LOGDP

Program Example
(1) The following program seeks the natural logarithm of the value "10" set by D50, and stores the result at D30 and D31.
[Ladder Mode]

Sets data used for natural

logarithm operation ( 1 )
Converts the operation data
into a 32-bit floating-point real number ( 2 )
Executes natural logarithm operation ( 3 )

[List Mode]

Step Instruction Device

[Operation]
D50 Conversion to
1 b15 b0 2
floating-point D41 D40 3 LOG operation D31 D30
10 10 10 2 . 302585
MOV BIN value FLT 32-bit floating-point LOG 32-bit floating-point
real number real number

7.12.24 LOGD, LOGDP Natural logarithm operation on floating-point data

(Double precision)

7.12.24 LOGD, LOGDP Basic High

performance Process Redundant Universal LCPU

Command
LOGD LOGD S D

Command
LOGDP S D
LOGDP
S : Data of which the natural logarithm is obtained or head number of the devices where the data is stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– ––

D –– –– –– ––

Function
(1) Returns the natural logarithm of the value designated by S taking (e) as base, and stores operation results at device
designated by D .
S +3 S +2 S +1 S D +3 D +2 D +1 D
log ( ) ( )

64-bit floating-point 64-bit floating-point

real number real number

(2) Only positive values can be designated by S . (Operation cannot be performed on negative numbers.)
(3) When the operation results in -0 or an underflow, the result is processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

550
 LOGD, LOGDP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The value specified in S is negative.
4100
The value specified in S is 0.
–– –– –– ––
3
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The specified device value is -0. 4
The operation result exceeds the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |
4
Program Example
6
(1) The following program seeks the natural logarithm of the value "10" set by D50, and stores the result at D30 to D33.
[Ladder Mode]

Sets data used for natural logarithm

7
operation ( 1 ).
Converts the operation data into a 64-bit
floating-point real number ( 2 ).
Executes natural logarithm operation ( 3 ).
8

[List Mode]

7.12.24 LOGD, LOGDP

7.12 Special function instructions
Step Instruction Device

[Operation]
D50 2 Conversion to
1 b15 b0 floating-point D43 D42 D41 D40 3 LOG operation D33 D32 D31 D30
10 10 10 2.302585
MOV BIN value FLTD 64-bit floating-point LOGD 64-bit floating-point
real number real number

551
 LOG10, LOG10P
7.12.25 LOG10, LOG10P Common logarithm operation on floating-point data
(Single precision)

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.12.25 LOG10, LOG10P digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

Command
LOG10 LOG10 S D

Command
LOG10P S D
LOG10P
S : Data of which the common logarithm is obtained or head number of the devices where the data are stored (real number)
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
S –– –– –– *1 ––
D –– –– –– –– ––

*1: Available only for real number.

Function
(1) This instruction obtains the value specified by S for common logarithm (logarithm with base 10), and then stores the
operation result into the device specified by D.

Log10 S +1 S D +1 D

32-bit floating-point 32-bit floating-point

data type real number data type real number

(2) Only positive values can be specified by S . (Operation cannot be performed on negative numbers.)
(3) If the value resulted from the operation is -0 or an underflow occurs, the result will be processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified in S is negative.
4100 –– –– –– ––
The value specified in S is 0.
The specified device value is not within the following range:
4140 0, 2-126 | Specified device value | < 2128 –– –– –– ––
The value specified by S is -0.
The operation result is within the following range (when an overflow
4141 occurs): –– –– –– ––
2128 | Operation result |

552
 LOG10D, LOG10DP

Program Example
1
(1) The following program obtains the value for common logarithm of the 32-bit floating-point data type real number specified
by D600 or D601, when X10 is turned on. Then the program stores the operation result into D123 or D124.
[Ladder Mode] [List Mode] 2
Step Instruction Device

4
[Operation]
D601 D600 D124 D123

Log10 2.806 0.448088 4

6
7.12.26 LOG10D, LOG10DP Common logarithm operation on floating-point data
(Double precision)

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.12.26 LOG10D, LOG10DP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported
7

Command
LOG10D LOG10D S D 8
Command
LOG10DP S D
LOG10DP
S : Data of which the common logarithm is obtained or head number of the devices where the data are stored (real number)

7.12.26 LOG10D, LOG10DP

7.12 Special function instructions
D : Head number of the devices where the operation result will be stored (real number)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– *1 ––

D –– –– –– ––

*1: Available only for real number.

Function
(1) This instruction obtains the value specified by S for common logarithm (logarithm with base 10), and then stores the
operation result into the device specified by D.

Log10 S +3 S +2 S +1 S D +3 D +2 D +1 D

64-bit floating-point 64-bit floating-point

data type real number data type real number

(2) Only positive values can be specified by S . (Operation cannot be performed on negative numbers.)
(3) If the value resulted from the operation is -0 or an underflow occurs, the result will be processed as 0.
(4) When an input value is set using a programming tool, a rounding error may occur.
For precautions, refer to Page 95, Section 3.2.4 (3).

553
 RND, RNDP, SRND, SRNDP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified in S is negative.
4100 –– –– –– ––
The value specified in S is 0.
The specified device value is not within the following range:
4140 0, 2-1022 | Specified device value | < 21024 –– –– –– ––
The value specified by S is -0.
The operation result is within the following range (when an overflow
4141 occurs): –– –– –– ––
21024 | Operation result |

Program Example
(1) This following program obtains the value for common logarithm of the 64-bit floating-point data type real number
specified by D600 to D603 when M0 is turned on. Then the program stores the operation result into D123 to D126.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
D603 D602 D601 D600 D126 D125 D124 D123

Log10 2.806 0.448088

7.12.27 RND, RNDP Random number generation

SRND, SRNDP Series updates

Ver.
High
Basic Process Redundant Universal LCPU

7.12.27 RND, RNDP, SRND, SRNDP

performance
• Basic model QCPU: The serial number (first five digits) is
"04122" or later.

Command
RND RND D

Command
RNDP D
RNDP
Command
SRND SRND S

Command
SRNDP S
SRNDP

D : Head number of the devices where random numbers will be stored (BIN 16 bits)
S : Random number serial data or the first number of the devices where the random number serial data is stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
D –– ––
S ––

554
 BSQR, BSQRP, BDSQR, BDSQRP

Function
1
The random number generation instruction generates random numbers conforming to a certain calculation formula. In the
calculation using the formula, the result of previous calculation is used as a coefficient.
The random series change instruction can change the random number generation pattern.
2
RND
Generates random number of from 0 to 32767, and stores at device designated by .
3
D

SRND
Updates random number series according to the 16-bit BIN data being stored in device designated by S .
4
Operation Error
(1) There is no operation error in the RND(P) or SRND(P) instruction. 4

Program Example
6
(1) The following program stores random number at D100 when X10 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7

8
(2) The following program updates a random number series according to the contents of D0 when X10 is turned ON.
[Ladder Mode] [List Mode]

7.12.28 BSQR, BSQRP, BDSQR, BDSQRP

7.12 Special function instructions
Step Instruction Device

7.12.28 BSQR, BSQRP BCD 4-digit square roots

BDSQR, BDSQRP BCD 8-digit square roots

7.12.28 BSQR, BSQRP, BDSQR, BDSQRP Basic High

performance Process Redundant Universal LCPU

BSQR/BDSQR
Command
BSQR,BDSQR S D

Command
P S D
BSQRP,BDSQRP
S : Data of which the square root is obtained or the number of the device where the data is stored (BSQR(P): BCD 4 digits, BDSQR(P): BCD 8 digits)
D : Head number of the devices where the square root calculation result will be stored (BCD 4 digits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– ––

555
 BSQR, BSQRP, BDSQR, BDSQRP

Function
BSQR
(1) Returns the square root of the value designated at S , and stores the operation result in the device number designated at
D .
D D +1
S Integer part . Decimal fraction part

(2) Values that can be designated at S are BCD values with a maximum of 4 digits (from 0 to 9999).
(3) The operation results of D and D +1 are stored as their respective BCD values of between 0 and 9999.
(4) Operation results are rounded off from the fifth decimal place.
For this reason, the fourth decimal place has an error of ±1.

BDSQR
(1) Calculates the square root of the values designated by S and S +1 and stores the results at the device designated by
D .
D D +1
( S +1 S ) Integer part . Decimal fraction part

2-word data
(2) BCD value of a maximum of 8 digits (0 to 99999999) can be designated by S and S +1.
(3) The operation results of D and D +1 are stored as their respective BCD values of between 0 and 9999.
(4) Operation results are rounded off from the fifth decimal place.
For this reason, the fourth decimal place has an error of ±1.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The data specified in S is not a BCD value. ––

Program Example
(1) The following program calculates the square root of BCD value 1325 and outputs the integer part to the 4 BCD digits
from Y50 to Y5F, and the decimal fraction part to the 4 BCD digits from Y40 to Y4F.
[Ladder Mode]

Sets the data used for

square root operation ( 1 )
Executes square root operation ( 2 )

Outputs the integer part of the operation

result to a display device ( 3 )

Outputs the decimal fraction part of the

operation result to a display device ( 4 )

556
 BSIN, BSINP

[List Mode]

Step Instruction Device

1

[Operation]
2
D0 BSQR operation D1 Transfer Y5F Y50
1325H
MOV
1 3 2 5
BCD value BSQR
0 0 3 6
BCD value MOV
0 0 3 6 Integer part
BCD value
3
D2 Transfer Y4F Y40
4 0 0 5 4 0 0 5 Decimal fraction part 4
BCD value MOV BCD value

(2) The following program calculates the square root of BCD value 74625813 and outputs the integer part of the result to the
4 BCD digits at Y50 to Y5F, and the decimal fraction part to the 4 BCD digits from Y40 to Y4F. 4
[Ladder Mode]

Sets the data (BCD value) used

for square root operation ( 1 ) 6
Executes square root operation ( 2 )
Outputs the integer part of the
operation result to a display device ( 3 ) 7
Outputs the decimal fraction part of
the operation result to a display device ( 4 )
8
[List Mode]

Step Instruction Device

7.12.29 BSIN, BSINP

7.12 Special function instructions
[Operation]
1 D1 D0 2 BDSQR operation D2 3 Transfer Y5F Y50
74625813 7 4 6 2 5 8 1 3 8 6 3 8 8 6 3 8 Integer part
BCD value DMOV BCD value BDSQR BCD value MOV BCD value

D3 4 Transfer Y4F Y40

6 2 3 3 6 2 3 3 Decimal fraction part
BCD value MOV BCD value

7.12.29 BSIN, BSINP BCD type SIN operation

7.12.29 BSIN, BSINP Basic High

performance Process Redundant Universal LCPU

Command
BSIN BSIN S D

Command
BSINP S D
BSINP
S : Data of which the SIN (sine) value is obtained or the number of the device where the data is stored (BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– –– ––

557
 BSIN, BSINP

Function
(1) Calculates the SIN (sine) value of value (angle) designated by S , and stores the sign of the operation result in the device
designated at D , and the operation result in the devices designated at D +1 and D +2.
D D + 1 D + 2
SIN S Sign Integer part . Decimal fraction part

(2) The value designated at S is a BCD value which can be between 0 and 360 degrees (in units of degrees).
(3) The sign for the operation result stored in D will be "0" if the result is a positive value, and "1" if the result is a negative
value.
(4) The operation results stored in D +1 and D +2 are BCD values between -1.000 and 1.000.
(5) Operation results are rounded off from the fifth decimal place.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The data specified in S is not a BCD value.
4100 ––
The data specified in S is not within the range from 0 to 360.
The points of the device specified in D exceed those of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The program example below calculates the SIN of 3-digit BCD data designated by X20 to X2B, and outputs a 1-digit
BCD part to the integer part from Y50 to Y53, and a 4-digit BCD fraction part from Y40 to Y4F.
Y60 is turned ON if the results of the operation are negative. (If a value has been set at X20 to X2F that is greater than
360, it will be adjusted to be in the range from 0 to 360.)
[Ladder Mode]

Processes so that the input

angle is within 360° ( 1 )
Executes SIN operation ( 2 )
Outputs the integer part of the operation
result to a display device ( 3 )
Outputs the decimal fraction part of the
operation result to a display device ( 4 )
Outputs the sign of the operation result
by ON or OFF ( 5 )

[List Mode]

Step Instruction Device

558
 BCOS, BCOSP

[Operations involved when value designated by X20 to X2B is 590]

X2B X20 1 B/ operation D10
5 9 0
BCD value B/
0 0 0 1
BCD value
1
(quotient)
2 BSIN 5
D11 operation D20
0 2 3 0 0 0 0 1 Y60 ON 2
BCD value BSIN BCD value OUT
(remainder)

3
D21 3 Transfer Y53 Y50
0 0 0 0 0
BCD value MOV BCD value

D22 4 Transfer Y4F Y40 4

7 6 6 0 7 6 6 0
BCD value MOV BCD value

7.12.30 BCOS, BCOSP BCD type COS operations

4
7.12.30 BCOS, BCOSP Basic High
performance Process Redundant Universal LCPU

6
Command
BCOS BCOS S D

BCOSP
Command
BCOSP S D 7
S : Data of which the COS (cosine) value is obtained or head number of the devices where the data is stored (BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits) 8
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S ––

D –– –– ––

7.12.30 BCOS, BCOSP

7.12 Special function instructions
Function
(1) Calculates COS (cosine) value of value (angle) designated by S , then stores the sign for the operation result in the word
device designated by D , and the operation result in the word device designated by D +1 and D +2.
D D +1 D +2
COS S Sign Integer part . Decimal fraction part

(2) The value designated at S is a BCD value which can be between 0 and 360 degrees (in units of degrees).
(3) The sign for the operation result stored in D will be "0" if the result is a positive value, and "1" if the result is a negative
value.
(4) The operation results stored in D +1 and D +2 are BCD values between -1.000 and 1.000.
(5) Operation results are rounded off from the fifth decimal place.

559
 BCOS, BCOSP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The data specified in S is not a BCD value.
4100 ––
The data specified in S is not in the range from 0 to 360.
The points of the device specified in D exceed those of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program calculates the cosine of the data designated by the 3 BCD digits from X20 to X2B and outputs the
integer part of the result to 1 BCD digit from Y50 to Y53, and the decimal fraction part of the result to the 4 BCD digits
from Y40 to Y4F.
Y60 is turned ON if the results of the operation are negative.
[Ladder Mode]

Processes so that the input

angle is within 360° ( 1 )
Executes COS operation ( 2 )

Outputs the integer part of the operation

result to a display device ( 3 )
Outputs the decimal fraction part of the
operation result to a display device ( 4 )
Outputs the sign of the operation result
by ON or OFF ( 5 )

[List Mode]

Step Instruction Device

[Operations involved when value designated by X20 to X2B is 430]

X2B X20 1 B/ operation D10

4 3 0 0 0 0 1
BCD value B/ BCD value
(quotient)
2 BCOS
D11 D20 5
operation
0 0 7 0 0 0 0 0 Y60 ON
BCD value BCOS BCD value OUT
(remainder)
D21 3 Transfer Y53 Y50
0 0 0 0 0
BCD value MOV BCD value

D22 4 Transfer Y4F Y40

3 4 2 0 3 4 2 0
BCD value MOV BCD value

560
 BTAN, BTANP
7.12.31 BTAN, BTANP BCD type TAN operation

7.12.31 BTAN, BTANP Basic High

Process Redundant Universal LCPU
1
performance

Command
BTAN BTAN S D

Command
BTANP S D
2
BTANP
S : Data of which the TAN (tangent) value is obtained or head number of the devices where the data is stored (BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits) 3
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– 4
D –– –– ––

Function 4
(1) Calculates TAN (tangent) value for value (angle) designated by S , and stores the sign for the operation result in the
word device designated by D , and the operation result in the word device designated by D +1 and D +2. 6
D D +1 D +2
TAN S Sign Integer part . Decimal fraction part

(2) The value designated at S is a BCD value which can be between 0 and 360 degrees (in units of degrees).
7
(3) The sign for the operation result stored in D will be "0" if the result is a positive value, and "1" if the result is a negative
value.
8
(4) The operation results stored at D +1 and D +2 are BCD values within the range of from -57.2901 and 57.2902.
(5) Operation results are rounded off from the fifth decimal place.

Operation Error

7.12.31 BTAN, BTANP

7.12 Special function instructions
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The data specified in S is not a BCD value.
4100 The data specified in S is not in the range from 0 to 360. ––
The data specified in S is 90° or 270°.
The points of the device specified in D exceed those of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program calculates the tangent of the data stored in the 3 BCD digits from X20 to X2B, and stores the
integer part of the results in the 4 BCD digits from Y50 to Y53, and the decimal fraction part in the 4 BCD digits from Y40
to Y4F.
Y60 is turned ON if the results of the operation are negative.

561
 BASIN, BASINP

[Ladder Mode]

Processes so that the input

angle is within 360° ( 1 )

[List Mode]

Step Instruction Device

[Operations involved when X20 to X2B designate a value of 390]

X2B X20 1 B/ operation D10
3 9 0 0 0 0 1
BCD value B/ BCD value
(quotient)
2 BTAN
D11 operation D20 5
0 0 3 0 0 0 0 0 Y60 OFF
BCD value BTAN BCD value OUT
(remainder)
D21 3 Transfer Y53 Y50
0 0 0 0 0
BCD value MOV BCD value

D22 4 Transfer Y4F Y40

5 7 7 4 5 7 7 4
BCD value MOV BCD value

7.12.32 BASIN, BASINP BCD type arc sine operations

7.12.32 BASIN, BASINP Basic High

performance Process Redundant Universal LCPU

Command
BASIN BASIN S D

Command
BASINP S D
BASINP
S : Number of the device where data of which the SIN-1 (inverse sine) value is obtained is stored (BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– –– ––

D –– ––

562
 BASIN, BASINP

Function
1
(1) Returns the SIN-1 (inverse sine) value of the value designated by S and stores operation results (angles) at device
designated by D .
S S +1 S +2 2
SIN 1 ( Sign Integer part . Decimal fraction part ) D

(2) A sign for the operation data is set at S .

If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set at "1". 3
(3) The part before the decimal point and fraction part are stored at S +1 and S +2 respectively, as BCD values.
(Settings can be between 0 and 1.0000.)
4
(4) Operation results stored at D are BCD values between 0 and 90 degrees, and 270 and 360 degrees (degree units).
(5) Calculation results are a value from which the decimal fraction part has been rounded.
4
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into 6
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
7
The data specified in S is not a BCD value.
4100 ––
The data specified in is not within the range from -1.0000 to 1.0000.
8
S

The points of the device specified in S exceed those of the

4101 –– –– –– ––
corresponding device.

Program Example

7.12.32 BASIN, BASINP

7.12 Special function instructions
(1) The following program performs a SIN-1 operation on the sign (positive when X0 is OFF, and negative when X0 is ON),
the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the
calculated angle in 4 BCD digits from Y40 to Y4F.
[Ladder Mode]

Sets the sign of a SIN value ( 1 )

Sets the integer part of a SIN value ( 2 )

Sets the decimal fraction part of a SIN value ( 3 )

Executes range check for the set SIN value

Executes Sin-1 operation and outputs

the result of operation to Y40 to Y4F ( 4 )

563
 BACOS, BACOSP

[List Mode]

Step Instruction Device

[Operations involved when X20 to X33 designates value of 0.4753]

D0
X0 OFF 0 0 0 0
BCD value

X33 X30 Transfer D1 BASIN operation Y4F Y40

0 0 0 0 0 0 0 2 8
BCD value MOV BCD value BASIN BCD value

X2F X20 Transfer D2

4 7 5 3 4 7 5 3
BCD value MOV BCD value

7.12.33 BACOS, BACOSP BCD type arc cosine operation

7.12.33 BACOS, BACOSP Basic High

performance Process Redundant Universal LCPU

Command
BACOS BACOS S D

Command
BACOSP S D
BACOSP
S : Number of the device where data of which the COS-1 (inverse cosine) value is obtained is stored (BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S –– –– ––

D ––

Function
(1) Returns the COS-1 (inverse cosine) value of the value designated by S , and stores operation results at device
designated by D .
S S +1 S +2
COS 1 ( Sign Integer part . Decimal fraction part ) D

(2) A sign for the operation data is set at S .

If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set at "1".
(3) The part before the decimal point and fraction part are stored at S +1 and S +2 respectively, as BCD values.
(Settings can be between 0 and 1.0000.)
(4) The operation results stored at D will be a BCD value in the range of between 0 and 180° (degree units).
(5) Calculation results are a value from which the decimal fraction part has been rounded.

564
 BACOS, BACOSP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The operation data specified in S is not a BCD value.
4100 The operation data specified in S is not in the range from -1.0000 to –– 3
1.0000.
The points of the device specified in S exceed those of the
4101 –– –– –– ––
corresponding device. 4

Program Example
4
-1
(1) The following program performs a COS operation on the sign (positive when X0 is OFF, and negative when X0 is ON),
the BCD 1-digit integer part from X30 to X33 and the BCD 4-digit decimal fraction part from X20 to X2F, and outputs the
calculated angle in 4 BCD digits from Y40 to Y4F. 6
[Ladder Mode]

7
Sets the sign of a COS value ( 1 )

Sets the integer part of a COS value ( 2 ) 8

Sets the decimal fraction part of a COS value ( 3 )

Turns M0 ON when D1>1 or D1=1 and D2 0

7.12.33 BACOS, BACOSP

7.12 Special function instructions
Executes COS-1 operation and outputs
the result of operation to Y40 to Y4F ( 4 )

[List Mode]

Step Instruction Device

565
 BATAN, BATANP

[Operations involved if X0 and X20 to X33 designate a value of 0.7650]

1 D0
X0 ON 0 0 0 1
BCD value

X33 X30 2 Transfer D1 4 BACOS operation Y4F Y40

0 0 0 0 0 0 1 4 0
BCD value MOV BCD value BACOS BCD value

X2F X20 3 Transfer D2

7 6 5 0 7 6 5 0
BCD value MOV BCD value

7.12.34 BATAN, BATANP BCD type arc tangent operations

7.12.34 BATAN, BATANP Basic High

performance Process Redundant Universal LCPU

Command
BATAN BATAN S D

Command
BATANP S D
BATANP
S : Number of the device where data of which the TAN-1 (inverse tangent) value is obtained is stored (BCD 4 digits)
D : Head number of the devices where the operation result will be stored (BCD 4 digits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S –– –– ––

D ––

Function
(1) Performs TAN-1 (inverse tangent) on value designated by S and stores operation results (angles) at device designated
by D .
S S +1 S +2
TAN 1 ( Sign Integer part . Decimal fraction part ) D

(2) A sign for the operation data is set at S .

If the operation data is a positive value, this is set at "0", and if it is a negative value, it is set at "1".
(3) The part before the decimal point and fraction part are stored at S +1 and S +2 respectively, as BCD values.
(Values from 0 to 9999.9999 can be set.)
(4) Operation results stored at D are BCD values between 0 and 90 degrees, and 270 and 360 degrees (degree units).
(5) Calculation results are a value from which the decimal fraction part has been rounded.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The operation data specified in S is not a BCD value. ––
The points of the device specified in S exceed those of the
4101 –– –– –– ––
corresponding device.

566
 BATAN, BATANP

Program Example
1
(1) The following program performs a TAN-1 operation on the sign (positive when X0 is OFF, and negative when X0 is ON),
the BCD 4-digit integer part from X20 to X2F and the BCD 4-digit decimal fraction part from X30 to X3F, and outputs the
calculated angle in 4 BCD digits from Y40 to Y4F. 2
[Ladder Mode]

Sets the sign of a TAN value ( 1 ) 3

Sets the integer part of a TAN value ( 2 )

4
Sets the decimal fraction part of a TAN value ( 3 )

Executes TAN-1 operation and outputs

the result of operation to Y40 to Y4F ( 4 )
4

[List Mode]
6
Step Instruction Device

[Operations involved when X0 and X20 to X2F designate a value of 1.2654]

8
1 D0
X0 OFF 0 0 0 0
BCD value

7.12.34 BATAN, BATANP

7.12 Special function instructions
X2F X20 2 Transfer D1 4 BATAN operation Y4F Y40
0 0 0 1 0 0 0 1 0 0 5 2
BCD value MOV BCD value BATAN BCD value

X3F X30 3 Transfer D2

2 6 5 4 2 6 5 4
BCD value MOV BCD value

567
 LIMIT, LIMITP, DLIMIT, DLIMITP

7.13 Data Control Instructions

7.13.1 LIMIT, LIMITP Upper and lower limit controls for BIN 16-bit data

7.13.1
DLIMIT, DLIMITP Upper and lower limit controls for BIN 32-bit data

LIMIT, LIMITP, DLIMIT, DLIMITP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of LIMIT/DLIMIT.

Command
LIMIT, DLIMIT S1 S2 S3 D

Command
P S1 S2 S3 D
LIMITP, DLIMITP

S1 : Lower limit value (minimum output threshold value) (BIN 16/32 bits)
S2 : Upper limit value (maximum output threshold value) (BIN 16/32 bits)
S3 : Input value to be controlled by the upper and lower limit control (BIN 16/32 bits)
D : Head number of the devices where the output value controlled by the upper and lower limit control will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––
S3 ––

D –– ––

Function
LIMIT
(1) Controls the output value to be stored at the device designated by D by checking whether the input value (BIN 16 bits)
designated by S3 is within the range of upper and lower limit values specified by S1 and S2 or not.
Output value is controlled in the way shown below:
• When S1 Lower limit value S3 Input value ................................. S1 Lower limit value D Output value

• When S2 Upper limit value S3 Input value ................................. S2 Upper limit value D Output value

• When S1 Lower limit value S3 Input value S2 Upper limit value ..... S3 Input value D Output value

Output value ( D )

Value designated by S2
Value designated Input value( S3 )
by S1

(2) Values in the range from -32768 and 32767 can be designated at S1 , S2 , and S3 .

(3) When control based only on upper limit values is performed, the lower limit value designated at S1 is set at " 32678".
(4) When control based only on lower limit values is performed, the upper limit value designated at S2 is set at "32767".

568
 LIMIT, LIMITP, DLIMIT, DLIMITP

DLIMIT
(1) The function controls the output value to be stored at the device designated by ( D , +1) by checking whether the input
1
D

value (BIN 32 bits) designated by ( S3 , S3 +1) is within the range of upper and lower limit values specified by ( S1 , S1 +1)

and ( S2 , S2 +1) or not.

S1 +1 S1 S3 +1 S3 S1 +1 S1 D +1 D 2
When Lower limit value Input value Lower limit value Output value
S2 +1 S2 S3 +1 S3 S2 +1 S2 D +1 D
When Upper limit value
S1 +1 S1
Input value
S3 +1 S3 S2 +1 S2
Upper limit value
S3 +1 S3
Output value
D +1 D
3
When Lower limit value Input value Upper limit value Input value Output value

Output value ( D +1, D ) 4

Value designated by S2 +1, S2

Output value ( S3 +1, S3 ) 4
0

Value designated by S1 +1, S1 6

(2) The values designated by ( S1 , S1 +1), ( S2 , S2 +1), or ( S3 , S3 +1) are within the range of -2147483648 to 2147483647.
(3) To perform controls based only on the upper limit value, set the lower limit value designated by ( S1 , S1 +1) to 7
"-2147483648".
(4) To perform controls based only on the lower limit value, set the upper limit value designated by ( S2 , S2 +1) to
"2147483647". 8

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.

7.13.1 LIMIT, LIMITP, DLIMIT, DLIMITP

7.13 Data Control Instructions
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The lower limit value specified in S1 is greater than the upper limit value
4100 –– –– –– ––
specified in S2 .

Program Example
(1) The following program conducts limit controls from 500 to 5000 on the data set as BCD values from X20 to X2F, and
stores the result at D1 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

569
 BAND, BANDP, DBAND, DBANDP

[Operation]
• D1 becomes 500 if D0 500.

Example D0 400 D1 500

• D1 becomes the value of D0 when 500 D0 5000.

Example D0 1300 D1 1300

• D1 becomes 5000 when 5000 D0.

Example D0 9600 D1 5000

(2) The following program conducts limit value controls from 10000 to 1000000 on the data set as BCD values from X20 to
X3F when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• (D11, D10) become 10000 if (D1, D0) are less than 10000.

Example (D1, D0) 400 (D11, D10) 10000

• (D11, D10) become the value of (D1, D0) if 10000 (D1, D0) 1000000.

Example (D1, D0) 345678 (D11, D10) 345678

• (D11, D10) become 1000000 if 1000000 (D1, D0).

Example (D1, D0) 9876543 (D11, D10) 1000000

7.13.2 BAND, BANDP BIN 16-bit dead band controls

7.13.2
DBAND, DBANDP BIN 32-bit dead band controls

BAND, BANDP, DBAND, DBANDP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of BAND/DBAND.

Command
BAND, DBAND S1 S2 S3 D

Command
P S1 S2 S3 D
BANDP, DBANDP

S1 : Lower limit value of dead band (no output band) (BIN 16/32 bits)
S2 : Upper limit value of dead band (no output band) (BIN 16/32 bits)
S3 : Input value to be controlled by a dead band control (BIN 16/32 bits)
D : Head number of the devices where the output value controlled by the dead band control will be stored (BIN 16/32 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
S2 ––
S3 ––

D –– ––

570
 BAND, BANDP, DBAND, DBANDP

Function
1
BAND
(1) Controls the output value to be stored at the device designated by D by checking whether the input value (BIN 16 bits)
designated by S3 is within the range of dead band upper and lower limit values specified by S1 and S2 or not. 2
Output value is controlled in the way shown below:
• When S1 Lower limit value S3 Input value .......................... S3 Input value - S1 Lower limit value D Output value

• When S2 Upper limit value S3 Input value ......................... S3 Input value - S2 Upper limit value D Output value
3
• When S1 Lower limit value S3 Input value S2 Upper limit value .......0 D Output value

Output value ( D ) 4
Dead band
lower limit value ( S1 )

0
Input value ( S2 )
4
Dead band upper
limit value ( S3 )

(2) The values that can be designated by S1 , S2 , and S3 are in the range of from -32768 to 32767. 6
(3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results exceed the range of from
-32768 to 32767, the following will take place:
7
Dead band lower limit value S1 ..............10
When :
Input value S3 ................................................-32768
8
Output value -32768-10 8000H- AH 7FF6H 32758

DBAND
(1) Controls the output value to be stored at the device designated by D by checking whether the input value (BIN 32 bits)

7.13.2 BAND, BANDP, DBAND, DBANDP

7.13 Data Control Instructions
designated by ( S3 , S3 +1) is within the range of dead band upper and lower limit values specified by ( S1 , S1 +1) and ( S2 ,
S2 +1) or not.
Output value is controlled in the way shown below:
S1 +1 S1 S3 +1 S3 S3 +1 S3 S1 +1 S1 D +1 D
When Lower limit value Input value Input value Lower limit value Output value
S2 +1 S2 S3 +1 S3 S3 +1 S3 S2 +1 S2 D +1 D
When Upper limit value Input value Input value Upper limit value Output value
S1 +1 S1 S3 +1 S3 S2 +1 S2 D +1 D
When Lower limit value Input value Upper limit value 0 Output value

Output value ( D +1, D )

Dead band lower
limit value ( S1 , S1 +1)

Input value ( S3 , S3 +1)

0
Dead band upper
limit value ( S2 , S2 +1)

(2) The values designated by ( S1 , S1 +1), ( S2 , S2 +1), or ( S3 , S3 +1) are within the range of from -2147483648 to 2147483647.

571
 BAND, BANDP, DBAND, DBANDP

(3) The output value stored at D , D +1 is a signed 32-bit BIN value. Therefore, if the operation results exceed the range of
from -2147483648 to 2147483647, the following takes place:

Dead band lower limit value ( S1 , S1 +1) ................1000

When :
Input value ( S3 , S3 +1) ...................................................-2147483648

Output value -2147483648-1000 80000000H-000003E8H

7FFFFC18H 2147482648

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The lower limit value specified in S1 is greater than the upper limit value
4100 –– –– –– ––
specified in S2 .

Program Example
(1) The following program performs the dead band control by applying the lower and upper limits of 0 and 1000 for the data
set in BCD at X20 to X2F and stores the result of control at D1 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• "0" is stored at D1 if 0 D0 1000.

Example D0 500 D1 0
• The value of (D0) 1000 is stored at D1 if 1000 D0.

Example D0 7000 D1 6000

(2) The following program performs the dead band control by applying the lower and upper limits of -10000 and 10000 for
the data set at D0 and D1 and stores the result of control at D10 and D11 when X0 is turned ON
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• The value (D1, D0) - (-10000) is stored at (D11, D10) if (D1, D0) ( 10000).

Example (D1, D0) -12345 (D11, D10) -2345

• The value 0 is stored at (D11, D10) if -10000 (D1, D0) 10000.

Example (D1, D0) 6789 (D11, D10) 0

• The value (D1, D0) -10000 is stored at (D11, D10) if 10000 (D1, D0).

Example (D1, D0) 50000 (D11, D10) 40000

572
 ZONE, ZONEP, DZONE, DZONEP
7.13.3 ZONE, ZONEP Zone control for BIN 16-bit data

7.13.3
DZONE, DZONEP Zone control for BIN 32-bit data

ZONE, ZONEP, DZONE, DZONEP Basic High

performance Process Redundant Universal LCPU

1
indicates an instruction symbol of ZONE/DZONE.

Command
ZONE, DZONE
2
S1 S2 S3 D

Command
P S1 S2 S3 D
ZONEP, DZONEP

S1 : Negative bias value to be added to an input value (BIN 16/32 bits)

3
S2 : Positive bias value to be added to an input value (BIN 16/32 bits)
S3 : Input value used for a zone control (BIN 16/32 bits)
D : Head number of the devices where the output value controlled by the zone control will be stored (BIN 16/32 bits). 4
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 ––
4
S2 ––

S3 ––

D –– –– 6

Function
7
ZONE
(1) Adds bias value designated by S1 or S2 to input value designated by S3 , and stores at device number designated by D .
Bias values are calculated in the following manner: 8
• When S3 Input value 0........ S3 Input value + S1 Negative bias value D Output value

• When S3 Input value 0........................................................................ 0 D Output value

• When S3 Input value 0........ S3 Input value + S2 Positive bias value D Output value

7.13.3 ZONE, ZONEP, DZONE, DZONEP

7.13 Data Control Instructions
Output value ( D )

Positive bias value ( S2 )

Input value ( S3 )
0
Negative bias value ( S1 )

(2) The values that can be designated by S1 , S2 , and S3 are in the range of from 32768 to 32767.
(3) The output value stored at D is a signed 16-bit BIN value. Therefore, if the operation results exceed the range of
32768 to 32767, the following will take place:

Negative bias value S1 .........................................-100

When :
Input value S3 ............................................................-32768

Output value -32768 + (-100) 8000H + FF9C 7F9CH 32668

573
 ZONE, ZONEP, DZONE, DZONEP

DZONE
(1) Adds bias value designated by ( S1 , S1 +1) or ( S2 , S2 +1) to input value designated by ( S3 , S3 +1), and stores the result at
device number designated by ( D , D +1).
Addition of the bias value is performed as follows:
S3 +1 S3 S3 +1 S3 S1 +1 S1 D +1 D
When Input value 0 Input value + Negative bias value Output value
S3 +1 S3 D +1 D
When Input value 0 0 Output value
S3 +1 S3 S3 +1 S3 S2 +1 S2 D +1 D
When Input value 0 Input value + Positive bias value Output value

Output value ( D +1, D )

Positive bias value

( S2 , S2 +1)
Input value
0 ( S3 , S3 +1)
Negative bias value
( S1 , S1 +1)

(2) The values designated by ( S1 , S1 +1), ( S2 , S2 +1), or ( S3 , S3 +1) are within the range of from 2147483648 to
2147483647.
(3) The value stored at ( D , D +1) is a signed 32-bit BIN value.
Therefore, if the operation results exceed the range of from -2147483648 to 2147483647, the following takes place:

Negative bias value ( S1 , S1 +1).......................-1000

When :
Input value ( S3 , S3 +1).........................................-2147483648

Output value -2147483648 + (-1000) 80000000H + FFFFFC18H

7FFFFC18 2147482648.

Operation Error
(1) There is no operation error in the ZONE(P) or DZONE(P) instruction.

Program Example
(1) The following program performs zone control by applying negative and positive bias values of 100 to 100 for the data
set at D0 and stores the result of control at D1 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• The value (D0) + (-100) is stored at D1 if D0 0.

Example D0 -200 D1 -300

• The value 0 is stored at D1 if D0 0.
• The value of (D0) + 100 is stored at D1 if 0 D0.

Example D0 700 D1 800

574
 SCL, SCLP, DSCL, DSCLP

(2) The following program performs zone control by applying negative and positive bias values of -10000 to 10000 for the
data set at D0 and D1 and stores the result of control at D10 and D11 when X1 is turned ON.
[Ladder Mode] [List Mode] 1
Step Instruction Device

2
[Operation]
• The value (D1, D0) + (-10000) is stored at (D11, D10) if (D1, D0) 0. 3
Example (D1,D0) -12345 (D11,D10) -22345
• The value 0 is stored at (D11, D10) if (D1, D0) 0.
4
• The value (D1, D0) + 10000 is stored at (D11, D10) if 0 (D1, D0).

Example (D1,D0) 50000 (D11,D10) 60000

4
7.13.4 SCL, SCLP, DSCL, Scaling (Coordinate data by point)
DSCLP

Ver.
High
Basic performance Process Redundant Universal LCPU
6
• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.13.4 SCL, SCLP, DSCL, DSCLP digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

7
indicates an instruction symbol of SCL/DSCL.
Command
SCL, DSCL S1 S2 D 8
Command
SCLP, DSCLP P S1 S2 D

S1 : Input values for scaling or head number of the device where input values are stored(BIN 16/32 bits)

7.13.4 SCL, SCLP, DSCL, DSCLP

7.13 Data Control Instructions
S2 : Head number of the devices where scaling conversion data are stored(BIN 16/32 bits)
D : Head number of the devices where output values depending on scaling are stored(BIN 16/32 bits).
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– ––

S2 –– –– –– ––

D –– –– ––

575
 SCL, SCLP, DSCL, DSCLP

Function
SCL(P)
(1) This instruction executes scaling for the scaling conversion data (16-bit data units) specified by S2 with the input value
specified by S1 , and then stores the operation result into the devices specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the device specified by S2 and up.
Scaling conversion data component Y
Setting item Device assignment
Number of coordinate points S2

X coordinate S2 +1 Point 2
Point 1 Output Point 3
Y coordinate S2 +2 value D

X coordinate S2 +3
Point 2 Point n
Y coordinate S2 +4

Point 1

Point n 1
X coordinate S2 +2n 1
X
Point n Input value S1
Y coordinate S2 +2n
Operation error Operable range Operation error
n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole number.
(3) Set the X coordinate of the scaling conversion data in ascending order.
(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2 devices).
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output.
(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

DSCL(P)
(1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified by S2 with the input value
specified S1 , and then stores the operation result into the devices specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the device specified by S2 and up.
Scaling conversion data component
Setting item Device assignment
Y
Number of coordinate points S2 +1 , S2

X coordinate S2 +3 , S2 +2 Operation Operable range Operation error

Point 1 error
Y coordinate S2 +5 , S2 +4 Input value S1
X
X coordinate S2 +7 , S2 +6
Point 2 Point n 1
Y coordinate S2 +9 , S2 +8

Output D Point n
X coordinate value
S2 +4n 1 , S2 +4n 2
Point n Point 1
Y coordinate S2 +4n+1 , S2 +4n
Point 2
n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole number.
(3) Set the X coordinate of the scaling conversion data in ascending order.
(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2 and S2 +1 devices).
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output.
(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

576
 SCL, SCLP, DSCL, DSCLP

(1) There are two searching methods that depend on whether SM750 is on or off.
1
SM750 Searching method Range of number of searches
OFF Sequential search 1 Number of times 32767
ON Binary search 1 Number of times 15
2
(2) When the scaling conversion data are set in ascending order, the searching methods change from one to the other
depending on the SM750 status. Therefore, the processing speed also changes. The number of searches determines
the processing speed. Fewer number of serches make the processing run faster.
(a) If the data processing speed with the sequential search rises: 3
If the number of coordinates is highest and the input value S1 is within the coordinate range from 1 to 15 point,
the number of sequential searches will be 15 or smaller. Therefore, the data processing speed with the
sequential search will rise.
(b) If the data processing speed with the binary search rises: 4
If the maximum number of searches is 15 and the input value S1 is out of the coordinate range, 16 or over, the
number of binary searches will be equal to the number of sequential numbers or smaller. Therefore, the data
processing speed with the binary search will rise.

Number of coordinate points=32767 Number of sequential searches=32767

4
Number of binary searches=15
The processing speed with binary search
rises since the number of binary searches is

6
smaller than the number of sequential searches.

S1
Number of sequential searches=1
S1
8
Number of binary searches=15

The processing speed with sequential searches

rises since the number of binary searches is
larger than the number of sequential searches.

7.13.4 SCL, SCLP, DSCL, DSCLP

7.13 Data Control Instructions
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The X coordinates of the scaling conversion data positioned before the
point specified in S1 are not set in ascending order. (However, this error
is not detected when SM750 is on.)
4100 The input value specified in S1 is not within the range of the scaling –– –– –– ––
conversion data set.
The number of X and Y coordinates of the device specified in S2 is not
within the range from 1 to 32767.
The number of X and Y coordinates of the device specified in S2 is not
4101 –– –– –– ––
within the specified range.

577
 SCL2, SCL2P, DSCL2, DSCL2P

Program Example
(1) The following program executes scaling for the scaling conversion data of which the devices specified at D100 and up
are set with the input value specified at D0, and then outputs the data at D20.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
Scaling conversion data component
Setting item Device Setting contents
Number of coordinate points D100 K5 Y

X coordinate D101 K5 Point 5

Point 1 (25, 22)
Y coordinate D102 K13
Point 2
X coordinate D103 K10
Point 1 (10, 15) Point 3
Point 2
Y coordinate D104 K15 (5, 13) (17, 13)

X coordinate D105 K17 D20=11

Point 3 (Output value)
Y coordinate D106 K13 Point 4
(20, 8)
X coordinate D107 K20
Point 4
Y coordinate D108 K8

X coordinate D109 K25 X

Point 5 D0=18
Y coordinate D110 K22 (Input value)

7.13.5 SCL2, SCL2P, DSCL2, Scaling (Coordinate data by X and Y)

DSCL2P

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.13.5 SCL2, SCL2P, DSCL2, DSCL2P digits) is "10102" or later

• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

indicates an instruction symbol of SCL2/DSCL2.

Command
SCL2, DSCL2 S1 S2 D
Command
SCL2P, DSCL2P P S1 S2 D

S1 : Input values for scaling or head number of the device where input values are stored(BIN 16/32 bits)
S2 : Head number of the devices where scaling conversion data are stored(BIN 16/32 bits)
D : Head number of the devices where output values depending on scaling are stored(BIN 16/32 bits).
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– ––

S2 –– –– –– ––

D –– –– ––

578
 SCL2, SCL2P, DSCL2, DSCL2P

Function
1
SCL2(P)
(1) This instruction executes scaling for the scaling conversion data (16-bit data units) specified by S2 with the input value
specified by S1 , and then stores the operation result into the devices specified by D . 2
The scaling conversion is executed based on the scaling conversion data stored in the device specified by S2 and up.
Scaling conversion data component Y
Setting item
Number of coordinate points
Device assignment
S2
3
Point 1 S2 +1
Point 2
S2 Output Point 3
Point 2 +2
D Point n 1
X coordinate value
Point n
4
Point n S2 +n

Point 1
Point 1 S2 +n+1

Y coordinate
Point 2 S2 +n+2

Input value S1
X 4
Point n S2 +2n Operation error Operable range Operation error
n indicates the number of coordinates

6
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole number.
(3) Set the X coordinate of the scaling conversion data in ascending order.
(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2 devices). 7
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output.

DSCL2(P) 8
(1) This instruction executes scaling for the scaling conversion data (32-bit data units) specified by S2 with the input value
specified S1 , and then stores the operation result into the devices specified by D .
The scaling conversion is executed based on the scaling conversion data stored in the device specified by S2 and up.
Scaling conversion data component

7.13.5 SCL2, SCL2P, DSCL2, DSCL2P

7.13 Data Control Instructions
Setting item Device assignment
Y
Number of coordinate points S2 +1 , S2

Point 1 S2 +3 , S2 +2
Operation Operable range Operation error
error
Point 2 S2 +5 , S2 +4 Input value S1
X coordinate X

Point n 1
Point n S2 +2n+1 , S2 +2n

Point 1 S2 +2n+3 , S2 +2n+2

Output D Point n
Point 2 S2 +2n+5 , S2 +2n+4
value
Y coordinate
Point 1
Point n S2 +4n+1 , S2 +4n Point 2
n indicates the number of coordinates
specified by (S2).

(2) If the value does not result in an integer, this instruction rounds the value to the whole number.
(3) Set the X coordinate of the scaling conversion data in ascending order.
(4) Set the input value S1 within the range of the scaling conversion data (within the range of S2 and S2 +1 devices).
(5) If some specified points have same X coordinates, the Y coordinate data of the highest point number will be output.
(6) Specify the number of coordinate points of scaling conversion data from 1 to 32767.

When the coordinates of the scaling conversion data are set in ascending order, the searching methods change from one
to the other depending on the SM750 status. Therefore, the processing speed also change. The number of searches
determines the processing speed. Fewer number of searches make the processing run faster.
For details, refer to Page 575, Section 7.13.4.

579
 SCL2, SCL2P, DSCL2, DSCL2P

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The X coordinates are not set in ascending order.
The input value specified in S1 is not within the range of the scaling
4100 conversion data set. –– –– –– ––
The number of X and Y coordinates of the device specified in S2 is not
within the range from 1 to 32767.
The number of X and Y coordinates of the device specified in S2
4101 –– –– –– ––
exceeds the specified range.

Program Example
(1) The following program executes scaling for the scaling conversion data of which the devices specified at D110 and up
are set with the input value specified at D0, and then outputs the data at D200.
[Ladder Mode] [List Mode]
Step Instruction Device

[Operation]
Scaling conversion data component
Setting item Device Setting contents
Number of coordinate points D110 K5 Y
Point 1 D111 K7

Point 2 D112 K13 D0=11

X coordinate (Input value)
Point 3 D113 K15 X

Point 4 D114 K18 Point 2

(13, -7) Point 4
Point 5 D115 K20
(18, -11)
Point 1 D116 K-14 D200=-9 Point 3
Y coordinate (15, -9)
(Output value) Point 5
Point 2 D117 K-7 (20, -13)
Point 3 D118 K-15 Point 1
(7, -14)
Point 4 D119 K-11

Point 5 D120 K-18

580
 RSET, RSETP

7.14 File register switching instructions

1
7.14.1 RSET, RSETP Switching file register block numbers

Ver. Ver.

2
High
Basic performance Process Redundant Universal LCPU

7.14.1 RSET, RSETP • Q00JCPU cannot be used.

• Universal model QCPU: Models other than Q00UJCPU

RSET
Command
RSET S 3
Command
RSETP S
RSETP
4
S : Block number data used to change the block number or the number of the device where the block number data is stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
4
S ––

Function 6
(1) Changes the file register block number used in the program to the block number stored in the device designated at S .
Following the block number change, all file registers used in the sequence program are processed to the file register of 7
the block number after the change.

Example When switching block number from block No. 0 to block No. 1
8
Processing executed to file registers

7.14.1 RSET, RSETP

7.14 File register switching instructions
S Setting of a
block number

R0 Block 0 R0 Block 1 R0 Block n

File register

R32767
Presently
used file
register
used after the
execution of
RSET
R32767 instruction
( ) ( ) R32767

When a file register (R) is refreshed and the block No. of the file register is switched with the RSET instruction, follow
restrictions.
For the restrictions on file registers, refer to Page 127, Section 3.10.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The block number specified in S does not exist. –– –– –– ––
4101 There is no file register for the specified block No. –– –– –– ––

581
 QDRSET, QDRSETP

Program Example
(1) The following program compares R0 of block No. 0 and R0 of block No. 1.
[Ladder Mode]

Designates block No. 0

Executes reading R0 of block No.0

Designates block No. 1

Executes reading R0 of block No.1

Compares the read values

[List Mode]

Step Instruction Device

[Operation]
Block No. 0 Block No. 1
R0 -3216 756 R0
R1 5001 9330 R1
R2 128 D0 D1 -1762 R2
R3 -7981 -3216 756 3911 R3
R4 9610 -5 R4
R5 0 -3781 R5
Y41 turns ON since D0<D1

7.14.2 QDRSET, QDRSETP File setting for file register

Ver.

7.14.2
High
Basic Process Redundant Universal LCPU
QDRSET, QDRSETP performance
• Universal model QCPU: Models other than Q00UJCPU

Command
QDRSET QDRSET S

Command
QDRSETP S
QDRSETP
S : Character string data of the drive No./file name in which the file register is set, or head number of the devices where the character string data is stored
(character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $
S –– –– ––

582
 QDRSET, QDRSETP

Function
1
(1) Changes the file register file name used in the program to the file name being stored at the device designated by S .
After the file names have been changed, all the file registers being used by the sequence program process the file
register of the renamed file.
2
The block No. of the file register of the renamed file is 0.
Block number switches are performed by the RSET instruction.

Example When switching from Drive No. 1/File name B to Drive No. 3/File name A 3
Processing executed to file registers
Setting of a drive number
4
S and file name

6
Drive 1 Drive 1 Drive 1 Drive 2 Drive 3 Drive 4
File name File name File name File name File name File name
A B C A A
File name of file
A 7
(
File name of
the presently )
used file register
( )
register used after
the execution of
QDRSET instruction
(2) Drive number can be designated from 1 to 4. 8
(The drive number cannot be designated as drive 0 (program memory).)
Note that available drives vary depending on the CPU module used.
Refer to the manual of the CPU module and check the drives that can be specified.
(3) It is not necessary to designate the extension (.QDR) with the file name.

7.14.2 QDRSET, QDRSETP

7.14 File register switching instructions
(4) A file name setting can be deleted by designating the NULL character (00H) for the file name.
(5) File names designated with this instruction will be given priority even if a drive number and file name have been
designated in the parameters.

1. If the file name is changed with the QDRSET instruction, the file name returns to the name specified by the parameter
when the CPU module is switched from STOP to RUN. To maintain the file name even after the CPU mode is changed
from STOP to RUN, execute the QDRSET instruction with the SM402 special relay, which turns ON during one scan when
the CPU enters from STOP to RUN mode.
2. For refreshing a file register, do not change the file name of the file register with the QDRSET instruction. For restrictions
on file registers, refer to Page 127, Section 3.10.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The file name does not exist at the drive number specified in S . –– ––

583
 QCDSET, QCDSETP

Program Example
(1) The following program compares R0 of ABC in block No. 1 and R0 of DEF in block No. 1.
[Ladder Mode]

[List Mode]

Step Instruction Device

[Operation]
Block No. 0 Block No. 1
R0 -3216 756 R0
R1 5001 9330 R1
R2 128 D0 D1 -1762 R2
R3 -7981 -3216 756 3911 R3
R4 9610 -5 R4
R5 0 -3781 R5
Y41 turns ON since D0<D1

7.14.3 QCDSET, QCDSETP File setting for comments

7.14.3 QCDSET, QCDSETP Basic High

performance Process Redundant Universal LCPU

Command
QCDSET QCDSET S

Command
QCDSETP S
QCDSETP
S : Character string data of the drive No./file name in which the comment file is set, or head number of the devices where the character string data is stored
(character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $
S –– –– ––

584
 QCDSET, QCDSETP

Function
1
(1) Changes the file register file name used in the program to the file name being stored at the device designated by S .
After the file name change, comment data being used by the sequence program perform processing in relation to the
comment data of the file name after the change.
2
Example When switching from Drive No. 1/File name B to Drive No. 4/File name B

Processing executed to file registers 3

Setting of a drive number
S and file name
4

4
Drive 1 Drive 1 Drive 1 Drive 2 Drive 4 Drive 4
File name File name File name File name File name File name
A B C A A B
6
File name of file
(presently used
comment file )
File name of the
( )
register used after
the execution of
QCDSET instruction
7
(2) Drive number can be designated from 1 to 4.
(The drive number cannot be designated as drive 0 (program memory).)
Note that available drives vary depending on the CPU module used. 8
Refer to the manual of the CPU module and check the drives that can be specified.
(3) It is not necessary to designate the extension (.QCD) with the file name.
(4) A file name setting can be deleted by designating the NULL character (00H) for the file name.
(5) File names designated with this instruction will be given priority even if a drive number and file name have been

7.14.3 QCDSET, QCDSETP

7.14 File register switching instructions
designated in the parameters.

If the file name is changed with the QCDSET instruction, the file name returns to the name specified by the parameter
when the CPU module is switched from STOP to RUN.
To maintain the file name even after the CPU mode is changed from STOP to RUN, execute the QCDSET instruction with
the SM402 special relay, which turns ON during one scan when the CPU enters from STOP to RUN mode.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The file name does not exist at the drive number specified in S . ––

585
 QCDSET, QCDSETP

Program Example
(1) The following program switches object file to file name ABC. QCD at drive No. 1 when X0 is ON, and to DEF. QCD at
drive No. 3 when X1 is ON.
[Ladder Mode]

Switches to ABC at drive No. 1

Switches to DEF at drive No. 4

[List Mode]

Step Instruction Device

Caution
(1) This instruction will not be executed even when the execution command of this instruction is ON while SM721 (file
access in execution) is ON for the Universal model QCPU and LCPU. Execute this instruction when SM721 is OFF.
(2) For the High-speed Universal model QCPU and LCPU, when the drive 2 (SD memory card) is specified as the drive
number, this instruction cannot be executed while SM606 (SD memory card forced disable instruction) is ON. If the
instruction is executed, the command will be ignored.

586
 DATERD, DATERDP

7.15 Clock instructions

1
7.15.1 DATERD, DATERDP Reading clock data

7.15.1 DATERD, DATERDP Basic High

performance Process Redundant Universal LCPU
2
Command
DATERD DATERD D

Command
DATERDP D
3
DATERDP
: Head number of the devices where the read clock data will be stored (BIN 16 bits)
4
D

Setting Internal Devices J \

R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D –– ––
4
Function
(1) Reads "year, month, day, hour, minute, second, and day of week" from the clock element of the CPU module and stores 6
it as BIN value to the device designated by D or later device.
D Year (1980 to 2079)
D +1 Month (1 to 12) 7
D +2 Day (1 to 31)
Clock element D +3 Hour (24-hour clock) (0 to 23)
D
D
+4
+5
Minute
Second
(0 to 59)
(0 to 59)
8
D +6 Day of week (0 to 6)

(2) The "year" at D is stored as 4-digit year indication.

(3) The "day of week" at D +6 is stored as 0 to 6 to represent the days Sunday to Saturday.

7.15.1 DATERD, DATERDP

7.15 Clock instructions
Day of week Sun Mon Tue Wed Thu Fri Sat
Stored data 0 1 2 3 4 5 6

(4) Compensation is made automatically for leap years.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The range of the device specified by D exceeds the range of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program outputs the following clock data as BCD values:
Year .................. Y70 to Y7F
Month ............... Y68 to Y6F
Day................... Y60 to Y67
Hour ................. Y58 to Y5F
Minute .............. Y50 to Y57
Second ............. Y48 to Y4F
Week ................ Y44 to Y47

587
 DATEWR, DATEWRP

[Ladder Mode]

Outputs "Year"

Outputs "Month"

Outputs "Day"

Outputs "Hour"

Outputs "Minute"

Outputs "Second "

Outputs "Day of week"

[List Mode]

Step Instruction Device

[Operation]
BCD Y7F Y70
2 0 0 5 (Year)

D0 2005
Y6F Y68 Y67 Y60
D1 12
1 2 2 4 (Month, Day)
Clock data D2 24
2005, 12, 24, 12:57:39, Sunday D3 12
Y5F Y58 Y57 Y50
D4 57
1 2 5 7 (Hour, Minute)
D5 39
D6 0
Y4F Y48 Y47 Y44
BIN 3 9 0 (Second, Day of week)

7.15.2 DATEWR, DATEWRP Writing clock data

7.15.2 DATEWR, DATEWRP Basic High

performance Process Redundant Universal LCPU

Command
DATEWR DATEWR S

Command
DATEWRP S
DATEWRP
S : Head number of the devices where clock data to be written into the clock device is stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S –– ––

588
 DATEWR, DATEWRP

Function
1
(1) Writes clock data stored in the device number designated by S or later device number to the clock element of the CPU
module.
S Year 2
S +1 Month
S +2 Day
S +3 Hour Clock element
S +4 Minute 3
S +5 Second
S +6 Day of week
(2) Each item is set as a BIN value. 4
(3) The "year" at S is designated by using four-digit year indication between 1980 to 2079.
(4) S +1 designates the "month" in values of from 1 to 12 (January to December).
(5) S +2 designates the "day" in values of from 1 to 31.
4
(6) S +3 designates the "hour" in values of from 0 to 23 (using 24-hour clock, from 0 hours to 23 hundred hours). (Uses the
24-hour clock.)
6
(7) S +4 designates the "minute" in values of from 0 to 59.
(8) S +5 designates the "second" in values of from 0 to 59.
(9) S +6 designates the "day of week" in values of from 0 to 6 (Sunday to Saturday).
7
Day of week Sun Mon Tue Wed Thu Fri Sat
Stored data 0 1 2 3 4 5 6
8
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

7.15.2 DATEWR, DATEWRP

7.15 Clock instructions
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value outside the setting range has been set for each item. –– –– –– ––
The range of the device specified by S exceeds the range of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program writes the following clock data to the clock element as BCD values when X40 is turned ON.
Year.................. X30 to X3F Hour..........................X18 to X1F
Month ............... X28 to X2F Minute.......................X10 to X17
Day................... X20 to X27 Second .....................X8 to XF
Week ................ X4 to X7

589
 DATE+, DATE+P

[Ladder Mode]

Sets "Year"

Sets "Month"

Sets "Day"

Sets "Hour"

Sets "Minute"

Sets "Second "

Sets "Day of week"

Writes the clock data (D0 to D6)

to the clock element

[List Mode]

Step Instruction Device

[Operation]

X3F X38 X37 X30 BIN

(Year) 2 0 0 0

D0 2000
X2F X28 X27 X20
D1 12
(Month, Day) 1 2 2 4
D2 24 Clock data
D3 12 2000, 12, 24 12:57:39 Sunday
X1F X18 X17 X10
D4 57
(Hour, Minute) 1 2 5 7
D5 39
D6 0
XF X8 X7 X4
(Second, Day of week) 3 9 0 BIN

7.15.3 DATE+, DATE+P Clock data addition operation

7.15.3 DATE+, DATE+P Basic High

performance Process Redundant Universal LCPU

Command
DATE+ DATE+ S1 S2 D

Command
DATE+P S1 S2 D
DATE+P
S1 : Head number of the devices where the clock data to be adjusted by addition is stored (BIN 16 bits)
S2 : Head number of the devices where the time data to be added for adjustment is stored (BIN 16 bits)
D : Head number of the devices where the result of addition of clock (time) data will be stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S1 –– ––
S2 –– ––

D –– ––

590
 DATE+, DATE+P

Function
1
(1) Adds the time data designated by S2 to the clock data designated by S1 , and stores the result into the area starting from
the device designated by D .
Data range Data range Data range 2
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) + S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
Second Second Second
3
S1 +2 (0 to 59) S2 +2 (0 to 59) D +2 (0 to 59)

For example, adding the time 7:48:10 to 6:32:40 would result in the following operation:
S1 Hour: 6 S2 Hour: 7 D Hour: 14
S1 +1 Minute: 32
S1 +2 Second: 40
+ S2 +1 Minute: 48
S2 +2 Second: 10
D +1
D +2
Minute: 20
Second: 50
4
(2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the sum to make the final operation
result. 4
For example, if the time 20:20:20 were added to 14:20:30, the result would not be 34:40:50, but would instead be
10:40:50.
S1 Hour: 14 S2 Hour: 20 D Hour: 10 6
S1 +1 Minute: 20 + S2 +1 Minute: 20 D +1 Minute: 40
S1 +2 Second: 30 S2 +2 Second: 20 D +2 Second: 50

7
Remark
See Page 588, Section 7.15.2 for further information regarding the data that can be set for hours, minutes, and seconds.
8

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into

7.15.3 DATE+, DATE+P

7.15 Clock instructions
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value set for S1 and S2 is not within the setting range. –– –– –– ––
The range of the device specified by S1 , S2 or D exceeds the range of
4101 –– –– –– ––
the corresponding device.

Program Example
(1) The following program adds 1 hour to the clock data read from the clock element, and stores the results in the area
starting from D100 when X20 is ON.
[Ladder Mode]

Reads data in the clock element to D0 or later

Sets the time to D0 or later

591
 DATE-, DATE-P

[List Mode]

Step Instruction Device

[Operation]
• Time data read operation triggered by DATERDP instruction.
Clock element D0 95 Year
D1 5 Month
D2 15 Day
D3 10 Hour
D4 23 Minute Time data
D5 41 Second
D6 2 Day of week

• Addition triggered by DATE+P instruction.

D3 Hour: 10 D10 Hour: 1 D100 Hour: 11
D4 Minute: 23 + D11 Minute: 0 D101 Minute: 23
D5 Second: 41 D12 Second: 0 D102 Second: 41

7.15.4 DATE-, DATE-P Clock data subtraction operation

7.15.4 DATE-, DATE-P Basic High

performance Process Redundant Universal LCPU

Command
DATE- DATE- S1 S2 D

Command
DATE-P DATE-P S1 S2 D

S1 : Head number of the devices where the clock time data to be adjusted by substraction is stored (BIN 16 bits)
S2 : Head number of the devices where time data to be subtracted for adjustment is stored (BIN 16 bits)
D : Head number of the devices where the result of subtraction of clock (time) data will be stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S1 –– ––
S2 –– ––

D –– ––

Function
(1) Subtracts the time data designated by S2 from the clock data designated by S1 , and stores the result into the area starting
from the device designated by D .
Data range Data range Data range
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
S1 +2 Second (0 to 59) S2 +2 Second (0 to 59) D +2 Second (0 to 59)

For example, if the clock time 3:50:10 were subtracted from the clock time 10:40:20, the operation would be performed
as follows:
S1 Hour: 10 S2 Hour: 3 D Hour: 6
S1 +1 Minute: 40 S2 +1 Minute: 50 D +1 Minute: 50
S1 +2 Second: 20 S2 +2 Second: 10 D +2 Second: 10

592
 DATE-, DATE-P

(2) If the subtraction results in a negative number, 24 will be added to the result to make a final operation result.
For example, if the clock time 10:42:12 were subtracted from 4:50:32, the result would not be -6:8:20, but rather would
be 18:8:20. 1
S1 Hour: 4 S2 Hour: 10 D Hour: 18
S1 +1 Minute: 50 S2 +1 Minute: 42 D +1 Minute: 8
S1 +2 Second: 32 S2 +2 Second: 12 D +2 Second: 20
2
Remark
See Page 588, Section 7.15.2 for further information regarding the data that can be set for hours, minutes, and seconds.
3

4
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0. 4
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 6
4100 The value set for S1 and S2 is not within the setting range. –– –– –– ––
The range of the device specified by S1 , S2 or D exceeds the range of
4101 –– –– –– ––
the corresponding device.
7
Program Example
8
(1) The following program subtracts the time data stored in devices starting from D10 from the clock data read from the clock
element when X1C is turned ON, and stores the result at devices starting from R10.
[Ladder Mode] [List Mode]

7.15.4 DATE-, DATE-P

7.15 Clock instructions
Step Instruction Device

[Operation]
• Time data read operation triggered by DATERDP instruction.
Clock device D100 95 Year
D101 4 Month
D102 20 Day
D103 3 Hour
D104 21 Minute Time data
D105 20 Second
D106 1 Day of week
• Subtraction as triggered by DATE-P instruction (when 10 hours, 40 minutes, and 10 seconds have been designated
by D10 to D12).
D103 Hour: 3 D10 Hour: 10 R10 Hour: 16
D104 Minute: 21 D11 Minute: 40 R11 Minute: 41
D105 Second: 20 D12 Second: 10 R12 Second: 10

3:21:20 - 10:40:10 -8:41:10 16:41:10

24 is added to this value

593
 SECOND, SECONDP
7.15.5 SECOND, SECONDP Time data conversion (from Hour/Minute/Second to

7.15.5
Second)

SECOND, SECONDP Basic High

performance Process Redundant Universal LCPU

Command
SECOND SECOND S D

Command
SECONDP SECONDP S D

S : Head number of the devices where the clock data before conversion is stored (BIN 16 bits)
D : Head number of the devices where the clock data after conversion will be stored (BIN 32 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S –– –– ––

D ––

Function
(1) Converts the time data stored in the area starting from the device designated by S to seconds and stores the conversion
result into the device designated by D .
Data range
D +1 D
S Hour (0 to 23)
S +1 Minute (0 to 59) Second
S +2 Second (0 to 59)

For example, if the value were 4 hours, 29 minutes, and 31 seconds, the conversion would be made as follows:
D 1 D
S 4
S +1 29 16171
S +2 31

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value set for S is not within the setting range. –– –– –– ––
The range of the device specified by S exceeds the range of the
4101 –– –– –– ––
corresponding device.

Program Example
(1) The following program converts the clock time data read from the clock element into second when X20 is turned ON, and
stores the result at D100 and D101.
[Ladder Mode] [List Mode]

Step Instruction Device

594
 HOUR, HOURP

[Operation]
• Time data read operation triggered by DATERDP instruction.

Clock device D10 95 Year 1

D11 4 Month
D12 20 Day
D13
D14
20
21
Hour
Minute Time data
2
D15 23 Second
D16 5 Day of week

• Conversion to seconds as triggered by the SECONDP instruction. 3

D13 20
D14 21 D101,D100 73283
D15 23 4
7.15.6 HOUR, HOURP Time data conversion (from Second to Hour/Minute/

7.15.6
Second)

HOUR, HOURP Basic High

performance Process Redundant Universal LCPU 4
Command
HOUR HOUR S D
6
Command
HOURP HOURP S D

S : Head number of the devices where clock data before conversion is stored (BIN 32 bits) 7
D : Head number of the devices where the clock data after conversion will be stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H 8
S ––

D –– –– –– ––

Function

7.15.6 HOUR, HOURP

7.15 Clock instructions
(1) Converts the data in seconds stored in the device number designated by S to an hour/minute/second format, and stores
the conversion result into the area starting from the device designated by D.

Data range Data range

S 1 S
D Hour (0 to 23)
Second (0 to 86399) D +1 Minute (0 to 59)
D +2 Second (0 to 59)
For example, if 45325 seconds were the value designated, the conversion operation would be conducted as follows:
S +1 S
D 12
45325 D +1 35
D +2 25

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The value set for S is not within the setting range. –– –– –– ––
The range of the device specified by D exceeds the range of the
4101 –– –– –– ––
corresponding device.

595
 DT=, DT<>, DT>, DT<=, DT<, DT>=

Program Example
(1) The following program converts the seconds stored at D0 and D1 into an hour, minute, second format, and stores the
result at devices starting from D100 when X20 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation]
• Conversion to hour minute, and second format by the HOURP instruction (when the value 40000 seconds has been
designated by D1 and D0).
D100 11
D1,D0 40000 D101 6
D102 40

7.15.7 DT=, DT<>, DT>, DT<=, Date comparison

DT<, DT>=

Ver.
High
Basic performance Process Redundant Universal LCPU

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.15.7 DT=, DT<>, DT>, DT<=, DT<, DT>= digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

indicates an instruction symbol of DT=/DT<>/DT</DT<=/DT>/DT>=.

LD n

Command
AND n

Command

OR
n

S1 : Head number of the devices where the data to be compared are stored (BIN 16 bits)
S2 : Head number of the devices where the data to be compared are stored (BIN 16 bits)
n : Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– –– –– ––
S2 –– –– –– ––
n –– ––

596
 DT=, DT<>, DT>, DT<=, DT<, DT>=

Function
1
(1) This instruction compares the date data specified by S1 with those specified by S2 , or the date data specified by S1 with
current date data. Setting n can determine the data to be compared.
(a) Comparison of given date data 2
• This instruction treats the date data specified by S1 and S2 as a normally open contact, and then compares the
data in accordance with the value of n.
Data range Data range 3
S1 Year (1980 2079) S2 Year (1980 2079)
Comparison Comparison
S1 +1 Month (1 12) S2 +1 Month (1 12)
operator operation result

4
S1 +2 Day (1 31) S2 +2 Day (1 31)

(b) Comparison of current date data

• This instruction treats the date data specified by S1 and the current date data as a normally open contact, and
then compares the data in accordance with the value of n. 4
• Time data specified by S2 is treated as dummy data, and is ignored.
Data range
S1 Year (1980 to 2079)
Comparison Comparison
6
S1 +1 Month (1 to 12) Current date
operator operation result
S1 +2 Day (1 to 31)

7
When either S1 or S2 corresponds to any of the following in comparing given or current date data with given date data, the
operation error (error code: 4101) or a malfunction may occurs.
• The range of the devices to be used for the index modification is specified over the range of the device specified by S1
8
or S2 .

• File registers are specified by S1 or S2 without a register set.

(2) This instruction sets BIN values for each item.

7.15.7 DT=, DT<>, DT>, DT<=, DT<, DT>=

7.15 Clock instructions
(3) This instruction sets the year of four digits selected from 1980 to 2079 with the BIN value specified by S1 or S2 .

(4) This instruction sets the month selected from 1 to 12 (January to December) with the BIN value specified by S1 +1 or
S2 +1.

(5) This instruction sets the day selected from 1 to 31 (1st to 31st) for with the BIN value specified by S1 +2 or S2 +2.

597
 DT=, DT<>, DT>, DT<=, DT<, DT>=

(6) This instruction specifies the following values at n so that the data to be compared can be specified.
The bit configuration specified at n is as follows.
This instruction specifies 0 at bits from 3rd to 14th.
The instruction will be non-conductive status without
specifying 0 regardless of the operation result.

b15 b14 b3 b2 b1 b0
0/1 0 0/1 0/1 0/1

Day
If this instruction specifies 1 (on) at 15th bit, the Month
instruction compares S1 with the current date in
accordance with the bit condition specified at 0 to 2nd Year
bit.

(a) Date data to be compared (from 0 to 2nd bit)

• 0: Does not compare specified date data (year/month/day).
• 1: Compares specified date data (year/month/day).
(b) Operation data to be compared (15th bit)
• 0: Compares the date data specified by S1 with the date data specified by S2 .

• 1: Compares the date data specified by S1 with the current date data.
• Ignores the date data specified by S2 .

(c) The following table shows processing details of bits to be compared.

n value for n value for
comparison of comparison of Date to be
Processing details
specified date data specified date data compared
with given date data with current date data
0001H 8001H Day Comparison of days ( S1 +2)
0002H 8002H Month Comparison of months ( S1 +1)
0003H 8003H Month, day Comparison of months ( S1 +1) and days ( S1 +2)
0004H 8004H Year Comparison of years ( S1 )
0005H 8005H Year, day Comparison of years ( S1 ) and days ( S1 +2)
0006H 8006H Year, month Comparison of years ( S1 ) and months ( S1 +1)
Comparison of years ( S1 ), months ( S1 +1),
0007H 8007H Year, month, day
and days ( S1 +2)
No comparison of years ( S1 ), months ( S1 +1),
Other than 0001H to 0007H, 8001H to 8007H No objects
and days ( S1 +2) (Non-conductive)

(7) If the data stored in the devices to be compared are not recognized as date data, SM709 will be turned on after the
instruction execution and no-conductive status will be made. Even if they are not recognized as date data but the range
of the devices is within the setting range, SM709 will not be turned on.
Moreover, if the range of devices specified by S1 to S1 +2 or S2 to S2 +2 exceeds the range of specified devices, SM709
will be turned on after the instruction execution and no-conductive status will be made.
Once SM709 is turned on, on-status will be retained till when the CPU modules are reset or powered off. Therefore, turn
off SM709 if necessary.

598
 DT=, DT<>, DT>, DT<=, DT<, DT>=

(8) The following table shows the comparison operation results for each instruction.
Instruction Comparison Instruction Comparison
Condition Condition
symbols in operation result symbols in operation result
1
DT= S1 = S2 DT= S1 S2

DT<> S1 S2 DT<> S2 = S1

DT> S1 > S2
Conductive status
DT> S1 S2 No-conductive 2
DT<= S1 S2 DT<= S1 > S2 status

DT< S1 < S2 DT< S1 S2

DT>= S1 S2 DT>= S1 < S2 3

(a) The following figure shows the comparison example of dates.
A B C
4
2006/1/1 2007/1/1 2008/1/1 2009/1/1
(2006/9/22) (2007/6/23) (2008/8/8)

The following table shows the conductive states resulting from performing the comparison operation of the dates A, 4
B, and C shown above.
Even if the objects to be compared are under the same condition, the comparison operation results vary depending
on the objects selected. 6
Comparison Comparison condition
objects A<B B<C A<C
Day
7
Month
Month, day
Year
8
Month, day
Year, month
Year, month, day
No objects

7.15.7 DT=, DT<>, DT>, DT<=, DT<, DT>=

7.15 Clock instructions
: Conductive : No-conductive

(b) Even if the dates to be compared do not exist practically, this instruction executes the comparison operation for the
objects with the settable dates in accordance with the following condition.
• Date A: 2006/02/30 (This date is settable, though it does not exist.)
• Date B: 2007/03/29
• Date C: 2008/02/31 (This date is settable, though it does not exist.)
Comparison Comparison condition
objects A<B B<C A<C
Day
Month
Month, day
Year
Month, day
Year, month
Year, month, day
No objects
: Conductive : No-conductive

599
 DT=, DT<>, DT>, DT<=, DT<, DT>=

Operation Error
(1) There is no operation error in the DT=, DT<>, DT>, DT<=, DT<, or DT>= instruction.

Program Example
(1) The following program compares the data stored in D0 with the data (year, month, and day) stored in D10, and makes
Y33 be conductive status when the data stored in D0 meet the data stored in D10.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program compares the data stored in D0 with the current date data (year and month), and makes Y33 be
conductive status when the data stored in D0 do not meet the current date data, when M0 is turned on.
[Ladder Mode] [List Mode]
Step Instruction Device

(3) The following program compares the data stored in D0 with the data (year and day) stored in D10, and makes Y33 be
conductive status when the data value stored in D10 is smaller than the data value stored in D0, when M0 is turned on.
[Ladder Mode] [List Mode]
Step Instruction Device

(4) The following program compares the data stored in D0 with the current date data (year), and makes Y33 be conductive
status when the value of the current date data is the data value stored in D0 or larger.
[Ladder Mode] [List Mode]
Step Instruction Device

600
 TM=, TM<>, TM>, TM<=, TM<, TM>=
7.15.8 TM=, TM<>, TM>, TM<=, Time comparison
TM<, TM>=

Ver.
High
Basic Process Redundant Universal LCPU
1
performance

• QnU(D)(H)CPU, QnUDE(H)CPU: the serial number (first five

7.15.8 TM=, TM<>, TM>, TM<=, TM<, TM>= digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU, QnUDVCPU: Supported

indicates an instruction symbol of DT=/DT<>/DT</DT<=/DT>/DT>=. 2

LD S1 S2 n
Command 3
AND S1 S2 n
Command

OR
4
S1 S2 n

S1 : Head number of the devices where the data to be compared are stored (BIN 16 bits) 4
S2 : Head number of the devices where the data to be compared are stored (BIN 16 bits)
n : Value of the data to be compared or the number of the stored data to be compared (BIN 16 bits)
Setting Internal Devices J \ Constants
Data Bit Word
R, ZR
Bit Word
U \G Zn
K, H
Other
6
S1 –– –– –– ––
S2 –– –– –– ––
n –– –– 7

Function 8
(1) This instruction compares the clock data specified by S1 with those specified by S1 , or the clock data specified by S1 with
the current time data. Setting n determines the data to be compared.
(a) Comparison of given clock data
• This instruction treats the clock data specified by and the clock data specified by as a normally open

7.15.8 TM=, TM<>, TM>, TM<=, TM<, TM>=

7.15 Clock instructions
S1 S1

contact, and compares the data in accordance with the value of n.

Data range Data range
S1 Hour (0 23) S2 Hour (0 23)
Comparison Comparison
S1 +1 Minute (0 59) S2 +1 Minute (0 59)
operator operation result
S1 +2 Second (0 59) S2 +2 Second (0 59)

(b) Comparison of current time data

• This instruction treats the clock data specified by S1 and the current time data as a normally open contact, and
compares the data in accordance with the value of n.
• This instruction treats the clock data specified by S1 as dummy data and ignores the data.
Data range
S1 Hour (0 23)
Comparison Comparison
S1 +1 Minute (0 59) Current time
operator operation result
S1 +2 Second (0 59)

When either S1 or S1 corresponds to any of the following conditions in comparing given or current time data with specified
clock data, the operation error (error code: 4101) or a malfunction may occurs.
• The range of the devices to be used for the index modification is specified over the range of the device specified by S1

or S1 .

• File registers are specified by S1 or S1 without a register set.

(2) This instructions set BIN values for each item.

601
 TM=, TM<>, TM>, TM<=, TM<, TM>=

(3) This instructions sets the time selected from 0 to 23 (midnight to 23 o'clock) with the BIN value specified by S1 or S1 .

(Uses the 24-hour clock.)

(4) This instructions sets the minute selected from 0 to 59 (0 to 59 minutes) with BIN value specified by S1 +1 or S1 +1.

(5) This instructions sets the second selected from 0 to 59 (0 to 59 seconds) with BIN value specified by S1 +2 or S1 +2.

(6) This instructions specifies the following values at n so that the data to be compared can be specified.
The bit configuration specified at n is as follows.
This instruction specifies 0 at bits from 3rd to 14th.
The instruction will be non-conductive status without
specifying 0 regardless of the operation result.

b15 b14 b3 b2 b1 b0
0/1 0 0/1 0/1 0/1

Second
If this instruction specifies 1 (on) at 15th bit, the Minute
instruction compares S1 with the current date in
accordance with the bit condition specified at 0 to 2nd Hour
bit.

(a) Clock data to be compared (from 0 to 2nd bit)

• 0: Does not compare specified clock data (hour/minute/second).
• 1: Compares specified clock data (hour/minute/second).
(b) Operation data to be compared (15th bit)
• 0: Compares the clock data specified by S1 with the clock data specified by S1 .

• 1: Compares the clock data specified by S1 with the current time data.
Ignores the clock data specified by S1 .

(c) The following table shows processing details of bits to be compared.

n value for n value for
comparison of comparison of Time to be
Processing details
pecified clock data with specified clock data compared
given clock data with current time data
0001H 8001H Second Comparison of seconds ( S1 +2)
0002H 8002H Minute Comparison of minutes ( S1 +1)
Minute, Comparison of minutes ( S1 +1) and seconds
0003H 8003H
second days ( S1 +2)
0004H 8004H Hour Comparison of hours ( S1 )
Hour, Comparison of hours ( S1 ) and
0005H 8005H
second seconds ( S1 +2)
0006H 8006H Hour, minute Comparison of hours ( S1 ) and minutes ( S1 +1)
Hour, minute, Comparison of hours ( S1 ), minutes ( S1 +1), and
0007H 8007H
second seconds ( S1 +2)
Other than 0001H to 0007H, No comparison of hours ( S1 ), minutes ( S1 +1),
No objects
8001H to 8007H and seconds ( S1 +2) (Non-conductive)

(7) If the data stored in the devices to be compared are not recognized as date data, SM709 will be turned on after the
instruction execution and no-conductive status will be made. Once SM709 is turned on, on-status will be retained till
when the CPU modules are reset or powered off. Therefore, turn off SM709 if necessary.
Moreover, if the range of devices specified by S1 to S1 +2 or S1 to S1 +2 exceeds the range of specified devices, SM709
will be turned on and no-conductive status will be made.

602
 TM=, TM<>, TM>, TM<=, TM<, TM>=

(8) The following table shows the comparison operation results for each instruction.
Instruction Comparison Instruction Comparison
Condition Condition
symbols in operation result symbols in operation result
1
TM= S1 = S2 TM= S1 S2

TM<> S1 S2 TM<> S2 = S1

TM> S1 > S2
Conductive status
TM> S1 S2 No-conductive 2
TM<= S1 S2 TM<= S1 > S2 status

TM< S1 < S2 TM< S1 S2

TM>= S1 S2 TM>= S1 < S2

3
(a) The following figure shows the comparison example of time.
A B C
4
0 Midnight 6:00 N00n 18:00 0 Midnight
4:50:55 14:08:58 22:47:05

The following table shows the conductive states resulting from performing the comparison operation of the dates A, 4
B, and C shown above.
Even if the objects to be compared are under the same condition, the comparison operation results vary depending
on the objects selected. 6
Comparison condition
Comparison objects
A<B B<C A<C
Second
Month
7
Month, day
Hour
Hour, second 8
Hour, minute
Hour, minute, second
No objects
: Conductive : No-conductive

7.15.8 TM=, TM<>, TM>, TM<=, TM<, TM>=

7.15 Clock instructions
Operation Error
(1) There is no operation error in the TM=, TM<>, TM>, TM<=, TM<, or TM>= instruction.

603
 TM=, TM<>, TM>, TM<=, TM<, TM>=

Program Example
(1) The following program compares the data stored in D0 with the data (hour, minute, and second) stored in D10, and
makes Y33 be conductive status when the data stored in D0 meet the data stored in D10.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program compares the data stored in D0 with the current time data (hour and minute), and makes Y33 be
conductive status when the data stored in D0 do not meet the current date data, when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

(3) The following program compares the data stored in D0 with the data (hour and second) stored in D10, and makes Y33 be
conductive status when the data value stored in D10 is smaller than the data value stored in D0, when M0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

(4) The following program compares the data stored in D0 with the current time data (hour), and makes Y33 be conductive
status when the value of the current time data is the data value stored in D0 or larger.
[Ladder Mode] [List Mode]

Step Instruction Device

604
 S.DATERD, SP.DATERD

7.16 Expansion Clock Instructions

1
7.16.1 S.DATERD, SP.DATERDReading expansion clock data

Ver. Ver. Ver.

2
High
Basic performance Process Redundant Universal LCPU

7.16.1 S.DATERD, SP.DATERD • High Performance model QCPU, Process CPU, Redundant
CPU: The serial number (first five digits) is "07032" or later.

S.DATERD
Command
S.DATERD D 3
Command
SP.DATERD D
SP.DATERD
4
D : Head number of the devices where the read clock data will be stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word 4
D –– ––

Function 6
(1) Reads "year, month, day, hour, minute, second, day of the week, and millisecond" from the clock element of the CPU
module, and stores it as BIN value into the device specified by D or later device. 7
D Year (1980 to 2079)
D +1 Month (1 to 12)
D
D
+2
+3
Day
Hour (24-hour clock)
(1 to 31)
(0 to 23)
8
Clock element
D +4 Minute (0 to 59)
D +5 Second (0 to 59)
D +6 Day of week (0 to 6)
D +7 Millisecond (0 to 999)

7.16.1 S.DATERD, SP.DATERD

7.16 Expansion Clock Instructions
(2) The "year" at D is stored as 4-digit year indication.
(3) The "day of the week" at D +6 is stored as 0 to 6 to represent the days Sunday to Saturday.
Day of week Sunday Monday Tuesday Wednesday Thursday Friday Saturday
Stored data 0 1 2 3 4 5 6

(4) Compensation is made automatically for leap years.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The range of the device specified by D exceeds the range of the
4101 –– –– –– ––
corresponding device.

605
 S.DATERD, SP.DATERD

Program Example
(1) The following program outputs the following clock data as BCD values:
Year ..................Y70 to Y7F
Month................Y68 to Y6F
Day ...................Y60 to Y67
Hour..................Y58 to Y5F
Minute...............Y50 to Y57
Second .............Y48 to Y4F
Week ................Y44 to Y47
Millisecond........Y38 to Y43
[Ladder Mode]

Outputs "Year"

Outputs "Month"

Outputs "Day"

Outputs "Hour"

Outputs "Minute"

Outputs "Second"

Outputs "Day of Week"

Outputs "Millisecond"

[List Mode]
Step Instruction Device

[Operation]
BCD Y7F Y70
2 0 0 5 (Year)

D0 2005
Y6F Y68 Y67 Y60
D1 12
1 2 2 4 (Month, Day)
Clock data D2 24
2005, 12, 24 12:57:39 Sunday 530 D3 12
Y5F Y58 Y57 Y50
D4 57
1 2 5 7 (Hour, Minute)
D5 39
D6 0
Y4F Y48 Y47 Y44
D7 530
3 9 0 (Second, Day of week)
BIN
Y43 Y38
5 3 0 (Millisecond)

606
 S.DATE+, SP.DATE+

Caution
1
(1) This instruction reads clock data and stores those to a specified device even if a wrong clock data is set to the CPU
module. (example: Feb. 30th)
When setting clock data with the DATEWR instruction or GX Developer, make sure to set a correct data.
2
(2) Time error of reading a clock data of millisecond is a maximum of 2ms. (Difference between the data memorized by clock
element inside of the CPU module and the data read by this function.)
(3) Specifying digit for the bit device can be used only when the following conditions (a) and (b) are met. 3
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR. 4
(error code: 4004) will occur.

4
7.16.2 S.DATE+, SP.DATE+ Expansion clock data addition operation

Ver. Ver. Ver.

High
Basic performance Process Redundant Universal LCPU

7.16.2 S.DATE+, SP.DATE+ • High Performance model QCPU, Process CPU, Redundant
CPU: The serial number (first five digits) is "07032" or later. 6
Command
S.DATE+ S.DATE+ S1 S2 D

Command
7
SP.DATE+ S1 S2 D
SP.DATE+
S1 : Head number of the devices where the clock data to be adjusted by addition is stored (BIN 16 bits) 8
S2 : Head number of the devices where the time data to be added for adjustment is stored (BIN 16 bits)
D : Head number of the devices where the result of addition of clock (time) data will be stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

7.16.2 S.DATE+, SP.DATE+

7.16 Expansion Clock Instructions
S1 –– ––
S2 –– ––

D –– ––

Function
(1) Adds the time data designated by S2 to the clock data designated by S1 , and stores the result into the area starting from
the device designated by D .
Setting data Setting data Setting data
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
S1 +2 Second (0 to 59) + S2 +2 Second (0 to 59) D +2 Second (0 to 59)
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond (0 to 999) S2 +4 Millisecond (0 to 999) D +4 Millisecond (0 to 999)

For example, adding the time 7:48:10:500 to 6:32:40:875 would result in the following operation:
S1 Hour: 6 S2 Hour: 7 D Hour: 14
S1 +1 Minute: 32 S2 +1 Minute: 48 D +1 Minute: 20
S1 +2 Second: 40 + S2 +2 Second: 10 D +2 Second: 51
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375

607
 S.DATE+, SP.DATE+

(2) If the results of the addition of time exceed 24 hours, 24 hours will be subtracted from the sum to make the final operation
result.
For example, when the time 20:20:20:500 is added to 14:20:30:875, the result is not 34:40:51:375, but 10:40:51:375.
S1 Hour: 14 S2 Hour: 20 D Hour: 10
S1 +1 Minute: 20 S2 +1 Minute: 20 D +1 Minute: 40
S1 +2 Second: 30 + S2 +2 Second: 20 D +2 Second: 51
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375

Devices, S1 +3, S2 +3, and D +3 are not used for operation.

A clock data read by the S(P).DATERD instruction can be directly added.

D Hour
D +1 Minute
D +2 Second
D +3 Day of week
D +4 Millisecond

When the clock data is read by the S(P).DATERD instruction,

day of week is inserted between "second" and "millisecond".
If the S(P).DATE+ instruction is used to read the clock data,
the data can be directly used for addition since it does not perform
the calculation for the day of a week.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value set for S1 and S2 is not within the setting range. (See
4100 ––
Function (1).)
The range of the device specified by S1 , S2 or D exceeds the range of
4101 –– –– –– ––
the corresponding device.

Caution
(1) Specifying digit for the bit device can be used only when the following conditions (a) and (b) are met.
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR.
(error code:4004) will occur.

608
 S.DATE+, SP.DATE+

Program Example
1
(1) The following program adds 1 hour to the clock data read from the clock element, and stores the results into the area
starting from D100 when X20 is turned ON.
[Ladder Mode] 2
Reads out the clock element
data to D0 or later.
3
Sets the time to D10 or later.

[List Mode] 6
Step Instruction Device

[Operation]
8
• Time data read operation by the SP.DATERD instruction
Clock element D0 05 Year
D1 5 Month

7.16.2 S.DATE+, SP.DATE+

7.16 Expansion Clock Instructions
D2 17 Day
D3 10 Hour
D4 23 Minute Time data
D5 41 Second
D6 2 Day of week
100 Millisecond Time data

• Addition by the SP.DATE+ instruction

D3 Hour: 10 D10 Hour: 1 D100 Hour: 11
D4 Minute: 23 D11 Minute: 0 D101 Minute: 23
D5 Second: 41 + D12 Second: 0 D102 Second: 41
D6 2 (Tuesday) D13 -- D103 --
D7 Millisecond: 100 D14 Millisecond: 0 D104 Millisecond: 100

609
 S.DATE-, SP.DATE-
7.16.3 S.DATE-, SP.DATE- Expansion clock data subtraction operation

Ver. Ver. Ver.

High
Basic performance Process Redundant Universal LCPU

7.16.3 S.DATE-, SP.DATE- • High Performance model QCPU, Process CPU, Redundant
CPU: The serial number (first five digits) is "07032" or later.

Command
S.DATE- S.DATE- S1 S2 D

Command
SP.DATE- SP.DATE- S1 S2 D

S1 : Head number of the devices where the clock time data to be adjusted by substraction is stored (BIN 16 bits)
S2 : Head number of the devices where time data to be subtracted for adjustment is stored (BIN 16 bits)
D : Head number of the devices where the result of subtraction of clock (time) data will be stored (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S1 –– ––
S2 –– ––

D –– ––

Function
(1) Subtracts the time data designated by S2 from the clock data designated by S1 , and stores the result into the area starting
from the device designated by D .
Setting data Setting data Setting data
S1 Hour (0 to 23) S2 Hour (0 to 23) D Hour (0 to 23)
S1 +1 Minute (0 to 59) S2 +1 Minute (0 to 59) D +1 Minute (0 to 59)
S1 +2 Second (0 to 59) - S2 +2 Second (0 to 59) D +2 Second (0 to 59)
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond (0 to 999) S2 +4 Millisecond (0 to 999) D +4 Millisecond (0 to 999)

For example, when the clock time 3:50:10:500 is subtracted from the clock time 10:40:20:875, the operation is performed
as follows:
S1 Hour: 10 S2 Hour: 3 D Hour: 6
S1 +1 Minute: 40 S2 +1 Minute: 50 D +1 Minute: 50
S1 +2 Second: 20 - S2 +2 Second: 10 D +2 Second: 10
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375

(2) If the subtraction results in a negative number, 24 will be added to the result to make a final operation result.
For example, when the clock time 10:42:12:500 is subtracted from 4:50:32:875, the result is not 6:8:20:375, but
18:8:20:375.
S1 Hour: 4 S2 Hour: 10 D Hour: 18
S1 +1 Minute: 50 S2 +1 Minute: 42 D +1 Minute: 8
S1 +2 Second: 32 - S2 +2 Second: 12 D +2 Second: 20
S1 +3 -- S2 +3 -- D +3 --
S1 +4 Millisecond: 875 S2 +4 Millisecond: 500 D +4 Millisecond: 375

610
 S.DATE-, SP.DATE-

Devices, S1 +3, S2 +3, and D +3 are not used for operation.

A clock data read by S(P).DATERD instruction can be directly subtracted.
1
D Hour

2
D +1 Minute
D +2 Second
D +3 Day of week
D +4 Millisecond

When the clock data is read by the S(P).DATERD instruction, 3

day of week is inserted between "second" and "millisecond".
If the S(P).DATE- instruction is used to read the clock data,

4
the data can be directly used for subtraction since it does not
perform the calculation for the day of the week.

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0. 6
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
7
The value set for S1 and S2 is not within the setting range. (See
4100 ––
Function (1).)
The range of the device specified by , or exceeds the range of
8
S1 S2 D
4101 –– –– –– ––
the corresponding device.

Caution
(1) Specifying digit for the bit device can be used only when the following conditions (a) and (b) are met.

7.16.3 S.DATE-, SP.DATE-

7.16 Expansion Clock Instructions
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR. (error code:4004) will occur.

Program Example
(1) The following program subtracts the time data stored in the area starting from D10 from the clock data read from the
clock element when X1C is turned ON, and stores the result into the area starting from D100.
[Ladder Mode]

Reads out the clock element

data to D0 or later.

Sets the time to D10 or later.

611
 S.DATE-, SP.DATE-

[List Mode]
Step Instruction Device

[Operation]
• Time data read operation by the SP.DATERD instruction
Clock element D0 05 Year
D1 2 Month
D2 23 Day
D3 8 Hour
D4 42 Minute Time data
D5 1 Second
D6 3 Day of week
D7 997 Millisecond Time data

• Subtraction by the SP.DATE- instruction

D3 Hour: 8 D10 Hour: 10 D100 Hour: 22
D4 Minute: 42 D11 Minute: 40 D101 Minute: 1
D5 Second: 1 - D12 Second: 10 D102 Second: 51
D6 3 (Wednesday) D13 -- D103 --
D7 Millisecond: 997 D14 Millisecond: 500 D104 Millisecond: 497

8:42:1:997 - 10:40:10:500 -2:1:51:497

Adds 24 to this value

22:1:51:497

612
7.17 Program control instructions
1
(1) Processing when the execution type is converted with the program control instruction is as follows.

Execution type before change

Executed Instruction 2
PSCAN PSTOP POFF PLOW
No change-remains Output turned OFF in
Scan execution type
scan type execution. next scan.
Becomes stand-by type. Becomes stand-by 3
Becomes low speed
Initial execution type type from the next
Becomes scan execution type.
scan after that.
execution type.
Stand-by type
No change-remains
Ignored 4
stand-by type
Low speed execution
Low speed execution
Low speed execution type execution is
type execution is
type execution is stopped, and output is 4
stopped, becomes No change -remains low
Low speed execution type stopped, becomes turned OFF in the next
scan execution type speed execution type.
stand-by type from next scan. Becomes
from the next scan.
(Execution from step 0)
scan. stand-by type from the 6
next scan after that.
Output turned OFF in
next scan.
Fixed scan execution type
Becomes scan
Becomes stand-by type. Becomes stand-by
Becomes low speed 7
execution type. execution type.
type from the next
scan after that.

8
Once the fixed scan execution type program is changed to another execution type, it cannot be returned to the fixed scan
execution type.

7.17 Program control instructions

(2) As program execution type conversions by PSCAN and PSTOP instructions occur at the END processing, such
conversions are impossible during program execution.
When different execution types have been set for the same program in the same scan, the execution type will be that
specified by the execution switching command that was executed last.
END processing END processing END processing
Execution
program name GHI "ABC" GHI GHI *1 DEF *1 GHI

PSTO executes "ABC" Converts "DEF" into the scan execution

PSCAN executes "DEF" type program and "ABC" to the stand-by
type program
*1: The order of "GHI" and "DEF" program execution is determined by the program settings parameters.
Switching from the fixed scan execution type program to the execution type program is performed in the following timing.
(a) For the Universal model QCPU, LCPU
The execution type is changed when the execution of the fixed scan execution type is stopped at the END
processing after the program control instruction execution.
(b) Basic model QCPU, High Performance model QCPU, Process CPU, and Redundant CPU
The execution of the fixed scan execution type is stopped at the execution of the program control instruction, and
the execution type is changed at the END processing.
(3) When the POFF instruction is executed, the output is turned OFF at the next scan, and the execution type will be the
stand-by type at the second next scan and later.
If executed prior to the output OFF processing, the program control instruction is ignored.

613
 PSTOP, PSTOPP

7.17.1 PSTOP, PSTOPP Program standby

7.17.1 PSTOP, PSTOPP Basic High

performance Process Redundant Universal LCPU

Command
PSTOP PSTOP S

Command
PSTOPP PSTOPP S

S : Character string for the name of the program file to be set in the stand-by status or head number of the devices where the character string data is stored
(character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $
S –– –– ––

Function
(1) Places the file name program stored in the device designated by S in the stand-by status.
(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as the stand-by type.
(3) The specified program is placed in the stand-by status when END processing is performed.
(4) This instruction will be given priority even in cases when a program execution type has been designated in the
parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The program with the file name specified by S does not exist. ––
2412 The program type of the file name specified by S is the SFC program. ––
The range of the device specified by S exceeds the range of the
4101 ––
corresponding device.

Program Example
(1) The following program places the program with the file name ABC in the stand-by status when X0 goes ON.
[Ladder Mode] [List Mode]

Step Instruction Device

614
 POFF, POFFP
7.17.2 POFF, POFFP Program output OFF standby

7.17.2 POFF, POFFP Basic High

Process Redundant Universal LCPU
1
performance

Command
POFF POFF S

POFFP
Command
POFFP S
2
S : File name of the program to be set in the standby status by turning OFF the output, or the device where the file name is stored (character string)
Setting Internal Devices
R, ZR
J \
U \G Zn
Constants
Other
3
Data Bit Word Bit Word $
S –– –– ––

4
Function
(1) Changes the execution type of the program with the file name stored in the device designated by S . 4
• Scan execution type :Turns OFF outputs at the next scan (Non-execution processing). Programs are set as
the stand-by type after the subsequent scan.
• Low speed execution type :Stops the execution of the low speed execution type program and turns OFF outputs at 6
the next scan. Programs are set as the stand-by type after the subsequent scan.
(2) Only the programs stored in the drive No. 0 (program memory) can be set as the stand-by type.
(3) This instruction will be given priority even in cases when a program execution type has been designated in the 7
parameters.
(4) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.) 8

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into

7.17.2 POFF, POFFP

7.17 Program control instructions
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The program with the file name specified by S does not exist. ––
The range of the device specified by S exceeds the range of the
4101 ––
corresponding device.

615
 PSCAN, PSCANP

Remark
1. Non-execution processing is identical to the processing that is conducted when the condition contacts for the individual coil
instructions are in the OFF state.
The operation results for the individual coil instructions following non-execution processing will be as follows, regardless of
the ON/OFF status of the individual contacts:
OUT instruction ............ Forced OFF
SET instruction
RST instruction
SFT instruction ............ Maintains status
Basic instruction
Application instruction
PLS instruction Processing identical to when
............
Pulse generation instruction ( P) condition contacts are OFF
Current value of low speed/high speed timer ............ 0
Current value of retentive timer
............ Preserves
Current value of counter

Program Example
(1) The following program makes the program with the file name ABC non-executionable and places it in the standby status
when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7.17.3 PSCAN, PSCANP Program scan execution registration

7.17.3 PSCAN, PSCANP Basic High

performance Process Redundant Universal LCPU

Command
PSCAN PSCAN S

Command
PSCANP PSCANP S

S : File name of the program to be set as a scan execution type, or head number of the devices where the file name is stored (character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $
S –– –– ––

Function
(1) Sets the program whose file name is being stored at the device designated by S in the scan execution type.
(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as the scan execution type.

616
 PLOW, PLOWP

(3) Designated programs assume the scan execution type with END processing.
Example
When programs A, B, and C exist and program A performs "PSCAN" of program D. 1
A B C END A B C D END

Execution of Program D
2
PSCAN is executed
Scan Scan
(4) This instruction will be given priority even in cases when a program execution type has been designated in the 3
parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.) 4

Operation Error 4
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

Error
Q00J/ 6
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The program with the file name specified by
The specified file name is the SFC program, and the SFC program for
S does not exist. ––
7
the other file name has been already started.
2504 –– –– ––
(For the High Performance model QCPU, Process CPU, Redundant
CPU) 8
The range of the device specified by S exceeds the range of the
4101 ––
corresponding device.
The specified file name is the SFC program, and the SFC program for
4131 the other file name has been already started. (Dual activation error of –– –– –– ––

7.17.4 PLOW, PLOWP

7.17 Program control instructions
the SFC program)

Program Example
(1) The following program sets the program with file name ABC as scan execution type when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7.17.4 PLOW, PLOWP Program low speed execution registration

7.17.4 PLOW, PLOWP Basic High

performance Process Redundant Universal LCPU

Command
PLOW PLOW S

Command
PLOWP PLOWP S

S : File name of the program to be set as a low speed execution type, or head number of the devices where the file name is stored (character string)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $

S –– –– ––

617
 PLOW, PLOWP

Function
(1) Sets the program whose file name is being stored at the device designated by S in low-speed execution type.
(2) Only the programs stored in the drive No. 0 (program memory/internal RAM) can be set as the low speed execution type.
(3) Designated programs assume the low speed execution type with END processing.
Example
When programs A, B, and C exist and program A performs "PLOW" of program D. (Assume that the constant scan has
been set.)
Waiting for constant
A B C END A B C END D

Execution of Program D
PLOW is executed

Scan Scan
(4) This instruction will be given priority even in cases when a program execution type has been designated in the
parameters.
(5) It is not necessary to designate the extension (.QPG) with the file name.
(Only .QPG files will be acted on.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The program with the specified file name does not exist. –– –– –– ––
4235 There is a CHK instruction in the program with the specified file name. –– –– –– ––

Program Example
(1) The following program sets the program with file name ABC as low-speed execution type when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

618
 PCHK
7.17.5 PCHK Program execution status check

7.17.5 PCHK Basic High

Process Redundant Universal LCPU
1
performance

LDPCHK PCHK File name

Command
ANDPCHK PCHK File name 2
Command
ORPCHK

PCHK File name

3
S : File name of the program whose execution status will be checked (character string)
Setting Internal Devices
R, ZR
J \
Zn
Constants
Other
4
U \G
Data Bit Word Bit Word $
S –– ––
\
4
Function
(1) Checks whether the program of the specified file name is in execution or not (non-execution).
(2) The instruction is in conduction when the program of the specified file name is in execution, and the instruction is in non- 6
conduction when the program is in non-execution.
(3) Specify the file name without an extension (.QPG).
For example, specify "ABC" when the file name is ABC.QPG. 7

Operation Error 8
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01

7.17.5 PCHK
7.17 Program control instructions
2410 The program with the specified file name does not exist. –– –– ––

Program Example
(1) Program that keeps Y10 ON when the program file "ABC.QPG" is being executed.

PCHK "ABC" Y10

Execution

Non-execution

Remark
Non-execution indicates that the program execution type is a stand-by type.
Execution indicates that the program execution type is a scan execution type (including during output OFF (during non-
execution processing)), low speed execution type or fixed scan execution type.

619
 PCHK

The PCHK instruction is in conduction when the program of the specified file name (target program) is in execution, and
the instruction is in non-conduction when the program is in non-execution.
When the target program is set to non-execution (stand-by type) with the POFF instruction, the PCHK instruction is in
conduction while the non-execution processing of the target program is being performed.
At the END processing of the scan where the non-execution processing is completed, the target program is put into non-
execution (stand-by type), and the PCHK instruction is brought into non-conduction.
Therefore, note that if the PCHK instruction is executed for the program where the non-execution processing has been
completed by the POFF instruction, the PCHK instruction may be brought into conduction.

The following chart shows the operation performed when program A executes the POFF instruction of program B and
program C executes the PCHK instruction of program B with the programs being executed in order of program A, program
B and program C.
Program B execution type change
(Scan execution type to stand-by type)

END processing END processing END processing

Scan Scan Scan Scan

execution execution execution execution
Program A Scan Scan
execution execution
Program B Scan Scan Scan
execution execution execution
Program C
POFF instruction is Non-execution processing
executed in program B is performed.
Continuity
PCHK B
Non-continuity

620
 WDT, WDTP

7.18 Other instructions

1
7.18.1 WDT, WDTP Watchdog timer reset

7.18.1 WDT, WDTP Basic High

performance Process Redundant Universal LCPU
2
Command
WDT WDT

WDTP
Command
WDTP
3

Setting Internal Devices

Data Bit Word
R, ZR
Bit
J \
Word
U \G Zn Constants Other 4
–– ––

4
Function
(1) Resets watchdog timer during the execution of a sequence program.
(2) Used in cases where the scan time exceeds the value set for the watchdog timer due to prevailing conditions. 6
If the scan time exceeds the watchdog timer setting value on every scan, change the watchdog timer settings at the
peripheral device parameter settings.
(3) Make sure that the setting for t1 from step 0 to the WDT instruction and the setting for t2 from the WDT instruction to the 7
END (FEND) instruction do not exceed the setting value of the watchdog timer.
Step 0
WDT
END (FEND)
8

T1 T2

7.18.1 WDT, WDTP

7.18 Other instructions
(4) The WDT instruction can be used two or more times during a single scan, but care should be taken in such cases,
because of the time required until the output goes OFF during the generation of an error.
(5) Scan time values stored at the special register will not be cleared even if the WDT or WDTP instruction is executed.
Accordingly, there are times when the value for the scan time for the special register is greater than the value of the
watchdog timer set at the parameters.

Operation Error
(1) There is no operation error in the WDT(P) instruction.

Program Example
(1) The following program has a watchdog timer setting of 200ms, when due to the execution conditions program execution
requires 300ms from step 0 to the END (FEND) instruction.
[When WDT instruction is used]

Program where
Program where scan time is
scan time is 150 ms.
300 ms.
WDT
END
Program where
scan time is
150 ms.

END

621
 DUTY
7.18.2 DUTY Timing pulse generation

7.18.2 DUTY Basic High

performance Process Redundant Universal LCPU

Command
DUTY DUTY n1 n2 D

n1 : Number of scans for ON (BIN 16 bits)

n2 : Number of scans for OFF (BIN 16 bits)
D : User timing clock (SM420 to SM424, SM430 to M434) (bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n1 ––
n2 ––
*1 –– ––
D

*1: Only SM420 to SM424, SM430 to SM434 can be used.

Function
(1) Turns the user timing clock (SM420 to SM424, SM430 to M434), designated by D , ON for the duration equivalent to the
number of scans specified by n1, and OFF for the duration equivalent to the number of scans specified by n2.
ON
SM420 to SM424 OFF
SM430 to SM434 n1 scans n2 scans

(2) Scan execution type programs use SM420 to SM424, and low speed execution type programs use SM430 to SM434.
(3) The following will take place if both n1 and n2 have been set for 0:
(a) n1 0, n2 0 SM420 to SM424 and SM430 to SM434 will stay OFF.
(b) n1 0, n2 0 SM420 to SM424 and SM430 to SM434 will stay ON.

(4) The data designated by n1, n2, and D is registered with the system when the DUTY instruction is executed, and the
timing pulse is turned ON and OFF by END processing.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The values of n1 and n2 are less than 0. –– –– –– ––
The device specified in D is not from SM420 to SM424 or SM430 to
4101 –– –– –– ––
SM434.

Program Example
(1) The following program turns SM420 ON for 1 scan, and OFF for 3 scans if X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

622
 TIMCHK

[Operation]
ON

X0
OFF 1
ON
OFF
SM420
1 scan 3 scans 2
7.18.3 TIMCHK Time check

Ver.
High
3
Basic performance Process Redundant Universal LCPU

7.18.3 TIMCHK • Basic model QCPU: The serial number (first five digits) is
"04122" or later.
4
command
TIMCHK TIMCHK S1 S2 D

4
S1 : Device where the measured current value will be stored (BIN 16 bits)
S2 : Device where the set value of measurement is stored (BIN 16 bits)
: Device to be turned ON at time-out (bits)
6
D

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S1 –– –– ––

S2 –– 7
D –– –– ––

8
Function
(1) Measures the ON time of the device used as a condition, and turns ON the device specified by S2 if the condition device
remains ON for longer than the time set to the device specified by D .

7.18.3 TIMCHK
7.18 Other instructions
(2) The current value of the device specified by S1 is cleared to 0 and the device specified by D is turned OFF at the leading
edge of the execution command.
The current value of the device designated by S1 and the ON status of the device designated by D are retained after the
execution command turns OFF.
(3) Set the set value of measurement in units of 100ms.

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4100 The device that cannot be specified has been specified. –– –– –– ––

Program Example
(1) Program where the ON time of X0 is set to 5s, the current value storage device to D0, and the device that will turn ON at
time-out to Y10.
[Ladder Mode] [List Mode]

Step Instruction Device

623
 ZRRDB, ZRRDBP
7.18.4 ZRRDB, ZRRDBP Direct 1-byte read from file register

7.18.4 ZRRDB, ZRRDBP Basic High

performance Process Redundant Universal LCPU

Command
ZRRDB ZRRDB n D

Command
ZRRDBP ZRRDBP n D

n : Serial byte number for the file register to be read (BIN 32 bits)
D : Number of the device where the read data will be stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n ––

D –– ––

Function
(1) Reads the serial byte number designated by n that does not signify a block number, and stores at the lower 8 bits of the
device designated by D .
The upper 8 bits designated by D will become 00H.

File register
ZR0 Area for
block No. 0
ZR32767
ZR32768 Area for
block No. 1 b15 b8B7 B0
n Serial byte number D 00H
ZR65535 Read-out contents
ZR65536 Area for
block No. 2

(2) The correspondence between file register numbers and serial byte numbers is as indicated below:
b15 b8b7 b0
ZR0 Serial byte No. 1 Serial byte No. 0
ZR1 Serial byte No. 3 Serial byte No. 2
ZR2 Serial byte No. 5 Serial byte No. 4

ZR2500 Serial byte No. 5001 Serial byte No. 5000

ZR2501 Serial byte No. 5003 Serial byte No. 5002
ZR2502 Serial byte No. 5005 Serial byte No. 5004
ZR2503 Serial byte No. 5007 Serial byte No. 5006

Data when an even

number is designated
Data when an odd
number is designated
(a) If the value of n has been designated as 23560, the data at the lower 8 bits of ZR11780 will be read.
Read destination
designation b15 b8 b7 b0 b15 b8 b7 b0
n 23560 ZR11780 43H 21H D 00H 21H
Data is stored

(b) If the value of n has been designated as 43257, the data at the upper 8 bits of ZR21628 will be read.
Read destination
designation b15 b8 b7 b0 b15 b8 b7 b0
n 43257 ZR21628 93H 42H D 00H 93H
Data is stored

624
 ZRWRB, ZRWRBP

Operation Error
1
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
The specified device number (serial byte number) exceeds the
4101 –– –– –– ––
available range.
3
Program Example
(1) The following program reads the lower 8 bits of ZR16000 and the upper 8 bits of ZR16003, and stores them at D100 and 4
D101 when X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

4

[Operation]
7
b15 b8 b7 b0 b15 b8 b7 b0
Serial byte No. 32000
ZR16000 8FH 25H D100 00H 25H
(Lower 8 bits of ZR16000)
ZR16001
ZR16002
42H 32H D101 00H 93H 8
12H 34H
Serial byte No. 32007
(Upper 8 bits of ZR16003) ZR16003 93H 00H

7.18.5 ZRWRB, ZRWRBP

7.18 Other instructions
7.18.5 ZRWRB, ZRWRBP File register direct 1-byte write

7.18.5 ZRWRB, ZRWRBP Basic High

performance Process Redundant Universal LCPU

Command
ZRWRB ZRWRB n S

Command
ZRWRBP ZRWRBP n S

n : Serial byte number for the file register to be written (BIN 32 bits)
S : Number of the device where the data to be written is stored (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n ––

S ––

625
 ZRWRB, ZRWRBP

Function
(1) Writes the lower 8 bits of data stored in the device designated by S that does not signify a block number to the file
register of the serial byte number designated by n.
The upper 8 bits of data in the device designated by are ignored S .
File register
ZR0 Area for
ZR32767 block No. 0
ZR32768 Area for
Write destination block No. 1
designation Writing the data b15 b8b7 b0
n Serial byte number S Ignored
ZR65535
Contents to
ZR65536 Area for be written
block No. 2

(2) The correspondence between file register numbers and serial byte numbers is as indicated below:
b15 b8b7 b0
ZR0 Serial byte No. 1 Serial byte No. 0
ZR1 Serial byte No. 3 Serial byte No. 2
ZR2 Serial byte No. 5 Serial byte No. 4

ZR2500 Serial byte No. 5001 Serial byte No. 5000

ZR2501 Serial byte No. 5003 Serial byte No. 5002
ZR2502 Serial byte No. 5005 Serial byte No. 5004
ZR2503 Serial byte No. 5007 Serial byte No. 5006

Storage destination
when an even number is designated
Storage destination
when an odd number is designated
If n 12340 is specified, the data will be written to the lower 8 bits of ZR6170.
Write destination
designation b15 b8 b7 b0 b15 b8 b7 b0
n 12340 ZR6170 43H 21H S Ignored 54H

b15 b8 b7 b0
43H 54H

If n 43257 is specified, the data will be written to the upper 8 bits of ZR21628.
Write destination
designation b15 b8 b7 b0 b15 b8 b7 b0
n 43257 ZR21628 12H 50H S Ignored 43H

b15 b8 b7 b0
43H 50H

Operation Error
(1) In the following case, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The specified device number (serial byte number) exceeds the
4101 –– –– –– ––
available range.

626
 ADRSET, ADRSETP

Program Example
1
(1) The following program writes the data at the lower bits of D100 and D101 to the lower 8 bits of ZR16000 and the upper 8
bits of ZR16003 when X0 is turned ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

[Operation]
4
b15 b8 b7 b0 b15 b8 b7 b0
Serial byte No. 32000
ZR16000 54H 59H D100 Ignored 10H
(Lower 8 bits of ZR16000)
ZR16001 4AH BAH 4
ZR16002 ABH 80H b15 b8 b7 b0
Serial byte No. 32007 01H
ZR16003 99H 77H D101 Ignored
(Upper 8 bits of ZR16003)
6

b15 b8 b7 b0 7
ZR16000 54H 10H
ZR16001 4AH BAH
ZR16002 ABH 80H
ZR16003 01H 77H 8

7.18.6 ADRSET, ADRSETP Indirect address read operations

7.18.6

7.18.6 ADRSET, ADRSETP

7.18 Other instructions
ADRSET, ADRSETP Basic High
performance Process Redundant Universal LCPU

Command
ADRSET ADRSET S D

Command
ADRSETP ADRSETP S D

S : Number of the device whose indirect address is read out (Device name)
D : Head number of the device where the indirect address of the device designated by S will be stored (BIN 32 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
S ––

D ––

627
 KEY

Function
(1) Stores the indirect address of the device designated by S at D and D +1.
The address stored at the device designated by D is used when an indirect device address is performed by the
sequence program.

ADRSET W100 D100 Stores the address of W100 address to D100 and D101.

MOV K1234 @D100

Writes 1234 to the address
specified by D100 and D101.
Reads the contents of D100.

Device area
D0
D1

D100 Address of
D101 W100 W100 1234

(2) A bit device designation cannot be made at S .

Operation Error
(1) There is no operation error in the ADRSET(P) instruction.

Remark
See Page 107, Section 3.4 for further information on indirect designations.

7.18.7 KEY Numerical key input using keyboard

7.18.7 KEY Basic High

performance Process Redundant Universal LCPU

Command
KEY KEY S n D1 D2

S : Head number of the devices (X) to which a numeral will be input (bits)
n : Number of digits of the numeral to be input (BIN 16 bits)
D1 : Head number of the devices where the input numeral will be stored (BIN 16 bits)
D2 : Number of the bit device to turn ON at the completion of input (bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S (Only X) –– –– –– ––
n ––
D1 –– –– –– ––
D2 –– ––

628
 KEY

Function
1
(1) Fetches ASCII data from the 8 points of input (X) designated by S , converts it to hexadecimal values and stores the
result in the area starting from the device designated by D1 .

Designation of 2
n the number of Input module
digits to be input
S
S
S
+1
+2
+3
3
b15 b12 b11 b8b7 b4 b3 b0
S "0" (30H) to "9" (39H)
S +4
S +5 "A" (41H) to "F" (46H)
D1 Number of digits that are input
S +6
D1 +1
4
5 digits 6 digits 7 digits 8 digits S +7
D1 +2 1 digit 2 digits 3 digits 4 digits S +8 Strobe signal

For example, in a case where the number of digits (n) of input data has been set at 5, and the values "31H", "33H", "35H",
"37H" and "39H" have been input through X10 to X18 of the input module, the following will take place: 4
Number of digits
5 Input module
of input data (n)
The first input value
X10
X11
X12
6
b15 b12 b11 b8 b7 b4 b3 b0
X13 " 1 3 5 7 9 "
X14 (31H)(33H)(35H)(37H)(39H)
D1 5 X15
D1 +1 3H 5H 7H 9H
X16
X17
X18
7
D1 +2 0H 0H 0H 1H Strobe signal

(2) Numerical input to input (X) designated by undergoes bit development at through +7 and is input as the ASCII
8
S S S

code corresponding to the numbers.

ASCII code which can be input is from 30H (0) to 39H (9), and from 41H (A) to 46H (F).

(3 H) (1 H)
Input module
b7 b4 b3 b0
"1"(31 H)= 0 0 1 1 0 0 0 1

7.18.7 KEY
7.18 Other instructions
S
S +1
S +2
S +3
S +4
S +5
S +6
S +7

(3) After ASCII code is input to S to S +7, the strobe signal at S +8 goes ON to incorporate the designated numbers
internally.
The strobe signal should be held at its ON or OFF status for more than one scan of the sequence program.
If this time is less than 1 scan, there will be cases when the data is correctly incorporated.

Execution command
Condition contact for ON for 1 scan OFF for 1 scan
the execution of KEY or longer or longer
instruction

Strobe signal ( S +8)

ASCII code input
31H 32H 33H 34H
( S to S +7)

Fetches "1" Fetches "2" Fetches "3" Fetches "4"

(4) Be sure to keep the execution command (condition contact for the KEY instruction) ON until the specified number of
digits has been input.
The KEY instruction cannot be executed if the execution command turns OFF.

629
 KEY

(5) The digits for the numbers actually fetched to D1 will be stored at the device designated by D1 , and these will be
converted to the ASCII codes input at D1 +1 and D1 +2, converted to hexadecimal BIN values, and stored.

Execution command
Condition contact for the
execution of KEY instruction
Strobe signal ( S 8)

ASCII code input

31H 33H 35H 37H 39H
( S to S 7)

D1 1 2 3 4 5
D1 1 0 0 0 1 0 0 1 3 0 1 3 5 1 3 5 7 3 5 7 9
D1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

(6) The number of digits that can be designated by n is from 1 to 8.

(7) Fetching of the input data is completed when any of the inputs shown below has been made. At the completion, the bit
device designated by D2 is turned ON.
• When the number of digits specified by n has been input
• When the "0DH" code has been input
For example, the operations at the location designated if n 5 will be as indicated below:

Execution command

Strobe signal
( S +8)
ASCII code input
When the 31H 42H 35H 37H 39H
designated ( S to S +7)
number of digits
are input
D1 1 2 3 4 5
D1 +1 0 0 0 1 0 0 1 B 0 1 B 5 1 B 5 7 B 5 7 9
D1 +2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Processing
completed ( D2 )

Execution command

Strobe signal
( S +8)
When 0DH code ASCII code input
31H 42H 35H 0DH
is input ( S to S +7)

D1 1 2 3 3
D1 +1 0 0 0 1 0 0 1 B 0 1 B 5 0 1 B 5
D1 +2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Processing
completed ( D2 )

If input processing is to be performed a second time, it is necessary to clear the number of digits input and the input data
stored at D1 , and turn OFF the designated device at the user program.
If D1 is not cleared and D2 not turned OFF, the next input processing cannot be performed.

630
 KEY

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The device specified in S is not an input (X) device.
4100
The number of digits specified in n is outside the range from 1 to 8.
–– –– –– ––
3

Program Example 4
(1) The following program fetches data of the 5 or fewer digits from the numerical keypad connected to X20 to X28, and
stores it to the area from D0 to D2 when X0 is turned ON.
[Ladder Mode] 4

Clears the previous input data 6

Sets the number of digits to be input

Resets the data input completion fag

8

[List Mode]

7.18.7 KEY
7.18 Other instructions
Step Instruction Device

[Operation]

Input module

X20
" 1 2 3 4 5" X21
X22 b15 b12b11 b8 b7 b4 b3 b0
X23 D0 5
X24 D1 2H 3H 4H 5H
X25 D2 0H 0H 0H 1H
X26
Numerical keypad X27
(Strobe signal) X28

631
 ZPUSH, ZPUSHP, ZPOP, ZPOPP

7.18.8 ZPUSH, ZPUSHP Batch save of index register

7.18.8
ZPOP, ZPOPP Batch recovery of index register

ZPUSH, ZPUSHP, ZPOP, ZPOPP Basic High

performance Process Redundant Universal LCPU

indicates an instruction symbol of ZPUSH/ZPOP.

Command
ZPUSH, ZPOP D

Command
ZPUSHP, ZPOPP P D

D : Head number of the devices to/from which contents of an index register are saved/recovered (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
D –– ––

Function
ZPUSH
(1) Saves the contents of the following index registers to after the device specified by D .
(When contents of an index register are saved, D + 0 (the number of saves made) is increased by 1.)
• Basic model QCPU: Z0 to Z9
• High Performance model QCPU/Process CPU/Redundant CPU: Z0 to Z15
• Universal model QCPU/LCPU: Z0 to Z19
(2) The ZPOP instruction is used for data recovery. Nesting is possible within the ZPUSH to ZPOP cycle.

(3) If nesting has been done, each time the ZPUSH instruction is executed, the field used following D will be added to, so a
field large enough to accommodate the number of times the instruction will be used should be maintained from the
beginning.

(4) The composition of the field used following D is as shown below:

• When Basic model QCPU is used
D +0 Number of saves
+1 Z0
+2 Z1
1st nesting
(15 words for the 1st nesting)
+10 Z9
+11 Reserved by the
+15 system (5 words)
+16 Z0
+17 Z1
2nd nesting

• When using a High Performance model QCPU/Process CPU/Redundant CPU

D +0 Number of saves
+1 Z0
+2 Z1
1st nesting
(18 words for the 1st nesting)
+16 Z15
+17 Reserved by the
+18 system (2 words)
+19 Z0
+20 Z1
2nd nesting

632
 ZPUSH, ZPUSHP, ZPOP, ZPOPP

• When using Universal model QCPU/LCPU

D +0 Number of saves
+1 Z0 1
+2 Z1
1st nesting

+20 Z19
(20 words for the 1st nesting)
2
+21 Z0
+22 Z1 2nd nesting
3

ZPOP
4
(1) Recovers the contents saved in the area starting from the device designated by D to the index register. (When the
saved content is read out to the index register, D + 0 (the number of saves made) is decreased by 1.)

4
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
6
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 7
The operation result of D +0 (the number of saves made) is 0 in the
4100 ––
ZPOP(P) instruction.

4101
For the ZPUSH(P) instruction, the range of the device specified by D ,
––
8
exceeds the range of the corresponding device.

Program Example

7.18.8 ZPUSH, ZPUSHP, ZPOP, ZPOPP

7.18 Other instructions
(1) The following program saves the contents of the index register to the fields following D0 before calling the subroutine
following P0 that uses the index register.
[Ladder Mode] [List Mode]

Step Instruction Device

633
 UNIRD, UNIRDP
7.18.9 UNIRD, UNIRDP Reading module information

7.18.9 UNIRD, UNIRDP Basic High

performance Process Redundant Universal LCPU

Command
UNIRD UNIRD n1 D n2

Command
UNIRDP UNIRDP n1 D n2

n1 : Value (0 to FFn) which the start I/O number of the module information read source is divided by 16 (BIN 16 bits)
D : Head number of the devices where the module information will be stored (device name)
n2 : The number of points of read data (0 to 256) (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n1 –– ––

D –– –– –– ––

n2 –– ––

Function
(1) Reads the module information as much as designated by n2 from the module designated by n1, and stores that
information into the area starting from the device designated by D.

(Reads the status of the actually installed modules even if the module type and the number of points are changed by I/O
assignment.)

Remark
The value of n1 is specified by the first 3 digits of the hexadecimal 4 digits that represent the head I/O number of the
module from which the module information is read.
QCPU

Power
Q68 QY41
supply CPU QX10 QX10 QX10 QX10 QY10 QY10
ADV P
module

0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Head I/O number configured in
the I/O assignment setting

Specify K4 or H4 as the head I/O number to be read.

LCPU
CPU module
(L26CPU-BT)

Power
Built-in Built-in LX40 LX40 LX40 L60 LY41 LY10 LY10 LY10
supply CPU
I/0 CC-Link C6 C6 C6 AD4 NT1P R2 R2 R2
module

0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Head I/O number configured in th
I/O assignment setting

Specify K6 or H6 as the head I/O number to be read.

634
 UNIRD, UNIRDP

The details of the module information are described as follows:

Bit b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Individual module 1
information
Meaning
Bit Item

000: 16 points
QCPU
001: 32 points
LCPU
2
b0
010: 48 points 011: 64 points
b1 Number of I/O points
100: 128 points 101: 256 points
b2 110: 512 points 111: 1024 points 3
b3 000: Input module 000: Input module
001: Output module 001: Output module
b4 Module type
b5
010: I/O mixed module
011: Intelligent function module
011: Intelligent function module
111: CPU Built-in I/O
4
External supply power status 1: External supply power is connected.
b6 Fixed to 0
(For future expansion) 0: External supply power is not connected.

b7 Presence/absence of fuse blown

1: Some modules have fuse blown.
Fixed to 0
4
0: Normal
1: Module information on the extension
Online module replacement base unit is tried to be read during online
module change or from the CPU module
6
status/
b8 Fixed to 0
execution from the standby of standby system in the redundant
system system.*1
0: Other than above 7
b9 Minor/medium error status 1: Minor/medium error occurred 0: Normal
b10 00: No module error 01: Minor error
Module error status
b11 10: Medium error 11: Serious error 8
b12 Module ready status 1: Normal 0: Module error occurred
b13 Empty Fixed to 0
1: A series module
b14 Module type Fixed to 0
0: Q series module
b15 Module installation status 1: Modules are installed. 0: No modules are installed.

7.18.9 UNIRD, UNIRDP

7.18 Other instructions
*1: The Universal model QCPU used in the multiple CPU system is turned ON during the online module change of the module
controlled by the other CPU.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
n1 is a value other than 0 to FFH.
n2 is a value other than 0 to 256. –– *1

The total of n1 and n2 is equal to or greater than 257.

n1 is a value other than 0 to 3FH.
Q00/ *2
4100 n2 is a value other than 0 to 64. –– –– –– ––
Q01
The total of n1 and n2 is equal to or greater than 65.
n1 is a value other than 0 to FH.
n2 is a value other than 0 to 16. Q00J –– –– –– –– ––
The total of n1 and n2 is equal to or greater than 17.
The range of the device specified by D exceeds the range from D to D
4101
+ n2 (including D ).
*1: For only L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT, and L26CPU-PBT
*2: For only L02SCPU, L02SCPU-P, L02CPU, and L02CPU-P

635
 UNIRD, UNIRDP

Program Example
(1) The following program stores the module information at I/O numbers 10H and 20H into the devices starting from D0 when
X0 is turned ON.
Module information Device
X/Y0 module information D0
X/Y10 module information D1
X/Y20 module information

X/YFE0 module information

X/YFF0 module information

[Ladder Mode] [List Mode]

Step Instruction Device

Readout result (When read to D0)

(a) 32-point intelligent function module for Q series
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1

32-point module
Intelligent function module
No external power supply connected
No blown-fuse error existing
Execution other than during online module
change or from the standby system
No module error existing

Module ready status

(Empty)
Q series module
Module installed

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

All of these bits turn 0 because information is stored to "D0".

A module is installed as latter 16 points of a 32-point module.

• With a 48- or 64-point module, the same contents as those of D1 are stored in D2 or D2 and D3 respectively.

636
 UNIRD, UNIRDP

(b) 32-point module for A series

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
For an A series module, all of these bits turn 0 because information is not stored.

A series module
2
Module is installed

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

3
D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

All of these bits turn 0 because information is stored to "D0". 4

A module is installed as latter 16 points of a 32-point module.

• With a 48- or 64-point module, the same contents as those of D1 are stored in D2 or D2 and D3 respectively.
4
(c) Empty slot
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6
For an empty slot, all of these bits turn 0.

(d) Performing online module replacement 7

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Performing online module replacement

8
(e) Module information on the extension base unit is tried to be read from the standby system of the redundant system
in separate mode.
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

7.18.9 UNIRD, UNIRDP

7.18 Other instructions
D0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Execution from the standby system

(Module information on the extension base unit is tried
to be read from the standby system of the redundant
system in separate mode.)

637
 TYPERD, TYPERDP

(f) L series 32-point intelligent function module

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0
D0 1 0 0 1 0 0 0 0 0 0 0 1 1 0 0 1

32-point module
Intelligent function module
(Empty)
(Empty)
(Empty)
No module errors
Module preparation complete
(Empty)
Module connected

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

D1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

All 0, because information is stored in "D0".

The module is mounted as the second 16 points of a 32-point module

7.18.10 TYPERD,TYPERDP Reading module model name

Ver.
High
Basic performance Process Redundant Universal LCPU

7.18.10 TYPERD, TYPERDP • Universal model QCPU: The serial number (first five digits) is
"11043" or later.

Command
TYPERD TYPERD n D

Command
TYPERDP TYPERDP n D

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n –– –– ––

D –– –– –– ––

Set Data
Setting data Description Setting range Set by Data type
0 to FFH,
3E0 to 3E3H
Value obtained by dividing the start I/O number of a module (Universal model
n User BIN 16 bits
whose model name is to be read by 16 QCPU)
0 to FFH, 3E0H
(LCPU)
D +0 Execution result of the instruction Within each BIN 16 bits
D System
D +1 to D +9 Module model name device range Character string

638
 TYPERD, TYPERDP

Function
1
(1) This instruction reads the module information stored in the area starting from the I/O number specified by "n", and stores
it in the area starting from the device specified by D .
The following 6 modules (Q series only) support the instruction. 2
• CPU module
• Input module
• Output module
3
• I/O combined module
• Intelligent function module
• GOT (bus connection)
4
For the LCPU, the following four models are supported.
• CPU module
• Input module
4
• Output module
• Intelligent function module
(2) The value of n is specified by the first 3 digits of the hexadecimal 4 digits that represent the start I/O number of a module 6
whose model name is to be read.
• When the target module occupies one slot
Universal model QCPU
7
Power
CPU Q68 QY41
supply
module
module
QX10 QX10 QX10 QX10
ADV P
QY10 QY10
8
3E00H 0000H 0010H 0020H 0030H 0040H 0050H 0070H 0080H Start I/O number configured in
the I/O assignment setting

Specify K3 or H3 as the start I/O number to be read.

7.18.10 TYPERD, TYPERDP

7.18 Other instructions
Specify H3E0 as the start I/O number of the CPU slot.

LCPU
CPU module
(L26CPU-BT)

Power
Built-in Built-in LX40 LX40 LX40 L60A LY41 LY10 LY10 LY10
supply CPU
I/0 CC-Link C6 C6 C6 D4 NT1P R2 R2 R2
module

0000H 0010H 0030H 0040H 0050H 0060H 0070H 0090H 00A0H 00B0H Start I/O number configured in
the I/O assignment setting

Specify K6 or H6 as the start I/O number to be read.

Specify H3E0 to read the module name of the CPU module.

1. On the LCPU, if the built-in I/O or first I/O on the built-in CC-Link is specified, then the model name of the CPU module is
read.

639
 TYPERD, TYPERDP

• When the target module occupies two slots

The start I/O number to be specified may differ from that of the target module.
For the start I/O number, refer to the manual of each module.

Example QJ71GP21S-SX
• Specify a value that is the sum of the start I/O number of the mounted module and 0010H.

Power
supply CPU QJ71G P21S-SX Empty Empty Empty Empty Empty Empty
module module

3E00H 0000H 0010H 0030H 0040H 0050H 0060H 0070H 0080H Start I/O number configured in
the I/O assignment setting

Specify K1 or H1 as the start I/O number to be read.

• When the target module is a CPU module in multiple CPU systems

Specify the value obtained by dividing the start I/O number of the target CPU module by 16.

Power
CPU Q20UDH Q20UDH Q20UDH QY41 Q68 QY41
supply QY10 QY10
module CPU CPU CPU P ADV P
module

3E00H 3E10H 3E20H 3E30H 0000H 0020H 0030H 0050H 0060H Start I/O number configured in
the I/O assignment setting

Specify 3E3H as the start I/O number to be read.

Or, the model name can be read by specifying the start I/O number of a module controlled by another CPU.

(3) D +0 and D +1 to D +9 store the execution result of the instruction and module model name, respectively.
A value stored in D is as follows:
(a) When the model name has been written to the target module (example: QJ71GP21-SX)
b15 to b8 b7 to b0

D +0 0 Stores 0.
D +1 4AH (J) 51H (Q) Indicates that the model name
that has been written to
Nine words are used. D +2 31H (1) 37H (7) the target module is stored.

D +3 50H (P) 47H (G) Stores the model name that has been
written to the target module
D +4 31H (1) 32H (2) (stored in ASC II).
D +5 53H (S) 2DH (-)
D +6 00H 58H (X)

D +7 00H 00H
D +8 00H 00H Stores the remaining model name and
00H to the 12th to 17th devices and
D +9 00H 00H the 18th device, respectively.

The following table shows the examples of model names stored in D +1 to D +9.
Target module Stored model name
CPU module Q06UDEHCPU
Intelligent function module QJ71GP21-SX
GOT GOT1000

640
 TYPERD, TYPERDP

(b) When the model name has not been written to the target module (example: QX40)
b15 to b8 b7 to b0

D +0 1 Stores 1. 1
D +1 4EH (N) 49H (I) Indicates that the character
string consists of module type and
Nine words are used. D +2 55H (U) 50H (P) the number of points is stored.

D +3 5FH (_) 54H (T) Stores the character string consists

of module type and the number of points.
2
D +4 36H (6) 31H (1) (stored in ASC II).
D +5 00H 00H
D +6 00H 00H 3
D +7 00H 00H
D +8 00H 00H Stores the remaining model name and

4
00H to the 12th to 17th devices and
D +9 00H 00H the 18th device, respectively.

The following table shows the examples of character strings stored in D +1 to D +9.
Target module Stored character string 4
Input module (16 points) INPUT_16
Output module (32 points) OUTPUT_32
I/O combined module (64 points)
Intelligent function module (16 points)
MIXED_64
INTELLIGENT_16
6

[Character string indicating module type]

7
• Input module: INPUT
• Output module: OUTPUT
• I/O combined module: MIXED
8
• Intelligent function module*1: INTELLIGENT
• 1: Includes the QI60 and GOT.
[Character string indicating the number of points]
• 16 points:_16

7.18.10 TYPERD, TYPERDP

7.18 Other instructions
• 32 points:_32
• 48 points:_48
• 64 points:_64
• 128 points:_128
• 256 points:_256
• 512 points:_512
• 1024 points:_1024
(c) Others
• The specified slot is empty or the target module is during online module change.
• The specified value (n) is not the start I/O number.
• The specified value (n) is within the allowable setting range, but cannot be set in the I/O assignment setting
screen of the PLC parameter dialog box.
b15 to b8 b7 to b0

D +0 -1 Stores -1.
D +1 Indicates that the model
00H 00H
name is not stored.
Nine words are used. D +2 00H 00H
D +3 00H 00H

D +4 00H 00H
D +5 00H 00H
D +6 00H 00H
D +7 00H 00H
D +8 00H 00H Stores 00H.

D +9 00H 00H

641
 TYPERD, TYPERDP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2110 The target module cannot be communicated due to a failure. –– –– –– ––
The range of the device specified by D exceeds that of the device that
–– –– –– ––
can be used.
4101 The value specified in n is not within the range from 0 to FFH or 3E0H to
–– –– –– –– ––
3E3H.
The value specified in n is not within the range from 0 to FFH or 3E0H. –– –– –– –– ––

Program Example
(1) The following program stores the model name of a module having the start I/O number 0020H in the area starting from
D0 when X0 is turned on.
[Ladder Mode] [List Mode]

Step Instruction Device

642
 TRACE, TRACER

7.18.11 TRACE Trace set

TRACER Trace reset

Ver.

7.18.11 TRACE, TRACER Basic High

performance Process Redundant Universal LCPU 1
• Universal model QCPU: Models other than Q00UJCPU

TRACE
Command
TRACE 2
Command
TRACER TRACER
3
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word
–– –– 4
Function
4
The sampling trace is the function that collects the device data of a CPU module consecutively.
To execute the sampling trace, turn ON SM801 when SM800 is ON.

TRACE
Trace ends by
number of trace TRACER
6
Trace start request Trigger condition enabled after trigger Trace reset

Number of trace
after trigger
7
Total number of traces

8
SM800
(Preparation for trace)

SM801
(Starting trace)

7.18.11 TRACE, TRACER

7.18 Other instructions
SM802
(During the execution of trace)

SM803
(Trigger for trace)

SM804
(After the execution of trace
trigger)

SM805
(Completion of trace)

TRACE
(1) The TRACE instruction is an instruction which performs the following: turn ON SM803, perform the sampling for the
number of the sampling trace after executing the TRACE instruction, latch the sampling traces result, and stop the
sampling trace.
(2) The sampling is stopped if SM801 is turned OFF during the trace execution.
(3) After the TRACE instruction is executed and the sampling trace is stopped, SM805 is turned ON.
(4) Once the TRACE instruction is executed, the second and the subsequent TRACE instructions are ignored.
When the TRACER instruction is executed, the TRACE instruction is enabled again.

643
 SP.FWRITE

TRACER
(1) The TRACER instruction resets the TRACE instruction. When the TRACER instruction is executed, the TRACE
instruction is enabled again.
(2) When the TRACER instruction is executed, SM803 to SM805 are turned OFF.

Remark
1. The target devices for the sampling trace and its timing can be set with a programming tool.
For details of the sampling trace, refer to the user's manual (Function Explanation, Program Fundamentals) for the CPU
module used.
2. For the execution of sampling traces by the programming tool, refer to the operating manual for the programming tool
used.

Operation Error
(1) There is no operation error in the TRACE or TRACER instruction.

Program Example
(1) The following program executes the TRACE instruction when X0 is turned ON, and resets the TRACE instruction with
the TRACER instruction when X1 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

7.18.12 SP.FWRITE Writing data to designated file

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU
• Universal model QCPU: Models other than Q00UJCPU,
Q00UCPU, and Q01UCPU

7.18.12 SP.FWRITE • Built-in Ethernet port LCPU: Supported

• L02SCPU and L02SCPU-P cannot be used.

Command
SP.FWRITE SP.FWRITE U0 S0 D0 S1 S2 D1

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $
S0 –– –– ––
D0 –– *1 –– –– –– ––
S1 –– –– –– –– ––
S2 –– *2 –– –– ––
D1 *1 *1 –– –– –– ––
*1: Local devices and the devices designated for individual programs cannot be used.
*2: For the Universal model QCPU and LCPU, the file registers that have been specified separately for each local device and
program cannot be used only if the number of requested write data exceeds 1024.

644
 SP.FWRITE

Operation Error
1
Setting Setting
Meaning Set by Data Type
Data Range
U0 Dummy –– –– 2
S0 Drive designation 2 User
Head number of the devices storing the control data. The following control data is required.
Device Item Contents/Setting Data Setting Range Set by 3
Execution/ Designate the execution type.
0000H
D0 completion 0000H : Write binary data User
0100H
type 0100H : Write data after CSV format conversion

D0 +1 (Not used) Used by system –– System

4
Writing result Contains the number of actually written data against the data
D0 +2 (No. of written
data)
designated by S2 . The unit of the value depends on data type –– System
4
specified at D0 +7.

D0 +3 (Not used) –– –– ––

Set the file position when binary data writing is specified by D0 . 6

00000000H :Starting at the beginning of the file
00000001H to FFFFFFFEH: From the specified position
D0 (The unit of the value depends on data
type specification.)
7
FFFFFFFFH : Addition starts from the end of the file.
When write data after CSV format conversion is specified at
D0
8
D0 +4 File 00000000H to
• For the High Performance model QCPU of which the first 5 User
D0 +5 position digits of the serial number are "01111" or lower, always set FFFFFFFFH
the beginning (0H) of the file. BIN 16 bits

• For the High Performance model QCPU/Process CPU/

7.18.12 SP.FWRITE
7.18 Other instructions
Redundant CPU/Universal model QCPU of which the first 5
digits of the serial number are "01112" or higher, set the file
position.
00000000H to FFFFFFFEH
: Starting at the beginning of the file
FFFFFFFFH : Adding at the end of the file

When binary write is specified at D0 , always set 0.

When write data after CSV format conversion is specified at 0H to
No. of columns
D0 +6 D0 , set the number of columns where data will be written. FFFFH User
designation
D0
0 : No columns. Regarded as one row. (0 to 65535)
Other than 0 : Set to the specified number of columns.
Data type 0: Word
D0 +7 0,1 User
specification 1: Byte
Head number of the devices storing a file name. A file name is expressed as follows:
Device Item Contents/Setting Data Setting Range Set by
Designate the character string of a file name.
• When omitting an extension, also omit the "." (Period).
S1 File name • Limit the file name within 8 characters + period + 3
S1 to Character
character characters. User
S1 + string
string • When 9 or more characters are used, the extension is
ignored regardless of its presence, and "BIN" or "CSV" is
automatically assigned as an extension.

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 SP.FWRITE

Setting Setting
Meaning Set by Data Type
Data Range
Head number of the devices storing the data. Written data is expressed as follows:
Device Item Contents/Setting Data Setting Range Set by
Designate the number of data to request writing (word units).
No. of request 1 to 480
S2 This data should be designated in units of words even when
S2 write data 1 to 32767 *2 BIN 16 bits
byte is designated by D0 +7.
User
S2 +1
0000H to
to Write data Data to request writing.
FFFFH
S2 +

Bit device that turned ON at the completion of the processing.

( D1 +1 is also turned ON at error completion.)
Device Item Contents/Setting Data Setting Range Set by
Completion Indicates the completion of the processing. Bit
D1 D1 ––
signal ON: Completed OFF: Not completed
Error Indicates whether the processing is normally completed or System
D1 +1 completion abnormally completed. ––
signal ON: Error completion OFF: Normal completion
*2: Indicates the range applicable only for the Universal model QCPU and LCPU.

Caution
(1) For only QCPU, only the ATA card drive (2) can be set as S0 (drive designation).
Note that when the Flash card is loaded, the SP.FWRITE instruction cannot be used to perform writing.
The SRAM card, standard RAM or standard ROM drive cannot be set.
For only LCPU, only the SD memory card drive (2) can be set as S0 (drive designation).
(2) For CSV setting, the data written are decimal values.
Example Character "A" (41H) "65" is written.
Handling range: -32768 to 32767
(3) For binary write, the word-specified file position setting range is 00000000H to 7FFFFFFFH and FFFFFFFFH.
(4) For the LCPU, this instruction cannot be executed while SM606 (SD memory card forced disable instruction) is ON. Even
if the instruction is attempted to be executed, the command will be ignored.

Function
(1) The designated number of data is written to the designated file.
Set the execution/completion type in the control data to designate whether to write binary data without any conversion or
to convert binary data into CSV format data before writing it.
(For QCPU, writing is only supported for ATA cards. For LCPU, it is only supported for SD memory cards.)

(2) The execution completion bit device ( D1 ) is automatically turned ON at the END processing after the completion of the
instruction is detected. The bit device is turned OFF at the execution of the END instruction in the next scan.
Use this bit device as the execution completion flag for the SP.FWRITE instruction.
When this instruction is completed abnormally, the error completion device ( D1 +1) is turned ON/OFF in synchronization
with the processing complete ( D1 ) device. Use this device as the error completion flag for this instruction.
SM721 is turned ON during the execution of the instruction.
This instruction cannot be executed while SM721 is ON. (If an attempt is made, no processing is performed.)
When an error is detected at the execution of the instruction (before SM721 is turned ON), the processing complete
device ( D1 ), the error completion device ( D1 +1), and SM721 are not turned ON.

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 SP.FWRITE

(3) Be sure to use in units of words to designate the No. of request write data ( S2 ) and the file position ( D0 +4 and D0 +5).

The following shows the method for writing binary data when No. of request write data and file position are specified.

Control data
1
D0 +0 H0000 Execution/completion type

2
D0 +1 - (Not used)
D0 +2 K3 Writing result (No. of written data)
D0 +3 - (Not used)
D0 +4 K1
D0 +5 Head position of the file to be written 3
D0 +6 K0 No. of columns designation
D0 +7 K0 Data type specification
4
Data device File data (in byte unites)
S2 +0 K3 H00
One word
H00 shift 4
S2 +1 H33 22 H22
Total H33

Data to
S2 +2 H55 44 H44 6
H55
be written
S2 +3 H77 66 H66
H77
H00
7
H00

8
H00

(4) When writing binary data

(a) If the extension of the target file is omitted, ".BIN" is used as an extension.
(b) When the designated file does not exist, a new file is created and the data is saved from the beginning of the file.

7.18.12 SP.FWRITE
7.18 Other instructions
The attributes of this new file are set using the archive attributes.
(c) When the designated file exists, the data is saved from the beginning of the file.
When the size of the data exceeds that of the existing area in the file during the writing, the excess data is added/
saved.
(d) If the file position specified is greater than the existing file size:
• The High Performance model QCPU of which the first 5 digits of the serial number are "01111" or lower results in
an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU of which the
first 5 digits of the serial number are "01112" or higher performs writing at point 0 and is completed normally.
(e) An error occurs when the saving space becomes full while data is added and saved.
In such a case, the data that is successfully added/saved remains in the medium.
The error completion is indicated after as much data as possible is added/saved.
(5) When writing data after CSV format conversion
(a) If the extension is omitted, ".CSV" is used as an extension.
(b) When the existing file is specified:
[High Performance model QCPU of which the first 5 digits of the serial number are "01111" or lower]
File contents are all deleted and data are saved, starting at the beginning.
[High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU of which the first 5
digits of the serial number are "01112" or higher]
• When other than FFFFFFFFH is set at ( D0 +4, D0 +5), file contents are all deleted and data are saved, starting at
the beginning.
• When FFFFFFFFH is set at ( D0 +4, D0 +5), data are saved, starting at the end of the file.

647
 SP.FWRITE

(c) When the designated file does not exist, a new file is created and the data is saved from the beginning of the file.
The attributes of this new file are set using the archive attributes.
(d) An error occurs when the saving space becomes full while data is added and saved.
In such a case, the data that is successfully added/saved remains in the medium.
The error completion is indicated after as much data as possible is added/saved.
(e) When the designated number of columns is "0", the data is stored as single-row data in CSV format file.

Example

When data is written after CSV format conversion and the designated No. of columns is "0":

SP.FWRITE U0 K2 D10 D20 D99 M0 * Designation in word units

D10 H0100 Execution/completion type

D11 - Not used
Writing result (No. of written data) (In normal completion, it is the same number as the number of
D12 K0 data to be written.)
D13 - Not used
D14 K0
File position
D15 K0
D16 K0 No. of columns designation
D17 K0 Data type specification

D20 H4241 File name (If a file name consists of 8 or less characters, "00"s are stored in the remaining area.)
D21 H4443 "ABCDE"
D22 H0045

No. of request write data

D099 K7
Write data
D100 K0
D101 K10
D102 K20
D103 K30
D104 K40
D105 K-50
D106 K100

Data to be written to the file

0 , 10 , 20 , 30 , 40 , -50 , 100 CR LF

Data to be read out to EXCEL file

648
 SP.FWRITE

(f) When data is written after CSV format conversion and the designated number of columns is other than "0", the data
is stored as table data with designated number of columns in a CSV format file.
Example 1
When data is written after CSV format conversion and the designated No. of columns is other than "0":

SP.FWRITE U0 K2 D10 D20 D99 M0 2

* Designation in word units

D10 H0100
3
Execution/completion type
D11 - Not used
Writing result (No. of written data) (In normal completion, it is the same number as the number of
D12
D13
K0
-
data to be written.) 4
Not used
D14 K0
File position
D15
D16
K0
K3 No. of columns designation
4
D17 K0 Data type specification

D20 H4241 File name (If a file name consists of 8 or less characters, "00s" are stored in the remaining area.)
6
D21 H4443 "ABCD"

7
D22 H0000

No. of request write data

D099 K7
Write data
8
D100 K0
D101 K10
D102 K20
D103 K30
D104 K40

7.18.12 SP.FWRITE
7.18 Other instructions
D105 K-50
D106 K100

Data to be written to the file

0 , 10 , 20 CR LF
30 , 40 , -50 CR LF
100 CR LF

Data to be read to EXCEL file

649
 SP.FWRITE

(g) When data is added by the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/
LCPU of which the first 5 digits of the serial number are 01112 or higher:

[Specify the file to which data will be written.] (If a file exists, delete it and create a new file again.)

Execution type = CSV format File position = 0H (New file is created)

*3*5
No. of columns designation = 4H Write head device = D0
*3
Data type specification = Word No. of request write data = 6H

Device data
(Data to be written)
Column Column Column Column K6 D0 No. of request write data
1 2 3 4
K1 D1
Starting row Row 1 1 , 2 , 3 , 4 CR LF K2 D2
K3 D3
*3 K4 D4
Row 2 5 , 6 CR LF
K5 D5
K6 D6
K5 D7
K7 D8
K8 D9
K9 D10
K10 D11
K11 D12
K12 D13

[In the addition mode, make addition from the end of the file.]

Execution type = CSV format File position = FFFFFFFH (Addition mode)

*3*5
No. of columns designation = 3H Write head device = D7
*3
Data type specification = Word No. of request write data = 8H
Device data
(Data to be written)
K6 D0

Column Column Column Column K1 D1

1 2 3 4 K2 D2
Row 1 1 , 2 , 3 , 4 CR LF K3 D3
K4 D4
K5 D5
Row 2 5 , 6 CR LF K6 D6
K8 D7 No. of request write data
*4 *5 K7 D8
Present starting row Row 3 7 , 8 , 9 CR LF K8 D9
K9 D10
K10 D11
Row 4 10 , 11 , 12 CR LF K11 D12
K12 D13
*3 K13 D14
Row 5 13 , 14 CR LF K14 D15

*3: Unless the "No. of request write data" is set to an integral multiple of "No. of columns designation", the column numbers will be
random.
*4: Since the last data is always followed by the line feed code, addition normally starts at the beginning of the new row in the
addition mode.
*5: If, in the addition mode, "column designation" is changed from that in the previous writing, the column numbers are shifted.
(h) Do not execute the SP.FWRITE instruction in an interrupt program.
(If execute it, the operation is not guaranteed.)

650
 SP.FWRITE

(i) Below is the method for calculating the file size (total number of bytes) when a CSV format file is written to the ATA
card.
Total number of bytes = Total bytes excluding final line + bytes of final line 1
(Number of bytes on a line = number of columns*1 + 1 + total bytes of all data values on line*2)
*1: For all lines but the final line, this is the specified number of columns. The number of columns on the final line depends on the
number of columns specified via the amount of data written. It is calculated as follows.
(1) The number of lines excluding the final line is calculated.
2
Number of lines excluding final line = Amount of data in write request + number of columns (remainders discarded)
(2) The number of columns in the final line is calculated.

*2:
Number of columns in final line = Amount of data in write request - number of lines excluding final line number of columns)
The number of bytes for each data value is calculated as shown below.
3
Sign of Data
Bytes per Data Value Byte Count Range Examples
Value

Positive Num. digits

1 to 5 (word specified) 12345: 5 bytes 4
1 to 3 (byte specified) 67: 2 bytes
2 to 6 (word specified) -12345: 6 bytes
Negative Num. digits + 1
2 to 4 (byte specified) -67: 3 bytes
4
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
6
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU 7
code
Q01
4004 The device that cannot be specified has been specified. ––
Values specified in control data ( D0 ) and the subsequent devices are 8
out of the setting range.
No space is found when a new file is created. ––
A value that cannot be used has been set for the file name ( S1 ).
The attribute of the file name ( S1 ) is "read only".

7.18.12 SP.FWRITE
7.18 Other instructions
The drive specified by drive designation device ( S0 ) contains the
medium other than the ATA card.
–– ––
Space in the ATA card is insufficient.
4100 An access error occurred in the ATA card.
The drive specified by drive designation device ( S0 ) contains the
medium other than the SD Memory card.
–– –– –– ––
Space in the SD Memory card is insufficient.
An access error occurred in the SD Memory card.
If the instruction accesses a file which has been accessed by another
–– –– –– ––
function
If the instruction writes data into an SD memory card with the write
–– –– –– ––
protect switch enabled (write inhibited)
The value specified in "No. of request write data" ( S2 ) is out of the
setting range, or exceeds the device range specified in ( S2 +1) or the ––
4101 subsequent devices.
The range of the device specified in D0 or D1 exceeds that of the
–– –– –– ––
corresponding device.

651
 SP.FWRITE

Program Example
(1) When X10 is turned ON, the following program adds four bytes of binary data (00H, 01H, 02H, and 03H) to file
"ABCD.BIN" in the memory card inserted to drive 2.
• Assume that 8 points from D0 are reserved for the control data devices.
[Ladder Mode]

Sets the execution/completion type

Sets the designation of the number of columns

Sets the data type specified

Sets the file name
Sets the number of request write data

Sets the data to be written.

Normal completion display

Error completion display

[List Mode]

652
 SP.FWRITE

(2) When X10 is turned ON, the following program creates a file named "ABCD.CSV" in the memory card inserted to drive 2,
and writes four bytes of data (00H, 01H, 02H, and 03H) as two-column table data in CSV format.

• Assume that 8 points from D0 are reserved for the control data devices. 1
[Ladder Mode]

Sets the execution/completion type 2

Sets the designation of the number of columns

Sets the data type specified

Sets the file name 3
Sets the number of request write data

4
Sets the data to be written.

4
Normal completion display
6
Error completion display

[List Mode]
8
Step Instruction Device

7.18.12 SP.FWRITE
7.18 Other instructions

• The written file is displayed as follows:

0 , 0 , CR LF
1 , 0 , CR LF
2 , 0 , CR LF Contents of the file
3 , 0 , CR LF to be written

Data to be read to the EXCEL file

653
 SP.FREAD
7.18.13 SP.FREAD Reading data from designated file

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU
• Universal model QCPU: Models other than Q00UJCPU,
Q00UCPU, and Q01UCPU

7.18.13 SP.FREAD • Built-in Ethernet port LCPU: Supported

• L02SCPU and L02SCPU-P cannot be used.

Command
SP.FREAD SP.FREAD U0 S0 D0 S1 D1 D2

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H $
S0 –– –– ––
D0 –– –– –– –– ––
S1 –– –– –– ––
D1 –– *1 –– –– –– ––
D2
*1 *1 –– –– –– ––
*1: Local devices and the devices designated for individual programs cannot be used.

Setting Setting
Meaning Set by Data Type
Data Range
U0 Dummy –– ––
S0 Drive designation 2 User
Head number of the devices storing the control data
The following control data is required.
Device Item Contents/Setting Data Setting Range Set by
Execution/ Designate the execution type.
0000H
D0 completion 0000H: Read binary data User
0100H
type 0100H: Read data after CSV format conversion BIN 16 bits
D0 D0 +1 (Not used) Used by system –– System
Designate the number of data to request reading.
(Unit: Word)
No. of request 1 to 480
D0 +2 Even when byte is specified at D0 +7 by data type User
read data 1 to 32767*2
specification, specify the value in units of words (16 bits), not in
units of bit devices.
D0 +3 (Not used) –– –– ––

*2: Indicates the range applicable for the Universal model QCPU, LCPU.

654
 SP.FREAD

Setting Setting
Meaning Set by Data Type
Data Range
Designate the file position to start reading when binary data
1
reading is designated by D0 .

00000000H: Starting at the beginning of the file

00000001H to FFFFFFFEH: From the designated position
(The unit for the value is determined
2
by word/byte unit designation.)
FFFFFFFFH: Setting disabled

When CSV format read is specified at D0

3
D0 +4 File • For the High Performance model QCPU of which the first 5 00000000H to
digits of the serial number are "01111" or lower, always set User
position FFFFFFFFH
D0 +5
the beginning (0H) of the file. 4
• For the High Performance model QCPU/Process CPU/
Redundant CPU/Universal model QCPU/LCPU of which the
D0
first 5 digits of the serial number are "01112" or higher, set the
file position (Row).
4
00000000H: Read starts at the beginning of the file.
00000001H to FFFFFFFEH: Read starts at the specified row.
FFFFFFFFH 6
: Read continues, starting at the previous read position.

When binary read is specified at D0 , always set 0.

When read data after CSV format conversion is specified at
0H to FFFFH
7
No. of columns
D0 +6 D0 , User BIN 16 bits
designation set the number of columns from where data will be read. (0 to 65535)
0 : No columns. Regarded as one row.
Other than 0: Regarded as the specified number of columns. 8
Data type 0: Word
D0 +7 0,1 User
specification 1: Byte
Head number of the devices storing a file name. A file name is expressed as follows:
Device Item Contents/Setting Data Setting Range Set by

7.18.13 SP.FREAD
7.18 Other instructions
Designate the character string of a file name.
• When omitting an extension, also omit the "." (Period).
S1 File name • Limit the file name within 8 characters + period + 3
S1 to Character
character characters. User
S1 + string
string • When 9 or more characters are used, the extension is
ignored regardless of its presence, and "BIN" or "CSV" is
regarded as an extension.
Head number of the devices for storing the read data.
Device Item Contents/Setting Data Setting Range Set by
Reading result Contains the number of actually read data against the data
D1 (No. of read designated by D0 +2. The unit on the value depends on data –– System
D1 data) type specification.
D1 +1

to Reading data Read data –– System

D1 +

655
 SP.FREAD

Setting Setting
Meaning Set by Data Type
Data Range
Bit device that turned ON at the completion of the processing.
( D2 +1 is also turned ON at error completion.)
Device Item Contents/Setting Data Setting Range Set by
Indicates the completion of the processing.
Completion
D2 ON: Completed –– Bit
D2 signal
OFF: Not completed
Indicates whether the processing is normally completed or System
Error
abnormally completed.
D2 +1 completion ––
ON: Error completion
signal
OFF: Normal completion

Caution
(1) At S0 (drive designation), only the ATA card drive (2) can be set.(For QCPU)
Note that when the Flash card is loaded, the SP.FREAD instruction cannot be used to perform read.
The SRAM card, standard RAM or standard ROM drive cannot be set.
For the High-speed Universal model QCPU and LCPU, only the SD memory card drive (2) can be set for S0 (drive
designation).
(2) For CSV setting, the data read are decimal values.

Example Character "A" (41H) "65" is read.

Handling range: -32768 to 32767
(3) For binary read, the word-specified file position setting range is 00000000H to 7FFFFFFFH.
(4) For the High-speed Universal model QCPU and LCPU, this instruction cannot be executed while SM606 (SD memory
card forced disable instruction) is ON. If the instruction is executed, the processing is not performed.

Function
(1) Data is read from the designated file.
Set the execution/completion type in the control data to designate whether to read binary data without any conversion or
to convert binary data into CSV format data before reading it. (The QCPU reads data only from ATA cards; on the other
hand, the High-speed Universal model QCPU and LCPU reads data only from SD memory cards.)

(2) The execution completion bit device ( D2 ) is automatically turned ON at the END processing after the completion of the
instruction is detected. The bit device is turned OFF at the execution of the END instruction in the next scan.
Use this bit device as the execution completion flag for the SP.FWRITE instruction.
When this instruction is completed abnormally, the error completion device ( D2 +1) is turned ON/OFF in synchronization
with the execution completion ( D2 ) device. Use this device as the error completion flag for this instruction.
SM721 is turned ON during the execution of the instruction.
This instruction cannot be executed while SM721 is ON. (If an attempt is made, no processing is performed.)
When an error is detected at the execution of the instruction (before SM721 is turned ON), the processing complete
device ( D1 ), the error completion device ( D1 +1), and SM721 are not turned ON.

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 SP.FREAD

(3) Be sure to use word units to designate the number of request read data ( D0 +2), file position ( D0 +4 and D0 +5), and
reading result (No. of read data) ( D1 ).
The following shows how the data is read in binary data reading operation. 1
Control data
D0 +0
D0 +1
H0000
-
Execution/completion type
(Not used)
2
D0 +2 K3 No. of request read data
D0 +3 - (Not used)
D0 +4 K1 3
D0 +5 Location to start reading in the file
D0 +6 K0 No. of columns designation
D0 +7 K0 Data type specification 4
Data device File data (in byte units)
D1 +0 K3 H00 4
H11
D1 +1 H33 22 H22
Total H33 6
D1 +2 H55 44 H44
Read
H55
data
D1 +3 H77 66 H66
7
H77
H88
H99
HAA
8

(4) When reading binary data

(a) If the extension of the target file is omitted, ".BIN" is used as an extension.

7.18.13 SP.FREAD
7.18 Other instructions
(b) When the designated file does not exist, an error occurs.
(c) If the position specified is greater than the existing file size:
• The High Performance model QCPU of which the first 5 digits of the serial number are "01111" or lower results in
an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU of which the
first 5 digits of the serial number are '01112' or higher will perform reading at point 0 and will be completed
normally.
(5) When reading data after CSV format conversion
(a) The elements in CSV format file (cells for EXCEL) are read by each row. The numerical value and character strings
are converted into binary data and stored in the device.
(b) If the extension is omitted, ".CSV" is used as an extension.
(c) When the designated file does not exist, an error occurs.
(d) The data designated by the number of request read data ( D0 +2) are read from the beginning of the file.
When the last data of the file is reached before the specified number of data are read:
• The High Performance model QCPU of which the first 5 digits of the serial number are "01111" or lower results in
an error.
• The High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU whose the
first 5 digits of the serial number are '01112' or higher reads the data up to the point where the reading is
possible.

657
 SP.FREAD

(e) When the designated number of columns is 0, the data is read by ignoring the rows in CSV format file.

Example When data is read after CSV format conversion and the designated No. of columns is 0:

Data created by EXCEL

Main / sub item Measured value

Length
Temperature

Data saved in the CSV format

Main / sub item , , Measured value CR LF
Length , 1 , 3 CR LF
Temperature , -21 , CR LF

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

Data that was read

File name
Control data
Control data

D10 H0100 Execution/completion type

D11 - Not used
D12 K9 No. of request read data
D13 - Not used
D14 K0
File position
D15 K0
D16 K0 No. of columns designation
D17 K0 Data type specification

D20 H4241 File name

D21 H4443 "ABCDE"
D22 H0045

Loaded data
Stores the number of read data Reading result (No. of read data)
D099 K9
Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.
Measured value D102 K0 Conversion data (0) is stored since "Measured value" is nonnumeric data.

Length D103 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
Read D104 K1 Since " 1 " is a numeric value, it is converted to a binary value.
1
data
3 D105 K3 Since " 3 " is a numeric value, it is converted to a binary value.

Temperature D106 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.

-21 D107 K-21 Since " -21 " is a numeric value, it is converted to a binary value.
Data between , and CR D108 K0 Conversion data (0) is stored since " " is nonnumeric data.

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 SP.FREAD

If the number of columns varies in each row, the data is also read by ignoring the rows.

1
Such file cannot be created using EXCEL. This happens when CSV file is modified by a user.

Example If the number of columns varies in each row when the data is read: 2
Main / sub item , , Measured value , Excess CR LF
Length CR LF 3
Temperature , -21 , CR LF

Data to be read into devices

4
SP.FREAD U0 K2 D10 D20 D99 M0

Data that was read

File name
4
Control data

Control data 6
D10 H0100 Execution/completion type
D11 - Not used
D12 K7 No. of request read data 7
D13 - Not used
D14 K0
8
File position
D15 K0
D16 K0 No. of columns designation
D17 K0 Data type specification

D20 H4241 File name

7.18.13 SP.FREAD
7.18 Other instructions
D21 H4443 "ABCD"
D22 H0000

Loaded data
Stores the number of read data
D099 K7 Reading result (No. of read data)
Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.
Measured value D102 K0 Conversion data (0) is stored since "Measured value" is nonnumeric data.
Excess D103 K0 Conversion data (0) is stored since "Excess" is nonnumeric data.
Read Length D104 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
data
Temperature D105 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.
-21 D106 K-21 Since " -21 " is a numeric value, it is converted to a binary value.

659
 SP.FREAD

(f) When data is read after CSV format conversion and the designated number of columns is other than 0, the data is
read as the table with designated number of columns in CSV format file. The elements outside of the designated
columns are ignored.

Example When data is read after CSV format conversion and the designated No. of columns is other than "0":

Data created by EXCEL

Main / sub item Measured value

Length
Temperature

Data saved in the CSV format

Main / sub item , , Measured value CR LF

Length , 1 , 3 CR LF
Temperature , -21 , CR LF
Elements outside the designated
number of columns are ignored.

Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

Data that was read

File name
Control data
Control data

D10 H0100 Execution/completion type

D11 - Not used
D12 K6 No. of request read data
D13 - Not used
D14 K0
File position
D15 K0
D16 K2 No. of columns designation
D17 K0 Data type specification

D20 H4241 File name

D21 H4443 "ABCD"
D22 H0000

Loaded data
Stores the number of read data
D099 K6 Reading result (No. of read data)

Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.

Read Length D102 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
data 1 D103 K1 Since " 1 " is a numeric value, it is converted to a binary value.

Temperature D104 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.

-21 D105 K-21 Since " -21 " is a numeric value, it is converted to a binary value.

660
 SP.FREAD

If the number of columns varies in each row, the elements outside of the designated columns are ignored and "0" is
added to the places where elements do not exist.

Example If the number of columns varies in each row when the data is read: 1
Main / sub item , , Measured value , Excess CR LF
Length CR LF
Temperature , -21 , CR LF Elements outside the designated
2
number of columns are ignored.

3
Data to be read into devices

SP.FREAD U0 K2 D10 D20 D99 M0

Data that was read 4

File name
Control data
Control data
4
D10 H0100 Execution/completion type
D11 - Not used
D12 K6 No. of request read data
6
D13 - Not used
D14 K0
D15 K0
File position 7
D16 K2 No. of columns designation
D17 K0 Data type specification
8
D20 H4241 File name
D21 H4443 "ABCD"
D22 H0000

7.18.13 SP.FREAD
7.18 Other instructions
Loaded data
Stores the number of read data
D099 K6 Reading result (No. of read data)
Main/sub item D100 K0 Conversion data (0) is stored since "Main/sub item" is nonnumeric data.
Data between , and , D101 K0 Conversion data (0) is stored since " " is nonnumeric data.

Read Length D102 K0 Conversion data (0) is stored since "Length" is nonnumeric data.
data No data D103 K0 No data since no element exists here, conversion data (D) is added.
Temperature D104 K0 Conversion data (0) is stored since "Temperature" is nonnumeric data.
-21 D105 K-21 Since " -21 " is a numeric value, it is converted to a binary value.

661
 SP.FREAD

(g) With the High Performance model QCPU/Process CPU/Redundant CPU/Universal model QCPU/LCPU whose first
5 digits of the serial number are "01112" or later, it is possible to divide read operation into multiple times.
[Specify the row desired to start read.]
Execution type = CSV format Starting row number = 2H
No. of columns designation = 4H Read head device = D0
Data type specification = Word No. of request read data = 6H
Device data
(Data to be read out)
Column 1 Column 2 Column 3 Column 4 K6 D0 No. of request read data
K5 D1
Row 1 1 , 2 , 3 , 4 CR LF K6 D2
K7 D3
K8 D4
Starting row Row 2 5 , 6 , 7 , 8 CR LF
K9 D5
K10 D6
D7
Row 3 9 , 10 , 11 , 12 CR LF D8
position D9
D10
starting
Next

D11
D12
Row 4 13 , 14 , 15 , 16 CR LF D13

Row 5 17 , 18 , 19 , 20 CR LF

[In the continuation mode, read continues from the end of the previous read position.]
Execution type = CSV format Starting row number = FFFFFFFH (Continuation mode)
No. of columns designation = 4H Read head device = D7
Data type specification = Word No. of request read data = 5H
Device data
(Data to be read out)
K6 D0

Column 1 Column 2 Column 3 Column 4

K5 D1
K6 D2
Row 1 1 , 2 , 3 , 4 CR LF K7 D3
K8 D4
K9 D5
Row 2 5 , 6 , 7 , 8 CR LF K10 D6
K5 D7 No. of request read data
Present

position
starting

K11 D8
K12 D9
K13 D10
Row 3 9 , 10 , 11 , 12 CR LF K14 D11
K15 D12
D13
Row 4 13 , 14 , 15 , 16 CR LF
position
starting
Next

Row 5 17 , 18 , 19 , 20 CR LF

• When read is performed in the continuation mode, the previous addition cannot be made normally if the "execution
type", "No. of columns designation" and "data type specification" settings differ from those at the previous time.
• The previous addition cannot be made normally if the SP.FREAD instruction or SP.FWRITE instruction with another
setting is executed while data is being read continuously in the continuation mode.

662
 SP.FREAD

(h) When data is read after CSV format conversion, the numerical values that are out of range or the elements other
than numerical values in the object CSV format file are converted into 0H.
(i) When data is read after CSV format conversion, numerical values are read and converted as follows: 1
Numerical Values in CSV
-32768 to -1 0 to 32767 32768 to 65535
Format

Word device
Without a sign
With a sign
32768 to 65535
-32768 to -1
0 to 32767
0 to 32767
32768 to 65535
-32768 to -1
2
(j) Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)
3
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
4
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU 4
code
Q01
The file name specified in file name character string ( S1 ) or the
2410 ––
subsequent devices does not exist in the specified drive. 6
4004 The device that cannot be specified has been specified. ––
Values designated in control data ( D0 ) and the subsequent devices are
––
out of the setting range. (Excluding ( D0 +2) 7
The drive specified by drive designation device ( S0 ) contains the
medium other than the ATA card. –– ––

4100
An access error occurred in the ATA card.
When binary data is read, the number of data in the file is less than the
8
–– –– –– –– ––
size designated by the number of request read data ( D0 +2).
The drive specified by drive designation device ( S0 ) contains the
medium other than the SD Memory card. –– –– –– ––
An access error occurred in the SD Memory card.

7.18.13 SP.FREAD
7.18 Other instructions
The value specified in number of data blocks to be read ( D0 +2) is out of
the setting range. ––
4101 The size of read data exceeds that of the reading device.
The range of the device specified by D0 or D2 exceeds the range of the
–– –– –– ––
corresponding device.

663
 SP.FREAD

Program Example
(1) The following program reads 4 bytes of binary data from the beginning of file "ABCD.BIN" in the memory card inserted to
drive 2 when X10 is turned ON.
• Assume that 8 points from (D0) are reserved for the control data devices.
• Assume that 100 bytes from D20 are reserved for the reading devices.
[Ladder Mode]

Sets the execution/completion type

Sets the number of request read data

Sets the file position

Sets the file name

Normal completion display

Error completion display

[List Mode]
Step Instruction Device

664
 SP.DEVST

(2) The following program reads file "ABCD.CSV" in the memory card inserted to drive 2 as two-column table data in CSV
format when X10 is turned ON.
• Assume that 8 points from (D0) are reserved for the control data devices. 1
• Assume that 100 bytes from D20 are reserved for the reading devices.
• Assume that the target CSV format file contains numerical values only.
[Ladder Mode] 2
Sets the execution/completion type

Sets the number of request read data 3

Sets the designation of number of columns

Sets the file name 4

Normal completion display 4

Error completion display 6

7
[List Mode]
Step Instruction Device 8

7.18.14 SP.DEVST
7.18 Other instructions
7.18.14 SP.DEVST Writing data to standard ROM

7.18.14 SP.DEVST Basic High

performance Process Redundant Universal LCPU

Command
SP.DEVST SP.DEVST n1 S n2 D

n1 :Write offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit)
S :Head device number written to the standard ROM (device name)
n2 :The number of write points (BIN 16-bit)
D : D +0: Completion device (bit)
D +1: Error completion device (bit)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n1 –– –– ––
S –– –– –– ––
n2 –– –– ––
D *1 –– *1 –– –– ––
*1: Devices assigned as local devices can not be used.

665
 SP.DEVST

Function
(1) Writes device data for the number of points specified at n2 of the device S to the write offset, which is specified for n1, of
the device data storage file in the standard ROM.
n1 is the offset from the head of device data storage file and specified by word offset (in units of 16-bit words).

Standard ROM

Head device Write offset n1 Device data

number S storage file Write offset of device
data storage file
Write
offset 16-bit
+0
Number of
+1
n2 points
+2

(2) Since the completion device ( D +0) in the standard ROM automatically turns ON at execution of the END instruction,
which detects the completion of this instruction, and turns OFF with the END instruction of next scan, it is used as an
execution completion flag of this instruction.
(3) When this instruction is completed in error, the error completion device ( D +1) turns ON/OFF at the same timing with the
completion device ( D +0). This device is used as an error completion flag of this instruction.
(4) SM721 turns ON during execution of this instruction.
When SM721 has already turned ON, this instruction can not be executed. (If executed, no processing is performed.)
(5) When an error is detected at execution of this instruction, the completion device ( D +0), error completion device ( D +1)
and SM721 do not turn ON.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The device data storage file is not set at "PLC file" of PLC parameter
2410 –– –– –– ––
on.
The range of the write offset specified in n1 is out of the device data
storage file range.
4100 –– –– –– ––
The number of n2 points from the write offset specified at n1 is out of
the device data storage file range.
The range of the device specified by D exceeds the range from D to D
+ n2 (including D ).
4101 –– –– –– ––
The device specified by D exceeds the range of the corresponding
device.

666
 S.DEVLD, SP.DEVLD

Program Example
1
(1) The program which writes the ten points of data from D100 to the device data storage file in the standard ROM when M0
turns ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

Caution 4
(1) The value written to the standard ROM is the value at execution of this instruction.
(2) The standard ROM write count index (SD687 and SD688) is increased by the execution of the SP.DEVST instruction. If
the standard ROM write count index exceeds hundred thousand times, FLASH ROM ERROR (error code: 1610) occurs. 4
(3) To prevent the number of ROM writes from increasing due to executing instruction carelessly, set the specification of
writing to standard ROM instruction count (SD695) to restrict the number of writes a day.
Exceeding the number of writes (the default values are 36 times.) set causes OPERATION ERROR (error code: 4113).
6
7.18.15 S.DEVLD, SP.DEVLD Reading data from standard ROM

7
7.18.15 S.DEVLD, SP.DEVLD Basic High
performance Process Redundant Universal LCPU

8
Command
S.DEVLD S.DEVLD n1 D n2

Command
SP.DEVLD SP.DEVLD n1 D n2

n1 : Read offset of the device data storage file (specified in units of 16-bit words) (BIN 32-bit)

7.18.15 S.DEVLD, SP.DEVLD

7.18 Other instructions
D : Head device number read from the standard ROM (device name)
n2 : The number of reading points (BIN 16-bit)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word E
n1 –– –– ––

D –– –– –– ––

n2 –– –– ––

Function
(1) Reads device data for the number of points specified at n2 from the read offset, which is specified for n1, of the device
data storage file in the standard ROM, and stores the data to the device specified for D .
n1 is the offset from the head of device data storage file and specified by word offset (in units of 16-bit words).

Standard ROM

Head device Read offset n1 Device data storage file

number D Read offset of device data
storage file
Read
offset 16-bit
+0
Number of
+1
n2 points
+2

667
 PLOADP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The device data storage file is not set at "PLC file" of PLC parameter. –– –– –– ––
The address specified in n1 is out of the standard ROM range.
4100 –– –– –– ––
The address of n2, specified in n1, is out of the standard ROM range.
4101 The range of n2 exceeds that of the device specified in D . –– –– –– ––

Program Example
(1) The program which reads the ten points of data from D100 to the device data storage file in the standard ROM when M0
turns ON.
[Ladder Mode] [List Mode]
Step Instruction Device

7.18.16 PLOADP Loading program from memory card

7.18.16 PLOADP Basic High

performance Process Redundant Universal LCPU

Command
PLOADP PLOADP S D

S : Drive No. storing the program to be loaded, character string data of the file name, or head number of the devices storing the character string data (BIN 16
bits) *1
D : Device that turns ON for 1 scan by the instruction completion (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $
S –– –– ––

D *2 –– –– –– ––
*1: Designated as "<Drive No.>:<File Name>". Example) 1:MAIN
*2: Local devices cannot be used.

Function
(1) The program stored in the memory card or standard ROM is transferred to the program memory (drive 0).
If the transferred program is not registered to the program setting of the PLC parameter window, its program setting in
the CPU module is set to the standby type.
At this time, the program setting of the PLC parameter dialog box does not change.
(To transfer a program with the PLOADP instruction, a continuous free space is required in the program memory.)
(2) The program added using the PLOADP instruction is assigned the lowest number among the unused program Nos.
(To assign a program number manually, store the program number to be assigned in SD720.)
The following example assumes that "MAIN6" is added by the PLOADP instruction.

668
 PLOADP

(a) When the program Nos. have been set consecutively, the new program is added at the end of the preset program
Nos.
When programs No. 1 to 5 have been set, the new program is added as program No. 6. 1
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 MAIN2 2 MAIN2
3 MAIN3
Adds "MAIN6" by the
PLOADP instruction. 3 MAIN3 2
4 MAIN4 4 MAIN4
5 MAIN5 5 MAIN5
6 MAIN6 Added at the end.

(b) When there are multiple open program Nos., the program designated by the PLOADP instruction is added to the
3
lowest number among them to be added.
(The open program Nos. are made when programs are deleted by the PUNLOADP instruction.)
When programs No. 2 and 4 are open, the new program is added as program No. 2.
4
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 Empty Adds "MAIN6" by the 2 MAIN6 Added to the smallest program
number which is empty.
4
3 MAIN3 PLOADP instruction. 3 MAIN3
4 Empty 4 Empty
5 MAIN5 5 MAIN5

(3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.)

6
• Drive 1: Memory card (RAM)
• Drive 2: Memory card (ROM)
• Drive 4: Standard ROM
7
(4) An extension (.QPG) need not be specified for the file name.

(5) The bit device specified by D is turned ON during the END processing of the scan where this instruction is completed. 8
The bit device is turned OFF at the next END processing.
(6) The PLC file settings of the loaded program are set as follows:
(a) File usage for each program
All the usage of file register, device initial value, comment, and local device of the program transferred by this

7.18.16 PLOADP
7.18 Other instructions
instruction are set as "Use PLC file setting".
However, an error will be returned if both of the conditions below are met when the program is transferred using this
instruction.
• Setting is made so that local devices are used in the PLC file setting.
• The number of programs in the program memory exceeds the number of programs set at the parameters.
To use local devices in the program transferred by this instruction, register a dummy program file in the parameter,
delete the dummy file with the PUNLOADP instruction, and then load the program with the PLOADP instruction.
(b) I/O refresh setting
Nothing is set for both input and output for the I/O refresh setting of the program transferred by this instruction.

669
 PLOADP

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2401 The file size of the local devices cannot be reserved. –– –– –– ––
The file name does not exist at the drive number specified in S .
2410 The program file which has the same name as the program file to be –– –– –– ––
loaded already exists.
2413 There is not enough memory to load the specified program in drive 0. –– –– –– ––
4100 The drive No. specified in S is invalid. –– –– –– ––
The same number of files as that indicated in the table below has been
already registered in the program memory.
4101 –– –– –– ––
The program No. stored in SD720 is already used, or is larger than the
largest program No. shown in the table below.

CPU Model Name Program Memory (No. of Files) Largest Program No.
Q02 (H) CPU 28 28
Q06HCPU 60 60
Q12HCPU 124 124
Q25HCPU 124 124
Q12PHCPU 124 124
Q25PHCPU 124 124

Program Example
(1) The following program transfers "ABCD.QPG" stored in drive 4 to drive 0 and places the program in standby status when
M0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

670
 PUNLOADP

Caution
1
(1) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous execution.
2
(2) Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)
(3) To execute the program that was transferred to the program memory with the PLOADP instruction, execute the scan 3
execution type with the PSCAN instruction (See Page 616, Section 7.17.3).
(4) The "PLOADP instruction" and "Write during RUN" processing cannot be executed simultaneously.
(a) When a write during RUN request is given during processing of the PLOADP instruction, write during RUN is 4
delayed.
Write during RUN is started after the processing of the PLOADP instruction is completed.
(b) When the PLOADP instruction is executed during write during RUN, the processing of the PLOADP instruction is 4
delayed.
The processing of the PLOADP instruction is started after completion of write during RUN.
(5) Do not execute "Read from PLC" or "Verify with PLC" and the instruction simultaneously. 6
If the instruction is executed, "Read from PLC" or "Verify with PLC" is not complete normally because the program file
status stored in the program memory is changed.
If executed, execute "Read from PLC" or "Verify with PLC" again after the instruction completion. 7
7.18.17 PUNLOADP Unloading program from program memory

7.18.17 PUNLOADP Basic High

performance Process Redundant Universal LCPU
8

Command
PUNLOADP PUNLOADP S D

7.18.17 PUNLOADP
7.18 Other instructions
S : Character string data of the program file name to be unloaded, or head number of the devices storing the character string data (BIN 16 bits)
D : Device turned ON for 1 scan on completion of the instruction (bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word $
S –– –– ––

D *1 –– –– –– ––

*1: Local devices cannot be used.

671
 PUNLOADP

Function
(1) The standby program stored in the program memory (drive 0) is deleted from the program memory.
(The program set as the "scan execution type" with the PSCAN instruction or the program set as the "low speed
execution type" with the PLOW instruction cannot be deleted.)
(2) The program No. deleted by the PUNLOADP instruction is made "Empty".
When programs No. 1 to 5 have been set in the program setting of the PLC parameter dialog box, deleting program No.
2 with this instruction makes program No. 2 open.
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 MAIN2 Deletes "MAIN2" by the 2 Empty Program No. 2
3 MAIN3 PUNLOADP instruction. 3 MAIN3 is deleted.
4 MAIN4 4 MAIN4
5 MAIN5 5 MAIN5

(3) An extension (.QPG) need not be specified for the file name.

(4) The bit device specified by D is turned ON during the END processing of the scan where this instruction is completed.
The bit device is turned OFF at the next END processing.
(5) When the programmable controller is powered OFF, then ON or the CPU module is reset after execution of the
PUNLOADP instruction, the following operation is performed.
(a) When boot setting has been made in the PLC parameter dialog box, the program where the boot setting has been
made is transferred to the program memory.
When the program deleted by the PUNLOADP instruction is not to be executed, delete the corresponding program
name from the boot setting and program setting of the PLC parameter dialog box.
(b) When boot setting has not been made in the PLC parameter dialog box, "FILE SET ERROR (error code: 2400)"
occurs.
1) When the program deleted by the PUNLOADP instruction is not to be executed, delete the corresponding
program name from the program setting of the PLC parameter dialog box.
2) When the program deleted by the PUNLOADP instruction is to be executed again, write the corresponding
program to the CPU module.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The file name specified in S does not exist. –– –– –– ––
The program specified in S is not in standby status or is being
4101 –– –– –– ––
executed.

Program Example
(1) The following program deletes "ABCD.QPG" stored in drive 0 from the memory when M0 turns from OFF to ON.
[Ladder Mode] [List Mode]
Step Instruction Device

672
 PSWAPP

Caution
1
(1) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous execution.
2
(2) Do not execute this instruction in an interrupt program.
(Otherwise, a malfunction may result.)
(3) The program to be deleted from the program memory by this instruction should be set to the "standby execution type" 3
with the PSTOP instruction beforehand. (See Page 614, Section 7.17.1)
(4) The "PUNLOADP instruction" and "write during RUN" processing cannot be executed simultaneously.
(a) When a write during RUN request is given during processing of the PUNLOADP instruction, write during RUN is 4
delayed.
Write during RUN is started after the processing of the PUNLOADP instruction is completed.
(b) When the PUNLOADP instruction is executed during write during RUN, the processing of the PUNLOADP 4
instruction is delayed.
The processing of the PUNLOADP instruction is started after completion of write during RUN.
(5) Do not execute "Read from PLC" or "Verify with PLC" and the instruction simultaneously. 6
If the instruction is executed, "Read from PLC" or "Verify with PLC" is not complete normally because the program file
status stored in the program memory is changed.
If executed, execute "Read from PLC" or "Verify with PLC" again after the instruction completion. 7
7.18.18 PSWAPP Loading and unloading

7.18.18 PSWAPP Basic High

performance Process Redundant Universal LCPU
8

Command
PSWAPP PSWAPP S1 S2 D

7.18.18 PSWAPP
7.18 Other instructions
S1 : Character string data of the file name of the program to be unloaded, or head number of the devices storing the character string data (BIN 16 bits)
S2 : Drive No. storing the program to be loaded, character string data of the file name, or head number of the devices storing the character string data (BIN 16
bits) *1
D : Device turned ON for 1 scan on completion of the instruction (bits)

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word $
S1 –– –– ––

S2 –– –– ––

D *2 –– –– –– ––

*1: Designated as "<Drive No.>:<File Name>". Example) 1:MAIN

*2: Local devices cannot be used.

Function
(1) The standby type program stored in the program memory (drive 0) designated by S1 is deleted from the program
memory, and at the same time, the program stored in the memory card or standard ROM designated by S2 is transferred
to the program memory and placed in standby status.
(When the program is transferred to the program memory, the program must have a continuous free space.)
The program set as the "scan execution type" with the PSCAN instruction or the program set as the "low speed
execution type" with the PLOW instruction cannot be deleted.

673
 PSWAPP

(2) The program to be transferred to the program memory by the PSWAPP instruction will have the program No. of the
program to be deleted from the program memory.
(If there is an open program No. before the program to be deleted from the program memory, the program to be
transferred to the program memory will not have the open program No.)
When program No. 2 is "Empty", the program transferred to the program memory is registered as program No. 3 by the
program swapping of program No. 3 with this instruction.
Program No. Program name Program No. Program name
1 MAIN1 1 MAIN1
2 Empty Swaps "MAIN3" with "MAIN6" 2 Empty
3 MAIN3 by the PSWAPP instruction. 3 MAIN6 MAIN6 enters
4 MAIN4 4 MAIN4
5 MAIN5 5 MAIN5

(3) Drive Nos. 1, 2, and 4 can be specified. (Drive 3 cannot be specified.)

• Drive 1: Memory card (RAM)
• Drive 2: Memory card (ROM)
• Drive 4: Standard ROM
(4) An extension (.QPG) need not be specified for the file name.

(5) The bit device specified by D is turned ON during the END processing of the scan where this instruction is completed.
The bit device is turned OFF at the next END processing.
(6) When the programmable controller is powered OFF, then ON or the CPU module is reset after execution of the PSWAPP
instruction, the following operation is performed.
(a) When boot setting has been made in the PLC parameter dialog box, the program where the boot setting has been
made is transferred to the program memory.
When the program replaced by the PSWAPP instruction is to be executed, change the boot setting and program
setting of the PLC parameter dialog box for the corresponding program name.
(b) When boot setting has not been made in the PLC parameter dialog box, "FILE SET ERROR (error code: 2400)"
occurs.
1) When the program replaced by the PSWAPP instruction is to be executed, change the program setting of the
PLC parameter dialog box for the corresponding program name.
2) To execute the program set in the program setting of the PLC parameter dialog box, write the corresponding
program to the CPU module again.
(7) The PLC file settings of the program on which the PSWAPP instruction has been conducted are set as follows:
(a) File usage for each program
All the usage of file register, device initial value, comment, and local device of the program after the execution of the
PSWAPP instruction are set as "Use PLC file setting".
(b) I/O refresh setting
Nothing is set for both input and output for the I/O refresh setting of the program after the PSWAPP instruction has
been executed.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
2410 The drive No. or the file name specified in S1 or S2 does not exist. –– –– –– ––
2413 There is not enough memory to load the specified program in drive 0. –– –– –– ––
4100 The drive No. specified in S1 is invalid. –– –– –– ––
The program specified in S1 is not in standby status or is being
4101 –– –– –– ––
executed.

674
 RBMOV, RBMOVP

Program Example
1
(1) The following program deletes "EFGH.QPG" stored in drive 0 from the memory, transfers "ABCD.QPG" stored in drive 4
to drive 0, and places the program in standby status when M0 is turned from OFF to ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

Caution 4
(1) The PLOADP, PUNLOADP and PSWAPP instructions cannot be executed simultaneously.
If two or more of the above instructions are executed simultaneously, the instruction executed later will not be executed.
When using the above instructions, provide interlocks manually to avoid simultaneous execution. 4
(2) Do not execute this instruction in an interrupt program.
(Execution of this instruction in an interrupt program can cause a malfunction.)
(3) The "PSWAPP instruction" and "write during RUN" processing cannot be executed simultaneously.
6
(a) When a write during RUN request is given during processing of the PSWAPP instruction, write during RUN is
delayed.
Write during RUN is started after the processing of the PSWAPP instruction is completed.
7
(b) When the PSWAPP instruction is executed during write during RUN, the processing of the PSWAPP instruction is
delayed.
The processing of the PSWAPP instruction is started after completion of write during RUN.
8
(4) Do not execute "Read from PLC" or "Verify with PLC" and the instruction simultaneously.
If the instruction is executed, "Read from PLC" or "Verify with PLC" is not complete normally because the program file
status stored in the program memory is changed.

7.18.19 RBMOV, RBMOVP

7.18 Other instructions
If executed, execute "Read from PLC" or "Verify with PLC" again after the instruction completion.

7.18.19 RBMOV, RBMOVP High-speed block transfer of file register

Ver.

7.18.19 RBMOV, RBMOVP

High
Basic performance Process Redundant Universal LCPU
• Universal model QCPU: Models other than Q00UJCPU

Command
RBMOV RBMOV S D n

Command
RBMOVP RBMOVP S D n

S : Head number of the devices where the data to be transferred is stored (BIN 16 bits)
D : Head number of the devices of transfer destination (BIN 16 bits)
n : Number of data to be transferred (BIN 16 bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– ––

D –– ––

n ––

675
 RBMOV, RBMOVP

Function
(1) Transfers in batch 16-bit data of n points from the device designated by S to location n points from the device
designated by D .
b15 b0 b15 b0
S 1234H D 1234H
S +1 5678H Block D +1 5678H
S +2 7FF0H transfer D +2 7FF0H
n n

S +(n-2) 6FFFH D +(n-2) 6FFFH

S +(n-1) 553FH D +(n-1) 553FH

(2) The transfer is available even if there is an overlap between the source and destination devices.
For the transmission to the smaller number of device, the data is transferred from S . For the transmission to the larger
number of device, the data is transferred from S +(n-1).
However, as shown in the example below, when transferring data from R to ZR, or from ZR to R, the range to be
transferred (source) and the range of destination must not overlap.
• ZR transfer range ((specified head No. of ZR) to (specified head No. of ZR + the number of transfers -1))
• R transfer range ((specified head No. of R + file register block No. 32768) to (specified head No. of R + file register
block No. 32768 + the number of transfers -1))

Example Transfer ranges of ZR and R overlap when transferring 10000 points of data from ZR30000 (source) to

R10 (block No.1 of the destination).

• ZR transfer range (30000) to (30000+10000-1) (30000) to (39999)
• R transfer range (10+(1 32768)) to (10+(1 32768)+10000-1) (32778) to (42777)
Therefore, the range 32778 to 39999 overlaps.

Source of transfer Destination of transfer

ZR0 R0

Overlapped Block No. 0

ZR30000 R32767
ZR39999 R10

R10009 Block No. 1

(3) When S is a word device and D is a bit device, the number of bits designated by the bit device digit specification will be
transferred. If K1Y30 has been designated by D , the lower four bits of the word device designated by S will be
transferred.
b15 b4b3b2b1b0 D +2 D +1 D
S R100 1011
Y3B Y38Y37 Y34Y33 Y30
S +1 R101 0011 n 011100111011
n
S +2 R102 0111

676
 RBMOV, RBMOVP

Operation Error
1
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.

Error
Error details
Q00J/
Q00/ QnH QnPH QnPRH QnU LCPU
2
code
Q01
The range of n exceeds that of the corresponding device specified in
3
S

4101 or D . –– ––
The file register is not specified for either S or D .

4
Program Example
(1) The following program outputs the lower four bits of data in R66 to R69 to Y30 through Y3F in units of 4 points.
[Ladder Mode] [List Mode]
4
Step Instruction Device

Before execution 7
(source of transfer) After execution
b15 b4b3 b0 (destination of transfer)
R66 1110 1 1 1 0 1 Y33 to Y30
R67 00000 0 0 0 0 Y37 to Y34 8
R68 10011 0 0 1 1 Y3B to Y38
R69 0 110 1 1 1 0 1 Y3F to Y3C

Ignored

7.18.19 RBMOV, RBMOVP

7.18 Other instructions
(2) The following program outputs the data in X20 to X2F to R100 to R103 in units of 4 points.
[Ladder Mode] [List Mode]
Step Instruction Device

Before X2F X2CX2B X28 X27 X24X23 X20

execution 1 0 0 0 0 1 1 1 0 1 1 0 0 1 0 0 After execution
(destination of transfer)
b15 b4 b3 b0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 R100

0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 R101
4 points
0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 R102

0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 R103

Filled with 0s

677
 RBMOV, RBMOVP

The RBMOV (P) instruction is useful to batch transfer a large quantity of file register data with the QnHCPU/QnPHCPU/
QnPRHCPU.
For the QnUCPU, the processing speed of the RBMOV instruction is equivalent to that of the BMOV instruction.
The comparison of processing speed between the RBMOV and BMOV instructions is as follows:
(1) Transfer from file registers to internal devices/internal devices to file registers
Target memory 1 word 1000 words 10000 words
CPU Instruction where file register
Min. Max. Min. Max. Min. Max.
is stored
Standard RAM 20.0 µs 91.0 µs 775.0 µs
RBMOV SRAM card 22.0 µs 305.0 µs 2900.0 µs
QnHCPU
Flash card *1 22.5 µs 405.0 µs 3950.0 µs
QnPHCPU
Standard RAM 7.5 µs 76.2 µs 720.0 µs
QnPRHCPU
BMOV SRAM card 384.0 µs 3900.0 µs
8.0 µs
Flash card *1 418.0 µs 4250.0 µs
Standard RAM 45.5 µs 215.0 µs 1850.0 µs
RBMOV SRAM card
49.5 µs 540.0 µs 5150.0µs
Flash card *1
QnCPU
Standard RAM 17.5 µs 177.0 µs 1700.0 µs
BMOV SRAM card 500.0 µs 5050.0 µs
18.0 µs
Flash card *1 572.0 µs 5800.0 µs
Standard RAM 12.2 µs 34.9 µs 121.5 µs 145.1 µs 1111.5 µs 1135.1 µs
RBMOV SRAM card*2 - - - - - -
Q00UCPU Flash card *2 - - - - - -
Q01UCPU Standard RAM 7.3 µs 13.8 µs 116.5 µs 124.2 µs 1106.5 µs 1114.2 µs
BMOV SRAM card*2 - - - - - -
Flash card *2 - - - - - -
Standard RAM 9.4 µs 31.3 µs 118.5 µs 141.3 µs 1108.5 µs 1131.3 µs
RBMOV SRAM card 9.4 µs 31.4 µs 178.5 µs 201.3 µs 1708.5 µs 1731.3 µs
Flash card *1 9.4 µs 32.1 µs 278.5 µs 301.3 µs 2708.5 µs 2731.3 µs
Q02UCPU
Standard RAM 5.0 µs 11.6 µs 114.5 µs 122.3 µs 1104.5 µs 1112.3 µs
BMOV SRAM card 5.1 µs 11.7 µs 174.5 µs 182.3 µs 1704.5 µs 1712.3 µs
Flash card *1 5.0 µs 11.6 µs 274.5 µs 282.3 µs 2704.5 µs 2712.3 µs
Standard RAM 11.3 µs 16.8 µs 120.7 µs 127.1 µs 1110.7 µs 1117.1 µs
RBMOV SRAM card 11.2 µs 16.7 µs 180.7 µs 187.1 µs 1710.7 µs 1717.1 µs
Flash card *1 11.3 µs 16.8 µs 280.7 µs 287.1 µs 2710.7 µs 2717.1 µs
Q03UD(E)CPU
Standard RAM 4.8 µs 6.6 µs 114.7 µs 117.1 µs 1104.7 µs 1107.1 µs
BMOV SRAM card 4.8 µs 6.6 µs 174.7 µs 177.1 µs 1704.7 µs 1707.1 µs
Flash card *1 4.8 µs 6.5 µs 274.7 µs 277.1 µs 2704.7 µs 2707.1 µs
Q04UD(E)HCPU Standard RAM 9.2 µs 15.1 µs 61.0 µs 68.6 µs 531.0 µs 538.6 µs
Q06UD(E)HCPU RBMOV SRAM card 9.4 µs 15.6 µs 165.0 µs 172.6 µs 1576.0 µs 1583.6 µs
Q10UD(E)HCPU Flash card *1 9.4 µs 15.7 µs 260.0 µs 267.6 µs 2526.0 µs 2533.6 µs
Q13UD(E)HCPU Standard RAM 4.1 µs 5.6 µs 56.0 µs 58.6 µs 526.0 µs 528.6 µs
Q20UD(E)HCPU SRAM card 4.5 µs 6.1 µs 160.0 µs 162.6 µs 1571.0 µs 1573.6 µs
Q26UD(E)HCPU BMOV
Q50UDEHCPU Flash card *1 4.3 µs 6.2 µs 255.0 µs 257.6 µs 2521.0 µs 2523.6 µs
Q100UDEHCPU
Standard RAM 3.7 µs 21.0 µs 80.6 µs 89.3 µs 822.2 µs 831.4 µs
RBMOV Extended SRAM
3.7 µs 21.0 µs 102.6 µs 118.1 µs 1056.4 µs 1072.0 µs
cassette
Q03UDVCPU
Standard RAM 1.9 µs 7.9 µs 79.5 µs 82.0 µs 820.6 µs 823.1 µs
BMOV Extended SRAM
1.9 µs 7.9 µs 102.6 µs 107.9 µs 1055.5 µs 1057.5 µs
cassette

678
 RBMOV, RBMOVP

Target memory 1 word 1000 words 10000 words

CPU Instruction where file register
Min. Max. Min. Max. Min. Max.
is stored
Standard RAM 3.7 µs 21.0 µs 42.1 µs 57.7 µs 413.0 µs 428.6 µs 1
Q04UDVCPU, RBMOV Extended SRAM
3.7 µs 21.0 µs 102.6 µs 118.1 µs 1056.4 µs 1072.0 µs
Q06UDVCPU, cassette
Q13UDVCPU, Standard RAM 1.9 µs 7.9 µs 41.0 µs 47.1 µs 411.6 µs 417.7 µs 2
Q26UDVCPU BMOV Extended SRAM
1.9 µs 7.9 µs 102.6 µs 107.9 µs 1055.4 µs 1060.9 µs
cassette
*1:
*2:
When file registers are stored in the Flash card, no processing is performed for transfer from internal devices to file registers.
Unusable for the Q00UCPU and Q01UCPU.
3
(2) Transfer from file registers to file registers
Target memory 1 word 1000 words 10000 words
CPU Instruction where file register
Min. Max. Min. Max. Min. Max.
4
is stored
Standard RAM 20.0 µs 91.0 µs 775.0 µs
QnHCPU RBMOV
QnPHCPU
SRAM card 22.5 µs 545.0 µs 5300.0 µs 4
Standard RAM 7.5 µs 77.0 µs 720.0 µs
QnPRHCPU BMOV
SRAM card 8.5 µs 692.0 µs 7050.0 µs
Standard RAM 45.5 µs 215.0 µs 1850.0 µs
RBMOV
SRAM card 50.0 µs 870.0 µs 8350.0 µs 6
QnCPU
Standard RAM 17.5 µs 179.0 µs 1700.0 µs
BMOV
SRAM card 18.5 µs 839.0 µs 8600.0 µs

RBMOV
Standard RAM 12.6 µs 35.3 µs 232.5 µs 256.1 µs 2211.5 µs 2235.1 µs 7
Q00UCPU SRAM card*1 - - - - - -
Q01UCPU Standard RAM 7.7 µs 14.2 µs 227.5 µs 234.2 µs 2206.5 µs 2214.2 µs
BMOV
SRAM card*1
Standard RAM
-
9.6 µs
-
31.5 µs
-
228.5 µs
-
252.3 µs
-
2208.5 µs 2231.3 µs
-
8
RBMOV
SRAM card 9.6 µs 31.5 µs 378.5 µs 401.3 µs 3708.5 µs 3731.3 µs
Q02UCPU
Standard RAM 5.2 µs 11.8 µs 224.5 µs 232.3 µs 2204.5 µs 2212.3 µs
BMOV
SRAM card 5.2 µs 11.8 µs 374.5 µs 382.3 µs 3704.5 µs 3712.3 µs
Standard RAM 11.2 µs 16.7 µs 230.7 µs 237.1 µs 2210.7 µs 2217.1 µs

7.18.19 RBMOV, RBMOVP

7.18 Other instructions
RBMOV
SRAM card 11.6 µs 16.7 µs 380.7 µs 387.1 µs 3710.7 µs 3717.1 µs
Q03UD(E)CPU
Standard RAM 4.9 µs 6.7 µs 224.7 µs 227.1 µs 2204.7 µs 2207.1 µs
BMOV
SRAM card 5.2 µs 6.7 µs 374.7 µs 377.1 µs 3704.7 µs 3707.1 µs
Q04UD(E)HCPU Standard RAM 9.3 µs 15.5 µs 118.0 µs 124.6 µs 1102.0 µs 1107.6 µs
RBMOV
Q06UD(E)HCPU SRAM card 9.7 µs 15.5 µs 365.0 µs 371.6 µs 3571.0 µs 3578.6 µs
Q10UD(E)HCPU Standard RAM 4.3 µs 6.2 µs 113.0 µs 115.6 µs 1096.0 µs 1098.6 µs
Q13UD(E)HCPU
Q20UD(E)HCPU
BMOV
Q26UD(E)HCPU SRAM card 4.5 µs 6.1 µs 360.0 µs 362.6 µs 3566.0 µs 3568.6 µs
Q50UDEHCPU
Q100UDEHCPU
Standard RAM 3.7 µs 20.7 µs 162.0 µs 171.2 µs 1637.7 µs 1646.4 µs
RBMOV Extended SRAM
3.7 µs 20.7 µs 216.7 µs 232.1 µs 2197.4 µs 2212.5 µs
cassette
Q03UDVCPU
Standard RAM 1.9 µs 8.0 µs 161.1 µs 163.7 µs 1636.2 µs 1638.8 µs
BMOV Extended SRAM
1.9 µs 8.3 µs 216.4 µs 221.7 µs 2197.4 µs 2201.7 µs
cassette
Standard RAM 3.5 µs 20.7 µs 84.6 µs 99.5 µs 836.3 µs 851.7 µs
Q04UDVCPU, RBMOV Extended SRAM
3.6 µs 20.7 µs 216.7 µs 232.1 µs 2197.4 µs 2212.5 µs
Q06UDVCPU, cassette
Q13UDVCPU, Standard RAM 1.8 µs 8.0 µs 83.1 µs 89.0 µs 835.0 µs 840.9 µs
Q26UDVCPU BMOV Extended SRAM
1.8 µs 8.3 µs 216.4 µs 221.7 µs 2197.4 µs 2201.7 µs
cassette

*1: Unusable for the Q00UCPU and Q01UCPU.

679
 UMSG

7.18.20 UMSG User Message

Ver.
High
Basic performance Process Redundant Universal LCPU

7.18.20 UMSG • Built-in Ethernet port LCPU: Supported

• L02SCPU and L02SCPU-P cannot be used.

Command
UMSG UMSG S

S : String to display on display unit, or lead number (string) of device storing string to display
Internal Devices J \ Constants
Setting Indirect
R, ZR U \G Zn Real Other
Data Bit Word Specification Bit Word K, H
String

S –– –– *1 ––

*1: Only strings can be used

Function
(1) The string data specified by S is displayed as a user message in the display unit.
The string specified directly by S (surrounded by double quotation marks (")) or the string from the device number
specified by S until the device number storing "00H" is displayed.

b15 to b8 b7 to b0
S 2nd char 1st char
S +1 4th char 3rd char User message
S +2 6th char 5th char Process A complete.
S +3 8th char 7th char
S +4 10th char 9th char
Run UMSG
instruction Message appears
00H on display unit.

Indicates end of string.

(2) Strings of up to 128 single-byte characters can be displayed in the display unit.
(3) The user message is displayed when the UMSG instruction command is rising.
If the string is changed while the command is on, then the modified user message will appear in the display unit.
(4) The string specified by the UMSG instruction is displayed upon END processing. If two or more UMSG instructions are
executed, then the last UMSG instruction executed before the END is valid. If two or more programs are running, then
the last UMSG instruction to be executed is valid.
(5) This instruction is not processed if it is run when no display unit is mounted.
(6) If the "ESC" key on the display unit is pressed while a user message is being displayed, the displayed message will
disappear.
To display the message again, execute "User Message" from the menu screen on the display unit.
(7) If a NULL code (00H) is specified as the argument to this instruction, then any message currently being displayed will
disappear.
The procedure for specifying a NULL code (00H) in the instruction parameter is as follows.

Specifying a NULL code(00H)

See the MELSEC-L CPU Module User's Manual (Function Explanation, Program Fundamentals) for details about the display
unit.

680
 UMSG

Operation Error
1
(1) The following will cause a computation error, setting the error flag (SM0), and storing an error code in SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
4100 More than 128 characters are specified in the S string. –– –– –– –– ––
There is no NULL code (00H) within the range of the target device
4101
following the device number specified by S
–– –– –– –– ––
3

Program Example 4
(1) This program displays the string stored after D10 on the display unit, when X10 is set to "on".
[Ladder Mode] [List Mode]
Step Instruction Device
4

6
[Action]

b15 to b8 b7 to b0
7
D10 4CH (i) 69H (L)
D11 6EH (e) 65H (n)
D12 2DH (A) 41H (-)
User message 8
D13 20H (w) 77H ( ) Line-A Working
D14 6FH (r) 72H (o)
D15 6BH (i) 69H (k)
D16 6EH (g) 67H (n) Run UMSG
instruction
D17 00H

7.18.20 UMSG
7.18 Other instructions
(2) This program displays "Line-A Working" on the display unit when M0 is set to "on".
[Ladder Mode] [List Mode]
Step Instruction Device
"Line-A Working"
"Line-A Working"

[Action]

b15 to b8 b7 to b0
60H 82H
89H 83H
"Line-A Working"

43H 83H User message

93H 83H Line-A Working
40H 81H
5EH 89H
5DH 93H Run UMSG
instruction
86H 92H
0000 H

681
 UMSG

(3) This program displays "Line-B stop" on the display unit when X10 is set to "on", and clears the message when X10 is set
to "off".
[Ladder Mode] [List Mode]

"Line-B stop" Step Instruction Device

"Line-B stop"

[Action]

X10 set to "on" X10 set to "off"

User message
Line-B stop

682
 S.ZCOM, SP.ZCOM

CHAPTER 8 INSTRUCTIONS FOR DATA LINK

1
8.1 Network refresh instructions
2
Remark
In this chapter, instruction names are abbreviated as follows if not specified particularly. 3
• S(P).ZCOM ZCOM
• S(P).RTWRITE RTWRITE
• S(P).RTREAD RTREAD
4
8.1.1 S.ZCOM, SP.ZCOM Refresh for the designated module

8.1.1 S.ZCOM, SP.ZCOM Basic High

performance Process Redundant Universal LCPU
6
Command
S.ZCOM
6
S.ZCOM Jn

Command
SP.ZCOM SP.ZCOM Jn

S.ZCOM
Command
S.ZCOM Un
7
Command
SP.ZCOM SP.ZCOM Un
8
Jn : Network No. of host station (BIN 16 bits)
Un : Head I/O number of host station network module (BIN 16 bits)
Setting Internal Devices J \
R, ZR U \G Zn Constants Other
Data Bit Word Bit Word

8.1.1
8.1 Network refresh instructions
–– ––
The ZCOM instruction is used to perform refresh at any timing during execution of a sequence program.

S.ZCOM, SP.ZCOM
The targets of refresh performed by the ZCOM instruction are indicated below.
• Refresh of CC-Link IE Controller Network (when refresh parameters are set) (QCPU only)
• Refresh of CC-Link IE Field Network (when refresh parameters are set)
(Universal model QCPU whose serial number (first five digits) is "12012" or later and LCPU whose serial number (first five
digits) is "13012" or later only)
• Refresh of MELSECNET/H (when refresh parameters are set) (QCPU only)
• Auto refresh of CC-Link (when refresh device is set)
• Auto refresh of intelligent function module (when auto refresh is set)

Function
(1) When the ZCOM instruction is executed, the CPU module temporarily suspends processing of the sequence program
and conducts refresh processing of the network modules designated by Jn/Un. (For LCPU whose serial number (first five
digits) is "13011" or earlier, the designation by Jn cannot be made.)
Execution of ZCOM Execution of ZCOM Execution of ZCOM
instruction instruction instruction
0 END END

Refresh Refresh Refresh Refresh Refresh

processing processing processing processing processing

683
 S.ZCOM, SP.ZCOM

(2) The ZCOM instruction does not perform the following processing.
(a) Communication processing between CPU module and programming tool
(b) Monitor processing of other station
(c) Read processing of buffer memory of other intelligent function module by serial communication module.
(d) Low-speed cyclic data transmission of MELSECNET/H
(3) CC-Link IE Controller Network and MELSECNET/H (PLC to PLC network)
(a) When the scan time for the sequence program of host station is longer than the scan time for the other station, the
ZCOM instruction is used to ensure the data reception from the other station.
(1) Example of data communications when the ZCOM instruction is not used

Control station 0 END 0 END 0 END

program

Link scan

Normal station 0 END 0 END 0

program

(2) Example of data communications when the ZCOM instruction is used

Control station 0 END 0 END 0 END

program

Link scan

Normal station 0 END 0 END 0

program
ZCOM ZCOM ZCOM

For details on the transmission delay time on CC-Link IE Controller Network and MELSECNET/H (PLC to PLC
network), refer to the manuals below:
• CC-Link IE Controller Network Reference Manual
• Q Corresponding MELSECNET/H Network System Reference Manual (PLC to PLC network)
(b) When the link scan time is longer than the sequence program scan time, data communications will not be faster
even if the ZCOM instruction is used.
END

Sequence program 0 ZCOM END 0 ZCOM END 0 ZCOM 0 ZCOM END

Link scan

684
 S.ZCOM, SP.ZCOM

(4) MELSECNET/H (remote I/O network)

The link refresh of the remote master station is performed by the "END processing" of the CPU module.
Since link scan is performed at completion of link refresh, link scan 'synchronizes' with the program of the CPU module. 1
When the ZCOM instruction is used at the remote master station, link refresh is performed at the point of ZCOM
instruction execution, and link scan is performed at completion of link refresh.
Hence, use of the ZCOM instruction at the remote master station speeds up send/receive processing to/from the remote 2
I/O station.
(1) When the ZCOM instruction is not used

Remote master 0 0
3
0 END 0 END END
station program
Link refresh

Link scan 4
Link refresh
Remote I/O station
network refresh
I/O refresh 6
I/O module
Auto refresh
Intelligent
function module
6
(2) When the ZCOM instruction is used
ZCOM ZCOM ZCOM 7
Remote master 0 END 0 END END 0
0
station program
Link refresh
8
Link scan
Link refresh

Remote I/O station

network refresh
I/O refresh

8.1.1
8.1 Network refresh instructions
I/O module
Auto refresh

S.ZCOM, SP.ZCOM
Intelligent
function module

For details on the transmission delay time on MELSECNET/H (remote I/O network), refer to the manual below:
• Q Corresponding MELSECNET/H Network System Reference Manual (Remote I/O network)
(5) The ZCOM instruction can be used as many times as desired in sequence programs.
However, note that each execution of a refresh operation will lengthen the sequence program scan time by the amount of
time required for the refresh operation.
(6) Designating "Un" in the argument enables the target designation of the intelligent function as well as the network
modules.
In this case, the auto refresh is performed for the buffer memory of the intelligent function modules. (It replaces the
FROM/TO instructions.)
(7) Only with the Universal model QCPU and LCPU, interruption of processing is enabled during the execution of the ZCOM
instruction. However, when refresh data are used in an interrupted program, the data can split.

1. The ZCOM instruction cannot be used in a fixed cycle execution type program or interrupt program.
2. The Redundant CPU has restrictions on use of the ZCOM instruction.
Refer to the manual below for details.
• QnPRHCPU User's Manual (Redundant System)

685
 S.ZCOM, SP.ZCOM

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The module specified with the head I/O number is not a network
2111 ––
module or intelligent function module.
The specified network number is not connected to the host station. *1

4102 The module specified with the head I/O number is not a network
–– –– –– ––
module or intelligent function module.
*1: This error applies to modules whose first five digits of the serial number is "13012" or later.

To perform only communication with external devices, use the COM instruction (refer to Page 419, Section 7.6.9 and Page
421, Section 7.6.10).

Program Example
(1) The following program conducts a link refresh for the network module of network No. 6 while X0 is ON.
[Ladder Mode] [List Mode]

Step Instruction Device

(2) The following program conducts a link refresh for the network module mounted to the position whose head I/O number is
a X/Y30 to X/Y4F while X0 is ON.
[Ladder Mode] [List Mode]
Step Instruction Device

686
 S.RTREAD, SP.RTREAD

8.2 Reading/Writing Routing Information

1
8.2.1 S.RTREAD, SP.RTREADReading routing information

Ver.

8.2.1 S.RTREAD, SP.RTREAD

Basic High
performance Process Redundant Universal LCPU 2
• LCPU: The serial number (first five digits) is "13012" or later.

S.RTREAD
Command
S.RTREAD n D 3
Command
SP.RTREAD n D
SP.RTREAD
4
n : Transfer destination network No. (1 to 239) (BIN 16 bits)
D : Head number of the devices that stores the read data (Device name)

Setting Internal Devices

R, ZR
J \
U \G Zn
Constants
Other
6
Data Bit Word Bit Word K, H
n –– ––
D –– –– –– ––
6
Function
7
(1) Reads data from transfer destination network number specified by n, using routing information set by the routing
parameters, and stores it into the area starting from D .
(2) If no data for the transfer destination network number specified by n is set at the routing parameters, stores 0 into the 8
area starting from D .
(3) The contents of the data stored in the area starting from D is as indicated below.
(Individual data ranges)
D +0 Relay network number

8.2.1
8.2 Reading/Writing Routing Information
(1 to 239)
+1 Relay station number See the table below.
+2 Dummy

S.RTREAD, SP.RTREAD
[Specification range of relay station number]
Network Type Specification Range
MELSECNET/H 1 to 64
CC-Link IE Controller Network 1 to 120
• Master station: Fixed at 125. (The fixed value is stored.)
CC-Link IE Field Network
• Local station: 1 to 120 (A station number is stored.)

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
4004 When the device which cannot be used the argument is specified ––
4100 The value in n is the value other than 1 to 239. ––
The device specified for n and D exceeds the range of the
4101 –– –– –– ––
corresponding device.

687
 S.RTWRITE, SP.RTWRITE

Program Example
(1) The following program reads the routing information for the network number specified by D0 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation] [Content of routing parameter setting]

D0 1 Transfer Relay network Relay station
destination
network number number number
D1 10 1 10 3
D2 3 2 10 2
D3 Dummy 3 10 1

8.2.2 S.RTWRITE, Registering routing information

SP.RTWRITE

Ver.

8.2.2
High
Basic Process Redundant Universal LCPU
S.RTWRITE, SP.RTWRITE performance
• LCPU: The serial number (first five digits) is "13012" or later.

Command
S.RTWRITE S.RTWRITE n S

Command
SP.RTWRITE n S
SP.RTWRITE

n : Transfer destination network No. (1 to 239) (BIN 16 bits)

S : Head number of the devices where the data to be written is stored (Device name)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n –– ––
S –– –– –– ––

Function
(1) Registers routing information of S or later in the area for the transfer destination network number specified by n in the
routing parameters.
CPU module Registration Number
• High Performance model QCPU
• Process CPU
• Redundant CPU
• Universal model QCPU whose serial number (first five digits) is "14111" or
Up to 64 modules
earlier
• High-speed Universal model QCPU whose serial number (first five digits)
is "15042" or earlier
• LCPU
• The Universal model QCPU whose serial number (first five digits) is
"14112" or later, (except the High-speed Universal model QCPU)
Up to 238 modules
• High-speed Universal model QCPU whose serial number (first five digits)
is "15043" or later

688
 S.RTWRITE, SP.RTWRITE

(2) The following shows the contents of data to be set at S or later.

(Individual data ranges)
S +0 Relay network number 1
+1 Relay station number See the table below.
+2 Dummy
[Specification range of relay station number] 2
Network Type Specification Range
MELSECNET/H 1 to 64
CC-Link IE Controller Network 1 to 120

CC-Link IE Field Network

• Master station: Fixed at 125. 3
• Local station: 1 to 120

(3) If data for the transfer destination network number specified by n is set in the routing parameters, it is used to update the
data in the area starting from S . 4
(4) If data in both S + 0 and S + 1 are 0, data for the transfer destination network number specified by n are deleted from
the routing parameters.
6
Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into 6
SD0.
Q00J/
Error
code
Error details Q00/ QnH QnPH QnPRH QnU LCPU 7
Q01
4004 When the device which cannot be used the argument is specified ––
The value in n is the value other than 1 to 239.
The data of S or later exceeds each setting range.
8
If the number of routing data registered in the routing parameter of the
4100 network parameters plus the number of routing data registered using ––
the RTWRITE instruction exceeds the maximum registration number
If deleting a transfer destination network number, which is not

8.2.2
8.2 Reading/Writing Routing Information
registered in the routing parameter, is specified
The device specified for n and D exceeds the range of the
4101 –– –– –– ––

S.RTWRITE, SP.RTWRITE
corresponding device.

Program Example
(1) The following program writes the routing information specified by D1 to D3 to the network module of the network number
specified by D0 when X0 is turned ON.
[Ladder Mode] [List Mode]

Step Instruction Device

[Operation] [Content of routing parameter setting]

D0 1 Transfer Relay network Relay station

destination number number
network number
D1 20 1 20 1
D2 1 2 10 2
D3 Dummy 3 10 1

689
 S.REFDVWRB, SP.REFDVWRB

8.3 Refresh Device Write/Read Instruction

8.3.1 S.REFDVWRB, Refresh device write (in 1-bit units)

SP.REFDVWRB

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU
• QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five
digits) is "14072" or later
• Built-in Ethernet port LCPU: Supported

8.3.1 S.REFDVWRB, SP.REFDVWRB • Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, QnUDVCPU,

L02SCPU, and L02SCPU-P cannot be used.

Command
S.REFDVWRB S.REFDVWRB n1 S1 S2 n2 D1

Command
SP.REFDVWRB SP.REFDVWRB n1 S1 S2 n2 D1

n1 : Start I/O number (0H to FEH) (BIN 16-bit)*1 of the master station controlling the station assigned the refresh device which writes data
S1 : Start number of the device stored control data (device name)
S2 : Start number of the device stored write data to the refresh device assigned the device specified in S1 +0 and S1 +1 (device name)
n2 : Number of write points (1 to 2147483647) (BIN 32-bit)
D1 : Start number of the bit device which turns on for 1 scan by the instruction completion. D1 +1 also turns on at the error completion (bit).
Setting Internal Devices Indirect J \ Constants
R, ZR U \G Zn Other
Data Bit Word specification Bit Word K, H
n1 –– –– ––
S1 –– –– –– ––
*2 –– –– –– –– –– ––
S2

n2 –– –– ––
*2 –– –– –– –– –– ––
D1

*1: The first 3 digits of the hexadecimal 4 digits which represent the start I/O number.
*2: Local devices and the devices designated for individual programs cannot be used.

Function
(1) The contents of the data stored in the area starting from are as indicated below.
Device Item Setting contents Setting range
Station number for the station assigned the refresh device which writes data.
S1 +0 Station number When the link special relay (SB) is specified as type of S1 +1, the setting is 1 to 120
disabled.
Type of the refresh device which writes data
• 1: Remote input (RX)
S1 +1 Type 1 to 3
• 2: Remote output (RY)
• 3: Link special relay (SB)
S1 +2 Offset from the head of the refresh device assigned the device specified in
Offset 0 to 2147483647
S1 +3 S1 +0 and S1 +1

(2) Instruction execution possibility of an execution type for each program.

(a) Enabled: Initial program and scan execution type program
(b) Disabled: Fixed scan execution type program and interrupt program
(3) To write data to a refresh device, the data reflection to the station number specified by the instruction is executed at the
timing for the auto refresh.

690
 S.REFDVWRB, SP.REFDVWRB

(4) Number of points specified in n2 is written from the device specified in S2 to the offset specified in S1 +2 of the refresh
device assigned for the device specified in S1 +1 of the target station specified in n1 and S1 +0.
1
[Structure]
Master Specified
CPU Station
2
station: station:
.....
module Station No. 1 Station
No. 0 No. 4

Start I/O No.: n1=0 Station number:

Type: S1 +1=2 CC-Link master station:
S1 +0=4 3
Station No. 0 Remote device station: Remote device station:
CPU module Start I/O No.: 0000H Station No. 1 Station No. 4
Refresh device
Y1000
Y100F to Y1000
Remote output (RY)
RY0F to RY00
Remote output (RY)
RY0F to RY00
4
Y101F to Y1010 RY1F to RY10 RY1F to RY10
Y102F to Y1020 RY2F to RY20
Y103F to Y1030
Y104F to Y1040
RY3F to RY30
RY4F to RY40
6
.....
Y105F to Y1050 RY5F to RY50 Remote output (RY)
Y106F to Y1060 RY6F to RY60 RY0F to RY00

6
Y107F to Y1070 RY7F to RY70 RY1F to RY10
Y108F to Y1080 RY8F to RY80
Y109F to Y1090 RY9F to RY90
Y10AF to Y10A0 RYAF to RYA0
Y10BF to Y10B0 RYBF to RYB0

Refresh device areas assigned for station No. 4

7
At the above configuration, number of points specified in n2 is written from the device specified in S2 to the offset (Y1078)
specified in S1 +2 of the device assigned for the station number 4.
8
Start number of the device
where target data is stored:
S2 =M1240 Refresh device areas
assigned for the remote

8.3.1
8.3 Refresh Device Write/Read Instruction
9 8 7 6 5 4 3 2 1 0 M1240 Offset reference point
output (RY) of station No. 4 (start point: 0)
Number of
write points: Y1060
F E D C B A 9 8 7 6 5 4 3 2 1 0

S.REFDVWRB, SP.REFDVWRB
n2=4

F E D C B A 9 8 7 6 5 4 3 2 1 0
Y1070

Y1078 is the 24th bit from the offset reference

point. Specify the offset in hexadecimal, 18H.
S1 +2=18H

When a refresh range per station is assigned in transfer settings, specify number of write points so that the range written
data from the specified offset is within the range assigned in the same transfer setting. An error occurs if the number of
write points over the range assigned in each transfer setting is specified.

(5) The station type which can and cannot specify with the start I/O number is as follows.
Specification
Station type
possibility
CC-Link master station, CC-Link master station (compatible with redundant function), CC-Link IE Field Network
Enabled
master station
CC-Link local station, CC-Link standby master station, CC-Link IE Field Network local station, CC-Link IE Field
Disabled
Network submaster station

(6) Because the available range of the station number is 1 to 120, the station number for the master station in n1 cannot be
specified to S1 +0. If the station number is specified. the "OPERATION ERROR" (error code: 4102) occurs.

691
 S.REFDVWRB, SP.REFDVWRB

(7) SM739 (Refresh device write/read instruction in execution flag) turns on during the instruction execution. When SM739 is
on, the following instructions cannot be executed.
• S(P).REFDVWRB
• S(P).REFDVWRW
• S(P).REFDVRDB
• S(P).REFDVRDW
If these instructions are executed, no processing is performed. When an error is detected at the instruction execution
(before SM739 turns ON), the completion device ( D1 +0), the completion device ( D1 +1), and SM739 do not turn on.
(8) The instruction completion can be checked in the completion device ( D1 +0 and D1 +1).
(a) Completion device ( D1 +0)
The device turns on at the END processing in a scan where the instruction is completed and turns off at the next
END processing.
(b) Completion device ( D1 +1)
The device turns on or off by the status when the instruction is completed.
• Normal completion: No change from off
• Error completion: The device turns on at the END processing in a scan where the instruction is completed and
turns off at the next END processing.

END END END

Sequence program Scan Scan Scan
processing processing processing

S(P).REFDVWRB instruction Instruction execution

Refresh device write/read

instruction in execution flag
(SM739)

Completion device

Completion device + 1 Error completion

Writing device data

(9) A module set parameters by the dedicated instruction and a CC-Link module operating by the automatic CC-Link startup
cannot be specified with the instruction.
(10) The write source (points in n2 from S2 ) and write destination (points in n2 from a device specified in control data) are
overlapped, data can be written. Write data starting from S2 when data are written to the smaller device number. Write
data starting from S2 +((n2)-1) when data are written to the larger device number.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the instruction is used with the CPU module whose serial number
4002 (first five digits) is "14071" or earlier –– –– –– ––
When the module cannot be specified the start I/O number in n1
4004 When the device which cannot be specified is specified –– –– –– ––
When the specified device exceeds the range of the number of device
points
4101 When the start I/O number in n1 is out of the specified range –– –– –– ––
When the device type number in S1 +1 is out of the specified range
When the write offset in S1 +2 is out of the specified range

692
 S.REFDVWRB, SP.REFDVWRB

Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the number of write points in n2 is out of the specified range
1
4101 When the number of write points in n2 exceeds the range of the number –– –– –– ––
of device points
When the station number in S1 +0 is out of the specified range 2
4102 When the station number in S1 +0 does not exist –– –– –– ––
When the station number in S1 +0 is the master station specified in n1
When the start I/O number in n1 is the station type which cannot be 3
specified
4150 –– –– –– ––
When the start I/O number in n1 does not exist in the network
parameter
When the device in S1 +1 of the station number specified in S1 +0 is not
4
assigned the refresh device
When the write offset in +2 exceeds the refresh device range
6
S1
4151 –– –– –– ––
assigned for the device in S1 +1 of the station number specified in S1 +0
When the number of write points in n2 exceeds the assignment range of
the setting for one transfer from the write offset in S1 +2
6
Program Example
(1) The following program writes 16 device values in B100 to the head of the refresh device (offset: 0) assigned for the 7
remote output (RY) in the remote I/O station on the station number 32 controlled by the CC-Link master station of the
start I/O number 0080H when X1C is turned on.
[Ladder Mode] [List Mode] 8
Step Instruction Device

8.3.1
8.3 Refresh Device Write/Read Instruction
S.REFDVWRB, SP.REFDVWRB

Caution
(1) Do not execute the instruction in an interrupt program. If the instruction is executed, no processing is performed. In
addition, the completion device ( D1 +0), the completion device ( D1 +1), and SM739 do not turn on. If the instruction is
executed in a fixed scan execution type program, they also do not turn on.
(2) When the instruction is executed, do not rewrite the device data in S2 until the completion device turns on.

693
 S.REFDVWRW, SP.REFDVWRW

8.3.2 S.REFDVWRW, Refresh device write (in 16-bit units)

SP.REFDVWRW

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU
• QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five
digits) is "14072" or later
• Built-in Ethernet port LCPU: Supported

8.3.2 S.REFDVWRW, SP.REFDVWRW • Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, QnUDVCPU,

L02SCPU, and L02SCPU-P cannot be used.

Command
S.REFDVWRW S.REFDVWRW n1 S1 S2 n2 D1

Command
SP.REFDVWRW SP.REFDVWRW n1 S1 S2 n2 D1

n1 : Start I/O number (0H to FEH) (BIN 16-bit)*1 of the master station controlling the station assigned the refresh device which writes data
S1 : Start number of the device stored control data (device name)
S2 : Start number of the device stored write data to the refresh device assigned the device specified in S1 +0 and S1 +1 (device name)
n2 : Number of write points (1 to 2147483647) (BIN 32-bit)
D1 : Start number of the bit device which turns on for 1 scan by the instruction completion. D1 +1 also turns on at the error completion (bit).
Setting Internal Devices Indirect J \ Constants
R, ZR U \G Zn Other
Data Bit Word specification Bit Word K, H
n1 –– –– ––
S1 –– –– –– ––
–– *2 *2 *2 –– –– ––
S2

n2 –– –– ––
*2 –– –– –– –– –– ––
D1

*1: The first 3 digits of the hexadecimal 4 digits which represent the start I/O number.
*2: Local devices and the devices designated for individual programs cannot be used.

Function
(1) The contents of the data stored in the area starting from S1 are as indicated below.
Device Item Setting contents Setting range
Station number for the station assigned the refresh device which writes data.
S1 +0 Station number When the link special register (SW) is specified as type of S1 +1, the setting 1 to 120
is disabled.
Type of the refresh device which writes data
• 1: Remote register (RWr)
S1 +1 Type 1 to 3
• 2: Remote register (RWw)
• 3: Link special register (SW)
S1 +2 Offset from the head of the refresh device assigned the device specified in
Offset 0 to 2147483647
S1 +3 S1 +0 and S1 +1

(2) Instruction execution possibility of an execution type for each program.

(a) Enabled: Initial program and scan execution type program
(b) Disabled: Fixed scan execution type program and interrupt program
(3) To write data to a refresh device, the data reflection to the station number specified by the instruction is executed at the
timing for the auto refresh.

694
 S.REFDVWRW, SP.REFDVWRW

(4) Number of points specified in n2 is written from the device specified in S2 to the offset specified in S1 +2 of the refresh
device assigned for the device specified in S1 +1 of the target station specified in n1 and S1 +0.
1
[Structure]
Master Specified

2
CPU station: Station station:
.....
module Station No. 1 Station
No. 0 No. 4

Start I/O No.: n1=0 Station number:

Type: S1 +1=2 CC-Link master station:
S1 +0=4 3
Station No. 0 Remote device station: Remote device station:
CPU module Start I/O No.: 0000H Station No. 1 Station No. 4
Refresh device
W1000 Remote register (RWw) Remote register (RWw) 4
W1000 RWw00 RWw00
to to to
W100F RWw0F RWw0F
W1010
to
RWw10
to
6
.....
W105F RWw5F Remote register (RWw)
W1060 RWw60 RWw00
to
W106F
to
RWw6F
to
RWw0F 6
W1070 RWw70
to to
W10BF RWwBF
7
Refresh device areas assigned for station No. 4

At the above configuration, number of points specified in n2 is written from the device specified in S2 to the offset
(W1063) specified in S1 +2 of the device assigned for the station number 4.
8
Start number of the device
where target data is stored:
S2 =D1240 Refresh device areas
assigned for the remote

8.3.2
8.3 Refresh Device Write/Read Instruction
D1240 register (RWw) of station No. 4
D1241 Offset reference point
W1060
D1242 Write area size:
W1061 (start point: 0)

S.REFDVWRW, SP.REFDVWRW
D1243 n2=4
W1062
W1063 W1063 is the 3rd word from
W1064 the offset reference point.
W1065 Specify the offset in
W1066 hexadecimal, 3H.
W1067 S1 +2=3H
W1068
W1069
to
W106F

When a refresh range per station is assigned in transfer settings, specify number of write points so that the range written
data from the specified offset is within the range assigned in the same transfer setting. An error occurs if the number of
write points over the range assigned in each transfer setting is specified.

(5) The station type which can and cannot specify with the start I/O number is as follows.
Specification
Station type
possibility
CC-Link master station, CC-Link master station (compatible with redundant function), CC-Link IE Field Network
Enabled
master station
CC-Link local station, CC-Link standby master station, CC-Link IE Field Network local station, CC-Link IE Field
Disabled
Network submaster station

(6) Because the available range of the station number is 1 to 120, the station number for the master station in n1 cannot be
specified to S1 +0. If the station number is specified. the "OPERATION ERROR" (error code: 4102) occurs.

695
 S.REFDVWRW, SP.REFDVWRW

(7) SM739 (Refresh device write/read instruction in execution flag) turns on during the instruction execution. When SM739 is
on, the following instructions cannot be executed.
• S(P).REFDVWRB
• S(P).REFDVWRW
• S(P).REFDVRDB
• S(P).REFDVRDW
If these instructions are executed, no processing is performed. When an error is detected at the instruction execution
(before SM739 turns ON), the completion device ( D1 +0), the completion device ( D1 +1), and SM739 do not turn on.
(8) The instruction completion can be checked in the completion device ( D1 +0 and D1 +1).
(a) Completion device ( D1 +0)
The device turns on at the END processing in a scan where the instruction is completed and turns off at the next
END processing.
(b) Completion device ( D1 +1)
The device turns on or off by the status when the instruction is completed.
• Normal completion: No change from off
• Error completion: The device turns on at the END processing in a scan where the instruction is completed and
turns off at the next END processing.

END END END

Sequence program Scan Scan Scan
processing processing processing

S(P).REFDVWRW instruction Instruction execution

Refresh device write/read

instruction in execution flag
(SM739)

Completion device

Completion device + 1 Error completion

Writing device data

(9) A module set parameters by the dedicated instruction and a CC-Link module operating by the automatic CC-Link startup
cannot be specified with the instruction.
(10) The write source (points in n2 from S2 ) and write destination (points in n2 from a device specified in control data) are
overlapped, data can be written. Write data starting from S2 when data are written to the smaller device number. Write
data starting from S2 +((n2)-1) when data are written to the larger device number.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the instruction is used with the CPU module whose serial number
4002 (first five digits) is "14071" or earlier –– –– –– ––
When the module cannot be specified the start I/O number in n1
4004 When the device which cannot be specified is specified –– –– –– ––
When the specified device exceeds the range of the number of device
points
4101 When the start I/O number in n1 is out of the specified range –– –– –– ––
When the device type number in S1 +1 is out of the specified range
When the write offset in S1 +2 is out of the specified range

696
 S.REFDVWRW, SP.REFDVWRW

Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the number of write points in n2 is out of the specified range 1
4101 When the number of write points in n2 exceeds the range of the number –– –– –– ––
of device points
When the station number in S1 +0 is out of the specified range 2
4102 When the station number in S1 +0 does not exist –– –– –– ––
When the station number in S1 +0 is the master station specified in n1
When the start I/O number in n1 is the station type which cannot be 3
specified
4150 –– –– –– ––
When the start I/O number in n1 does not exist in the network
parameter
When the device in S1 +1 of the station number specified in S1 +0 is not
4
assigned the refresh device
When the write offset in S1 +2 exceeds the refresh device range
4151
assigned for the device in S1 +1 of the station number specified in S1 +0
–– –– –– ––
6
When the number of write points in n2 exceeds the assignment range of
the setting for one transfer from the write offset in S1 +2

6
Program Example
(1) The following program writes 16 device values in W100 to the head of the refresh device (offset: 0) assigned for the
remote register (RWw) in the remote device station on the station number 32 controlled by the CC-Link master station of
7
the start I/O number 0080H when X1C is turned on.

[Ladder mode] [List mode] 8

Step Instruction Device

8.3.2
8.3 Refresh Device Write/Read Instruction
S.REFDVWRW, SP.REFDVWRW

Caution
(1) Do not execute the instruction in an interrupt program. If the instruction is executed, no processing is performed. In
addition, the completion device ( D1 +0), the completion device ( D1 +1), and SM739 do not turn on. If the instruction is
executed in a fixed scan execution type program, they also do not turn on.
(2) When the instruction is executed, do not rewrite the device data in S2 until the completion device turns on.
(3) Specifying digit for the bit device can be used only when the following conditions (a) and (b) are met.
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR. (error code: 4004) will occur.

697
 S.REFDVRDB, SP.REFDVRDB

8.3.3 S.REFDVRDB, Refresh device read (in 1-bit units)

SP.REFDVRDB

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU
• QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five
digits) is "14072" or later
• Built-in Ethernet port LCPU: Supported

8.3.3 S.REFDVRDB, SP.REFDVRDB • Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, QnUDVCPU,

L02SCPU, and L02SCPU-P cannot be used.

Command
S.REFDVRDB S.REFDVRDB n1 S1 D1 n2 D2

Command
SP.REFDVRDB SP.REFDVRDB n1 S1 D1 n2 D2

n1 : Start I/O number (0H to FEH) (BIN 16-bit)*1 of the master station controlling the station assigned the refresh device which reads data
S1 : Start number of the device stored control data (device name)
D1 : Start number of the device stored read data from the refresh device assigned the device specified in S1 +0 and S1 +1 (device name)
n2 : Number of read points (1 to 2147483647) (BIN 32-bit)
D2 : Start number of the bit device which turns on for 1 scan by the instruction completion. D1 +1 also turns on at the error completion (bit)
Setting Internal Devices Indirect J \ Constants
R, ZR U \G Zn Other
Data Bit Word specification Bit Word K, H
n1 –– –– ––
S1 –– –– –– ––
D1
*2 –– –– –– –– –– ––
n2 –– –– ––
D2
*2 –– –– –– –– –– ––
*1: The first 3 digits of the hexadecimal 4 digits which represent the start I/O number.
*2: Local devices and the devices designated for individual programs cannot be used.

Function
(1) The contents of the data stored in the area starting from S1 are as indicated below.
Device Item Setting contents Setting range
Station number for the station assigned the refresh device which reads data.
S1 +0 Station number When the link special relay (SB) is specified as type of S1 +1, the setting is 1 to 120
disabled.
Type of the refresh device which reads data
• 1: Remote input (RX)
S1 +1 Type 1 to 3
• 2: Remote output (RY)
• 3: Link special relay (SB)
S1 +2 Offset from the head of the refresh device assigned the device specified in S1 +0
Offset 0 to 2147483647
S1 +3 and S1 +1

(2) Instruction execution possibility of an execution type for each program.

(a) Enabled: Initial program and scan execution type program
(b) Disabled: Fixed scan execution type program and interrupt program
(3) To read data from a refresh device, the data reflection to the station number specified by the instruction is executed at the
timing for the auto refresh.

698
 S.REFDVRDB, SP.REFDVRDB

(4) Number of points specified in n2 is read from the device specified in D1 to the offset specified in S1 +2 of the refresh
device assigned for the device specified in S1 +1 of the target station specified in n1 and S1 +0.
1
[Structure]
Master Specified
CPU station: Station station:
module Station
No. 0
No. 1
.....
Station
No. 4
2

Start I/O No.: n1=0 Station number:

Type: S1 +1=1 CC-Link master station: S1 +0=4 3
Station No. 0 Remote device station: Remote device station:
CPU module Start I/O No.: 0000H Station No. 1 Station No. 4
Refresh device
X1000
X100F to X1000
Remote input (RX)
RX0F to RX00
Remote input (RX)
RX0F to RX00
4
X101F to X1010 RX1F to RX10 RX1F to RX10
X102F to X1020 RX2F to RX20
X103F to X1030
X104F to X1040
RX3F to RX30
RX4F to RX40
.....
6
X105F to X1050 RX5F to RX50 Remote input (RX)
X106F to X1060 RX6F to RX60 RX0F to RX00

6
X107F to X1070 RX7F to RX70 RX1F to RX10
X108F to X1080 RX8F to RX80
X109F to X1090 RX9F to RX90
X10AF to X10A0 RXAF to RXA0
X10BF to X10B0 RXBF to RXB0

Refresh device areas assigned for station No. 4

7

At the above configuration, number of points specified in n2 is read starting from the offset (X1078) specified in
the device assigned for the station number 4, then the number of points is read to devices starting from the device
S1 +2 of
8
specified in D1 .

Start number of the device

where target data is stored:

8.3.3
8.3 Refresh Device Write/Read Instruction
D1 =M1240 Refresh device areas
M1240 assigned for the remote Offset reference point
9 8 7 6 5 4 3 2 1 0
output (RX) of station No. 4 (start point: 0)

S.REFDVRDB, SP.REFDVRDB
Number of
read points: X1060
F E D C B A 9 8 7 6 5 4 3 2 1 0
n2=4

F E D C B A 9 8 7 6 5 4 3 2 1 0
X1070

X1078 is the 24th bit from the offset reference

point. Specify the offset in hexadecimal, 18H.
S1 +2=18H

When a refresh range per station is assigned in transfer settings, specify number of read points so that the range read data
from the specified offset is within the range assigned in the same transfer setting. An error occurs if the number of read
points over the range assigned in each transfer setting is specified.

(5) The station type which can and cannot specify with the start I/O number is as follows.
Specification
Station type
possibility
CC-Link master station, CC-Link master station (compatible with redundant function), CC-Link IE Field Network
Enabled
master station
CC-Link local station, CC-Link standby master station, CC-Link IE Field Network local station, CC-Link IE Field
Disabled
Network submaster station

(6) Because the available range of the station number is 1 to 120, the station number for the master station in n1 cannot be
specified to S1 +0. If the station number is specified. the "OPERATION ERROR" (error code: 4102) occurs.

699
 S.REFDVRDB, SP.REFDVRDB

(7) SM739 (Refresh device write/read instruction in execution flag) turns on during the instruction execution. When SM739 is
on, the following instructions cannot be executed.
• S(P).REFDVWRB
• S(P).REFDVWRW
• S(P).REFDVRDB
• S(P).REFDVRDW
If these instructions are executed, no processing is performed. When an error is detected at the instruction execution
(before SM739 turns ON), the completion device ( D2 +0), the completion device ( D2 +1), and SM739 do not turn on.

(8) The instruction completion can be checked in the completion device ( D2 +0 and D2 +1).
(a) Completion device ( D2 +0)
The device turns on at the END processing in a scan where the instruction is completed and turns off at the next
END processing.
(b) Completion device ( D2 +1)
The device turns on or off by the status when the instruction is completed.
• Normal completion: No change from off
• Error completion: The device turns on at the END processing in a scan where the instruction is completed and
turns off at the next END processing.

END END END

Sequence program Scan Scan Scan
processing processing processing

S(P).REFDVRDB instruction Instruction execution

Refresh device write/read

instruction in execution flag
(SM739)

Completion device

Completion device + 1
Error completion

Reading
device data

(9) A module set parameters by the dedicated instruction and a CC-Link module operating by the automatic CC-Link startup
cannot be specified with the instruction.

(10) The read source (points in n2 from a device specified in control data) and read destination (points in n2 from D1 ) are
overlapped, data can be read. Read data starting from a device specified in control data when data are read to the
smaller device number. Read data starting from a device specified in control data + ((n2)-1) when data are read to the
larger device number.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the instruction is used with the CPU module whose serial number
4002 (first five digits) is "14071" or earlier –– –– –– ––
When the module cannot be specified the start I/O number in n1
4004 When the device which cannot be specified is specified –– –– –– ––
When the specified device exceeds the range of the number of device
points
4101 When the start I/O number in n1 is out of the specified range –– –– –– ––
When the device type number in S1 +1 is out of the specified range
When the read offset in S1 +2 is out of the specified range

700
 S.REFDVRDB, SP.REFDVRDB

Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the number of read points in n2 is out of the specified range 1
4101 When the number of read points in n2 exceeds the range of the number –– –– –– ––
of device points
When the station number in S1 +0 is out of the specified range 2
4102 When the station number in S1 +0 does not exist –– –– –– ––
When the station number in S1 +0 is the master station specified in n1
When the start I/O number in n1 is the station type which cannot be 3
specified
4150 –– –– –– ––
When the start I/O number in n1 does not exist in the network
parameter
4
When the device in S1 +1 of the station number specified in S1 +0 is not
assigned the refresh device
When the read offset in S1 +2 exceeds the refresh device range
4151
assigned for the device in S1 +1 of the station number specified in S1 +0
–– –– –– –– 6
When the number of read points in n2 exceeds the assignment range of
the setting for one transfer from the read offset in +2
6
S1

Program Example
(1) The following program reads 16 device values from the head of the refresh device (offset: 0) assigned for the remote 7
input (RX) in the remote I/O station on the station number 32 controlled by the CC-Link master station of the start I/O
number 0080H to B100 when X1C is turned on.
8
[Ladder mode] [List mode]

Step Instruction Device

8.3.3
8.3 Refresh Device Write/Read Instruction
S.REFDVRDB, SP.REFDVRDB

Caution
(1) Do not execute the instruction in an interrupt program. If the instruction is executed, no processing is performed. In
addition, the completion device ( D2 +0), the completion device ( D2 +1), and SM739 do not turn on. If the instruction is
executed in a fixed scan execution type program, they also do not turn on.

701
 S.REFDVRDW, SP.REFDVRDW

8.3.4 S.REFDVRDW, Refresh device read (in 16-bit units)

SP.REFDVRDW

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU
• QnUD(H)CPU, QnUDE(H)CPU: the serial number (first five
digits) is "14072" or later
• Built-in Ethernet port LCPU: Supported

8.3.4 S.REFDVRDW, SP.REFDVRDW • Q00UJCPU, Q00UCPU, Q01UCPU, Q02UCPU, QnUDVCPU,

L02SCPU, and L02SCPU-P cannot be used.

Command
S.REFDVRDW S.REFDVRDW n1 S1 D1 n2 D2

Command
SP.REFDVRDW SP.REFDVRDW n1 S1 D1 n2 D2

n1 : Start I/O number (0H to FEH) (BIN 16-bit)*1 of the master station controlling the station assigned the refresh device which reads data
S1 : Start number of the device stored control data (device name)
D1 : Start number of the device stored read data from the refresh device assigned the device specified in S1 +0 and S1 +1 (device name)
n2 : Number of read points (1 to 2147483647) (BIN 32-bit)
D2 : Start number of the bit device which turns on for 1 scan by the instruction completion. D2 +1 also turns on at the error completion (bit)
Setting Internal Devices Indirect J \ Constants
R, ZR U \G Zn Other
Data Bit Word specification Bit Word K, H
n1 –– –– ––
S1 –– –– –– ––
D1 –– *2 *2 *2 –– –– ––
n2 –– –– ––
D2
*2 –– –– –– –– –– ––
*1: The first 3 digits of the hexadecimal 4 digits which represent the start I/O number.
*2: Local devices and the devices designated for individual programs cannot be used.

Function
(1) The contents of the data stored in the area starting from S1 are as indicated below.
Device Item Setting contents Setting range
Station number for the station assigned the refresh device which reads data.
S1 +0 Station number When the link special register (SW) is specified as type of S1 +1, the setting 1 to 120
is disabled.
Type of the refresh device which reads data
• 1: Remote register (RWr)
S1 +1 Type 1 to 3
• 2: Remote register (RWw)
• 3: Link special register (SW)
S1 +2 Offset from the head of the refresh device assigned the device specified in
Offset 0 to 2147483647
S1 +3 S1 +0 and S1 +1

(2) Instruction execution possibility of an execution type for each program.

(a) Enabled: Initial program and scan execution type program
(b) Disabled: Fixed scan execution type program and interrupt program
(3) To read data from a refresh device, the data reflection to the station number specified by the instruction is executed at the
timing for the auto refresh.

702
 S.REFDVRDW, SP.REFDVRDW

(4) Number of points specified in n2 is read from the device specified in D1 to the offset specified in S1 +2 of the refresh
device assigned for the device specified in S1 +1 of the target station specified in n1 and S1 +0.
1
[Structure]
Master Specified
CPU station: Station station:
module Station
No. 0
No. 1
.....
Station
No. 4
2

Start I/O No.: n1=0 Station number:

Type: S1 +1=1 CC-Link master station: S1 +0=4 3
Station No. 0 Remote device station: Remote device station:
CPU module Start I/O No.: 0000H Station No. 1 Station No. 4
Refresh device
W1000
W1000
Remote register (RWr)
RWr00
Remote register (RWr)
RWr00
4
to to to
W100F RWr0F RWr0F
W1010
to
RWr10
to
.....
6
W105F RWr5F Remote register (RWr)
W1060 RWr60 RWr00
to to to
W106F RWr6F RWr0F 6
W1070 RWr70
to to
W10BF RWrBF

Refresh device areas assigned for station No. 4

7
At the above configuration, number of points specified in n2 is read starting from the offset (W1063) specified in S1 +2 of
the device assigned for the station number 4, then the number of points is read to devices starting from the device 8
specified in D1 .

Start number of the device

where target data is stored:
Refresh device areas

8.3.4
8.3 Refresh Device Write/Read Instruction
D1 =D1240
assigned for the remote
D1240 register (RWr) of station No. 4
D1241 Offset reference point
W1060

S.REFDVRDW, SP.REFDVRDW
D1242 Read area size:
W1061 (start point: 0)
D1243 n2=4
W1062
W1063 W1063 is the 3rd word from
W1064 the offset reference point.
W1065 Specify the offset in
W1066 hexadecimal, 3H.
W1067 S1 +2=3H
W1068
W1069
to
W106F

When a refresh range per station is assigned in transfer settings, specify number of read points so that the range read data
from the specified offset is within the range assigned in the same transfer setting. An error occurs if the number of read
points over the range assigned in each transfer setting is specified.

(5) The station type which can and cannot specify with the start I/O number is as follows.
Specification
Station type
possibility
CC-Link master station, CC-Link master station (compatible with redundant function), CC-Link IE Field Network
Enabled
master station
CC-Link local station, CC-Link standby master station, CC-Link IE Field Network local station, CC-Link IE Field
Disabled
Network submaster station

(6) Because the available range of the station number is 1 to 120, the station number for the master station in n1 cannot be
specified to S1 +0. If the station number is specified. the "OPERATION ERROR" (error code: 4102) occurs.

703
 S.REFDVRDW, SP.REFDVRDW

(7) SM739 (Refresh device write/read instruction in execution flag) turns on during the instruction execution. When SM739 is
on, the following instructions cannot be executed.
• S(P).REFDVWRB
• S(P).REFDVWRW
• S(P).REFDVRDB
• S(P).REFDVRDW
If these instructions are executed, no processing is performed. When an error is detected at the instruction execution
(before SM739 turns ON), the completion device ( D2 +0), the completion device ( D2 +1), and SM739 do not turn on.

(8) The instruction completion can be checked in the completion device ( D2 +0 and D2 +1).
(a) Completion device ( D2 +0)
The device turns on at the END processing in a scan where the instruction is completed and turns off at the next
END processing.
(b) Completion device ( D2 +1)
The device turns on or off by the status when the instruction is completed.
• Normal completion: No change from off
• Error completion: The device turns on at the END processing in a scan where the instruction is completed and
turns off at the next END processing.

END END END

Sequence program Scan Scan Scan
processing processing processing

S(P).REFDVRDW instruction Instruction execution

Refresh device write/read

instruction in execution flag
(SM739)

Completion device

Completion device + 1
Error completion

Reading
device data

(9) A module set parameters by the dedicated instruction and a CC-Link module operating by the automatic CC-Link startup
cannot be specified with the instruction.

(10) The read source (points in n2 from a device specified in control data) and read destination (points in n2 from D1 ) are
overlapped, data can be read. Read data starting from a device specified in control data when data are read to the
smaller device number. Read data starting from a device specified in control data + ((n2)-1) when data are read to the
larger device number.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the instruction is used with the CPU module whose serial number
4002 (first five digits) is "14071" or earlier –– –– –– ––
When the module cannot be specified the start I/O number in n1
4004 When the device which cannot be specified is specified –– –– –– ––
When the specified device exceeds the range of the number of device
points

4101 When the start I/O number in n1 is out of the specified range –– –– –– ––
When the device type number in S1 +1 is out of the specified range
When the read offset in S1 +2 is out of the specified range

704
 S.REFDVRDW, SP.REFDVRDW

Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the number of read points in n2 is out of the specified range 1
4101 When the number of read points in n2 exceeds the range of the number –– –– –– ––
of device points
When the station number in S1 +0 is out of the specified range 2
4102 When the station number in S1 +0 does not exist –– –– –– ––

When the station number in S1 +0 is the master station specified in n1

When the start I/O number in n1 is the station type which cannot be 3
specified
4150 –– –– –– ––
When the start I/O number in n1 does not exist in the network
parameter 4
When the device in S1 +1 of the station number specified in S1 +0 is not
assigned the refresh device

4151
When the read offset in S1 +2 exceeds the refresh device range
–– –– –– ––
6
assigned for the device in S1 +1 of the station number specified in S1 +0
When the number of read points in n2 exceeds the assignment range of
the setting for one transfer from the read offset in S1 +2 6
Program Example
7
(1) The following program reads 16 device values from the head of the refresh device (offset: 0) assigned for the remote
register (RWr) in the remote device station on the station number 32 controlled by the CC-Link master station of the start
I/O number 0080H to W100 when X1C is turned on.
8
[Ladder mode] [List mode]

Step Instruction Device

8.3.4
8.3 Refresh Device Write/Read Instruction
S.REFDVRDW, SP.REFDVRDW

Caution
(1) Do not execute the instruction in an interrupt program. If the instruction is executed, no processing is performed. In
addition, the completion device ( D2 +0), the completion device ( D2 +1), and SM739 do not turn on. If the instruction is
executed in a fixed scan execution type program, they also do not turn on.
(2) Specifying digit for the bit device can be used only when the following conditions (a) and (b) are met.
(a) Digit specification: K4
(b) Head of device: multiple of 16
When the above conditions (a) and (b) are not met, INSTRCT CODE ERR. (error code: 4004) will occur.

705
CHAPTER 9 MULTIPLE CPU DEDICATED
INSTRUCTION

9.1 Writing to the CPU Shared Memory of Host CPU

The S.TO or TO instruction is used to write to the CPU shared memory of the host station in the multiple CPU system.

The following table indicates the usability of the S.TO and TO instructions.
CPU Module S.TO Instruction TO Instruction
Q00JCPU Unusable Unusable
Basic model QCPU
Q00CPU, Q01CPU Usable Usable
Q02CPU, Q02HCPU,
High Performance model QCPU Q06HCPU, Q12HCPU, Usable Unusable
Q25HCPU
Process CPU Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU Usable Unusable
Redundant CPU Q12PRHCPU, Q25PRHCPU Unusable Unusable
Q00UJCPU Unusable Unusable
Q00UCPU, Q01UCPU, Q02UCPU, Q03UDCPU,
Q03UDVCPU, Q03UDECPU, Q04UDHCPU,
Q04UDVCPU, Q04UDEHCPU, Q06UDHCPU,
Universal model QCPU Q06UDVCPU, Q06UDEHCPU, Q10UDHCPU,
Usable Usable
Q10UDEHCPU, Q13UDHCPU, Q13UDVCPU,
Q13UDEHCPU, Q20UDHCPU, Q20UDEHCPU,
Q26UDHCPU, Q26UDVCPU, Q26UDEHCPU,
Q50UDEHCPU, Q100UDEHCPU
L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU,
LCPU L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT, Unusable Unusable
L26CPU-PBT
(1) Operation of S.TO instruction
The S.TO instruction can write data to the CPU shared memory of the host CPU module.
The following figure shows the processing performed when the S.TO instruction is executed in CPU No. 1.
Intelligent
CPU No. 1 CPU No. 2 function module

Device Data CPU Device CPU Buffer

memory write shared memory shared memory
memory memory

[ SP.TO H3E0 n2 n3 n4 D ]

Designation of CPU shared memory in CPU No. 1

(2) Operation of the TO instruction

The TO instruction can write device memory data to the following memories.
• CPU shared memory of host CPU module
• Buffer memory of intelligent function module

706
 S.TO, SP.TO

The following figure shows the processing performed when the TO instruction is executed in CPU No. 1.
Intelligent

9
CPU No. 1 CPU No. 2 function module

Device Data CPU Device CPU Buffer

memory write shared memory shared memory
memory memory
2

Writes data 3

[ TO H3E0 n2 S n3 ]
4
Designation of CPU shared memory in CPU No. 1

[ TO H0 n2 S n3 ]
4

Designation of intelligent function module

6

Both of the S.TO and TO instructions can be used for the Basic model QCPU and Universal model QCPU to write data to
the CPU shared memory. However, use of the TO instruction is recommended to write data to the CPU shared memory of 7
the host CPU module, since use of S.TO instruction reduces the number of steps and processing time.

8
Remark
Refer to Page 441, Section 7.8.2 when writing to the buffer memory of the intelligent function module by the TO instruction.

9.1.1
9.1 Writing to the CPU Shared Memory of Host CPU
9.1.1 S.TO, SP.TO Writing to host CPU shared memory

Ver. Ver.
High
Basic performance Process Redundant Universal LCPU

S.TO, SP.TO
• Q00CPU, Q01CPU: The serial number (first five digits) is

9.1.1 S.TO, SP.TO "04122" or later.

• High Performance model QCPU: Function version B or later

Command
S.TO S.TO n1 n2 n3 n4 D

Command
SP.TO SP.TO n1 n2 n3 n4 D

n1 : Head I/O number of the host CPU (BIN 16 bits)

n2 : CPU shared memory address of the write destination host CPU (BIN 16 bits)
•Basic model QCPU: 0 to 511
•High Performance model QCPU, Process CPU, Universal model QCPU: 0 to 4095
n3 : Head number of the devices where data to be written is stored (BIN 16 bits)
n4 : Number of data blocks to be written (BIN 16 bits)
•Basic model QCPU: 1 to 320
•High Performance model QCPU, Process CPU: 1 to 256
•Universal model QCPU: 1 to 2048
D : Device of the host CPU which is turned ON for one scan by the completion of writing (bits)
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n1 –– –– ––
n2 –– –– ––
n3 –– –– –– ––
n4 –– –– ––
D –– –– ––

707
 S.TO, SP.TO

Function
(1) Writes device data of words n3 to n4 to the CPU shared memory address specified by n2 of the host CPU module or later
address.
When writing is completed, the completion bit specified by D turns ON.

Host CPU

CPU shared memory

Device memory of host CPU (n1)
n3 n2

n4
Writes the
data of n4
words

(a) CPU shared memory address of the Basic model QCPU

CPU shared memory address

0(0H) Host CPU operation information area

96(60H) Write designation
System area prohibited area
192(C0H) *1
Host CPU refresh area

Write designation
permitted area
User free area

511(1FFH)

(b) CPU shared memory address of the High Performance model QCPU, Process CPU and Universal model QCPU*2
CPU shared memory address

0(0H) Host CPU operation information area

512(200H) Write designation
System area prohibited area
2048(800H) *1
Host CPU refresh area

Write designation
permitted area
User free area

4095(0FFFH)
*1: Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is usable as a user free area.
*2: Data cannot be written to the multiple CPU high speed transmission area of the Universal model QCPU with the S(P).TO
instruction.
(2) When the number of write points is 0, no processing is performed and the completion device does not turn ON, either.
(3) The S.TO instruction can be executed once to one scan for each CPU.
When execution condition is established at two or more places at the same time, the S.TO instruction executed later is
not processed since handshake is established automatically.
(4) The number of data that can be written varies depending on the target CPU module.
CPU module Number of Write Points
Basic model QCPU 1 to 320
High Performance model QCPU
1 to 256
Process CPU
Universal model QCPU 1 to 2048

708
 S.TO, SP.TO

Writing data to CPU shared memory can be performed using the intelligent function module device.
For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals)
9
or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).

2
Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0. 3
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
When the head I/O number (n1) of the host CPU is other than that of
4
2107 –– –– –– ––
the host CPU.
No CPU module is installed at the position specified for the head I/O
2110 –– ––
number of the CPU module. 4
4002 When the specified instruction is improper. –– ––
4003 When the number of devices specified is incorrect. –– ––
4004 When an Unavailable device is specified. –– –– 6
When the head I/O number (n1) of the host CPU is other than 3E0H/
4100 –– ––
3E1H/3E2H/3E3H.
When the host CPU operation information area, system area, or host 7
CPU refresh area is specified to the CPU shared memory address (n2) –– –– –– ––
of the write destination.
When the number of write points (n4) is outside the specified range of
the setting data. 8
When the head of the CPU shared memory address (n2) of the write
4101
destination host CPU exceeds the CPU shared memory address range.
When the CPU shared memory address (n2) + the number of write –– ––
points (n4) of the write destination host CPU exceeds the CPU shared

9.1.1
9.1 Writing to the CPU Shared Memory of Host CPU
memory address range.
When the head number of the devices (n3) where the data to be written
is stored + the number of write points (n4) exceeds the device range.

S.TO, SP.TO
When the host CPU operation information area, system area, or host
4111 CPU refresh area is specified to the CPU shared memory address (n2) –– –– –– ––
of the write destination.
When the head I/O number (n1) of the host CPU is other than that of
4112 –– –– –– ––
the host CPU.

Program Example
(1) The following program stores 10 points of data from D0 into address 800H of the CPU shared memory of CPU No. 1
when X0 is turned ON.
[Ladder Mode] [List Mode]
Step Instruction Device

709
 TO, TOP, DTO, DTOP

Remark
The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent the head I/O number of the slot mounted
to the CPU module.
CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30
n1 3E0 3E1 3E2 3E3

9.1.2 TO, TOP, DTO, DTOP Writing to host CPU shared memory

Ver.
High
Basic performance Process Redundant Universal LCPU

9.1.2 TO, TOP, DTO, DTOP • Q00CPU, Q01CPU: The serial number (first five digits) is
"04122" or later.

indicates an instruction symbol of TO/DTO.

Command
TO, DTO n1 n2 S n3

Command
TOP, DTOP P n1 n2 S n3

n1 : Head I/O number of the host CPU (BIN 16 bits)

• Basic model QCPU: 3E0H
• Universal model QCPU: 3E0H to 3E3H
n2 : CPU shared memory address of the write destination host CPU (BIN 16 bits)
• Basic model QCPU: 192 to 511
• Universal model QCPU: 2048 to 4095, 10000 to 24335*2
S : Data to be written or head number of the devices where the data to be written is stored (BIN 16 bits)
n3 : Number of data blocks to be written (BIN 16 bits)
• Basic model QCPU: TO(P): 1 to 320, DTP(P) : 1 to 160
• Universal model QCPU: TO(P): 1 to 14336*2, DTP(P) : 1 to 7168*2
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n1
n2 ––

S –– ––

n3 ––
*2: The setting range varies depending on the auto refresh setting range of the multiple CPU high speed transmission function.

Function
TO
(1) Writes device data of words S to n3 to the CPU shared memory address specified by n2 of the host CPU module or later
address.
Host CPU
CPU shared memory
Device memory of host CPU (n1)
S n2

n3
Writes the
data of n3
words

710
 TO, TOP, DTO, DTOP

When a constant is specified to S , writes the same data (value specified to S ) to the area of n3 words from the specified
CPU shared memory.

CPU shared memory 9

of host CPU (n1)
Constant n2 5
S 5 5
(When "5" is designated Writes the
5
n3 words
2
for S ) same data to
the area of n3
words
5
3
(a) CPU shared memory addresses of the Basic model QCPU
CPU shared memory address

0(0H) Host CPU operation information area

4
96(60H) Write designation
System area prohibited area
192(C0H)
Host CPU refresh area
*2
4
Write designation
permitted area
User free area
6
511(1FFH)

(b) CPU shared memory address of the Universal model QCPU*3

CPU shared memory address 7
0(0H) Host CPU operation information area
512(200H) Write designation
System area
2048(800H) *2
prohibited area
8
Host CPU refresh area

User free area

4096(1000H)

9.1.2
9.1 Writing to the CPU Shared Memory of Host CPU
Write designation
Unusable permitted area
10000(2710H)

TO, TOP, DTO, DTOP

Multiple CPU high speed
transmission area

24335(5F0FH)

*2: Usable as a user free area when auto refresh setting is not made.
In addition, even when auto refresh setting is made, the auto refresh send range or later is usable as a user free area.
*3: With the following CPU modules, data cannot be written to the multiple CPU high speed transmission area.
•Q00UCPU
•Q01UCPU
•Q02UCPU
(2) No processing is performed when the number of write points is 0.
(3) The number of write data varies depending on the target CPU module.
CPU module Number of Write Points
Basic model QCPU 1 to 320
Universal model QCPU 1 to 14336

711
 TO, TOP, DTO, DTOP

DTO
(1) Writes device data of words S to (n32) to the CPU shared memory address specified by n2 of the host CPU module or
later address.
Host CPU
CPU shared memory
Device memory of host CPU (n1)
S n2

n3 2
Writes the
data of (n3 2)
words

When a constant is specified to S , writes the same data (value specified to S ) to the area of (n32) words from the
specified CPU shared memory.

CPU shared memory

of host CPU (n1)
Constant n2 5
S 5 5
(When "5" is designated 5
Writes the same (n3 2)
for S ) data to the area words
of (n3 2) words
5

(2) No processing is performed when the number of write points is 0.

(3) The number of data that can be written varies depending on the target CPU module.
CPU module Number of Write Points
Basic model QCPU 1 to 160
Universal model QCPU 1 to 7168

Writing data to CPU shared memory can be performed using the intelligent function module device.
For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals)
or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
No CPU module is installed at the position specified for the head I/O
2110 –– –– –– ––
number of the CPU module.
When the number of write points (n3) is outside the specified range of
the setting data.
When the CPU shared memory address (n2) of the write destination
4101 host CPU + the number of write points (n3) exceeds the CPU shared –– –– –– ––
memory range.
When the head of CPU shared memory address (n2) of the write
destination host CPU is outside the allowable range.
When the head of CPU shared memory address (n2) of the write
4111 –– –– –– ––
destination host CPU is an invalid value.
When the I/O number specified in (n1) is other than that of the host
4112 CPU (Exclude the case of when the multiple CPU high speed –– –– –– ––
transmission area of other CPU is used.)

712
 TO, TOP, DTO, DTOP

Program Example
9
(1) The following program stores 10 points of data from D0 into address 10000 of the CPU shared memory of CPU No. 1
when X0 is turned ON.
[Ladder Mode] [List Mode] 2
Step Instruction Device

3
(2) The following program stores 20 points of data from D0 into address 10000 of the CPU shared memory of CPU No. 4
when X0 is turned ON. 4
[Ladder Mode] [List Mode]
Step Instruction Device
4

6
Remark
The n1 is specified by the first 3 digits of the hexadecimal 4 digits which represent the head I/O number of the slot mounted
to the CPU module. 7
CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30
n1 3E0 3E1 3E2 3E3
8

9.1.2
9.1 Writing to the CPU Shared Memory of Host CPU
TO, TOP, DTO, DTOP

713
9.2 Reading from the CPU Shared Memory of another CPU

The FROM(P)/DFRO(P) instruction of Multiple CPU system can be read from the following memories.
• Buffer memory of intelligent function module
• CPU shared memory of other CPU module
• CPU shared memory of host CPU module (applicable for the Basic model QCPU and Universal model QCPU)

The following figure shows the processing performed when the FROM(P) instruction is executed in CPU No. 1.

Intelligent
CPU No. 1 CPU No. 2 function module
Data read

*1
Device Data CPU Device CPU Buffer
memory read shared memory shared memory
memory memory

Reads data

[ FROM H3E1 n1 n2 D n3]

Designation of CPU shared memory of CPU No. 2

[ FROM H3E0 n1 n2 D n3]

Designation of CPU shared memory of CPU No. 1

[ FROM H0 n1 n2 D n3]

Designation of intelligent function module

*1: Applicable for the Basic model QCPU and Universal model QCPU

Remark
Refer to Page 439, Section 7.8.1 for reading the buffer memory of the intelligent function module with the FROM/DFRO
instruction.

714
 FROM, FROMP, DFRO, DFROP

9.2.1 FROM, FROMP, DFRO, Reading from other CPU shared memory
DFROP

Ver. Ver.
Basic High
performance Process Redundant Universal LCPU 9
• Q00CPU, Q01CPU: The serial number (first five digits) is

9.2.1 FROM, FROMP, DFRO, DFROP "04122" or later.

• High Performance model QCPU: Function version B or later
2
When Basic model QCPU, Universal model QCPU is used

Command
indicates an instruction symbol of FROM/DFRO.
3
FROM, DFRO n1 n2 D n3

Command
FROMP, DFROP P n1 n2 D n3 4
n1 : Head I/O number of the reading target CPU module (BIN 16 bits)
• Basic model QCPU: 3E0H to 3E2H
• Universal model QCPU: 3E0H to 3E3H 4
n2 : Head address of data to be read (BIN 16 bits)
•Basic model QCPU: 0 to 512

D
• Universal model QCPU: 0 to 4095, 10000 to 24335*1
: Head number of the devices where the read data is stored (BIN 16 bits)
6
n3 : Number of read data (BIN 16 bits)
•Basic model QCPU: FROM(P): 1 to 512, DFRO(P) : 1 to 256
•Universal model QCPU: FROM(P): 1 to 14336*1, DRRO(P) : 1 to 7168*1 7
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H U
n1
n2
––
–– ––
8
D –– –– –– ––
n3 –– ––
*1: The setting range varies depending on the auto refresh setting range of the multiple CPU high speed communication function.

9.2.1
9.2 Reading from the CPU Shared Memory of another CPU
Function

FROM, FROMP, DFRO, DFROP

FROM
(1) Reads the data of n3 words from the CPU shared memory address designated by n2 of the CPU module designated by
n1, and stores that data into the area starting from the device designated by D .
CPU shared memory of
Device memory the designated CPU (n1)
n2
D

n3
Reads the
data of n3
words
(a) CPU shared memory address of the Basic model QCPU
CPU shared memory address

0(0H) Host CPU operation information area

96(60H)
System area
192(C0H) *2
Host CPU refresh area Read designation
permitted area

User free area

511(1FFH)

715
 FROM, FROMP, DFRO, DFROP

(b) CPU shared memory address of the Universal model QCPU*3

CPU shared memory address

0(0H) Host CPU operation information area

512(200H)
System area
2048(800H) *2
Host CPU refresh area

User free area

4096(1000H) Read designation

Unusable permitted area
10000(2710H)

Multiple CPU high speed

transmission area

24335(5F0FH)
*2: Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user free area.
*3: With the following CPU modules, data cannot be read from the multiple CPU high speed transmission area.
•Q00UCPU
•Q01UCPU
•Q02UCPU
(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.
(3) The number of data to be read changes depending on the target CPU module.
CPU Module Number of Read Points
Basic model QCPU 1 to 512
Universal model QCPU 1 to 14336

DFRO
(1) Reads the data of (n32) words from the CPU shared memory address designated by n2 of the CPU module designated
by n1, and stores that data into the area starting from the device designated by D .
CPU shared memory of the
Device memory designated CPU (n1)
n2
D

n3
Reads the data
of (n3 2)
words
(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.
(3) The number of data to be read changes depending on the target CPU module.
CPU Module Number of Read Points
Basic model QCPU 1 to 256
Universal model QCPU 1 to 7168

Read of data from the CPU shared memory can also be performed using the intelligent function module devices.
For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals)
or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).

716
 FROM, FROMP, DFRO, DFROP

Operation Error
9
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
No CPU module is installed at the position specified for the head I/O
2110 –– –– –– ––
number of the CPU module.
The head of the CPU shared memory address (n2) which performs 3
reading is outside the CPU shared memory range.
The address of the CPU shared memory (n2) which performs reading +
the number of read points (n3) is outside the CPU shared memory
4101 range. –– –– –– –– 4
The read data storage device number D plus the number of read points
(n3) is outside the specified device range.
When the head of the CPU shared memory address (n2) which 4
performs reading is an invalid value. (4097 to 9999)

Program Example 6
(1) The following program stores 10 points of data from address C0H of the CPU shared memory of CPU No. 2 into the area
starting from D0 when X0 is turned ON. 7
[Ladder Mode] [List Mode]

Step Instruction Device

8

(2) The following program stores 20 points of data from address 10000 of the CPU shared memory of CPU No. 4 into the
area starting from D0 when X0 is turned ON.

9.2.1
9.2 Reading from the CPU Shared Memory of another CPU
[Ladder Mode] [List Mode]

Step Instruction Device

FROM, FROMP, DFRO, DFROP

Remark
(1) The value of n1 is specified by the first 3 digits of the hexadecimal 4digits which represent the head I/O number of the
slot mounted to the CPU module.
CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30
n1 3E0 3E1 3E2 3E3
(2) The QCPU provides automatic interlocks for the FROM and TO instructions.

717
 FROM, FROMP, DFRO, DFROP

When High Performance model QCPU, Process CPU is used

Command
FROM FROM n1 n2 D n3

Command
FROMP FROMP n1 n2 D n3

n1 : Head I/O number of the reading target CPU module (BIN 16 bits)
n2 : Head address of data to be read (BIN 16 bits)
D : Head number of the devices where the read data is stored (BIN 16 bits)
n3 : Number of read data (BIN 16 bits)
Setting Internal Devices J \ Constants Other
R, ZR U \G Zn
Data Bit Word Bit Word K, H U
n1 ––
n2 –– ––

D –– –– –– ––

n3 –– ––

Function
(1) Reads the data of n3 words from the CPU shared memory address designated by n2 of the CPU module designated by
n1, and stores that data into the area starting from the device designated by D .
CPU shared memory of
Device memory the designated CPU (n1)
n2
D

n3
Reads the
data of n3
words
CPU shared memory address of the High Performance model QCPU and Process CPU
CPU shared memory address

0(0H) Host CPU operation information area

512(200H)
System area
2048(800H) *1
Host CPU refresh area Read designation
permitted area

User free area

4095(0FFFH)
*1: Usable as a user free area when auto refresh setting is not made.
When auto refresh setting is made, the auto refresh send range and later are usable as a user free area.
(2) When 0 is specified in n3 as the number of data to be read, no processing is performed.
(3) The number of data to be read changes depending on the target CPU module.
CPU Module Number of Read Points
High Performance model QCPU
1 to 4096
Process CPU

Read of data from the CPU shared memory can also be performed using the intelligent function module devices.
For intelligent function module device, refer to the QnUCPU User's Manual (Function Explanation, Program Fundamentals)
or Qn(H)/QnPH/QnPRHCPU User's Manual (Function Explanation, Program Fundamentals).

718
 FROM, FROMP, DFRO, DFROP

Operation Error
9
In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01 2
No CPU module is installed at the position specified for the head I/O
2110 –– –– –– ––
number of the CPU module.
The head of the CPU shared memory address (n2) which performs 3
reading is outside the CPU shared memory range.
The address of the CPU shared memory (n2) which performs reading +
the number of read points (n3) is outside the CPU shared memory
4101 range. –– –– –– –– 4
The read data storage device number D plus the number of read points
(n3) is outside the specified device range.
When the head of the CPU shared memory address (n2) which 4
performs reading is an invalid value. (4097 to 9999)

Program Example 6
(1) The following program stores data of 10 points from address 800H of the CPU shared memory of CPU No. 2. into the
area starting from D0 when X0 is turned ON. 7
[Ladder Mode] [List Mode]

Step Instruction Device

8

Remark

9.2.1
9.2 Reading from the CPU Shared Memory of another CPU
(1) The value of n1 is specified by the first 3 digits of the hexadecimal 4digits which represent the head I/O number of the
slot mounted to the CPU module.

FROM, FROMP, DFRO, DFROP

CPU Slot Slot 0 Slot 1 Slot 2
Head I/O number 3E00 3E10 3E20 3E30
n1 3E0 3E1 3E2 3E3
(2) The QCPU provides automatic interlocks for the FROM and TO instructions.

719
CHAPTER 10 MULTIPLE CPU HIGH-SPEED
TRANSMISSION DEDICATED
INSTRUCTIONS

10.1 Overview

The multiple CPU high-speed transmission dedicated instruction directs the Universal model QCPU to write/read device data
to/from the Universal model QCPU in another CPU.
The following shows an operation when CPU No.1 writes device data to CPU No.2 with the multiple CPU high-speed
transmission dedicated instruction.

CPU No.1 CPU No.2

User program

DP.DDWR U3E1 D0 D100 D200 M0

D0 D0

D100
Writing
D200

The multiple CPU high-speed transmission dedicated instruction in either host CPU or another CPU (target CPU module of
instruction) is available only for the following CPU modules.
• Q03UDCPU, Q04UDHCPU, Q06UDHCPU
The first five digits of serial number is 10012 or higher.
• Q10UDHCPU, Q13UDHCPU, Q20UDHCPU, Q26UDHCPU
• QnUDE (H) CPU

(1) Parameter setting and system configuration to execute the multiple CPU high-speed transmission dedicated instruction
The multiple CPU high-speed transmission dedicated instruction can be executed in the following parameter setting and
system configuration.
• For CPU No. 1, QnUD(H)CPU or, Built-in Ethernet port QCPU is used.
• The multiple CPU high speed main base unit (Q3 DB) is used.
• "Use multiple CPU high speed transmission" is selected in the Multiple CPU settings screen of PLC parameter.

720
(2) Writable/readable devices
(a) Writable/readable device names
The following table shows the devices that can be written to/read from the Universal model QCPU in another CPU 1
with the multiple CPU high-speed transmission dedicated instruction.
Setting of target
Category Type Device name Remarks
device
Requirements for the setting
10
• Digits are specified by 16 bits (4 digits).
Bit device X, Y, M, L, B, F, SB
Internal user device • The start bit device is multiples of
16(10H). 3
Word device T, ST, C, D, W, SW ––
Requirements for the setting

Bit device SM
• Digits are specified by 16 bits (4 digits). 4
Internal system device • The start bit device is multiples of
16(10H).

File register
Word device
Word device
SD
R, ZR
––
––
6
:Settable :Settable with conditions

6
SB, SW, SM, and SD include system information area. Take care not to destroy the system information when writing data
to the devices above with the D(P).DDWR instruction of the multiple CPU high-speed transmission dedicated instruction.
7
(3) Specification method of a device and writable/readable device range
There are two methods for specifying a device in another CPU: device specification and string specification. They differ
in writable/readable device range to another CPU. 8
(a) Device specification
The device specification is a method to directly specify a device in another CPU to be written/read.

Program for device specification with the DP.DDWR instruction

10.1 Overview
X0
DP.DDWR H3E1 D0 D100 D200 M0

Directly specifies "D200", a

device in another CPU to be
written.

In the device specification, data can be written/read within the device range of host CPU.
For example, when data register in host CPU is 12k points and data register in another CPU is 16k points, data can be
written/read by 12k points from the start of the data register in another CPU.
Writable/readable device range in device specification
Host CPU Another CPU
D0 D0

Data register Data register

Writable/readable
(12k points) (16k points)

D12287 D12287
D12288
Not writable/not readable
D16383

721
 (b) String specification
The string specification is a method to specify a device in another CPU to be written/read by character string.
Program for string specification with the DP.DDWR instruction

X0
DP.DDWR H3E1 D0 D100 "D200" M0

Specifies "D200", a device in another CPU

to be written by character string.

In the string specification, data can be written to/read from all device ranges of another CPU.
For example, when data register in host CPU is 12k points and data register in another CPU is 16k points, data can
be written/read by 16k points from the start of the data register in another CPU.
Writable/readable device range in string specification
Host CPU Another CPU
D0 D0

Data register Data register

to to
(12k points) (16k points)
Writable/readable

D12287

D16383

Remark
The following explains precautions for string specification.
• The number of characters that can be specified is 32.
• Whether "0" is appended at the start of the device number or not, the devices are processed as the same.
For example, both "D1" and "D0001" are processed as "D1".
• Whether a device is specified by upper case character or lower-case character, they are processed as the same.
For example, both "D1" and "d1" are processed as "D1".
• If a device not existing in another CPU is specified by a character string, the instruction will be completed abnormally.

(4) Managing the multiple CPU high speed transmission area

(a) The multiple CPU high speed transmission area is managed by blocks in units of 16 words.
The following table shows the number of blocks that can be used in each CPU and the number of blocks used in the
instruction.
System area*1
C Number of CPU modules
1k points 2k points
2 46 110
3 22 54
4 14 35
*1: For setting of the system area, refer to the QCPU User's Manual (Multiple CPU System).

722
 (b) The following shows configuration of the multiple CPU high speed transmission area when the multiple CPU system
is configured with three CPU modules and the system area size is 1k word.
Multiple CPU high speed Multiple CPU high speed Multiple CPU high speed 1
transmission area in transmission area in transmission area in
CPU No.1 CPU No.2 CPU No.3
Area to be sent from CPU No.1 to CPU No.s 2 and 3
22 Send area to Receive area from 22 10
blocks CPU No.2 CPU No.1 blocks
22 Send area to Receive area from 22
blocks CPU No.3 CPU No.1 blocks
3
Area to be sent from CPU No.2 to CPU No.s 1 and 3

22 Receive area to Send area to 22

blocks
4
CPU No.2 CPU No.1 blocks
22 Send area to Receive area to 22
blocks CPU No.3 CPU No.2 blocks

Area to sent from CPU No.3 to CPU No.s 1 and 2

22
6
Receive area to Send area to 22
blocks CPU No.3 CPU No.1 blocks
22 Receive area to Send area to 22
blocks CPU No.3 CPU No.2 blocks
6
(5) The number of blocks used for the instruction
The number of blocks used for the instruction depends on the number of write points.
The following table shows the number of blocks used for the instruction.
7
Number of write/read points specified by the instruction D(P).DDWR instruction D(P).DDRD instruction
1 to 4 1
5 to 20 2 8
21 to 36 3
37 to 52 4 1
53 to 68 5
69 to 84 6

10.1 Overview
85 to 100 7

(6) The multiple CPU high-speed transmission dedicated instructions that can be executed concurrently
For the Universal model QCPU, the multiple CPU high-speed transmission dedicated instructions can be concurrently
executed within the range satisfying the following formula.

The number of blocks that Total number of blocks used for the
can be used in each CPU instructions concurrently executed

When the number of blocks used for the multiple CPU high-speed transmission dedicated instructions exceeds the total
number of blocks in the multiple CPU high speed transmission area, the instruction will not be executed in the scan (no
processing) but executed at the next scan.
Note that the instruction will be completed abnormally when the number of empty blocks in the multiple CPU high speed
transmission area is less than the setting values of SD796 to SD799 (maximum number of used blocks for multiple CPU
high-speed transmission dedicated instruction setting) at the execution of the instruction.
The following table shows execution possibility of the multiple CPU high-speed transmission dedicated instructions when
the number of empty blocks in the multiple CPU high speed transmission area is less than the number of blocks used for
the multiple CPU high-speed transmission dedicated instructions or the setting values of SD796 to SD799.

Magnitude relation between the number of blocks

used for the instructions*1 and
the number of empty Number of blocks used Number of blocks used
Number of empty blocks*2 Number of empty blocks*2
Magnitude relation blocks for the instruction*1 for the instruction*1
between SD setting value
and the number of empty blocks
SD setting value*3 Number of empty blocks*2 Executed Not executed (no processing)
SD setting value*3 Number of empty blocks*2 Completed abnormally

*1:The number of blocks used for the multiple CPU high-speed transmission dedicated instruction.
*2:The number of empty blocks in the multiple CPU high-speed transmission area.
*3:Setting values from SD796 of SD799.

723
(7) Interlock when using the multiple CPU high-speed transmission dedicated instruction
(a) Special relays SM796 to SM799 (maximum number of used blocks for multiple CPU high-speed transmission
dedicated instruction setting) can be used as an interlock for the multiple CPU high-speed transmission dedicated
instruction.
When executing the multiple CPU high-speed transmission dedicated instructions concurrently, use SM796 to
SM799 as an interlock for the instructions.

When using special relays SM796 to SM799, set the maximum number of blocks for the instruction used for each CPU to
special registers SD796 to SD799. (For example, when the maximum number of blocks for the multiple CPU high-speed
transmission dedicated instruction to be executed to CPU No.3 is 5, set 5 to SD798.)
When the multiple CPU high speed transmission area becomes equal to or less than the number of blocks set at SD796 to
SD799, the corresponding special relay (SM796 to SM799) turns on.
CPU No.1 CPU No.2
Multiple CPU high speed transmission area Multiple CPU high speed transmission area

SM
Execution Send area Receive area
command 797
(1 2) (1 2)
DP.DDWR H3E1

Number of request blocks: 4 During use

Number of empty blocks:

Turns on when the number of empty blocks 2
is less than the number of blocks used for
the DP.DDWR instruction.
Insufficient for writing a request from
(The DP.DDWR instruction is not executed.)
the DP.DDWR instruction.

Empty area of the request blocks in send area (1 2) has been increased.
CPU No.1 CPU No.2
Multiple CPU high speed transmission area Multiple CPU high speed transmission area

SM
Execution 797 Send area Receive area
command (1 2) (1 2)
DP.DDWR H3E1
During use

Number of request blocks: 4

Number of empty blocks:
8

Turns off as empty blocks by the number of blocks

used for the DP.DDWR instruction became available
(The DP.DDWR instruction can be written.)
The request from the DP.DDWR instruction can be written.

724
 (b) Program example when SM796 to SM799 are used as an interlock
The following shows a program that executes the D.DDWR instruction to CPU No.2 at the rise of X0, and executes
the D.DDWR instruction to CPU No.3 at the rise of X1. 1
The maximum number of used blocks for multiple CPU high-speed transmission dedicated instruction

0
SM402
MOV K7 SD797 10
Turn-on for one Maximum number of
scan after RUN used blocks
(CPU No.2)

MOV K7 SD798
3
Maximum number of
used blocks
(CPU No.3)

SM402 4
8 MOV K100 D1
Turn-on for one Number of write points
scan after RUN to CPU No.2

6
MOV K100 D3
Number of write points
to CPU No.3
6
The DDWR instruction is executed to CPU No.2 at the rise of X0
X0
11 SET M0
Execution command of the
DDWR instruction to CPU No.2
During execution the
DDWR instruction to
CPU No.3
7
M0 SM797
14 D.DDWRH3E1 D0 ZR0 ZR0 M1
During execution Number of used
of the DDWR blocks information
Completion
status
Write data
to CPU No.2
Write data
to CPU No.2
Completion
device
8
instruction to (CPU No.2) (CPU No.2) (CPU No.2)
CPU No.3

RST M0
During execution of the
DDWR instruction to CPU No.2

10.1 Overview
The DDWR instruction is executed to CPU No.3 at the rise of X1
X1
29 SET M3
During execution of the DDWR During execution the
instruction to CPU No.3 DDWR instruction to
CPU No.3

M3 SM798
32 D.DDWRH3E2 D2 ZR1000 ZR1000 M4
During execution Number of used Completion Write data Write data Completion
of the DDWR blocks information status to CPU No.3 to CPU No.3 device
instruction to (CPU No.3) (CPU No.3) (CPU No.3)
CPU No.3

RST M3
During execution of the
DDWR instruction to CPU No.3

725
(8) Program example when the multiple CPU high-speed transmission dedicated instructions are executed to CPU modules
by turns
When the multiple CPU high-speed transmission dedicated instructions are executed to Universal model QCPUs by
turns, release an interlock to prevent the concurrent execution.
Use the cyclic transmission area device (from U3En\G10000) as an interlock.
The following shows a program example when the multiple CPU high-speed transmission dedicated instructions are
executed at CPU No. 1 and 2 by turns.
Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.1

SM402
MOV K7 SD797
Turn-on for one scan Maximum number
after RUN of used blocks
(CPU No.2)

X0
SET M0
Write command During execution of the
DDWR instruction

U3E0\G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction.

M0 U3E1\G10000.0 SM797 U3E0\

SET G10000.0
During execution CPU No.2 is Number of used CPU No.1 is during
of the DDWR during execution blocks information execution of the
instruction of the instruction (CPU No.2) instruction

MOV K100 D1
Number of
write points

DP.DDWR H3E1 D0 ZR100 ZR100 M1

Completion Completion
status device

RST M0
During execution of
the DDWR instruction

U3E0\G10000.0 is turned on while CPU No.1 is executing the DP.DDWR instruction.

M1 U3E0\
SET G10000.0
Completion device CPU No.1 is during of
the instruction

726
 Program example when the multiple CPU high-speed transmission dedicated instruction is executed at CPU No.2

SM402 1
MOV K1 SD796
Turn-on for one Maximum number of
scan after RUN used blocks
(CPU No.1)
10
X20
SET M0
Read instruction During execution the
DDRD instruction
3
U3E1\G10000.0 is turned on while CPU No.2 is executing the DP.DDRD instruction.

M0 U3E0\G10000.0 SM796 U3E1\

During execution CPU No.1 is Number of used

SET G10000.0
CPU No.2 is during
4
of the DDWR during execution blocks information execution of the
instruction of the instruction (CPU No.1) instruction

6
MOV K50 D1
Read instruction

6
DP.DDRD H3E0 D0 D1000 D1000 M1
Completion
status
Completion
device 7

RST M0 8
During execution of
the DDRD instruction

U3E1\G10000.0 is turned off at the completion of the DP.DDRD instruction.

M1 U3E1\

10.1 Overview
RST G10000.0
Completion device CPU No.2 is during of
execution the instruction

(9) Program example when data exceeding 100 words are written/read with the multiple CPU high-speed transmission
dedicated instruction
The maximum number of write/read points that can be processed with the multiple CPU high-speed transmission
dedicated instruction is 100 words. Data exceeding 100 words can be written/read by executing the multiple CPU high-
speed transmission dedicated instruction at several times.
The following shows a program example using the D(P).DDWR instruction of the multiple CPU high-speed transmission
dedicated instruction. The similar program can be used when using the D(P).DDRD instruction of the multiple CPU high-
speed transmission dedicated instruction.

727
 (a) Program example when one D(P).DDWR instruction is executed.
The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in
CPU No.2 with the D.DDWR instruction.
In the following program example, the next D.DDWR instruction is executed after the completion device of the
D.DDWR instruction (M2) turns on so that only one D.DDWR instruction may be executed.
Program example when one D(P).DDWR instruction is executed
The maximum number of used blocks for multiple CPU high-speed
transmission dedicated instruction setting is set to CPU No.2
SM402
0 MOV K7 SD797
Turn-on for one Maximum number of
scan after RUN used blocks
(CPU No.2)

MOV K100 D1
Number of
write points

Data writing is started at the rise of the write command (X0)

X0 M0
37 RST Z2
Write During
command writing

SET M0
During writing
M0
68 SET M1
During During execution of
writing the DDWR instruction

M4

Execution request of the next

DDWR instruction

The DDWR instruction is executed

M1 SM797
71 D.DDWR H3E1 D0 ZR0Z2 ZR0Z2 M2
During execution Number of used Completion Write source/write Completion
of the DDWR blocks information status destination device
instruction (CPU No.2)

RST M1
During execution of the
DDWR instruction
When the DDWR instruction is completed abnormally, the annunciator is turned on and data writing is stopped
M2 M3
98 SET F0
Completion Error
device completion
device
RST M0
During
writing
Next data writing is requested at normal completion of the DDWR instruction
M2 M3
134 + K100 Z2
Completion Error
device completion
device
< Z2 K1000 PLS M4
Execution request of the
next DDWR instruction
= Z2 K1000 RST M0
During writing

173 END

728
(b) Program example when the D(P).DDWR instructions are executed concurrently
The following shows a program example that writes ZR0 to ZR999 (1000 points) in CPU No.1 to ZR0 to ZR999 in
CPU No.2 with the D.DDWR instruction. 1
As shown on the program example, multiple CPU device write/read instructions can be executed concurrently.
When reading/writing devices with the multiple CPU high-speed transmission dedicated instructions concurrently,
the more the total number of blocks in the multiple CPU high speed transmission area (send area), the more the 10
time taken to complete reading/writing with the multiple CPU high-speed transmission dedicated instruction can be
shortened.
Program example when the D(P).DDWR instructions are executed concurrently 3
The maximum number of used blocks for multiple CPU high-speed
transmission dedicated instruction setting is set to CPU No.2
SM402 4
0 MOV K7 SD797
Turn-on for one Maximum number of
scan after RUN used blocks
(CPU No.2)
MOV K100 D1
Number of
write points 1
6
MOV K100 D3
Number of
Data writing is started at the rise of the write command (X0) write points 2

39
X0 M0
RST Z2
6
Write During
command writing
SET M0
First DDWR instruction, Second DDWR instruction
During writing
7
M0
70 SET M1
During During execution of
writing
M7
the DDWR instruction 1
8
SET M2
Execution request of the next During execution of
DDWR instruction the DDWR instruction 2
The first DDWR instruction is executed
M1 SM797
94 D.DDWR H3E1 D0 ZR0Z2 ZR0Z2 M3

10.1 Overview
During execution Number of used Completion Write source write Completion
of the DDWR blocks information status 1 destination device 1
instruction 1 (CPU No.2)
RST M1
The second DDWR instruction is executed During execution of the
DDWR instruction 1
M2 SM797
126 D.DDWR H3E1 D2 ZR100Z2 ZR100Z2 M5
During execution Number of used 3 Completion Write source write Completion
of the DDWR blocks information status 2 destination device 2
instruction 2 (CPU No.2)
RST M2
During execution of the
DDWR instruction 2
When the DDWR instruction is completed abnormally, the annunciator is turned on and data writing is stopped
M3 M4
158 SET F0
Completion Error DDWR instruction
device 1 completion error display
device 1
M5 M6
RST M0
Completion Error During
device 2 completion writing
device 2
Next data writing is requested at normal completion of the second DDWR instruction
M5 M6
197 + K200 Z2
Completion Error
device 2 completion
device 2 < Z2 K1000 PLS M7
Execution request of the
next DDWR instruction
= Z2 K1000 RST M0
During writing
241 END

729
 D.DDWR, DP.DDWR
10.2 D.DDWR, DP.DDWR Writing Devices to Another CPU

Ver.
High
Basic performance Process Redundant Universal LCPU
• Universal model QCPU: The serial number (first five digits) is
"10012" or later.

10.2 D.DDWR, DP.DDWR • Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU cannot

be used.

Command
D.DDWR D.DDWR n S1 S2 D1 D2

Command
DP.DDWR DP.DDWR n S1 S2 D1 D2

Setting Internal Devices J \ Constants

R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n *1 –– –– ––
S1
*2 –– *3 *4 –– –– ––
S2
*2 –– –– –– ––
D1
*2 –– –– –– ––
D2 *2 *6 –– *4 –– –– ––
*1: Index modification cannot be made to setting data n.
*2: Index modification cannot be made to setting data from S1 to D2 .
*3: Local devices cannot be used.
*4: File registers cannot be used per program.
*5: FD @ (indirect specification) cannot be used.
*6: FX and FY cannot be used.

Set Data
Setting data Description Data type
The result of dividing the start I/O number of another CPU by 16
n BIN 16 bits
CPU No.1: 3E0H, CPU No.2: 3E1H, CPU No.3: 3E2H, CPU No.4: 3E3H
S1 Start device of the host CPU that stores control data
Device name
S2 Start device of the host CPU that stores data to be written
Device*7
D1 Start device of another CPU where data to be written will be stored Character
string*8*9
D2 Completion device Bit

*7: By specifying a file register (R, ZR), data can be written to devices in another CPU, outside the range of host CPU.
*8: By specifying the start device by " ", data can be written to devices in another CPU, outside the range of host CPU.
*9: Indexed devices cannot be specified (e.g. D0Z0).

Control Data
Device Item Setting data Setting range Set by
An execution result upon completion of the
instruction is stored.
S1 +0 Completion status –– System
0000(H): No errors (normal completion)
Other than 0000(H): Error code (error completion)
Number of write
S1 +1 Set the number of write points in units of words. 1 to 100 User
points

730
 D.DDWR, DP.DDWR

Function
1
(1) In multiple CPU system, data stored in a device specified by host CPU ( S2 ) or later is stored by the number of write points
specified by ( D2 +1) into a device specified by another CPU (n) ( D1 ) or later.

Start device number of the Start device number of the storage

location where write data has stored
10
storage location for write data
S2 D1
Host CPU Another CPU n
(CPU that requests writing) (CPU to be read)

Number of write points

S1 +1 4

6
(2) Whether to complete the D(P).DDWR instruction normally can be checked by the completion device ( D2 +0) and
completion status display device ( D2 +1).
6
(a) Completion device ( D2 +0)
Turns on at END processing in the scan where the instruction has been completed, and turns off at the next END
processing.
7
(b) Completion status display device ( D2 +1)
This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off 8
• Error completion: Turns on at END processing in the scan where the instruction has been completed, and turns
off at the next END processing (At error completion, an error code is stored at control data ( S1 +0): Completion
status)).
(3) The number of blocks used for the instruction depends on the number of write points (refer to Page 720, Section 10.1).

10.2 D.DDWR, DP.DDWR

Number of blocks used for the instruction
Number of write points D(P).DDWR
specified by the instruction instruction
1 to 4 1
5 to 20 2
21 to 36 3
37 to 52 4
53 to 68 5
69 to 84 6
85 to 100 7

(4) The instruction will be completed abnormally when there are no empty blocks in the multiple CPU high speed
transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and use the special relays
(SM796 to SM799) as an interlock prevent error completion (refer to Page 720, Section 10.1).

731
 D.DDWR, DP.DDWR

Operation Error
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
Specified another CPU is incorrect. Or the multiple CPU high-speed
transmission dedicated instruction is disabled.
• The reserved CPU has been specified.
• A CPU that is not mounted has been specified.
• Another CPU start I/O number divided by 16n is not within the range
from 3E0H to 3E3H.
4350 • The instruction was executed when the module is set to "Do not use –– –– –– –– ––
multiple CPU high speed transmission".
• The instruction was executed with the CPU module that cannot use
this instruction.
• The host CPU has been specified.
• The CPU where the instruction cannot be executed has been
specified.
4351 Another CPU does not support this instruction. –– –– –– –– ––
4352 The number of devices is incorrect. –– –– –– –– ––
4353 The device that cannot be used for the instruction has been specified. –– –– –– –– ––
A device has been specified by the character string that cannot be
4354 –– –– –– –– ––
used.
4355 The number of write points, ( S1 +1), is other than 0 to 100. –– –– –– –– ––

In any of the following cases, the instruction is completed abnormally, and an error code is stored into a device specified
at completion status storage device ( S1 +0).
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The request of the instruction to the target CPU is more than the
0010H acceptable value (no empty block exists in the multiple CPU high speed –– –– –– –– ––
transmission area).
A device of another CPU specified in D1 cannot be used for the CPU, or
1001H –– –– –– –– ––
is outside the device range.
The response of the instruction from another CPU cannot be returned
1003H (no empty block exists in the multiple CPU high speed transmission –– –– –– –– ––
area).
1080H The number of write points set with the D(P).DDWR instruction is 0. –– –– –– –– ––

Program Example
(1) This program stores data by 10 words starting from D0 in host CPU into W10 or later in CPU No.2 when X0 turns on.
[Ladder Mode] [List Mode]

732
 D.DDRD, DP.DDRD

Caution
1
(1) Digit specification of bit device is possible for n, S2 , and D1 . Note that when the digit specification of bit device is made to
S2 or D1 , the following conditions must be met.
• Digits are specified by 16 bits (4 digits). 10
• The start bit device is multiples of 16 (10H).
(2) Execute this instruction after checking that the write target CPU is powered on. Not doing so may end up no processing.
(3) If changing a range of the device specified at setting data between after execution of the instruction and turn-on of the 3
completion device, data to be stored by system (completion status, completion device) cannot be stored normally.
(4) SB, SW, SM, and SD include system information area. Take care not to destroy the system information when writing data
to the devices above with the D(P).DDWR instruction of the multiple CPU high-speed transmission dedicated instruction.
4
10.3 D.DDRD, DP.DDRD Reading Devices from Another CPU

6
Ver.
High
Basic performance Process Redundant Universal LCPU
• Universal model QCPU: The serial number (first five digits) is
"10012" or later.

10.3 D.DDRD, DP.DDRD • Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU cannot

be used. 6
Command
D.DDRD
7
D.DDRD n S1 S2 D1 D2

Command
DP.DDRD DP.DDRD n S1 S2 D1 D2

Internal Devices
8
Setting J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
n *1 –– –– ––
S1 *2 –– *3 *4 –– –– ––

10.3 D.DDRD, DP.DDRD

S2
*2 –– –– –– ––
D1
*2 –– –– –– ––
D2 *2 *6 –– *4 –– –– ––
*1: Index modification cannot be made to setting data n.
*2: Index modification cannot be made to setting data from S1 to D2 .
*3: Local devices cannot be used.
*4: File registers cannot be used per program.
*5: FD @ (indirect specification) cannot be used.
*6: FX and FY cannot be used.

Set Data
Setting data Description Data type
The result of dividing the start I/O number of another CPU by 16
n BIN 16 bits
CPU No.1: 3E0H, CPU No.2: 3E1H, CPU No.3: 3E2H, CPU No.4: 3E3H
S1 Start device of the host CPU that stores control data
Device name
S2 Start device of another CPU that stores data to be read
Device*7
D1 Start device of the host CPU where read data will be stored Character
string*8*9
D2 Completion device Bit
*7: By specifying a file register (R, ZR), data can be read to devices in another CPU, outside the range of host CPU.
*8: By specifying the start device by " ", data can be read to devices in another CPU, outside the range of host CPU.
*9: Indexed devices cannot be specified (e.g. D0Z0).

733
 D.DDRD, DP.DDRD

Control Data
Device Item Setting data Setting range Set by
An execution result upon completion of the
instruction is stored.
S1 +0 Completion status –– System
0000(H): No errors (normal completion)
Other than 0000(H): Error code (error completion)
Number of read
S2 +1 Set the number of read points in units of words. 1 to 100 User
points

Function
(1) In multiple CPU system, data stored in a device specified by another CPU (n) ( D1 ) or later is stored by the number of
read points specified by ( S1 +1) into a device specified by host CPU ( S2 ) or later.
Start device number of the storage
Start device number of the location where read has been stored
storage location for read data
D2 Host CPU Another CPU n S1
(CPU that requests reading) (CPU to be read)

Number of read points

S1 +1

(2) Whether to complete the D(P).DDRD instruction normally can be checked by the completion device ( D2 +0) and
completion status display device ( D2 +1).
(a) END processing in scan data that CPU completed the instruction turns on the device and the next END processing
turns off the device.
(b) This device turns on/off depending on the status upon completion of the instruction.
• Normal completion: Off
• Error completion: Turns on at END processing in the scan where the instruction has been completed, and turns
off at the next END processing (At error completion, an error code is stored at control data ( S1 +0): Completion
status)).
(3) The number of blocks used for the instruction depends on the number of read points (refer to Page 720, Section 10.1).
Number of blocks used for the instruction
Number of read points
D(P).DDRD instruction
specified by the instruction
1 to 100 1

(4) The instruction will be completed abnormally when there are no empty blocks in the multiple CPU high speed
transmission area.
Set the number of blocks used for the instruction at special registers (SD796 to SD799), and use the special relays
(SM796 to SM799) as an interlock prevent error completion (refer to Page 720, Section 10.1).

734
 D.DDRD, DP.DDRD

Operation Error
1
In any of the following cases, an operation error occurs, the error flag (SM0) turns on, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
10
code
Q01
Specified another CPU is incorrect. Or the multiple CPU high-speed
transmission dedicated instruction is disabled. 3
• The reserved CPU has been specified.
• A CPU that is not mounted has been specified.
• Another CPU start I/O number divided by 16n is not within the range
from 3E0H to 3E3H. 4
4350 • The instruction was executed when the module is set to "Do not use –– –– –– –– ––
multiple CPU high speed transmission".
• The instruction was executed with the CPU module that cannot use 6
this instruction.
• The host CPU has been specified.
• The CPU where the instruction cannot be executed has been
specified.
6
4351 Another CPU does not support this instruction. –– –– –– –– ––
4352 The number of devices is wrong. –– –– –– –– ––
4353 The device that cannot be used for the instruction has been specified. –– –– –– –– –– 7
A device has been specified by the character string that cannot be
4354 –– –– –– –– ––
used.
4355 The number of read points ( S1 +1) is other than 0 to 100. –– –– –– –– –– 8
In any of the following cases, the instruction is completed abnormally, and an error code is stored into a device specified
at completion status storage device ( S1 +0).
Q00J/

10.3 D.DDRD, DP.DDRD

Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The request of the instruction to the target CPU is more than the
0010H acceptable value (no empty block exists in the multiple CPU high speed –– –– –– –– ––
transmission area).
The device for another CPU specified at S2 cannot be used at another
1001H –– –– –– –– ––
CPU, or is out of device range.
The response of the instruction from another CPU module cannot be
1003H returned (no empty blocks exist in the multiple CPU high speed –– –– –– –– ––
transmission area).
The number of read points set with the D(P).DDRD instruction is other
1081H –– –– –– –– ––
than 0.

735
 D.DDRD, DP.DDRD

Program Example
(1) This program stores data by 10 words starting from D0 in CPU No.2 into W10 or later in host CPU when X0 turns on.
[Ladder Mode] [List Mode]

Caution
(1) Digit specification of bit device is possible for n, S2 , and D1 . Note that when the digit specification of bit device is made to
S2 or D1 , the following conditions must be met.
• Digits are specified by 16 bits (4 digits).
• The start bit device is multiples of 16 (10H).
(2) Execute this instruction after checking that the read target CPU is powered on. Not doing so may end up no processing.
(3) If changing a range of the device specified at setting data between after execution of the instruction and turn-on of the
completion device, data to be stored by system (completion status, completion device) cannot be stored normally.

736
 SP.CONTSW

CHAPTER 11 REDUNDANT SYSTEM INSTRUCTIONS

(For REDUNDANT CPU) 1

2
11.1 SP.CONTSW System Switching

11.1 SP.CONTSW Basic High

performance Process Redundant Universal LCPU

Command 11
SP.CONTSW SP.CONTSW S D

D
: Value other than 0 and used to identify the processing that issued the system switching request (BIN 16 bits)
: Error completion device number (bits)
4
Setting Internal Devices J \ Constants
R, ZR U \G Zn Other
Data Bit Word Bit Word K, H
S –– –– –– 4
D *1 –– –– ––
*1: The bit specification for the word device is available.
6
Function
(1) Switches between the control system and standby system at the END processing of the scan executed with the 7
SP.CONTSW instruction.
(2) When using the SP.CONTSW instruction for system switching, the "manual switching enable flag (SM1592)" must have
been turned ON (enabled) in advance. 8
(3) S is provided to identify the processing block of the program where system switching occurred when multiple
SP.CONTSW instructions are used.
At S , specify a value within the ranges -32768 to -1 and 1 to 32767 (1H to FFFFH).

11.1 SP.CONTSW
The S value specified by the SP.CONTSW instruction is stored into the "system switching instruction argument (SD6)" of
the error common information when the system switching is normally completed. *2
When multiple SP.CONTSW instructions are executed during the same scan, the argument of the SP.CONTSW
instruction executed first is stored into the system switching instruction argument (SD6).
(4) The S value specified by the SP.CONTSW instruction is stored into the "system switching instruction argument
(SD1602)" of the new control system CPU module when system switching is normally completed. *3
By reading the SD1602 value from the new control system CPU module, which the SP.CONTSW instruction was used
for system switching can be confirmed.
*2: The S value specified for the SP.CONTSW instruction can be confirmed in the error common information of the PLC
diagnostics dialog box on GX Developer.
*3: The new control system CPU module means the CPU module that was switched from the standby system to the control
system by the SP.CONTSW instruction.
(5) The error completion device is turned ON by the control system CPU module when system switching by the
SP.CONTSW instruction was unsuccessful.
(a) When OPERATION ERROR is detected due to any of the following reasons at the execution of the SP.CONTSW
instruction, the error completion device is turned ON during the instruction execution.
• 0 is specified at S of the executed SP.CONTSW instruction.
• The "manual switching enable flag (SM1592)" is OFF.
• The SP.CONTSW instruction was executed by the standby system in the separate mode.
• The SP.CONTSW instruction was executed in the debug mode.

737
 SP.CONTSW

(b) If systems could not be switched due to any of the reasons given in the following table, the error completion device
turns ON when system switching is executed in the END processing.
Reason No. Reasons for System Switching Failure
0 Normally completed
1 Tracking cable is disconnected or faulty.
Hardware fault, power-off, reset or watchdog timer error occurred in the
2
standby system.
3 Watchdog timer error occurred in the control system.
4 Preparations being made for tracking transfer.
5 Communication time-out.
6 Stop error occurred in the standby system. (Excluding watchdog timer error)
7 Operating status different between the control system and standby system.
8 Memory copy being executed from the control system to the standby system.
9 Write during RUN being executed.
10 Network fault detected by the standby system.
When the error completion device was turned ON due to unsuccessful system switching, 16 is stored into the
"reason(s) for system switching (SD1588)" and the reason No. of the above table into the "reason(s) for system
switching failure (SD1589)".
(6) Use a user program or GX Developer to turn OFF the error completion bit that has turned ON.
If normal system switching is performed by the execution of the SP.CONTSW instruction with the error completion device
ON, the error completion device of the new standby system CPU module is also turned OFF.
When system switching is performed due to a factor other than the SP.CONTSW instruction, however, the error
completion device is not turned OFF.

Operation Error
(1) In any of the following cases, an operation error occurs, the error flag (SM0) turns ON, and an error code is stored into
SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The value specified at S is 0 at execution of the SP.CONTSW
4110 –– –– –– –– ––
instruction.
The manual switching enable flag (SM1592) is OFF (disabled) at the
4120 –– –– –– –– ––
execution of the SP.CONTSW instruction.
The SP.CONTSW instruction was executed by the standby system CPU
4121 module in the separate mode. –– –– –– –– ––
The SP.CONTSW instruction was executed in the debug mode.

(2) If system switching was unsuccessful, the error flag (SM0) is turned ON and an error code is stored into SD0.
Q00J/
Error
Error details Q00/ QnH QnPH QnPRH QnU LCPU
code
Q01
The tracking cable is disconnected or faulty.
Hardware fault, power-off, reset or watchdog timer error occurred in the
standby system.
Watchdog timer error occurred in the control system.
Preparations are being made for tracking transfer.
Communication time-out occurred.
A stop error, excluding watchdog timer error, occurred in the standby
6220 –– –– –– –– ––
system.
The operating status differs between the control system and standby
system.
Memory copy is being executed from the control system to the standby
system.
Writing during RUN
Network fault was detected by the standby system.

738
 SP.CONTSW

Program Example
(1) The following program executes system switching on the leading edge of the system switching command (M100).
1
If the system switching command (M100) remains ON, the SP.CONTSW instruction is also executed by the new control
system CPU module after system switching. Therefore, M101 is added to the execution conditions as a consecutive
switching prevention flag.
2
[Ladder Mode] [List Mode]
Step Instruction Device 11

11.1 SP.CONTSW

739
APPENDICES

Appendix 1 OPERATION PROCESSING TIME

Appendix 1.1 Definition

(1) Processing time taken by the QCPU, LCPU is the total of the following processing times.
• Total of each instruction processing time
• END processing time (including I/O refresh time)
• Processing time for the function that increases the scan time
(2) Instruction processing time
This is the total of processing time of each instruction shown in Page 741, Appendix 1.2, Page 757, Appendix 1.3 and
Page 781, Appendix 1.4.
(3) END processing time, I/O refresh time, and processing time for the function that increases the scan time
Refer to the following manual(s) for the END processing time, I/O refresh time, and processing time for the function that
increases the scan time.
(a) For QCPUs
• QnUCPU User's Manual (Functions Explanation, Program Fundamentals)
• Qn(H)/QnPH/QnPRHCPU User's Manual
(Functions Explanation, Program Fundamentals)
• MELSEC-L CPU Module User's Manual
(Functions Explanation, Program Fundamentals)

740
Appendix 1.2 Operation Processing Time of Basic Model QCPU

The processing time for the individual instructions are shown in the table on the following pages. 3
Operation processing times can vary substantially depending on t
he nature of the sources and destinations of the instructions, and the values contained in the following tables should therefore
be taken as a set of general guidelines to processing time rather than as being strictly accurate.
2

When using a file resister (ZR), module access device (Un\G , U3En\G0 to G511), and link direct device (Jn\ ), add the
3
processing time shown in Page 756, Appendix 1.2(7) to that of the instruction.

(1) Sequence instructions A

Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
LD
X0 0.20 0.16 0.10
5
LDI
AND
ANI
OR D0.0 0.30 0.24 0.15 6
ORI
LDP
LDF
ANDP
X0
7
0.30 0.24 0.15
ANDF
ORP D0.0
ORF 8
ANB
ORB
MPS –– 0.20 0.16 0.10
MRD

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME
MPP
When not executed
INV 0.20 0.16 0.10
When executed
MEP When not executed
0.30 0.24 0.15
MEF When executed
When not (OFF OFF)
executed (ON ON)
EGP 0.20 0.16 0.10
When (OFF ON)
executed (ON OFF)
When not (OFF OFF)
17 9.5 9.4
executed (ON ON)
EGF
When (OFF ON)
18 14 14
executed (ON OFF)
When not (OFF OFF)
0.20 0.16 0.10
changed (ON ON)
Y
When (OFF ON)
0.20 0.16 0.10
changed (ON OFF)
When not (OFF OFF)
0.40 0.32 0.20
OUT changed (ON ON)
D0.0
When (OFF ON)
0.40 0.32 0.20
changed (ON OFF)
When OFF 24 20 19
F When When displayed 260 210 200
ON Display completed 205 165 155

741
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not executed 1.1 0.88 0.55
After time up 1.1 0.88 0.55
T When
K 1.1 0.88 0.55
executed When added
D 1.2 0.96 0.60
OUT
When not executed 1.1 0.88 0.55
After time up 1.1 0.88 0.55
C When
K 1.1 0.88 0.55
executed When added
D 1.2 0.96 0.60
When not executed 1.1 0.88 0.55
After time up 1.1 0.88 0.55
OUTH T When
K 1.1 0.88 0.55
executed When added
D 1.2 0.96 0.60
When not executed 0.20 0.16 0.10
When not changed
0.20 0.16 0.10
Y When (ON ON)
executed When changed
0.20 0.16 0.10
(OFF ON)
When not executed 0.40 0.32 0.20
SET When not changed
0.40 0.32 0.20
D0.0 When (ON ON)
executed When changed
0.40 0.32 0.20
(OFF ON)
When not executed 0.50 0.44 0.25
F When When displayed 255 205 195
executed Display completed 195 160 150
When not executed 0.20 0.16 0.10
When not changed
0.20 0.16 0.10
Y When (OFF OFF)
executed When changed
0.20 0.16 0.10
(ON OFF)
When not executed 0.40 0.32 0.20
When not changed
0.40 0.32 0.20
D0.0 When (ON ON)
executed When changed
0.40 0.32 0.20
(OFF ON)
When not executed 0.20 0.16 0.10
SM
RST When executed 0.20 0.16 0.10
When not executed 0.48 0.44 0.25
F When When displayed 75 69 65
executed Display completed 43 35 33
When not executed 0.80 0.64 0.40
T, C
When executed 1.0 0.80 0.50
When not executed 0.40 0.32 0.20
D
When executed 0.60 0.48 0.30
When not executed 0.50 0.40 0.25
Z
When executed 9.4 7.9 7.4
When not executed –– 0.32 0.20
R
When executed –– 0.48 0.30
PLS 12 9.5 9.2
PLF 11 9.5 8.9
When not executed 0.68 0.40 0.25
FF Y
When executed 7.5 6.2 5.7
When not executed 0.50 0.40 0.25
DELTA DY0
When executed 26 21 21
When not executed 0.48 0.40 0.25
DELTAP DY0
When executed 58 45 43

742
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
SFT When not executed 0.50 0.34 0.25 3
SFTP When executed 12 8.7 8.3
M0 0.40 0.32 0.20
MC

MCR
D0.0
––
3.3
0.20
2.9
0.16
2.8
0.10
2
Error check performed 660 600 520
No error check performed
FEND
END
(• Battery check)
660 600 520
3
(• Fuse blown check)
(• I/O module verification)
NOP
NOPLF
–– 0.20 0.16 0.10
A
–– 0.20 0.16 0.10
PAGE

(2) Basic instructions 5

The processing time when the instruction is not executed is calculated as follows:
Q00JCPU : 0.20 × (No. of steps for each instruction + 1) µs
Q00CPU : 0.16 × (No. of steps for each instruction + 1) µs 6
Q01CPU : 0.10 × (No. of steps for each instruction + 1) µs
Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU 7
In conductive status 0.80 0.64 0.40
LD =
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35 8
AND = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME
In conductive status 0.80 0.64 0.40
LD < >
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND < > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR < > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD >
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR > In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD < =
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND < = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR < = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD <
In non-conductive status 0.80 0.64 0.40

743
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not executed 0.70 0.56 0.35
AND < In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR < In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 0.80 0.64 0.40
LD > =
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
AND > = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
When not executed 0.70 0.56 0.35
OR > = In conductive status 0.80 0.64 0.40
When executed
In non-conductive status 0.80 0.64 0.40
In conductive status 1.0 0.80 0.50
LDD =
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ORD = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
In conductive status 1.0 0.80 0.50
LDD < >
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD < > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ORD < > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
In conductive status 1.0 0.80 0.50
LDD >
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ORD > In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
In conductive status 1.0 0.80 0.50
LDD < =
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD < = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ORD < = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
In conductive status 1.0 0.80 0.50
LDD <
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ANDD < In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
When not executed 0.80 0.64 0.40
ORD < In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50
In conductive status 1.0 0.80 0.50
LDD > =
In non-conductive status 1.0 0.80 0.50

744
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not executed 0.80 0.64 0.40 3
ANDD > = In conductive status 1.0 0.80 0.50
When executed
In non-conductive status 1.0 0.80 0.50

ORD > =
When not executed
In conductive status
0.80
1.0
0.64
0.80
0.40
0.50
2
When executed
In non-conductive status 1.0 0.80 0.50
BKCMP = n n=1 130 105 97
3
S1 S2 D

BKCMP = P S1 S2 D n n = 96 205 175 165

BKCMP<> S1 S2 D n n=1 130 105 98

BKCMP<>P S1 S2 D n n = 96 210 180 165

A
BKCMP> S1 S2 D n n=1 130 105 97

BKCMP>P S1 S2 D n n = 96 210 180 165

BKCMP>= S1 S2 D n n=1 130 105 98 5

BKCMP>=P S1 S2 D n n = 96 205 175 165

BKCMP< S1 S2 D n n=1 130 105 98

BKCMP<P S1 S2 D n n = 96 210 180 165 6

BKCMP<= S1 S2 D n n=1 130 105 97

BKCMP<=P S1 S2 D n n = 96 205 175 165

+ S D
7
When executed 1.0 0.80 0.50
+P S D

+ S1 S2 D
When executed 1.2 0.96 0.60 8
+P S1 S2 D

- S D
When executed 1.0 0.80 0.50
-P S D

- S1 S2 D
When executed 1.2 0.96 0.60

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME
-P S1 S2 D

D+ S D
When executed 1.3 1.04 0.65
D+P S D

D+ S1 S2 D
When executed 1.5 1.2 0.75
D+P S1 S2 D

D- S D
When executed 1.3 1.04 0.65
D-P S D

D- S1 S2 D
When executed 1.5 1.2 0.75
D-P S1 S2 D

* S1 S2 D
When executed 1.1 0.88 0.55
*P S1 S2 D

/ S1 S2 D
–– 19 16 15
/P S1 S2 D

D* S1 S2 D
–– 41 34 31
D*P S1 S2 D

D/ S1 S2 D
–– 28 23 21
D/P S1 S2 D

B+ S D
–– 34 28 26
B+P S D

B+ S1 S2 D
–– 47 39 37
B+P S1 S2 D

745
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
B- S D
–– 34 28 26
B-P S D

B- S1 S2 D
–– 48 40 38
B-P S1 S2 D

DB+ S D
–– 58 48 44
DB+P S D

DB+ S1 S2 D
–– 60 49 46
DB+P S1 S2 D

DB - S D
–– 59 48 45
DB - P S D

DB - S1 S2 D
–– 60 51 45
DB - P S1 S2 D

B* S1 S2 D
–– 42 35 33
B*P S1 S2 D

B/ S1 S2 D
–– 48 40 37
B/P S1 S2 D

DB * S1 S2 D
–– 140 120 110
DB * P S1 S2 D

DB/ S1 S2 D
–– 83 69 65
DB/P S1 S2 D

BK + S1 S2 D n n=1 105 86 80

BK + P S1 S2 D n n = 96 185 155 140

BK - S1 S2 D n n=1 105 86 80

BK - P S1 S2 D n n = 96 185 155 140

INC
–– 0.70 0.56 0.35
INCP
DINC
–– 0.90 0.72 0.45
DINCP
DEC
–– 0.70 0.56 0.35
DECP
DDEC
–– 0.90 0.72 0.45
DDECP
BCD
–– 20 16 15
BCDP
DBCD
–– 26 21 20
DBCDP
BIN
–– 19 16 15
BINP
DBIN
–– 22 18 17
DBINP
DBL
–– 19 16 15
DBLP
WORD
–– 23 19 17
WORDP
GRY
–– 19 16 15
GRYP
DGRY
–– 23 19 17
DGRYP
GBIN
–– 52 42 40
GBINP

746
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
DGBIN
–– 110 88 84
3
DGBINP
NEG
–– 16 13 12
NEGP
DNEG
2
–– 19 17 15
DNEGP
BKBCD S D n n=1 78 63 57

BKBCDP S D n n = 96 315 275 250 3

BKBIN S D n n=1 74 61 57
n = 96 285 255 230
BKBINP S D n
0.70 0.56 0.35
A
MOV S = D0, D = D1
MOVP S = D0, D = J1 \ W1 155 130 120

DMOV S = D0, D = D1 0.90 0.72 0.45

5
DMOVP S = D0, D = J1 \ W1 165 135 120
$MOV 0 characters 46 38 35
$MOVP 32 characters 98 80 73 6
CML
–– 0.70 0.56 0.35
CMLP
DCML
DCMLP
–– 0.90 0.72 0.45 7
BMOV S D n n=1 27 21 20
n = 96 72 62 53
BMOVP n
8
S D

FMOV S D n n=1 23 19 17

FMOVP S D n n = 96 48 41 36
XCH
–– 7.6 6.3 5.7
XCHP

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME
DXCH
–– 9.5 8.0 7.1
DXCHP

BXCH D1 D2 n n=1 62 51 48

BXCHP D1 D2 n n = 96 165 140 125

SWAP
–– 17 14 13
SWAPP
CJ –– 10 8.5 8.1
SCJ –– 10 8.5 8.1
JMP –– 11 8.5 8.1
GOEND –– 3.3 2.9 2.8
DI –– 13 12 11
EI –– 14 11 11
IMASK –– 41 34 35
IRET –– 205 170 155
n=1 55 46 43
X
RFS n = 96 79 64 59
RFSP n=1 54 45 41
Y
n = 96 73 61 56

747
(3) Application instructions
The processing time when the instruction is not executed is calculated as follows:
Q00JCPU : 0.20 × (No. of steps for each instruction + 1) µs
Q00CPU : 0.16 × (No. of steps for each instruction + 1) µs
Q01CPU : 0.10 × (No. of steps for each instruction + 1) µs
Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
WAND S D
When executed 1.0 0.80 0.50
WANDP S D

WAND S1 S2 D
When executed 1.2 0.96 0.60
WANDP S1 S2 D

DAND S D
When executed 1.3 1.04 0.65
DANDP S D

DAND S1 S2 D
When executed 1.5 1.2 0.75
DANDP S1 S2 D

BKAND S1 S2 D n n=1 110 87 79

BKANDP S1 S2 D n n = 96 185 155 140

WOR S D
When executed 1.0 0.80 0.50
WORP S D

WOR S1 S2 D
When executed 1.2 0.96 0.60
WORP S1 S2 D

DOR S D
When executed 1.3 1.04 0.65
DORP S D

DOR S1 S2 D
When executed 1.5 1.2 0.75
DORP S1 S2 D

BKOR S1 S2 D n n=1 110 87 81

BKORP S1 S2 D n n = 96 185 155 140

WXOR S D
When executed 1.0 0.80 0.50
WXORP S D

WXOR S1 S2 D
When executed 1.2 0.96 0.60
WXORP S1 S2 D

DXOR S D
When executed 1.3 1.04 0.65
DXORP S D

DXOR S1 S2 D
When executed 1.5 1.2 0.75
DXORP S1 S2 D

BKXOR S1 S2 D n n=1 110 87 81

BKXORP S1 S2 D n n = 96 185 155 140

WXNR S D
When executed 1.0 0.80 0.50
WXNRP S D

WXNR S1 S2 D
When executed 1.2 0.96 0.60
WXNRP S1 S2 D

DXNR S D
When executed 1.3 1.04 0.65
DXNRP S D

DXNR S1 S2 D
When executed 1.5 1.2 0.75
DXNRP S1 S2 D

BKXNR S1 S2 D n n=1 110 87 82

BKXNRP S1 S2 D n n = 96 185 155 140

ROR D n n=1 13 11 9.7

RORP D n n = 15 13 11 9.7

748
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
RCR D n n=1 15 12 12 3
RCRP D n n = 15 15 13 12

ROL D n n=1 13 11 10

ROLP D n n = 15 13 11 10 2
RCL D n n=1 15 13 12
n = 15 16 13 12
RCLP n
3
D

DROR D n n=1 15 12 12

DRORP D n n = 31 15 13 12

DRCR D n n=1 17 14 14
A
DRCRP D n n = 31 18 16 15

DROL D n n=1 14 13 12

DROLP D n n = 31 14 13 12 5
DRCL D n n=1 18 15 14

DRCLP D n n = 31 20 17 16

SFR D n n=1 13 10 9.7 6

SFRP D n n = 15 13 11 9.5

SFL n n=1 12 10 9.5

7
D

SFLP D n n = 15 12 9.8 9.5

BSFLR D n n=1 42 35 33

BSFLRP D n n = 96 69 58 54
8
BSFL D n n=1 41 34 32

BSFLP D n n = 96 63 53 50

DSFR D n n=1 19 16 15

DSFRP D n n = 96 71 61 53

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME
DSFL D n n=1 19 16 15

DSFLP D n n = 96 70 60 52

BSET D n n=1 27 22 20

BSETP D n n = 15 27 22 20

BRST D n n=1 27 22 21

BRSTP D n n = 15 27 22 21

TEST S1 S2 D
–– 35 30 27
TESTP S1 S2 D

DTEST S1 S2 D
–– 37 31 28
DTESTP S1 S2 D

BKRST D n n=1 49 41 38

BKRSTP D n n = 96 64 54 50
All match 56 54 42
n=1
SER S1 S2 D n None match 56 54 42
SERP S1 S2 D n All match 280 240 220
n = 96
None match 280 240 220
All match 71 67 53
n=1
DSER S1 S2 D n None match 71 67 54
DSERP S1 S2 D n All match 495 415 375
n = 96
None match 500 415 375

SUM S =0 32 26 25
SUMP S = FFFFH 27 22 21

749
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU

DSUM S =0 54 44 42
DSUMP S = FFFFFFFFH 54 44 42

DECO S D n n=2 60 50 46

DECOP S D n n=8 80 65 61
M1 = ON 66 55 51
n=2
ENCO S D n M4 = ON 66 54 51
ENCOP S D n M1 = ON 90 76 71
n=8
M256 = ON 76 74 71
SEG
–– 8.0 6.8 6.1
SEGP
DIS S D n n=1 47 39 36

DISP S D n n=4 53 43 40

UNI S D n n=1 54 44 41

UNIP S D n n=4 60 49 46

NDIS S1 D S2
–– 92 76 38
NDISP S1 D S2

NUNI S1 D S2
–– 47 39 36
NUNIP S1 D S2

WTOB S D n n=1 56 46 42

WTOBP S D n n = 96 190 155 145

BTOW S D n n=1 56 46 42

BTOWP S D n n = 96 190 155 145

MAX S D n n=1 48 40 36

MAXP S D n n = 96 300 240 235

MIN S D n n=1 48 40 36

MINP S D n n = 96 300 240 235

DMAX S D n n=1 52 43 39

DMAXP S D n n = 96 600 490 460

DMIN S D n n=1 52 43 39

DMINP S D n n = 96 585 475 445

n = 1, S2 =1 66 55 50
SORT S1 n S2 D1 D2
n = 96, S2 = 16 329 270 252

n = 1, S2 =1 98 57 52
DSORT S1 n S2 D1 D2
n = 96, S2 = 16 386 317 294

WSUM S D n n=1 52 43 40

WSUMP S D n n = 96 175 140 135

DWSUM S D n n=1 61 51 46

DWSUMP S D n n = 96 515 420 395

FOR n n=0 11 8.9 8.1
NEXT –– 8.8 7.3 6.8
BREAK
–– 37 30 28
BREAKP
CALL Pn
–– 17 14 13
CALLP Pn

CALL Pn S1 to S5
–– 245 200 190
CALLP Pn S1 to S5

RET Return to original program 16 13 12

750
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
FCALL Pn
–– 29 24 22
3
FCALLP Pn

FCALL Pn S1 to S5
–– 250 205 190
FCALLP Pn S1 to S5 2
COM –– 110 77 72
IX –– 65 54 51
IXEND ––
Number of contacts 1
30
145
26
120
25
110
3
IXDEV + IXSET
Number of contacts 14 770 630 585
FIFW Number of data points 0 36 32 28
FIFWP Number of data points 96 36 32 28 A
FIFR Number of data points 1 45 41 36
FIFRP Number of data points 96 93 82 70
FPOP Number of data points 1 40 37 32 5
FPOPP Number of data points 96 40 37 32
FINS Number of data points 0 53 44 38
FINSP
FDEL
Number of data points 96
Number of data points 1
100
60
89
50
76
43
6
FDELP Number of data points 96 110 95 82
FROM n1 n2 D n3 n3 = 1 125 105 93

FROMP n1 n2 D n3 *1 n3 = 1000 740 695 685 7

DFRO n1 n2 D n3 n3 = 1 130 110 100

DFROP n1 n2 n3 *1 n3 = 500 745 695 675

8
D

TO n1 n2 S n3 n3 = 1 120 105 92

TOP n1 n2 S n3 *1 n3 = 1000 735 680 645

DTO n1 n2 S n3 n3 = 1 130 110 99

DTOP n1 n2 S n3 *1 n3 = 500 740 680 640

LIMIT

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME
–– 34 28 26
LIMITP
DLIMIT
–– 41 34 30
DLIMITP
BAND
–– 33 28 25
BANDP
DBAND
–– 40 34 30
DBANDP
ZONE
–– 31 25 24
ZONEP
DZONE
–– 37 29 28
DZONEP
RSET
–– –– 18 16
RSETP
DATERD
–– 30 25 23
DATERDP
DATEWR
–– 69 57 54
DATEWRP
DATE+ No digit increase 47 39 36
DATE+P Digit increase 50 42 38
DATE - No digit increase 47 40 36
DATE - P Digit increase 50 42 38
SECOND
–– 28 24 22
SECONDP
*1: The FROM/TO instruction differs in processing time according to the number of slots and the loaded modules. (The CPU also
differs in processing time according to the extension base type.)

751
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
HOUR
–– 38 32 29
HOURP
WDT
–– 18 15 14
WDTP
DUTY –– 41 36 32
ZRRDB
–– –– 24 22
ZRRDBP
ZRWRB
–– –– 27 24
ZRWRBP
ADRSET
–– 23 19 18
ADRSETP
ZPUSH
–– 38 33 30
ZPUSHP
ZPOP
–– 37 31 29
ZPOPP

(4) Data link instruction

The processing time when the instruction is not executed is calculated as follows:
Q00JCPU : 0.20 × (No. of steps for each instruction + 1) µs
Q00CPU : 0.16 × (No. of steps for each instruction + 1) µs
Q01CPU : 0.10 × (No. of steps for each instruction + 1) µs
Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
ZCOM –– 105 82 80

(5) Processing time for QCPU instructions (QCPU instructions only)

Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
UNIRD n=1 96 80 74
UNIRDP n = 16 440 370 340

(6) Instructions executable by the product with the first 5 digits of the serial No. "04122" or higher
Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
In conductive status 43.0 35.5 33.0
LDE = Single precision
In non-conductive status 46.0 38.0 35.5
When not executed 1.5 1.2 1.0
ANDE = Single precision When In conductive status 35.5 29.5 26.5
executed In non-conductive status 42.0 35.0 32.5
When not executed 1.5 1.2 1.0
ORE = Single precision When In conductive status 42.0 35.0 32.5
executed In non-conductive status 37.0 31.0 28.5
In conductive status 46.0 38.0 35.5
LDE < > Single precision
In non-conductive status 43.5 36.0 33.0
When not executed 1.5 1.2 1.0
ANDE < > Single precision When In conductive status 38.5 31.5 29.0
executed In non-conductive status 39.5 33.0 30.5
When not executed 1.5 1.2 1.0
ORE < > Single precision When In conductive status 45.0 37.5 35.0
executed In non-conductive status 34.5 29.0 26.5
In conductive status 46.0 37.5 35.5
LDE > Single precision
In non-conductive status 46.0 38.5 35.0

752
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not executed 1.5 1.2 1.0
ANDE > Single precision When In conductive status 38.5 32.0 29.0
3
executed In non-conductive status 42.0 35.0 32.5
When not executed 1.5 1.2 1.0
ORE > Single precision When In conductive status 45.0 37.5 34.5 2
executed In non-conductive status 37.0 31.0 29.0
In conductive status 45.5 37.5 35.0
LDE < = Single precision
In non-conductive status
When not executed
46.5
1.5
38.5
1.2
35.5
1.0
3
ANDE < = Single precision When In conductive status 38.5 31.5 29.0
executed In non-conductive status 42.5 35.5 32.5
A

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME

753
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
When not executed 1.5 1.2 1.0
ORE < = Single precision When In conductive status 45.0 37.5 34.5
executed In non-conductive status 37.5 31.5 28.5
In conductive status 45.5 37.5 35.0
LDE < Single precision
In non-conductive status 46.5 38.5 35.5
When not executed 1.5 1.2 1.0
ANDE < Single precision When In conductive status 38.0 31.5 29.0
executed In non-conductive status 42.5 35.5 32.5
When not executed 1.5 1.2 1.0
ORE < Single precision When In conductive status 45.0 37.5 34.5
executed In non-conductive status 37.5 31.5 29.0
In conductive status 45.5 38.0 35.5
LDE > = Single precision
In non-conductive status 46.5 38.0 35.0
When not executed 1.5 1.2 1.0
ANDE > = Single precision When In conductive status 38.5 32.0 29.0
executed In non-conductive status 42.5 35.5 32.5
When not executed 1.5 1.2 1.0
ORE > = Single precision When In conductive status 45.0 38.5 34.5
executed In non-conductive status 37.5 31.0 28.5

E+ S D S = 0, D =0 29.5 25.0 23.0

Single precision
E+P S D S = 2127, D = 2127 65.5 60.5 49.5

E+ S1 S2 D S1 = 0, S2 =0 31.0 27.0 24.0

Single precision
E+P S1 S2 D S1 = 2127, S2 = 2127 66.5 56.0 51.0

E- S D S = 0, D =0 29.5 25.0 23.0

Single precision
E -P S D S = 2127, D = 2127 48.5 41.0 37.5

E- S1 S2 D S1 = 0, S2 =0 31.0 27.0 24.0

Single precision
E -P S1 S2 D S1 = 2127, S2 = 2127 50.5 42.5 38.5

E* S1 S2 D S1 = 0, S2 =0 30.0 25.5 23.0

Single precision
E*P S1 S2 D S1 = 2127, S2 = 2127 65.5 55.0 49.5

E/ S1 S2 D S1 = 0, S2 =1 30.0 26.0 23.0

Single precision
E/P S1 S2 D S1 = 2127, S2 = - 2126 69.5 57.5 53.0

INT S =0 21.5 18.5 16.0

Single precision
INTP S = 32766.5 38.0 32.0 29.5

DINT S =0 23.0 19.5 17.5

Single precision
DINTP S = 1234567890.3 42.0 35.5 32.0

FLT S =0 22.5 19.5 17.0

Single precision
FLTP S = 7FFFH 26.5 23.0 20.0

DFLT S =0 23.0 20.0 17.5

Single precision
DFLTP S = 7FFFFFFFH 26.0 23.5 19.5

ENEG S =0 20.5 17.0 15.5

ENEGP S = E - 1.0 31.5 26.0 24.0
EMOV
–– 1.5 1.2 1.0
EMOVP
ESTR
–– 604.0 686.0 831.0
ESTRP
EVAL Decimal point format all 2-digit specification 138.0 148.0 196.0
EVALP Exponent format all 6-digit specification 164.0 177.0 214.0

754
 Processing Time (µs)
Instruction Condition (Device)
Q00JCPU Q00CPU Q01CPU
SIN
Single precision 204.0 173.0 157.0
3
SINP
COS
Single precision 187.0 158.0 144.0
COSP
TAN
2
Single precision 224.0 190.0 173.0
TANP
RAD
RADP
Single precision 51.0 43.0 39.0
3
DEG
Single precision 51.0 43.0 39.0
DEGP
SQR
SQRP
Single precision 60.0 51.0 46.5 A
EXP S = - 10 306.0 259.0 235.0
Single precision
EXPP S =1 306.0 259.0 235.0
5
LOG S =1 73.0 61.5 56.0
Single precision
LOGP 301.0 255.0 232.0
S = 10
RND
–– 12.5 11.0 10.0
6
RNDP
SRND
–– 13.5 12.0 11.0
SRNDP
7

Appendix 1.2Operation Processing Time of Basic Model QCPU

Appendix 1OPERATION PROCESSING TIME

755
Instruction Processing Time (µs)
Condition/Number of Points Processed
Name Q00JCPU Q00CPU Q01CPU
With auto refresh of CPU Refresh range: 2k words
–– 920 880
shared memory (0.5k words assigned equally to all CPUs)
COM *2
Without auto refresh of
–– –– 150 135
CPU shared memory
Read from CPU shared n3 = 1 –– 100 90
memory of host CPU n3 = 320 –– 440 420
FROM
Read from CPU shared n3 = 1 –– 110 105
memory of another CPU n3 = 320 –– 305 290
Write to CPU shared n3 = 1 –– 100 95
TO
memory of host CPU n3 = 320 –– 440 425
Write to CPU shared n4 = 1 –– 205 195
S.TO
memory of host CPU n4 = 320 –– 545 525
*2: If the processing overlaps those of the other CPUs in a multiple CPU system, the processing time increases by a maximum of
the following time.
For a system having only the main base unit
(Instruction processing time increase) = 4 0.54 (number of points processed) (number of other CPUs) (µs)
For a system including extension base units
(Instruction processing time increase) = 4 1.30 (number of points processed) (number of other CPUs) (µs)
(7) Table of the time to be added when file register, module access device or link direct device is used
Device Specification Processing Time (µs)
Instruction Name Data
Location Q00JCPU Q00CPU Q01CPU
Source –– 34 32
Bit
Destination –– 23 22
Source –– 13 12
File register (ZR) Word
Destination –– 9 8
Double Source –– 14 13
word Destination –– 10 9
Source 99 82 77
Bit
Destination 167 137 129
Module access device Source 74 61 58
Word
(Un\G , U3En\G0 to G511) Destination 72 60 56
Double Source 76 63 59
word Destination 92 75 71
Source 178 147 137
Bit
Destination 303 248 233
Source 154 126 118
Link direct device (Jn\ ) Word
Destination 153 125 117
Double Source 155 127 119
word Destination 163 133 125

756
Appendix 1.3 Operation Processing Time of High Performance Model
QCPU/Process CPU/Redundant CPU 3
The processing time for the individual instructions are shown in the table on the following pages.
Operation processing time can vary substantially depending on the nature of the sources and destinations of the instructions,
2
and the values contained in the following tables should therefore be taken as a set of general guidelines to processing times
rather than as being strictly accurate.

3
When using a file resister (ZR), module access device (Un\G , U3En\G0 to G4095), and link direct device (Jn\ ), add the
processing time shown in Page 779, Appendix 1.3(6) to that of the instruction.
A

(1) Sequence instructions

Processing Time (µs) 5
Instruction Condition (Device)
Qn QnH QnPH QnPRH
LD
LDI 6
AND
–– 0.079 0.034 0.034 0.034
ANI
OR
ORI 7
LDP
LDF
ANDP
–– 0.158 0.068 0.068 0.068 8
ANDF
ORP
ORF
ANB
ORB

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
MPS –– 0.079 0.034 0.034 0.034
MRD

CPU
MPP
When not executed
INV 0.079 0.034 0.034 0.034
When executed
MEP When not executed
0.173 0.073 0.073 0.073
MEF When executed
(OFF OFF)
When not executed
EGP (ON ON)
0.158 0.068 0.068 0.068
EGF (OFF ON)
When executed
(ON OFF)
(OFF OFF)
When not changed 0.158 0.068 0.068 0.068
(ON ON)
(OFF ON)
When changed 0.158 0.068 0.068 0.068
(ON OFF)
When OFF 2.8 1.2 1.2 1.2
F When When displayed 162 69.7 69.7 69.7
ON Display completed 126 54 54 54
OUT When not executed 0.63 0.27 0.27 0.27
After time up 0.63 0.27 0.27 0.27
T When
K 0.63 0.27 0.27 0.27
executed When added
D 0.63 0.27 0.27 0.27
When not executed 0.63 0.27 0.27 0.27
After time up 0.63 0.27 0.27 0.27
C When
K 0.63 0.27 0.27 0.27
executed When added
D 0.63 0.27 0.27 0.27

757
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
When not executed 0.63 0.27 0.27 0.27
After time up 0.63 0.27 0.27 0.27
OUTH T When
K 0.63 0.27 0.27 0.27
executed When added
D 0.63 0.27 0.27 0.27
When not executed 0.158 0.068 0.068 0.068
When not changed (ON ON) 0.158 0.068 0.068 0.068
When executed
When changed (OFF ON) 0.158 0.068 0.068 0.068
SET
When not executed 0.47 0.20 0.20 0.20
F When When displayed 161 69 69 69
executed Display completed 0.47 0.20 0.20 0.20
When not executed 0.158 0.068 0.068 0.068
When not changed
0.158 0.068 0.068 0.068
When executed (OFF OFF)
When changed (ON OFF) 0.158 0.068 0.068 0.068
When not executed 0.158 0.068 0.068 0.068
SM
When executed 0.158 0.068 0.068 0.068
When not executed 0.47 0.20 0.20 0.20
F When When displayed 90 38 38 38
RST executed Display completed 0.47 0.20 0.20 0.20
When not executed 0.63 0.27 0.27 0.27
T, C
When executed 0.63 0.27 0.27 0.27
When not executed 0.24 0.10 0.10 0.10
D
When executed 0.24 0.10 0.10 0.10
When not executed 0.47 0.20 0.20 0.20
Z
When executed 4.3 1.9 1.9 1.9
When not executed 0.40 0.17 0.17 0.17
R
When executed 0.40 0.17 0.17 0.17
PLS
–– 1.0 0.44 0.44 0.44
PLF
When not executed 0.47 0.20 0.20 0.20
FF Y
When executed 0.47 0.20 0.20 0.20
DELTA When not executed 0.47 0.20 0.20 0.20
DY0
DELTAP When executed 5.9 2.6 2.6 2.6
SFT When not executed 0.47 0.20 0.20 0.20
SFTP When executed 1.66 0.71 0.71 0.71
MC –– 0.24 0.10 0.10 0.10
MCR –– 0.079 0.034 0.034 0.034
Error check performed 380 150 150 500
No error check performed
FEND
(• Battery check)
END 380 150 150 500
(• Fuse blown check)
(• I/O module verification)
NOP –– 0.079 0.034 0.034 0.034
NOPLF
–– 0.079 0.034 0.034 0.034
PAGE

758
(2) Basic instructions
The processing time when the instruction is not executed is calculated as follows:
Q02CPU : 0.079 × (No. of steps for each instruction + 1) µs 3
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU,
Q25PRHCPU : 0.034 × (No. of steps for each instruction + 1) µs

Instruction Condition (Device)

Processing Time (µs) 2
Qn QnH QnPH QnPRH
In conductive status 0.24 0.10 0.10 0.10
LD =
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
3
AND = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10 A
OR = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10

LD < >
In conductive status
In non-conductive status
0.24
0.24
0.10
0.10
0.10
0.10
0.10
0.10
5
When not executed 0.24 0.10 0.10 0.10
AND < > In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10 6
When not executed 0.24 0.10 0.10 0.10
OR < > In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10 7
In conductive status 0.24 0.10 0.10 0.10
LD >
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND > In conductive status 0.24 0.10 0.10 0.10
8
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR > In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
In conductive status 0.24 0.10 0.10 0.10
LD < =
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10

CPU
AND < = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR < = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
In conductive status 0.24 0.10 0.10 0.10
LD <
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND < In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR < In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
In conductive status 0.24 0.10 0.10 0.10
LD > =
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
AND > = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10
When not executed 0.24 0.10 0.10 0.10
OR > = In conductive status 0.24 0.10 0.10 0.10
When executed
In non-conductive status 0.24 0.10 0.10 0.10

759
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
In conductive status 0.55 0.24 0.24 0.24
LDD =
In non-conductive status 0.39 0.17 0.17 0.17
When not executed 0.39 0.17 0.17 0.17
ANDD = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.39 0.17 0.17 0.17
When not executed 0.39 0.17 0.17 0.17
ORD = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD < >
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD < > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD < > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD >
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD > In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD < =
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD < = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD < = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD <
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD < In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD < In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
In conductive status 0.55 0.24 0.24 0.24
LDD > =
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ANDD > = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24
When not executed 0.39 0.17 0.17 0.17
ORD > = In conductive status 0.55 0.24 0.24 0.24
When executed
In non-conductive status 0.55 0.24 0.24 0.24

760
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

In conductive status
93 40
6.4 6.4
3
Single 14.9 6.4
precision 92 40
In non-conductive status 6.4 6.4
LDE = *1
14.9
93
6.4
40
2
In conductive status –– ––
Double 14.9 6.4
precision 92 40
In non-conductive status
14.9 6.4
–– ––
3
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
precision
When 14.9 6.4 A
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE = *1
When not executed –– –– –– ––
93 40 5
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4 6
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
precision
When
executed
14.9
92
6.4
40
7
In non-conductive status 6.4 6.4
14.9 6.4
ORE = *1
When not executed 0.55 0.24 –– ––

Double In conductive status

93 40
–– ––
8
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
92 40
In conductive status 6.4 6.4

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
Single 14.9 6.4
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4

CPU
LDE<> *1
92 40
In conductive status –– ––
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 93 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE<> *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
*1: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the top and bottom.

761
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE<> *1
When not executed 0.55 0.24 –– ––
93 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 92 40
6.4 6.4
Single 14.9 6.4
precision In conductive status 92 40
6.4 6.4
14.9 6.4
*1
LDE>
92 40
–– ––
Double 14.9 6.4
In non-conductive status
precision 92 40
–– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 93 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE> *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE> *1
When not executed 0.55 0.24 –– ––
93 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
93 40
In conductive status 6.4 6.4
Single 14.9 6.4
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4
LDE<= *1
93 40
In conductive status –– ––
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
*1: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the top and bottom.

762
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
When not executed 0.55 0.24 0.24 0.24 3
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed
In non-conductive status
92
14.9
40
6.4
6.4 6.4 2
ANDE<= *1
When not executed 0.55 0.24 –– ––
92 40
Double
precision
When
In conductive status
14.9 6.4
–– ––
3
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24 A
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status
14.9 6.4
6.4 6.4 5
ORE<= *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
precision
When 14.9 6.4 6
executed 92 40
In non-conductive status –– ––
14.9 6.4

Single
In conductive status
92
14.9
40
6.4
6.4 6.4 7
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4
LDE< *1
In conductive status
92 40
–– ––
8
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40

CPU
In non-conductive status 6.4 6.4
14.9 6.4
ANDE< *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
93 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE< *1
When not executed 0.55 0.24 –– ––
93 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
*1: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the top and bottom.

763
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
93 40
In conductive status 6.4 6.4
Single 14.9 6.4
precision 92 40
In non-conductive status 6.4 6.4
14.9 6.4
*1
LDE>=
93 40
In conductive status –– ––
Double 14.9 6.4
precision 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ANDE>= *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
When not executed 0.55 0.24 0.24 0.24
92 40
Single In conductive status 6.4 6.4
When 14.9 6.4
precision
executed 92 40
In non-conductive status 6.4 6.4
14.9 6.4
ORE>= *1
When not executed 0.55 0.24 –– ––
92 40
Double In conductive status –– ––
When 14.9 6.4
precision
executed 92 40
In non-conductive status –– ––
14.9 6.4
In conductive status 38 16 16 16
LD$ =
In non-conductive status 34 15 15 15
When not executed 0.56 0.23 0.23 0.23
AND$ = In conductive status 39 17 17 17
When executed
In non-conductive status 32 14 14 14
When not executed 0.56 0.24 0.24 0.24
OR$ = In conductive status 40 17 17 17
When executed
In non-conductive status 33 14 14 14
In conductive status 32 14 14 14
LD$ < >
In non-conductive status 40 17 17 17
When not executed 0.56 0.23 0.23 0.23
AND$ < > In conductive status 33 14 14 14
When executed
In non-conductive status 39 17 17 17
When not executed 0.56 0.24 0.24 0.24
OR$ < > In conductive status 32 14 14 14
When executed
In non-conductive status 39 17 17 17
In conductive status 32 14 14 14
LD$ >
In non-conductive status 40 17 17 17
*1: The Qn/QnH changes in processing time depending on the serial No. of the CPU module.
Top : The first 5 digits of the serial No. are "05031" or lower
Bottom : The first 5 digits of the serial No. are "05032" or higher
For the condition to be satisfied when the instruction is not executed, there is no differentiation between the top and bottom.

764
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
When not executed 0.56 0.23 0.23 0.23 3
AND$ > In conductive status 33 14 14 14
When executed
In non-conductive status 39 17 17 17

OR$ >
When not executed
In conductive status
0.56
32
0.24
14
0.24
14
0.24
14
2
When executed
In non-conductive status 39 17 17 17
In conductive status 40 17 17 17
LD$ < =
In non-conductive status 32 14 14 14 3
When not executed 0.56 0.23 0.23 0.23
AND$ < = In conductive status 39 17 17 17
When executed
In non-conductive status 32 14 14 14 A
When not executed 0.56 0.24 0.24 0.24
OR$ < = In conductive status 40 17 17 17
When executed
In non-conductive status 33 14 14 14
In conductive status 32 14 14 14 5
LD$ <
In non-conductive status 40 17 17 17
When not executed 0.56 0.23 0.23 0.23
AND$ <
When executed
In conductive status 32 14 14 14 6
In non-conductive status 39 16 16 16
When not executed 0.56 0.24 0.24 0.24
OR$ <
When executed
In conductive status
In non-conductive status
32
39
14
16
14
16
14
16
7
In conductive status 40 17 17 17
LD$ > =
In non-conductive status 32 14 14 14
When not executed 0.56 0.23 0.23 0.23 8
AND$ > = In conductive status 39 16 16 16
When executed
In non-conductive status 32 14 14 14
When not executed 0.56 0.24 0.24 0.24
OR$ > = In conductive status 39 17 17 17
When executed

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
In non-conductive status 32 14 14 14
BKCMP = S1 S2 D n n=1 48 21 21 21

CPU
BKCMP = P S1 S2 D n n = 96 142 61 61 61

BKCMP <> S1 S2 D n n=1 48 21 21 21

BKCMP <>P S1 S2 D n n = 96 150 65 65 65

BKCMP > S1 S2 D n n=1 48 21 21 21

BKCMP >P S1 S2 D n n = 96 142 61 61 61

BKCMP >= S1 S2 D n n=1 48 21 21 21

BKCMP >=P S1 S2 D n n = 96 150 65 65 65

BKCMP < S1 S2 D n n=1 48 21 21 21

BKCMP <P S1 S2 D n n = 96 158 68 68 68

BKCMP <= S1 S2 D n n=1 48 21 21 21

BKCMP <=P S1 S2 D n n = 96 150 65 65 65

+ S D
When executed 0.39 0.17 0.17 0.17
+P S D

+ S1 S2 D
When executed 0.47 0.20 0.20 0.20
+P S1 S2 D

- S D
When executed 0.39 0.17 0.17 0.17
-P S D

- S1 S2 D
When executed 0.47 0.20 0.20 0.20
-P S1 S2 D

765
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
D+ S D
When executed 0.71 0.31 0.31 0.31
D+P S D

D+ S1 S2 D
When executed 0.79 0.34 0.34 0.34
D+P S1 S2 D

D- S D
When executed 0.71 0.30 0.30 0.30
D-P S D

D- S1 S2 D
When executed 0.79 0.34 0.34 0.34
D-P S1 S2 D

* S1 S2 D
When executed 0.47 0.20 0.20 0.20
*P S1 S2 D

/ S1 S2 D
–– 2.7 1.2 1.2 1.2
/P S1 S2 D

D* S1 S2 D
–– 7.9 3.4 3.4 3.4
D*P S1 S2 D

D/ S1 S2 D
–– 14 6.1 6.1 6.1
D/P S1 S2 D

B+ S D
–– 2.2 1.0 1.0 1.0
B+P S D

B+ S1 S2 D
–– 5.0 2.2 2.2 2.2
B+P S1 S2 D

B- S D
–– 2.0 0.9 0.9 0.9
B-P S D

B- S1 S2 D
–– 4.9 2.1 2.1 2.1
B-P S1 S2 D

DB+ S D
–– 12 5.0 5.0 5.0
DB+P S D

DB+ S1 S2 D
–– 12 5.3 5.3 5.3
DB+P S1 S2 D

DB - S D
–– 11 4.8 4.8 4.8
DB - P S D

DB - S1 S2 D
–– 12 5.2 5.2 5.2
DB - P S1 S2 D

B* S1 S2 D
–– 3.7 1.6 1.6 1.6
B*P S1 S2 D

B/ S1 S2 D
–– 3.8 1.6 1.6 1.6
B/P S1 S2 D

DB * S1 S2 D
–– 24 10 10 10
DB * P S1 S2 D

DB/ S1 S2 D
–– 27 12 12 12
DB/P S1 S2 D

766
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

Single S = 0, D =0 1.8 0.78 0.78 0.78 3

precision = 2127 , =2 127 1.8 0.78 0.78 0.78
E+ S D S D

E+P S D Double = 0, =0 203 87 –– ––

2
S D

precision S = 2127, D = 2127 203 87 –– ––

Single S1 = 0, S2 =0 2.4 1.1 1.1 1.1

E+ S1 S2 D precision S1 = 2127, S2 =2 127 2.4 1.1 1.1 1.1

3
E+P S1 S2 D Double S1 = 0, S2 =0 209 90 –– ––
precision S1 = 2127, S2 = 2127 209 90 –– ––

Single S = 0, D =0 1.8 0.78 0.78 0.78 A

E- S D precision S = 2127, D = 2127 1.8 0.78 0.78 0.78

E -P S D Double S = 0, D =0 202 87 –– ––
precision S = 2127 , D =2 127 202 87 –– ––
5
Single S1 = 0, S2 =0 2.4 1.1 1.1 1.1
precision
E- S1 S2 D S1 = 2127, S2 = 2127 2.4 1.1 1.1 1.1
6
E -P S1 S2 D Double S1 = 0, S2 =0 210 90 –– ––
precision S1 = 2127, S2 = 2127 210 90 –– ––

Single S1 = 0, S2 =0 2.4 1.1 1.1 1.1 7

E* S1 S2 D precision S1 = 2126, S2 = 2127 2.4 1.1 1.1 1.1

E*P S1 S2 D Double S1 = 0, S2 =0 222 96 –– ––

precision S1 = 2126, S2 =2 127 222 96 –– –– 8
Single S1 = 0, S2 =1 12 5.2 5.2 5.2

E/ S1 S2 D precision S1 = 2127, S2 = - 2126 12 5.2 5.2 5.2

E/P S1 S2 D Double S1 = 0, S2 =1 369 159 –– ––

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
precision S1 = 2127, S2 =-2 126 369 159 –– ––

$+ S D
–– 68 29 29 29

CPU
$+P S D

$+ S1 S2 D
–– 81 35 35 35
$+P S1 S2 D

INC
–– 0.32 0.14 0.14 0.14
INCP
DINC
–– 0.47 0.20 0.20 0.20
DINCP
DEC
–– 0.32 0.14 0.14 0.14
DECP
DDEC
–– 0.47 0.20 0.20 0.20
DDECP
BCD
–– 1.1 0.48 0.48 0.48
BCDP
DBCD
–– 3.2 1.4 1.4 1.4
DBCDP
BIN
–– 1.0 0.44 0.44 0.44
BINP
DBIN
–– 1.9 0.82 0.82 0.82
DBINP

767
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

Single S =0 3.2 1.4 1.4 1.4

precision = 32766.5 3.2 1.4 1.4 1.4
INT S

INTP =0 22 9.3 –– ––
Double S

precision S = 32766.5 22 9.3 –– ––

Single S =0 2.5 1.1 1.1 1.1

DINT precision S = 1234567890.3 2.5 1.1 1.1 1.1

DINTP =0 24 10 –– ––
Double S

precision S = 1234567890.3 24 10 –– ––

Single S =0 2.1 0.92 0.92 0.92

precision = 7FFFH 2.1 0.92 0.92 0.92
FLT S

FLTP =0 22 9.6 –– ––
Double S

precision S = 7FFFH 22 9.6 –– ––

Single S =0 2.1 0.88 0.88 0.88

precision = 7FFFFFFFH 2.1 0.88 0.88 0.88
DFLT S

DFLTP =0 26 11 –– ––
Double S

precision S = 7FFFFFFFH 26 11 –– ––
DBL
–– 4.5 1.9 1.9 1.9
DBLP
WORD
–– 4.7 2.0 2.0 2.0
WORDP
GRY
–– 4.7 2.0 2.0 2.0
GRYP
DGRY
–– 5.3 2.3 2.3 2.3
DGRYP
GBIN
–– 18 7.7 7.7 7.7
GBINP
DGBIN
–– 32 14 14 14
DGBINP
NEG
–– 3.6 1.6 1.6 1.6
NEGP
DNEG
–– 4.3 1.8 1.8 1.8
DNEGP
ENEG
–– 3.9 1.7 1.7 1.7
ENEGP
BKBCD S D n n=1 38 17 17 17

BKBCDP S D n n = 96 99 43 43 43

BKBIN S D n n=1 38 17 17 17

BKBINP S D n n = 96 99 43 43 43
S = D0, D = D1 0.24 0.10 0.10 0.10
MOV –– –– –– ––
MOVP S = D0, D = J1 \ W1 –– –– –– ––
140*1 60 *1
60 *1
60*1
S = D0, D = D1 0.47 0.20 0.20 0.20
DMOV –– –– –– ––
DMOVP S = D0, D = J1 \ W1 –– –– –– ––
*1 *1 *1
147 64 64 64*1
*1: The upper row indicates the processing time when A38B/A1S38B and the extension base are used.
The center row indicates the processing time when A38HB/A1S38HB is used.
The lower row indicates the processing time when Q312B is used.

768
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
EMOV
–– 0.63 0.27 0.27 0.27
3
EMOVP
$MOV
–– 40 17 17 17
$MOVP
CML
2
–– 0.40 0.17 0.17 0.17
CMLP
DCML
DCMLP
–– 0.55 0.24 0.24 0.24
3
BMOV S D n n=1 17 7.1 7.1 7.1

BMOVP S D n n = 96 32 14 14 14

FMOV S D n n=1 6.7 2.9 2.9 2.9 A

FMOVP S D n n = 96 14 6.1 6.1 6.1
XCH
XCHP
–– 1.3 0.54 0.54 0.54
5
DXCH
DXCHP

BXCH D1 D2 n n=1 31 13 13 13
6
BXCHP D1 D2 n n = 96 84 36 36 36
SWAP
–– 3.7 1.6 1.6 1.6
SWAPP
7
CJ –– 3.2 1.4 1.4 1.4
SCJ –– 3.2 1.4 1.4 1.4
JMP –– 3.2 1.4 1.4 1.4
GOEND –– 0.39 0.34 0.34 0.34 8
DI –– 0.95 0.41 0.41 0.41
EI –– 1.3 0.54 0.54 0.54
IMASK –– 11 4.6 4.6 4.6
IRET –– 1.6 0.68 0.68 0.68

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
RFS n=1 6.7 4.7 4.7 4.7
RFSP n = 96 19 13 13 13
UDCNT1 –– 15 6.5 6.5 ––

CPU
UDCNT2 –– 16 6.8 6.8 ––
TTMR –– 10 4.4 4.4 ––
STMR –– 20 7.1 7.1 ––
ROTC –– 26 11 11 ––
RAMP –– 18 7.7 7.7 ––
SPD –– 19 8.3 8.3 ––
PLSY –– 10 4.5 4.5 ––
PWM –– 9.1 3.9 3.9 ––
MTR –– 11 4.9 4.9 ––

769
(3) Application instructions
The processing time when the instruction is not executed is calculated as follows:
Q02CPU : 0.079 × (No. of steps for each instruction + 1) µs
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU, Q12PHCPU, Q25PHCPU, Q12PRHCPU,
Q25PRHCPU : 0.034 × (No. of steps for each instruction + 1) µs

Processing Time ( µs)

Instruction Condition (Device)
Qn QnH QnPH QnPRH
WAND S D
When executed 0.39 0.17 0.17 0.17
WANDP S D

WAND S1 S2 D
When executed 0.47 0.20 0.20 0.20
WANDP S1 S2 D

DAND S D
When executed 0.71 0.31 0.31 0.31
DANDP S D

DAND S1 S2 D
When executed 0.79 0.34 0.34 0.34
DANDP S1 S2 D

BKAND S1 S2 D n n=1 36 16 16 16

BKANDP S1 S2 D n n = 96 74 32 32 32

WOR S D
When executed 0.40 0.17 0.17 0.17
WORP S D

WOR S1 S2 D
When executed 0.47 0.20 0.20 0.20
WORP S1 S2 D

DOR S D
When executed 0.71 0.31 0.31 0.31
DORP S D

DOR S1 S2 D
When executed 0.79 0.34 0.34 0.34
DORP S1 S2 D

BKOR S1 S2 D n n=1 36 16 16 16

BKORP S1 S2 D n n = 96 74 32 32 32

WXOR S D
When executed 0.39 0.17 0.17 0.17
WXORP S D

WXOR S1 S2 D
When executed 0.47 0.20 0.20 0.20
WXORP S1 S2 D

DXOR S D
When executed 0.71 0.31 0.31 0.31
DXORP S D

DXOR S1 S2 D
When executed 0.79 0.34 0.34 0.34
DXORP S1 S2 D

BKXOR S1 S2 D n n=1 36 16 16 16

BKXORP S1 S2 D n n = 96 74 32 32 32

WXNR S D
When executed 0.40 0.17 0.17 0.17
WXNRP S D

WXNR S1 S2 D
When executed 0.47 0.20 0.20 0.20
WXNRP S1 S2 D

DNXR S D
When executed 0.71 0.31 0.31 0.31
DNXRP S D

DNXR S1 S2 D
When executed 0.79 0.34 0.34 0.34
DNXRP S1 S2 D

BKXNR S1 S2 D n n=1 36 16 16 16

BKXNRP S1 S2 D n n = 96 74 32 32 32

ROR D n n=1 2.0 0.85 0.85 0.85

RORP D n n = 15 2.0 0.85 0.85 0.85

770
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
RCR D n n=1 1.6 0.68 0.68 0.68 3
RCRP D n n = 15 1.6 0.68 0.68 0.68

ROL D n n=1 2.0 0.85 0.85 0.85

ROLP D n n = 15 2.0 0.85 0.85 0.85 2

RCL D n n=1 1.6 0.68 0.68 0.68
n = 15 1.6 0.68 0.68 0.68
RCLP n
3
D

DROR D n n=1 3.9 1.7 1.7 1.7

DRORP D n n = 31 4.0 1.7 1.7 1.7

DRCR D n n=1 4.3 1.8 1.8 1.8

A
DRCRP D n n = 31 4.3 1.9 1.9 1.9

DROL D n n=1 3.9 1.7 1.7 1.7

DROLP D n n = 31 4.0 1.7 1.7 1.7 5

DRCL D n n=1 4.3 1.8 1.8 1.8

DRCLP D n n = 31 4.3 1.9 1.9 1.9

SFR D n n=1 1.7 0.75 0.75 0.75 6

SFRP D n n = 15 2.0 0.85 0.85 0.85

SFL n n=1 1.7 0.75 0.75 0.75

7
D

SFLP D n n = 15 2.0 0.85 0.85 0.85

BSFR D n n=1 20 8.6 8.6 8.6

BSFRP D n n = 96 24 10 10 10
8
BSFL D n n=1 20 8.5 8.5 8.5

BSFLP D n n = 96 23 10 10 10

DSFR D n n=1 1.3 0.58 0.58 0.58

DSFRP D n n = 96 25 11 11 11

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
DSFL D n n=1 1.3 0.58 0.58 0.58

DSFLP D n n = 96 26 11 11 11

CPU
BSET D n n=1 7.6 3.3 3.3 3.3

BSETP D n n = 15 7.6 3.3 3.3 3.3

BRST D n n=1 7.6 3.3 3.3 3.3

BRSTP D n n = 15 7.6 3.3 3.3 3.3

TEST S1 S2 D
–– 8.2 3.5 3.5 3.5
TESTP S1 S2 D

DTEST S1 S2 D
–– 9.2 3.9 3.9 3.9
DTESTP S1 S2 D

BKRST S n n=1 18 7.8 7.8 7.8

BKRSTP S n n = 96 19 8.2 8.2 8.2

All match 22 9.6 9.6 9.6
n=1
SER S1 S2 D n None match 21 8.9 8.9 8.9
SERP S1 S2 D n All match 115 49 49 49
n = 96
None match 133 57 57 57
All match 23 9.9 9.9 9.9
n=1
DSER S1 S2 D n None match 23 9.7 9.7 9.7
DSERP S1 S2 D n All match 142 61 61 61
n = 96
None match 132 57 57 57

771
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
SUM S =0
3.9 1.7 1.7 1.7
SUMP S = FFFF

DSUM S =0 4.7 2.0 2.0 2.0

DSUMP S = FFFFFFFFH 12 5.0 5.0 5.0

DECO S D n n=2 20 8.6 8.6 8.6

DECOP S D n n=8 27 12 12 12
M1 = ON 21 9.1 9.1 9.1
n=2
ENCO S D n M4 = ON 21 9.1 9.1 9.1
ENCOP S D n M1 = ON 28 12 12 12
n=8
M256 = ON 26 11 11 11
SEG
–– 1.3 0.54 0.54 0.54
SEGP
DIS S D n n=1 18 7.7 7.7 7.7

DISP S D n n=4 19 8.3 8.3 8.3

UNI S D n n=1 21 8.9 8.9 8.9

UNIP S D n n=4 23 9.7 9.7 9.7

NDIS S1 D S2
–– 41 18 18 18
NDISP S1 D S2

NUNI S1 D S2
–– 42 18 18 18
NUNIP S1 D S2

WTOB S D n n=1 47 20 20 20

WTOBP S D n n = 96 99 43 43 43

BTOW S D n n=1 45 19 19 19

BTOWP S D n n = 96 89 38 38 38

MAX S D n n=1 17 7.1 7.1 7.1

MAXP S D n n = 96 136 59 59 59

MIN S D n n=1 17 7.1 7.1 7.1

MINP S D n n = 96 159 69 69 69

DMAX S D n n=1 27 12 12 12

DMAXP S D n n = 96 181 78 78 78

DMIN S D n n=1 27 12 12 12

DMINP S D n n = 96 112 48 48 48

n = 1, S2 =1 16 7.1 7.1 7.1

SORT S1 n S2 D1 D2
n = 96, S2 = 16 87.8 37.9 37.9 37.9

n = 1, S2 =1 17 7.1 7.1 7.1

DSORT S1 n S2 D1 D2
n = 96, S2 = 16 96.1 41.6 41.6 41.6

WSUM S D n n=1 16.4 7.1 7.1 7.1

WSUMP S D n n = 96 68.4 29.5 29.5 29.5

DWSUM S D n n=1 18.9 8.2 8.2 8.2

DWSUMP S D n n = 96 130.4 56.1 56.1 56.1

FOR n n=0 2.3 1.0 1.0 1.0
NEXT –– 3.3 1.4 1.4 1.4
BREAK
–– 11 4.6 4.6 4.6
BREAKP
CALL Pn Internal file pointer 2.1 0.88 0.88 0.88
CALLP Pn Common pointer 33 14 14 14

772
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH

CALL Pn S1 to S5 3
–– 135 58 58 58
CALLP Pn S1 to S5

Return to original program 2.9 1.3 1.3 1.3

RET
Return to other program 20 8.5 8.5 8.5 2
FCALL Pn Internal file pointer 3.6 1.6 1.6 1.6
FCALLP Pn Common pointer 20 8.7 8.7 8.7

FCALL Pn S1 to S5
–– 134 57 57 57
3
FCALLP Pn S1 to S5

ECALL * Pn
ECALLP * Pn –– 77 33 33 33 A
*: Program name

ECALL * Pn S1 to S5

ECALLP * Pn S1 to S5 –– 162 70 70 70
5
*: Program name
EFCALL * Pn
EFCALLP * Pn
*: Program name
–– 78 34 34 34
6
EFCALL * Pn S1 to S5

–– 200 86 86 86
EFCALLP * Pn
*: Program name
S1 to S5
7
COM –– 55 16 16 16
IX –– 12 5.2 5.2 5.2
IXEND –– 4.7 2.0 2.0 2.0 8
Number of contacts 1 48 21 21 21
IXDEV + IXSET
Number of contacts 14 93 40 40 40
FIFW Number of data points 0 11 4.5 4.5 4.5
FIFWP Number of data points 96 11 4.5 4.5 4.5

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
FIFR Number of data points 1 13 5.6 5.6 5.6
FIFRP Number of data points 96 32 14 14 14
FPOP Number of data points 1 16 7.0 7.0 7.0

CPU
FPOPP Number of data points 96 16 7.0 7.0 7.0
FINS Number of data points 0 20 8.4 8.4 8.4
FINSP Number of data points 96 36 15 15 15
FDEL Number of data points 1 19 7.5 7.5 7.5
FDELP Number of data points 96 39 15 15 15
–– –– –– ––
n3 = 1 –– –– –– ––
FROM n1 n2 D n3 47 22 22 22
FROMP n1 n2 D n3 *1 –– –– –– ––
n3 = 1000 –– –– –– ––
476 437 437 437
–– –– –– ––
n3 = 1 –– –– –– ––
DFRO n1 n2 D n3 51 24 24 24
DFROP n1 n2 D n3 *1 –– –– –– ––
n3 = 500 –– –– –– ––
478 437 437 437
*1: The upper row indicates the processing time when A38B/A1S38B and the extension base are used.
The center row indicates the processing time when A38HB/A1S38HB is used.
The bottom row indicates the processing times taken when the Q312B is used to execute the instruction for the QJ71C24 in
slot 0.
The FROM/TO instruction differs in processing time according to the number of slots and the loaded modules.
(The QnCPU/QnHCPU also differs in processing time according to the extension base type.)

773
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
–– –– –– ––
n3 = 1 –– –– –– ––
TO n1 n2 S n3 48 20 20 20
TOP n1 n2 S n3 *1 –– –– –– ––
n3 = 1000 –– –– –– ––
479 412 412 412
–– –– –– ––
n3 = 1 –– –– –– ––
DTO n1 n2 S n3 50 23 23 23
DTOP n1 n2 S n3 *1 –– –– –– ––
n3 = 500 –– –– –– ––
457 416 416 416
Variable 1 character 33 11 11 ––
SM701ON
PR Variable 32 character 48 18 18 ––
SM701OFF 21 7.8 7.8 ––
PRC –– 181 16 16 ––
When displayed –– –– –– ––
LED
Display completed –– –– –– ––
When displayed –– –– –– ––
LEDC
Display completed –– –– –– ––
No display no display 0.40 0.17 0.17 0.17
LEDR
LED instruction execution no display 103 44 44 44
CHKST –– 5.8 2.5 2.5 2.5
1 contact no error 24 10 10 10
CHK 150 contact no error 1676 721 721 721
1 contact error 88 38 38 38
CHKCIR 10 steps 5.8 2.5 2.5 2.5
All internal devices –– –– –– ––
SLT File register 8k points –– –– –– ––
SLT execution completion –– –– –– ––
SLTR –– –– –– –– ––
Start –– –– –– ––
STRA
STRA execution completion –– –– –– ––
STRAR –– –– –– –– ––
PTRA –– –– –– –– ––
PTRAR –– –– –– –– ––
PTRAEXE When operating –– –– –– ––
PTRAEXEP Trace in progress –– –– –– ––
BINDA S =1 15 6.7 6.7 6.7
BINDAP S = - 32768 24 10 10 10

DBINDA S =1 43 18 18 18
DBINDAP S = - 2147483648 86 37 37 37

BINHA S =1 18 7.7 7.7 7.7

BINHAP S = FFFFH 19 8.2 8.2 8.2

DBINHA S =1 23 10 10 10
DBINHAP S = FFFFFFFFH 24 10 10 10
*1: The upper row indicates the processing time when A38B/A1S38B and the extension base are used.
The center row indicates the processing time when A38HB/A1S38HB is used.
The bottom row indicates the processing times taken when the Q312B is used to execute the instruction for the QJ71C24 in
slot 0.
The FROM/TO instruction differs in processing time according to the number of slots and the loaded modules.
(The QnCPU/QnHCPU also differs in processing time according to the extension base type.)

774
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
BCDDA S =1 23 9.8 9.8 9.8 3
BCDDAP S = 9999 21 8.9 8.9 8.9

DBCDDA S =1 22 9.5 9.5 9.5

DBCDDAP S = 99999999 29 13 13 13 2
DABIN S =1 57 25 25 25
DABINP 58 25 25 25
= - 32768
3
S

DDABIN S =1 92 40 40 40
DDABINP S = - 2147483648 106 46 46 46

HABIN S =1 13 5.8 5.8 5.8

A
HABINP S = FFFFH 15 6.4 6.4 6.4

DHABIN S =1 22 9.5 9.5 9.5

DHABINP S = FFFFFFFFH 25 11 11 11 5
DABCD S =1 16 6.9 6.9 6.9
DABCDP S = 9999 17 7.2 7.2 7.2

DDABCD S =1 25 11 11 11 6
DDABCDP S = 99999999 29 13 13 13
COMRD
COMRDP
–– 40 17 17 17
7
LEN 1 character 18 8.0 8.0 8.0
LENP 96 characters 86 37 37 37
STR
–– 53 23 23 23 8
STRP
DSTR
–– 123 53 53 53
DSTRP
VAL
–– 95 41 41 41
VALP

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
DVAL
–– 166 72 72 72
DVALP

CPU
ESTR
–– 564 243 243 243
ESTRP

EVAL Decimal point format all 2-digit specification 100 43 43 43

EVALP Exponent format all 6-digit specification 127 55 55 55

ASC S D n n=1 64 28 28 28

ASCP S D n n = 96 289 125 125 125

HEX S D n n=1 60 26 26 26

HEXP S D n n = 96 343 148 148 148

RIGHT S D n n=1 49 21 21 21

RIGHTP S D n n = 96 131 56 56 56

LEFT S D n n=1 50 21 21 21

LEFTP S D n n = 96 131 56 56 56
MIDR
–– 53 23 23 23
MIDRP
MIDW
–– 128 55 55 55
MIDWP
No match 58 25 25 25
INSTR
Head 55 24 24 24
INSTRP Match
End 58 25 25 25

775
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
EMOD
–– 527 227 227 227
EMODP
EREXP
–– 1656 713 713 713
EREXPP
SIN Single precision 115 50 50 50
SINP Double precision 1945 837 –– ––
COS Single precision 122 53 53 53
COSP Double precision 2618 1127 –– ––
TAN Single precision 123 53 53 53
TANP Double precision 2618 1127 –– ––
ASIN Single precision 111 48 48 48
ASINP Double precision 2491 1072 –– ––
ACOS Single precision 115 49 49 49
ACOSP Double precision 2367 1019 –– ––
ATAN Single precision 157 68 68 68
ATANP Double precision 3140 1352 –– ––
RAD Single precision 17 7.2 7.2 7.2
RADP Double precision 24 10 –– ––
DEG Single precision 17 7.2 7.2 7.2
DEGP Double precision 23 9.9 –– ––
SQR Single precision 28 12 12 12
SQRP Double precision 1812 780 –– ––
S = - 10
Single precision 129 56 56 56
EXP S =1
EXPP S = - 10
Double precision 2386 1026 –– ––
S =1
S =1
Single precision 113 49 49 49
LOG S = 10
LOGP S =1
Double precision 2146 924 –– ––
S = 10
RND
–– 3.9 1.7 1.7 1.7
RNDP
SRND
–– 3.5 1.5 1.5 1.5
SRNDP

BSQR S =0 6.2 2.7 2.7 2.7

BSQRP S = 9999 38 16 16 16

BDSQR S =0 6.2 2.7 2.7 2.7

BDSQRP S = 99999999 38 16 16 16
BSIN
–– 12 5.1 5.1 5.1
BSINP
BCOS
–– 12 5.2 5.2 5.2
BCOSP
BTAN
–– 12 5.2 5.2 5.2
BTANP
BASIN
–– 20 8.7 8.7 8.7
BASINP
BACOS
–– 21 9.0 9.0 9.0
BACOSP
BATAN
–– 22 9.6 9.6 9.6
BATANP
LIMIT
–– 10 4.3 4.3 4.3
LIMITP

776
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
DLIMIT
–– 11 4.7 4.7 4.7
3
DLIMITP
BAND
–– 9.8 4.2 4.2 4.2
BANDP
DBAND
2
–– 11 4.9 4.9 4.9
DBANDP
ZONE
ZONEP
–– 9.1 3.9 3.9 3.9
3
DZONE
–– 11 4.6 4.6 4.6
DZONEP
RSET
RSETP
–– 6.8 2.9 2.9 2.9 A
QDRSET
–– 205 88 88 88
QDRSETP
QCDSET
–– 147 63 63 63
5
QCDSETP
DATERD
–– 13 5.5 5.5 5.5
DATERDP
DATEWR
6
–– 15 6.4 6.4 6.4
DATEWRP
DATE+ No digit increase 13 5.4 5.4 5.4
DATE+P Digit increase 13 5.4 5.4 5.4 7
DATE - No digit increase 12 5.2 5.2 5.2
DATE - P Digit increase 12 5.2 5.2 5.2
SECOND
–– 10 4.5 4.5 4.5 8
SECONDP
HOUR
–– 12 5.2 5.2 5.2
HOURP
1 character 3.0 1.3 1.3 1.3
MSG
32 characters 3.0 1.3 1.3 1.3

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
Initial time 20 8.6 8.6 8.6
PKEY
No reception 19 8.2 8.2 8.2

CPU
PSTOP
–– 79 34 34 34
PSTOPP
POFF
–– 79 34 34 34
POFFP
PSCAN
–– 75 32 32 32
PSCNAP
PLOW
–– 80 34 34 ––
PLOWP
WDT
–– 5.9 2.6 2.6 2.6
WDTP
DUTY –– 9.3 4.0 4.0 4.0
ZRRDB
–– 7.9 3.4 3.4 3.4
ZRRDBP
ZRWRB
–– 9.4 4.0 4.0 4.0
ZRWRBP
ADRSET
–– 4.9 2.1 2.1 2.1
ADRSETP
KEY –– 17 7.3 7.3 ––
ZPUSH
–– 11 4.7 4.7 4.7
ZPUSHP
ZPOP
–– 5.1 2.2 2.2 2.2
ZPOPP
EROMWR
–– –– –– –– ––
EROMWRP

777
 Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
READ –– –– –– –– ––
SREAD –– –– –– –– ––
WRITE –– –– –– –– ––
SWRITE –– –– –– –– ––
SEND –– –– –– –– ––
RECV –– –– –– –– ––
REQ –– –– –– –– ––
ZNFR –– –– –– –– ––
ZNTO –– –– –– –– ––
MELSECNET/10 –– –– –– ––
ZNRD
MELSECNET (II) –– –– –– ––
MELSECNET/10 –– –– –– ––
ZNWR
MELSECNET (II) –– –– –– ––
RFRP –– –– –– –– ––
RTOP –– –– –– –– ––

(4) Processing time for QCPU instructions (QCPU instructions only)

(a) Instructions available from function version A
Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
UNIRD –– 79 34 34 34
Start 176 76 76 76
TRACE
STRA execution completion 6.3 2.7 2.7 2.7
TRACER –– 19 8.2 8.2 8.2
SP.FWRITE –– 84 36 36 36
SP.FREAD –– 82 35 35 35
PLOADP –– 58 25 25 ––
PUNLOADP –– 272 117 117 ––
PSWAPP –– 308 133 133 ––

1 point 45.5 20 20 20
When standard RAM is used
1000 points 215 91 91 91
RBMOV
1 point 49.5 22 22 22
When SRAM card is used
1000 points 540 305 305 305

778
 (b) Instructions available from function version B
Processing Time (µs)
Instruction Condition/Number of Points Processed

Refresh range: 2k words

Qn QnH QnPH QnPRH
3
(0.5k words 720 660 660 ––
With auto refresh of assigned equally to all CPUs)
CPU shared memory Refresh range: 4k words 2
COM *1 (1k words assigned equally to all 860 730 730 ––
CPUs)
Without auto refresh
of CPU shared –– 43 20 20 20
3
memory
Reading from CPU n3 = 1 59 29 29 ––
shared memory of
n3 = 1000 530 500 500 ––
A
another CPU
FROM *1 Main base unit 51 24 24 ––
Reading buffer n3 = 1
memory of intelligent
n3 =
Extension base unit
Main base unit
54
540
27
480 480
27 ––
––
5
function module*2
1000 Extension base unit 1100 1050 1050 ––
n3 = 1 ("TO" instruction)
S.TO
Writing to CPU shared
n4 = 1 ("S.TO instruction")
74 33 33 –– 6
memory of host CPU
n2 = 256 126 54 54 ––

*3
Reading data of the
S (P).DATERD –– 25 11 11 11
expansion clock 7
*3
Expansion clock data
S (P).DATE+ –– 38 17 17 17
addition operation
Expansion clock data
S (P).DATE- *3
subtraction operation
–– 38 17 17 17 8
*1: If the processing overlaps those of the other CPUs in a multiple CPU system, the processing time increases by a maximum of
the following time.
For system having only the main base unit
(Instruction processing time increase) = 0.54 (number of points processed) (number of other CPUs) (µs)

Appendix 1.3Operation Processing Time of High Performance Model QCPU/Process CPU/Redundant

Appendix 1OPERATION PROCESSING TIME
For system including extension base units
(Instruction processing time increase) = 1.30 (number of points processed) (number of other CPUs) (µs)

CPU
*2: In a multiple CPU system, the instruction processing time for the intelligent function module under control of the host CPU is
equal to that for the intelligent function module under control of another CPU.
*3: Products with the first 5 digits of the serial No. "07032" or higher are applicable.

(5) Data link instruction

The processing time when the instruction is not executed is calculated as follows:
Q02CPU 0.079 × (No. of steps for each instruction + 1) µs
Q02HCPU, Q06HCPU, Q12HCPU, Q25HCPU, Q02PHCPU, Q06PHCPU,
Q12PHCPU, Q25PHCPU, Q12PRHCPU, Q25PRHCPU 0.034 × (No. of steps for each instruction + 1) µs
Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
ZCOM –– 691 289 289 289

(6) Redundant system instructions (for redundant CPU)

Processing Time (µs)
Instruction Condition (Device)
Qn QnH QnPH QnPRH
SP.CONTSW –– –– –– –– 9.6

779
(7) Table of the time to be added when file register, module access device or link direct device is used
Device Specification Processing Time (µs)
Instruction Data
Location Qn QnH QnPH QnPRH
Source 5.56 2.40 2.40 2.40
Bit
Destination 4.44 1.91 1.91 1.91
When standard Source 2.60 1.12 1.12 1.12
Word
RAM is used Destination 3.76 1.62 1.62 1.62
Source 2.83 1.22 1.22 1.22
Double word
Destination 4.00 1.72 1.72 1.72
Source 5.22 2.25 2.25 2.25
Bit
When SRAM Destination 4.09 1.76 1.76 1.76
card is used Source 2.25 0.97 0.97 0.97
File register (ZR) Word
(Q2MEM-1MBS, Destination 3.42 1.47 1.47 1.47
Q2MEM-2MBS) Source 2.49 1.07 1.07 1.07
Double word
Destination 3.65 1.57 1.57 1.57
Source 5.16 2.2 2.2 2.2
Bit
Destination 4.05 1.73 1.73 1.73
When SRAM
Source 2.23 0.92 0.92 0.92
card is used Word
Destination 3.34 1.44 1.44 1.44
(Q3MEM-4MBS)
Source 2.37 0.98 0.98 0.98
Double word
Destination 3.57 1.5 1.5 1.5
Source 35.56 15.31 15.31 15.31
Bit
Destination 65.08 28.01 28.01 28.01
Module access device Source 32.76 14.10 14.10 14.10
Word
(Un\G , U3En\G0 to G4095) Destination 28.84 12.41 12.41 12.41
Source 32.99 14.20 14.20 14.20
Double word
Destination 29.07 12.51 12.51 12.51
Source 75.67 32.57 32.57 32.57
Bit
Destination 138.65 59.67 59.67 59.67
Source 72.73 31.30 31.30 31.30
Link direct device (Jn\ ) Word
Destination 137.32 59.10 59.10 59.10
Source 72.96 31.40 31.40 31.40
Double word
Destination 137.55 59.20 59.20 59.20

780
Appendix 1.4 Operation Processing Time of Universal Model QCPU

The processing time for the individual instructions are shown in the table on the following pages.
3
Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions,
and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time
rather than as being strictly accurate.
2

Appendix 1.4.1 Subset instruction processing time 3

The following describes the subset instruction processing time.

A
(1) The processing time shown in "(1) Subset instruction processing time table" applies when the device used in an
instruction meets the device condition for subset processing (For device condition triggering subset processing, refer

(2)
to Page 109, Section 3.5.1).
When using a file resister (R, ZR), extended data register (D), extended link register (W), and module access device
5
(U3En\G10000 and the subsequent devices), add the processing time shown in (2) to that of the instruction.
(3) When using an F,T(ST),C device with an OUT/SET/RST instruction, add the processing time for each instruction, with

(4)
reference to the adding time in (3).
Since the processing time of an instruction varies depending on that of the cash function, both the minimum and 6
maximum values are described in the table.

(1) Subset instruction processing time table 7

(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU.
Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU
Min. Max.
Q00UCPU
Min. Max.
Q01UCPU
Min. Max.
Q02UCPU
Min. Max.
8
LD
LDI
AND
ANI

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
OR
ORI
When executed 0.120 0.080 0.060 0.040
LDP
LDF
ANDP
ANDF
ORP
Sequence
ORF
instruction
LDPI
When executed 0.360 0.240 0.180 0.120
LDFI
ANDPI
ANDFI
When executed 0.480 0.320 0.240 0.160
ORPI
ORFI
When not changed
OUT 0.120 0.080 0.060 0.040
When changed
When not executed
SET
When not changed 0.120 0.080 0.060 0.040
RST When executed
When changed
In conductive status
LD= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
Basic AND= In conductive status 0.360 0.240 0.180 0.120
When executed
instruction In non-conductive status
When not executed
OR= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status

781
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
In conductive status
LD<> 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND<> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR<> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LD> 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LD<= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND<= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR<= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LD< 0.360 0.240 0.180 0.120
In non-conductive status
Basic
When not executed
instruction
AND< In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR< In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LD>= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
AND>= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
OR>= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LDD= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
When not executed
ORD= In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status
In conductive status
LDD<> 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD<> In conductive status 0.360 0.240 0.180 0.120
When executed
In non-conductive status

782
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
When not executed
ORD<> When In conductive status 0.360 0.240 0.180 0.120
executed In non-conductive status
In conductive status
2
LDD> 0.360 0.240 0.180 0.120
In non-conductive status
When not executed
ANDD> When In conductive status 0.360 0.240 0.180 0.120 3
executed In non-conductive status
When not executed
ORD> When
executed
In conductive status
In non-conductive status
0.360 0.240 0.180 0.120
A
In conductive status
LDD<= 0.360 0.240 0.180 0.120
In non-conductive status
When not executed 5
ANDD<= When In conductive status 0.360 0.240 0.180 0.120
executed In non-conductive status
When not executed 6
ORD<= When In conductive status 0.360 0.240 0.180 0.120
executed In non-conductive status
In conductive status
LDD<
In non-conductive status
0.360 0.240 0.180 0.120 7
When not executed
ANDD< When In conductive status 0.360 0.240 0.180 0.120
executed In non-conductive status 8
When not executed
ORD< When In conductive status 0.360 0.240 0.180 0.120
executed In non-conductive status
Basic
instruction LDD>= In conductive status
0.360 0.240 0.180 0.120

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
In non-conductive status
When not executed
ANDD>= When In conductive status 0.360 0.240 0.180 0.120
executed In non-conductive status
When not executed
ORD>= When In conductive status 0.360 0.240 0.180 0.120
executed In non-conductive status
+ S D When executed 0.360 0.240 0.180 0.120

+ S1 S2 D When executed 0.480 0.320 0.240 0.160

- S D When executed 0.360 0.240 0.180 0.120

- S1 S2 D When executed 0.480 0.320 0.240 0.160

D+ S D When executed 0.360 0.240 0.180 0.120

D+ S1 S2 D When executed 0.480 0.320 0.240 0.160

D- S D When executed 0.360 0.240 0.180 0.120

D- S1 S2 D When executed 0.480 0.320 0.240 0.160

* S1 S2 D When executed 0.420 0.300 0.240 0.180

/ S1 S2 D When executed 0.520 0.400 0.340 0.280

D* S1 S2 D When executed 0.500 0.380 0.320 0.260

D/ S1 S2 D When executed 0.640 0.520 0.460 0.400

B+ S D When executed 3.100 12.300 3.100 12.300 3.100 12.300 3.300 8.300

B+ S1 S2 D When executed 5.900 13.500 5.900 13.500 5.900 13.500 4.600 6.200

B- S D When executed 3.150 12.300 3.150 12.300 3.150 12.300 3.300 9.000

B- S1 S2 D When executed 5.950 13.600 5.950 13.600 5.950 13.600 4.600 8.200

783
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
B* S1 S2 D When executed 3.700 12.100 3.700 12.100 3.700 12.100 4.000 8.200

B/ S1 S2 D When executed 4.000 14.000 4.000 14.000 4.000 14.000 4.200 12.400

Single S = 0, D =0 0.420 0.300 0.240 0.180

E+ S D
precision S =2 127
, D =2 127 0.420 0.300 0.240 0.180

Single S1 = 0, S2 =0 0.540 0.380 0.300 0.220

E+ S1 S2 D
precision S1 = 2127, S2 =2 127 0.540 0.380 0.300 0.220

Single S = 0, D =0 0.420 0.300 0.240 0.180

E- S D
precision S = 2127, D = 2127 0.420 0.300 0.240 0.180

Single S1 = 0, S2 =0 0.540 0.380 0.300 0.220

E- S1 S2 D
precision S1 = 2127, S2 =2 127 0.540 0.380 0.300 0.220

Single S1 = 0, S2 =0 0.420 0.300 0.240 0.180

E* S1 S2 D
precision S1 = 2127, S2 = 2127 0.420 0.300 0.240 0.180

Single
E/ S1 S2 D S1 = 2127, S2 = 2127 4.900 18.900 4.900 18.900 4.900 18.900 5.100 14.100
precision
INC When executed 0.240 0.160 0.120 0.080
DINC When executed 0.240 0.160 0.120 0.080
DEC When executed 0.240 0.160 0.120 0.080
DDEC When executed 0.240 0.160 0.120 0.080
BCD When executed 0.320 0.240 0.200 0.160
DBCD When executed 0.400 0.320 0.280 0.240
BIN When executed 0.260 0.180 0.140 0.100
DBIN When executed 0.260 0.180 0.140 0.100

Single S =0 0.300 0.220 0.180 0.140

FLT
Basic precision S = 7FFFH 0.300 0.220 0.180 0.140
instruction
Single S =0 0.300 0.220 0.180 0.140
DFLT
precision S = 7FFFFFFFH 0.300 0.220 0.180 0.140

Single S =0 0.300 0.220 0.180 0.140

INT
precision S = 32766.5 0.300 0.220 0.180 0.140

Single S =0 0.300 0.220 0.180 0.140

DINT
precision S = 1234567890.3 0.300 0.220 0.180 0.140

MOV –– 0.240 0.160 0.120 0.080

DMOV –– 0.240 0.160 0.120 0.080
EMOV –– 0.240 0.160 0.120 0.080
CML –– 0.240 0.160 0.120 0.080
DCML –– 0.240 0.160 0.120 0.080
SM237 n=1 4.200 4.600 4.200 4.600 4.200 4.600 4.100 4.500
=ON n=96 4.850 5.150 4.850 5.150 4.850 5.150 4.700 5.100
BMOV
SM237 n=1 6.800 11.300 6.800 11.300 6.800 11.300 6.300 8.900
=OFF n=96 7.450 11.900 7.450 11.900 7.450 11.900 5.900 9.500
SM=237 n=1 4.100 4.600 4.100 4.600 4.100 4.600 4.100 4.600
=ON n=96 4.800 5.200 4.800 5.200 4.800 5.200 4.800 5.200
FMOV
SM237 n=1 4.600 8.250 4.600 8.250 4.600 8.250 4.600 7.900
=OFF n=96 6.150 10.600 6.150 10.600 6.150 10.600 5.300 8.500
XCH –– 2.250 8.100 2.250 8.100 2.250 8.100 2.500 6.000
DXCH –– 2.400 8.200 2.400 8.200 2.400 8.200 2.800 7.900
SM237 n=1 2.700 2.800 2.700 2.800 2.700 2.800 2.350 2.450
=ON n=96 6.500 6.800 6.500 6.800 6.500 6.800 5.950 6.000
DFMOV
SM237 n=1 4.000 8.150 4.000 8.150 4.000 8.150 3.000 6.950
=OFF n=96 8.000 12.200 8.000 12.200 8.000 12.200 6.600 10.600

784
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
CJ –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100
Basic
SCJ –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100
instruction
JMP –– 3.500 10.100 3.500 10.100 3.500 10.100 1.900 10.100

WAND S D When executed 0.360 0.240 0.180 0.120

2
WAND S1 S2 D When executed 0.480 0.320 0.240 0.160

DAND S D When executed 0.360 0.240 0.180 0.120

3
DAND S1 S2 D When executed 0.480 0.320 0.240 0.160

WOR S D When executed 0.360 0.240 0.180 0.120

WOR S1 S2 D When executed 0.480 0.320 0.240 0.160 A

DOR S D When executed 0.360 0.240 0.180 0.120

DOR S1 S2 D When executed 0.480 0.320 0.240 0.160

WXOR S D When executed 0.360 0.240 0.180 0.120 5

WXOR S1 S2 D When executed 0.480 0.320 0.240 0.160

DXOR S D When executed 0.360 0.240 0.180 0.120

DXOR S1 S2 D When executed 0.480 0.320 0.240 0.160

6
WXNR S D When executed 0.360 0.240 0.180 0.120

When executed
WXNR S1 S2 D 0.480 0.320 0.240 0.160
7
DXNR S D When executed 0.360 0.240 0.180 0.120

DXNR S1 S2 D When executed 0.480 0.320 0.240 0.160

ROR D n
n=1
n = 15
2.250
2.250
10.800
10.800
2.250
2.350
10.800
10.800
2.250
2.350
10.800
10.800
2.300
2.400
7.800
7.800
8
n=1 2.250 10.800 2.250 10.800 2.250 10.800 2.300 3.900
RCR D n
n = 15 2.250 10.800 2.250 10.800 2.250 10.800 2.400 4.100
n=1 2.250 10.800 2.350 10.800 2.350 10.800 2.500 4.600
ROL D n
Application n = 15 2.250 10.800 2.350 10.800 2.350 10.800 2.400 4.600

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
instruction n=1 2.250 11.500 2.300 11.500 2.300 11.500 2.400 7.500
RCL D n
n = 15 2.250 11.500 2.300 11.500 2.300 11.500 2.500 7.500
n=1 2.350 11.500 2.350 11.500 2.350 11.500 2.400 10.300
DROR D n
n = 31 2.350 11.500 2.350 11.500 2.350 11.500 2.500 10.300
n=1 2.350 13.300 2.350 13.300 2.350 13.300 2.500 12.700
DRCR D n
n = 31 2.350 14.900 2.350 14.900 2.350 14.900 2.500 12.700
n=1 2.350 10.800 2.350 10.800 2.350 10.800 2.500 11.800
DROL D n
n = 31 2.350 10.800 2.350 10.800 2.350 10.800 2.500 11.800
n=1 2.350 13.300 2.350 13.300 2.350 13.300 2.500 5.100
DRCL D n
n = 31 2.350 13.300 2.350 13.300 2.350 13.300 2.500 5.100
n=1 2.350 9.900 2.350 9.900 2.350 9.900 2.400 6.100
SFR D n
n = 15 2.350 9.900 2.350 9.900 2.350 9.900 2.300 5.700
n=1 2.350 9.850 2.350 9.850 2.350 9.850 2.400 4.300
SFL D n
n = 15 2.350 9.850 2.350 9.850 2.350 9.850 2.400 4.300
n=1 3.250 15.500 3.250 15.500 3.250 15.500 3.300 12.000
DSFR D n
n = 96 32.600 45.000 32.600 45.000 32.600 45.000 32.600 42.200
n=1 3.200 15.500 3.200 15.500 3.200 15.500 3.300 8.200
DSFL D n
n = 96 32.600 45.100 32.600 45.100 32.600 45.100 32.600 37.700

S =0 3.100 8.950 3.100 8.950 3.100 8.950 3.400 6.700

SUM
S = FFFFH 3.000 8.850 3.000 8.850 3.000 8.850 3.500 6.700

SEG When executed 2.100 7.700 2.100 7.700 2.100 7.700 2.100 5.900
FOR –– 1.500 7.500 1.500 7.500 1.500 7.500 1.200 6.300
Internal file pointer 4.800 5.400 4.800 5.400 4.800 5.400 2.700 4.800
CALL Pn
Common pointer 7.100 30.500 7.100 30.500 7.100 30.500 4.400 5.700

CALL Pn S1 to S5 –– 50.200 62.000 50.200 62.000 50.200 62.000 28.700 42.600

785
 Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
execution instruction.
Example MOVP instruction, WANDP instruction etc.

(b) When using Q03UD(E)HCPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU,

Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, and Q100UDEHCPU
Processing Time (µs)
Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
Category Instruction Condition (Device) Q03UD(E)CPU
CPU Q26UD(E)HCPU CPU
Min. Max. Min. Max. Min. Max. Min. Max.
LD
LDI
AND
ANI
OR
ORI
When executed 0.020 0.0095 0.0095 0.0095
LDP
LDF
ANDP
ANDF
Sequence ORP
instruction ORF
LDPI
When executed 0.060 0.0285 0.0285 0.0285
LDFI
ANDPI
ANDFI
When executed 0.080 0.038 0.038 0.038
ORPI
ORFI
When not changed
OUT 0.020 0.0095 0.0095 0.0095
When changed
SET
When not executed 0.020 0.0095 0.0095 0.0095
RST
In conductive status
LD= 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
AND= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
OR= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LD<> 0.060 0.0285 0.0285 0.0285
In non-conductive status
Basic
When not executed
instruction
AND<> When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
OR<> When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LD> 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
AND> When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status

786
 Processing Time (µs)
Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
Category Instruction Condition (Device) Q03UD(E)CPU
CPU Q26UD(E)HCPU CPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed
OR> When In conductive status
executed In non-conductive status
0.060 0.0285 0.0285 0.0285
2
In conductive status
LD<= 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed 3
AND<= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
A
OR<= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LD<
In non-conductive status
0.060 0.0285 0.0285 0.0285 5
When not executed
AND< When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status 6
When not executed
OR< When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
7
LD>= 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
AND>= When In conductive status 0.060 0.0285 0.0285 0.0285 8
executed In non-conductive status
When not executed
OR>= When In conductive status 0.060 0.0285 0.0285 0.0285
Basic
executed In non-conductive status
instruction

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
In conductive status
LDD= 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
ANDD= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
ORD= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LDD<> 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
ANDD<> When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
ORD<> When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LDD> 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
ANDD> When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
ORD> When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LDD<= 0.060 0.0285 0.0285 0.0285
In non-conductive status

787
 Processing Time (µs)
Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
Category Instruction Condition (Device) Q03UD(E)CPU
CPU Q26UD(E)HCPU CPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed
ANDD<= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
ORD<= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LDD< 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
ANDD< When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
ORD< When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
In conductive status
LDD>= 0.060 0.0285 0.0285 0.0285
In non-conductive status
When not executed
ANDD>= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
When not executed
ORD>= When In conductive status 0.060 0.0285 0.0285 0.0285
executed In non-conductive status
+ S D When executed 0.060 0.0285 0.0285 0.0285

+ S1 S2 D When executed 0.080 0.038 0.038 0.038

- S D When executed 0.060 0.0285 0.0285 0.0285

Basic - S1 S2 D When executed 0.080 0.038 0.038 0.038

instruction D + S D When executed 0.060 0.0285 0.0285 0.0285

D+ S1 S2 D When executed 0.080 0.038 0.038 0.038

D- S D When executed 0.060 0.0285 0.0285 0.0285

D- S1 S2 D When executed 0.080 0.038 0.038 0.038

* S1 S2 D When executed 0.120 0.057 0.057 0.057

/ S1 S2 D When executed 0.220 0.110 0.110 0.110

D* S1 S2 D When executed 0.200 0.095 0.095 0.095

D/ S1 S2 D When executed 0.340 0.170 0.170 0.170

B+ S D When executed 3.300 5.500 3.000 4.100 3.000 4.100 3.000 4.100

B+ S1 S2 D When executed 4.600 6.200 4.200 5.900 4.200 5.900 4.200 5.900

B- S D When executed 3.300 4.400 2.900 3.800 2.900 3.800 2.900 3.800

B- S1 S2 D When executed 4.600 6.300 4.200 4.600 4.200 4.600 4.200 4.600

B* S1 S2 D When executed 4.000 4.800 3.400 4.800 3.400 4.800 3.400 4.800

B/ S1 S2 D When executed 4.200 5.700 3.700 5.200 3.700 5.200 3.700 5.200

Single S = 0, D =0 0.120 0.057 0.057 0.057

E+ S D
precision S = 2127, D = 2127 0.120 0.057 0.057 0.057

Single S1 = 0, S2 =0 0.140 0.0665 0.0665 0.0665

E+ S1 S2 D
precision S1 = 2127, S2 =2 127 0.140 0.0665 0.0665 0.0665

Single S = 0, D =0 0.120 0.057 0.057 0.057

E- S D
precision S =2 127
, D =2 127 0.120 0.057 0.057 0.057

Single S1 = 0, S2 =0 0.140 0.0665 0.0665 0.0665

E- S1 S2 D
precision S1 = 2127, S2 = 2127 0.140 0.0665 0.0665 0.0665

788
 Processing Time (µs)
Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
Category Instruction Condition (Device) Q03UD(E)CPU
CPU Q26UD(E)HCPU CPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
Single S1 = 0, S2 =0 0.120 0.057 0.057 0.057
E* S1 S2 D
precision S1 = 2127, S2 = 2127 0.120 0.057 0.057 0.057
2
Single
E/ S1 S2 D S1 = 2127, S2 = 2127 4.500 5.600 3.900 4.900 0.285 0.285
precision
INC When executed 0.040 0.019 0.019 0.019
DINC When executed 0.040 0.019 0.019 0.019
3
DEC When executed 0.040 0.019 0.019 0.019
DDEC When executed 0.040 0.019 0.019 0.019
BCD When executed 0.120 0.057 0.057 0.057 A
DBCD When executed 0.200 0.095 0.095 0.095
BIN When executed 0.060 0.0285 0.0285 0.0285
DBIN When executed 0.060
0.100
0.0285
0.0475
0.0285
0.0475
0.0285
0.0475
5
Single S =0
FLT
precision S = 7FFFH 0.100 0.0475 0.0475 0.0475

DFLT
Single S =0 0.100 0.0475 0.0475 0.0475 6
precision S = 7FFFFFFFH 0.100 0.0475 0.0475 0.0475

Single S =0 0.100 0.0475 0.0475 0.0475

INT
precision S = 32766.5 0.100 0.0475 0.0475 0.0475 7
Single S =0 0.100 0.0475 0.0475 0.0475
DINT
precision = 1234567890.3 0.100 0.0475 0.0475 0.0475
8
S

MOV –– 0.040 0.019 0.019 0.019

DMOV –– 0.040 0.019 0.019 0.019
Basic
EMOV –– 0.040 0.019 0.019 0.019
instruction
CML –– 0.040 0.019 0.019 0.019
DCML –– 0.040 0.019 0.019 0.019

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
6.300 8.200 5.400 7.000 5.400 7.000 5.400 7.000

SM237=OFF*1 8.200 10.600 3.900 5.100 3.900 5.100 3.900 5.100

n=1
*1 6.000 7.800 2.900 3.700 2.900 3.700 2.900 3.700
SM237=ON
BMOV
7.100 8.800 5.900 7.600 5.900 7.600 5.900 7.600

SM237=OFF*1 9.300 11.900 4.400 5.700 4.400 5.700 4.400 5.700

n = 96
*1 7.100 9.100 3.400 4.300 3.400 4.300 3.400 4.300
SM237=ON
5.300 5.900 4.200 4.800 4.200 4.800 4.200 4.800

SM237=OFF*1 7.000 8.000 3.400 3.800 3.400 3.800 3.400 3.800

n=1
SM237=ON*1 5.900 6.800 2.800 3.200 2.800 3.200 2.800 3.200
FMOV
5.300 7.600 4.400 6.800 4.400 6.800 4.400 6.800

SM237=OFF*1 7.400 12.200 3.600 5.800 3.600 5.800 3.600 5.800

n = 96
SM237=ON*1 6.300 11.000 3.000 5.200 3.000 5.200 3.000 5.200
XCH –– 2.500 2.900 1.800 2.300 1.800 2.300 1.800 2.300
DXCH –– 2.800 3.700 2.100 2.900 2.100 2.900 2.100 2.900
SM237=OFF 2.600 3.750 2.250 3.150 2.250 3.150 2.250 3.150
n=1
SM237=ON 2.050 2.250 1.750 1.750 1.750 1.750 1.750 1.750
DFMOV*2
SM237=OFF 5.850 7.350 4.200 5.500 4.200 5.500 5.380 7.440
n=96
SM237=ON 5.300 6.000 3.650 4.150 3.650 4.150 4.700 5.500
CJ –– 1.800 2.800 1.400 2.400 1.400 2.400 1.400 2.400
SCJ –– 1.800 2.800 1.400 2.400 1.400 2.400 1.400 2.400
JMP –– 1.800 2.800 1.100 2.400 1.100 2.400 1.100 2.400
*1: Can be used only for the Q03UDCPU, Q04UDHCPU and Q06UDHCPU whose first 5 digits of serial number is "10012" or
later.
*2: Can be used only for the Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q13UD(E)HCPU and Q26UD(E)HCPU
whose first 5 digits of serial number is "10012" or later.

789
 Processing Time (µs)
Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
Category Instruction Condition (Device) Q03UD(E)CPU
CPU Q26UD(E)HCPU CPU
Min. Max. Min. Max. Min. Max. Min. Max.
WAND S D When executed 0.060 0.0285 0.0285 0.0285

WAND S1 S2 D When executed 0.080 0.038 0.038 0.038

DAND S D When executed 0.060 0.0285 0.0285 0.0285

DAND S1 S2 D When executed 0.080 0.038 0.038 0.038

WOR S D When executed 0.060 0.0285 0.0285 0.0285

WOR S1 S2 D When executed 0.080 0.038 0.038 0.038

DOR S D When executed 0.060 0.0285 0.0285 0.0285

DOR S1 S2 D When executed 0.080 0.038 0.038 0.038

WXOR S D When executed 0.060 0.0285 0.0285 0.0285

WXOR S1 S2 D When executed 0.080 0.038 0.038 0.038

DXOR S D When executed 0.060 0.0285 0.0285 0.0285

DXOR S1 S2 D When executed 0.080 0.038 0.038 0.038

WXNR S D When executed 0.060 0.0285 0.0285 0.0285

WXNR S1 S2 D When executed 0.080 0.038 0.038 0.038

DXNR S D When executed 0.060 0.0285 0.0285 0.0285

DXNR S1 S2 D When executed 0.080 0.038 0.038 0.038

n=1 2.300 3.100 1.700 2.500 1.700 2.500 1.700 2.500

ROR D n
n = 15 2.400 3.100 1.800 2.500 1.800 2.500 1.800 2.500
n=1 2.300 3.900 1.700 3.200 1.700 3.200 1.700 3.200
RCR D n
n = 15 2.400 4.100 1.700 3.200 1.700 3.200 1.700 3.200
n=1 2.400 3.300 1.800 3.200 1.800 3.200 1.800 3.200
ROL D n
Application n = 15 2.400 3.300 1.800 3.200 1.800 3.200 1.800 3.200

instruction n=1 2.400 2.700 1.800 2.100 1.800 2.100 1.800 2.100
RCL D n
n = 15 2.400 2.800 1.800 2.200 1.800 2.200 1.800 2.200
n=1 2.400 3.400 1.900 2.700 1.900 2.700 1.900 2.700
DROR D n
n = 31 2.500 3.400 1.900 2.700 1.900 2.700 1.900 2.700
n=1 2.500 4.800 1.900 4.200 1.900 4.200 1.900 4.200
DRCR D n
n = 31 2.500 4.900 1.900 4.200 1.900 4.200 1.900 4.200
n=1 2.500 3.900 1.800 3.200 1.800 3.200 1.800 3.200
DROL D n
n = 31 2.500 3.900 1.800 3.300 1.800 3.300 1.800 3.300
n=1 2.500 4.800 1.900 3.800 1.900 3.800 1.900 3.800
DRCL D n
n = 31 2.500 4.600 1.900 3.800 1.900 3.800 1.900 3.800
n=1 2.400 3.900 1.700 2.600 1.700 2.600 1.700 2.600
SFR D n
n = 15 2.300 3.900 1.800 2.600 1.800 2.600 1.800 2.600
n=1 2.400 4.300 1.800 2.700 1.800 2.700 1.800 2.700
SFL D n
n = 15 2.400 4.300 1.800 2.700 1.800 2.700 1.800 2.700
n=1 2.700 4.800 2.200 4.300 2.200 4.300 2.200 4.300
DSFR D n
n = 96 32.600 35.900 23.900 26.100 23.900 26.100 23.900 26.100
n=1 2.700 4.600 2.100 4.000 2.100 4.000 2.100 4.000
DSFL D n
n = 96 32.600 35.300 23.700 25.800 23.700 25.800 23.700 25.800

S =0 3.400 4.300 2.900 3.600 2.900 3.600 2.900 3.600

SUM
S = FFFFH 3.500 4.200 2.900 3.600 2.900 3.600 2.900 3.600

SEG When executed 2.100 2.800 1.500 2.100 1.500 2.100 1.500 2.100
FOR –– 1.200 2.400 0.870 2.100 0.870 2.100 0.870 2.100
Internal file pointer 2.600 4.000 2.300 3.600 2.300 3.600 2.300 3.600
CALL Pn
Common pointer 4.000 5.300 3.200 4.900 3.200 4.900 3.200 4.900

CALL Pn S1 to S5 –– 28.700 33.400 26.100 29.300 26.100 29.300 26.100 29.300

790
 Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
3
execution instruction.
Example MOVP instruction, WANDP instruction etc.
2
(c) When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU
Processing Time (µs)
Q06UDVCPU, 3
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
LD A
LDI
AND
When executed 0.0019 0.0078 0.0019 0.0078 0.0019 0.0078
ANI 5
OR
ORI
LDP
LDF 6
ANDP
When executed 0.0058 0.015 0.0058 0.015 0.0058 0.015
ANDF

Sequence
ORP
ORF
7
instruction
LDPI
When executed 0.0058 0.015 0.0058 0.015 0.0058 0.015
LDFI
ANDPI 8
ANDFI
When executed 0.0058 0.015 0.0058 0.015 0.0058 0.015
ORPI
ORFI
When not changed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
OUT
When changed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
When not changed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
SET
When When not changed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
RST
executed When changed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LD=
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
AND= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
OR= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Basic status
instruction In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LD<>
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
AND<> When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
OR<> When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status

791
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LD>
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
AND> When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
OR> When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LD<=
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
AND<= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
OR<= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LD<
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
Basic
In conductive
instruction 0.0098 0.023 0.0098 0.023 0.0098 0.023
AND< When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
OR< When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LD>=
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
AND>= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
OR>= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDD=
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
ANDD= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status

792
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023

ORD= When
In conductive
status
0.0098 0.023 0.0098 0.023 0.0098 0.023 2
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status

LDD<>
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023 3
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
ANDD<> When status
0.0098 0.023 0.0098 0.023 0.0098 0.023 A
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed
In conductive
0.0078 0.023 0.0078 0.023 0.0078 0.023
5
0.0098 0.023 0.0098 0.023 0.0098 0.023
ORD<> When status
executed In non-conductive
status
0.0098 0.023 0.0098 0.023 0.0098 0.023
6
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDD>
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive 7
0.0098 0.023 0.0098 0.023 0.0098 0.023
ANDD> When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status 8
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
Basic 0.0098 0.023 0.0098 0.023 0.0098 0.023
ORD> When status
instruction
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDD<=
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
ANDD<= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
ORD<= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDD<
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
ANDD< When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
ORD< When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status

793
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDD>=
In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
ANDD>= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
ORD>= When status
executed In non-conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
status
+ S D When executed 0.0098 0.023 0.0098 0.023 0.0098 0.023
+ S1 S2 D When executed 0.011 0.031 0.011 0.031 0.011 0.031
- S D When executed 0.0098 0.023 0.0098 0.023 0.0098 0.023
- S1 S2 D When executed 0.011 0.031 0.011 0.031 0.011 0.031
D+ S D When executed 0.0098 0.023 0.0098 0.023 0.0098 0.023
D+ S1 S2 D When executed 0.011 0.031 0.011 0.031 0.011 0.031
D- S D When executed 0.0098 0.023 0.0098 0.023 0.0098 0.023
D- S1 S2 D When executed 0.011 0.031 0.011 0.031 0.011 0.031
* S1 S2 D When executed 0.015 0.023 0.015 0.023 0.015 0.023
/ S1 S2 D When executed 0.023 0.023 0.023 0.023 0.023 0.023
D* S1 S2 D When executed 0.023 0.023 0.023 0.023 0.023 0.023
D/ S1 S2 D When executed 0.033 0.054 0.033 0.054 0.033 0.054
B+ S D When executed 1.400 9.100 1.400 9.100 1.400 9.100
Basic
instruction B+ S1 S2 D When executed 2.100 7.400 2.100 7.400 2.100 7.400
B- S D When executed 1.400 9.000 1.400 9.000 1.400 9.000
B- S1 S2 D When executed 2.100 7.400 2.100 7.400 2.100 7.400
B* S1 S2 D When executed 1.600 10.900 1.600 10.900 1.600 10.900
B/ S1 S2 D When executed 1.700 10.200 1.700 10.200 1.700 10.200
S = 0, D =0 0.013 0.023 0.013 0.023 0.013 0.023
Single
E+ S D S = 2127 ,
precision 0.013 0.023 0.013 0.023 0.013 0.023
127
D =2
S1 = 0, S2 =0 0.015 0.031 0.015 0.031 0.015 0.031
Single 127,
E+ S1 S2 D S1 =2
precision 0.015 0.031 0.015 0.031 0.015 0.031
S2 = 2127
S = 0,
0.013 0.023 0.013 0.023 0.013 0.023
Single D =0
E- S D
precision S = 2127,
0.013 0.023 0.013 0.023 0.013 0.023
D = 2127
S1 = 0, S2 =0 0.015 0.031 0.015 0.031 0.015 0.031
Single 127
E- S1 S2 D S1 =2 ,
precision 0.015 0.031 0.015 0.031 0.015 0.031
S2 = 2127
S1 = 0, S2 =0 0.013 0.023 0.013 0.023 0.013 0.023
Single
E* S1 S2 D S1 = 2127,
precision 0.013 0.023 0.013 0.023 0.013 0.023
S2 = 2127
Single S1 = 2127,
E/ S1 S2 D 0.060 0.060 0.060 0.060 0.060 0.060
precision S2 = 2127

794
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
INC When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
DINC
DEC
When executed
When executed
0.0078
0.0078
0.015
0.015
0.0078
0.0078
0.015
0.015
0.0078
0.0078
0.015
0.015
2
DDEC When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
BCD When executed 0.013 0.015 0.013 0.015 0.013 0.015
DBCD When executed 0.021 0.019 0.021 0.019 0.021 0.019 3
BIN When executed 0.0098 0.015 0.0098 0.015 0.0098 0.015
DBIN When executed 0.0098 0.015 0.0098 0.015 0.0098 0.015
0.0098 0.015 0.0098 0.015 0.0098 0.015
Single =0
A
S
FLT
precision S = 7FFFH 0.0098 0.015 0.0098 0.015 0.0098 0.015

Single S =0 0.0098 0.015 0.0098 0.015 0.0098 0.015

DFLT
precision S = 7FFFFFFFH 0.0098 0.015 0.0098 0.015 0.0098 0.015
5
Single S =0 0.0098 0.015 0.0098 0.015 0.0098 0.015
INT
precision S = 32766.5 0.0098 0.015 0.0098 0.015 0.0098 0.015

Single
S =0 0.0098 0.015 0.0098 0.015 0.0098 0.015
6
DINT S =
precision 0.0098 0.015 0.0098 0.015 0.0098 0.015
1234567890.3
MOV –– 0.0039 0.015 0.0039 0.015 0.0039 0.015
Basic DMOV –– 0.0039 0.015 0.0039 0.015 0.0039 0.015 7
instruction EMOV –– 0.0039 0.015 0.0039 0.015 0.0039 0.015
CML –– 0.0058 0.015 0.0058 0.015 0.0058 0.015
DCML –– 0.0058 0.015 0.0058 0.015 0.0058 0.015
8
SM237=OFF*1 1.800 5.500 1.800 5.500 1.800 5.500
n=1
SM237=ON*1 0.800 0.800 0.800 0.800 0.800 0.800
BMOV
SM237=OFF*1 2.300 6.000 2.300 6.000 2.300 6.000
n = 96
SM237=ON*1 1.400 1.400 1.400 1.400 1.400 1.400

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
*1 1.400 5.000 1.400 5.000 1.400 5.000
SM237=OFF
n=1
SM237=ON*1 0.600 0.600 0.600 0.600 0.600 0.600
FMOV
SM237=OFF*1 2.100 5.700 2.100 5.700 2.100 5.700
n = 96
SM237=ON*1 1.400 1.400 1.400 1.400 1.400 1.400
XCH –– 0.700 1.900 0.700 1.900 0.700 1.900
DXCH –– 0.700 2.200 0.700 2.200 0.700 2.200
SM237=OFF 1.400 5.500 1.400 5.500 1.400 5.500
n=1
*2
SM237=ON 0.600 1.400 0.600 1.400 0.600 1.400
DFMOV
SM237=OFF 2.300 6.600 2.300 6.600 2.300 6.600
n=96
SM237=ON 1.500 2.400 1.500 2.400 1.500 2.400
CJ –– 1.000 4.400 1.000 4.400 1.000 4.400
SCJ –– 1.000 4.400 1.000 4.400 1.000 4.400
JMP –– 1.000 4.400 1.000 4.400 1.000 4.400
WAND S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
WAND S1 S2
When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
D

DAND S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023

DAND S1 S2
Application When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
D
instruction
WOR S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
WOR S1 S2 D When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
DOR S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
DOR S1 S2 D When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
WXOR S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023

795
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
WXOR S1 S2
When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
D

DXOR S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023

DXOR S1 S2
When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
D

WXNR S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023

WXNR S1 S2
When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
D

DXNR S D When executed 0.0078 0.023 0.0078 0.023 0.0078 0.023

DXNR S1 S2
When executed 0.0098 0.031 0.0098 0.031 0.0098 0.031
D

n=1 0.011 0.023 0.011 0.023 0.011 0.023

ROR D n
n = 15 0.011 0.023 0.011 0.023 0.011 0.023
n=1 0.015 0.031 0.015 0.031 0.015 0.031
RCR D n
n = 15 0.015 0.031 0.015 0.031 0.015 0.031
n=1 0.011 0.023 0.011 0.023 0.011 0.023
ROL D n
n = 15 0.011 0.023 0.011 0.023 0.011 0.023
n=1 0.015 0.031 0.015 0.031 0.015 0.031
RCL D n
n = 15 0.015 0.031 0.015 0.031 0.015 0.031
n=1 0.011 0.023 0.011 0.023 0.011 0.023
Application DROR D n
n = 31 0.011 0.023 0.011 0.023 0.011 0.023
instruction n=1 0.015 0.031 0.015 0.031 0.015 0.031
DRCR D n
n = 31 0.015 0.031 0.015 0.031 0.015 0.031
n=1 0.011 0.023 0.011 0.023 0.011 0.023
DROL D n
n = 31 0.011 0.023 0.011 0.023 0.011 0.023
n=1 0.015 0.031 0.015 0.031 0.015 0.031
DRCL D n
n = 31 0.015 0.031 0.015 0.031 0.015 0.031
n=1 0.011 0.023 0.011 0.023 0.011 0.023
SFR D n
n = 15 0.011 0.023 0.011 0.023 0.011 0.023
n=1 0.011 0.023 0.011 0.023 0.011 0.023
SFL D n
n = 15 0.011 0.023 0.011 0.023 0.011 0.023
n=1 1.000 6.300 1.000 6.300 1.000 6.300
DSFR D n
n = 96 8.100 14.100 8.100 14.100 8.100 14.100
n=1 1.000 6.300 1.000 6.300 1.000 6.300
DSFL D n
n = 96 8.100 14.100 8.100 14.100 8.100 14.100
S =0 1.300 4.900 1.300 4.900 1.300 4.900
SUM
S = FFFFH 1.300 4.900 1.300 4.900 1.300 4.900
SEG When executed 1.000 4.800 1.000 4.800 1.000 4.800
FOR –– 0.0058 0.015 0.0058 0.015 0.0058 0.015
Internal file pointer 0.900 0.900 0.900 0.900 0.900 0.900
CALL Pn
Common pointer 3.200 12.300 3.200 12.300 3.200 12.300
CALL Pn S1 to
–– 8.500 29.500 8.500 29.500 8.500 29.500
S5

Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
execution instruction.
Example MOVP instruction, WANDP instruction etc.

796
(2) Table of the time to be added when file register, extended data register, extended link register, and module access device
are used
(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU 3
Device Processing Time (µs)
Device name Data Specification
Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Location
Source 0.100 0.100 0.100 0.100
2
Bit
Destination 0.220 0.220 0.220 0.220
When standard Source 0.100 0.100 0.100 0.100
Word
RAM is used Destination 0.100 0.100 0.100 0.100 3
Source 0.200 0.200 0.200 0.200
Double word
Destination 0.200 0.200 0.200 0.200
Source –– –– –– 0.220
When SRAM
Bit
Destination –– –– –– 0.420 A
File register card is used Source –– –– –– 0.220
Word
(R) (Q2MEM-1MBS, Destination –– –– –– 0.180
Q2MEM-2MBS)
Double word
Source
Destination
––
––
––
––
––
––
0.440
0.380
5
Source –– –– –– 0.160
Bit
When SRAM Destination –– –– –– 0.320
card is used
(Q3MEM-4MBS,
Word
Source
Destination
––
––
––
––
––
––
0.160
0.140
6
Q3MEM-8MBS) Source –– –– –– 0.320
Double word
Destination –– –– –– 0.300

Bit
Source 0.220 0.180 0.160 0.140 7
Destination 0.280 0.320 0.300 0.280
When standard Source 0.220 0.180 0.160 0.140
Word
RAM is used Destination 0.220 0.180 0.160 0.140
Source 0.320 0.280 0.260 0.240 8
Double word
Destination 0.320 0.280 0.260 0.240
Source –– –– –– 0.260
File register Bit
(ZR)/ When SRAM Destination –– –– –– 0.480
Extended data card is used Source –– –– –– 0.260
Word
register (D)/ (Q2MEM-1MBS,

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Destination –– –– –– 0.220
Extended link Q2MEM-2MBS) Source –– –– –– 0.480
register (W) Double word
Destination –– –– –– 0.420
Source –– –– –– 0.200
Bit
When SRAM Destination –– –– –– 0.380
card is used Source –– –– –– 0.200
Word
(Q3MEM-4MBS, Destination –– –– –– 0.180
Q3MEM-8MBS) Source –– –– –– 0.360
Double word
Destination –– –– –– 0.340
Source –– –– –– ––
Bit
Module access device Destination –– –– –– ––
(Multiple CPU high speed Source –– –– –– ––
Word
transmission area) Destination –– –– –– ––
(U3En\G10000) Source –– –– –– ––
Double word
Destination –– –– –– ––

797
 (b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UDE(H)CPU,
Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU and Q100UDEHCPU
Device Processing Time (µs)
Device name Data Specification Q03UD(E) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
Location CPU CPU Q26UD(E)HCPU CPU
Source 0.100 0.048 0.048 0.048
Bit
Destination 0.100 0.038 0.038 0.038
When standard Source 0.100 0.048 0.048 0.048
Word
RAM is used Destination 0.100 0.038 0.038 0.038
Source 0.200 0.095 0.095 0.095
Double word
Destination 0.200 0.086 0.086 0.086
Source 0.220 0.200 0.200 0.200
Bit
When SRAM Destination 0.180 0.162 0.162 0.162
File register card is used Source 0.220 0.200 0.200 0.200
Word
(R) (Q2MEM-1MBS, Destination 0.180 0.162 0.162 0.162
Q2MEM-2MBS) Source 0.440 0.399 0.399 0.399
Double word
Destination 0.380 0.361 0.361 0.361
Source 0.160 0.152 0.152 0.152
Bit
When SRAM Destination 0.140 0.133 0.133 0.133
card is used Source 0.160 0.152 0.152 0.152
Word
(Q3MEM-4MBS, Destination 0.140 0.133 0.133 0.133
Q3MEM-8MBS) Source 0.320 0.304 0.304 0.304
Double word
Destination 0.300 0.295 0.295 0.295
Source 0.120 0.057 0.057 0.057
Bit
Destination 0.120 0.048 0.048 0.048
When standard Source 0.120 0.057 0.057 0.057
Word
RAM is used Destination 0.120 0.048 0.048 0.048
Source 0.220 0.105 0.105 0.105
Double word
Destination 0.220 0.095 0.095 0.095
Source 0.240 0.209 0.209 0.209
File register Bit
(ZR)/ When SRAM Destination 0.200 0.171 0.171 0.171
Extended data card is used Source 0.240 0.209 0.209 0.209
Word
register (D)/ (Q2MEM-1MBS, Destination 0.200 0.171 0.171 0.171
Extended link Q2MEM-2MBS) Source 0.460 0.409 0.409 0.409
register (W) Double word
Destination 0.400 0.371 0.371 0.371
Source 0.180 0.162 0.162 0.162
Bit
When SRAM Destination 0.160 0.143 0.143 0.143
card is used Source 0.180 0.162 0.162 0.162
Word
(Q3MEM-4MBS, Destination 0.160 0.143 0.143 0.143
Q3MEM-8MBS) Source 0.340 0.314 0.314 0.314
Double word
Destination 0.320 0.304 0.304 0.304
Source 0.220 0.181 0.181 0.181
Bit
Module access device Destination 0.140 0.105 0.105 0.105
(Multiple CPU high speed Source 0.220 0.181 0.181 0.181
Word
transmission area) Destination 0.140 0.105 0.105 0.105
(U3En\G10000) Source 0.500 0.437 0.437 0.437
Double word
Destination 0.340 0.285 0.285 0.285

798
 (c) When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU and, Q26UDVCPU
Processing Time (µs)
Q06UDVCPU,
Device name Data
Device Specification
Location Q03UDVCPU Q04UDVCPU Q13UDVCPU,
3
Q26UDVCPU
Source 0.074 0.043 0.043
Bit
When the extended
Destination 0.023 0.023 0.023 2
Source 0.074 0.043 0.043
SRAM cassette is not Word
Destination 0.023 0.023 0.023
used
Source 0.148 0.085 0.085

File register (R)

Double word
Destination 0.044 0.044 0.044 3
Source 0.099 0.099 0.099
Bit
Destination 0.028 0.028 0.028
0.099 0.099 0.099
When the extended
SRAM cassette is used
Word
Source
Destination 0.028 0.028 0.028
A
Source 0.198 0.198 0.198
Double word
Destination 0.054 0.054 0.054

Bit
Source
Destination
0.074
0.023
0.043
0.023
0.043
0.023
5
When the extended
Source 0.074 0.043 0.043
SRAM cassette is not Word
Destination 0.023 0.023 0.023
File register (ZR)/
used
Double word
Source 0.148 0.085 0.085 6
Extended data Destination 0.044 0.044 0.044
register (D)/Extended Source 0.099 0.099 0.099
Bit
link register (W) Destination 0.028 0.028 0.028
When the extended Source 0.099 0.099 0.099 7
Word
SRAM cassette is used Destination 0.028 0.028 0.028
Source 0.198 0.198 0.198
Double word
Destination
Source
0.054
0.042
0.054
0.042
0.054
0.042
8
Bit
Destination 0.049 0.049 0.049
Module access device (Multiple CPU high speed Source 0.042 0.042 0.042
Word
transmission area) (U3En\G10000) Destination 0.049 0.049 0.049
Source 0.092 0.092 0.092
Double word

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Destination 0.095 0.095 0.095

(3) Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction
(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU
Instruction Processing Time (µs)
Device name Condition
name Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
When not executed 2.900 2.900 2.900 2.100
F When displayed 116.000 116.000 116.000 68.800
When executed
Display completed 116.000 116.000 116.000 61.600
OUT
When not executed 0.360 0.240 0.180 0.120
T(ST), C After time up 0.360 0.240 0.180 0.120
When executed
When added 0.360 0.240 0.180 0.120
When not executed 0.120 0.080 0.006 0.004
SET F When displayed 116.000 116.000 116.000 68.600
When executed
Display completed 116.000 116.000 116.000 65.700
When not executed 0.120 0.080 0.006 0.004
F When displayed 55.800 55.800 55.800 26.500
When executed
RST Display completed 29.200 29.200 29.200 21.600
When not executed 0.360 0.240 0.180 0.120
T(ST), C
When executed 0.360 0.240 0.180 0.120

799
 (b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU,
Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU and Q100UDEHCPU
Processing Time (µs)
Instruction
Device name Condition Q03UD(E) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
name
CPU CPU Q26UD(E)HCPU CPU
When not executed 1.940 1.570 1.570 1.570
F When displayed 39.930 38.090 38.090 38.090
When executed
OUT Display completed 39.750 37.980 37.980 37.980
When not executed 0.060 0.030 0.030 0.030
T(ST), C
When executed After time up 0.060 0.030 0.030 0.030
When not executed 0.000 0.000 0.000 0.000
SET F When displayed 42.900 40.600 40.600 40.600
When executed
Display completed 39.270 37.900 37.900 37.900
When not executed 0.000 0.000 0.000 0.000
F When displayed 45.260 36.600 36.600 36.600
When executed
RST Display completed 19.020 16.190 16.190 16.190
When not executed 0.060 0.030 0.030 0.030
T(ST), C
When executed 0.060 0.030 0.030 0.030

(c) When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU, and Q26UDVCPU

Processing Time (µs)
Q06UDVCPU,
Instruction
Device name Condition Q03UDVCPU Q04UDVCPU Q13UDVCPU,
name
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
When not executed 1.100 3.900 1.100 3.900 1.100 3.900
F When displayed 15.000 49.000 15.000 49.000 15.000 49.000
When executed
Display completed 13.800 46.000 13.800 46.000 13.800 46.000
OUT
When not executed 0.011 0.011 0.011
T(ST), C After time up 0.011 0.011 0.011
When executed
When added 0.011 0.011 0.011
When not executed 0.005 0.005 0.005
SET F When displayed 14.000 49.000 14.000 49.000 14.000 49.000
When executed
Display completed 13.000 45.000 13.000 45.000 13.000 45.000
When not executed 0.005 0.005 0.005
F When displayed 7.900 26.000 7.900 26.000 7.900 26.000
When executed
RST Display completed 6.300 25.000 6.300 25.000 6.300 25.000
When not executed 0.011 0.011 0.011
T(ST), C
When executed 0.011 0.011 0.011

800
 Appendix 1.4.2 Processing time of instructions other than subset instruction
The following table shows the processing time of instructions other than subset instructions.
3

• The processing time shown in "(1) Table of the processing time of instructions other than subset instructions" applies
when the device used in an instruction does not meet the device condition for subset processing (For device condition 2
that does not trigger subset processing, refer to Page 109, Section 3.5.1).
For instructions not shown in the following table, refer to "(1) Subset instruction processing time table" in Page 781,
Appendix 1.4.1(1).
• When using a file resister (R, ZR), extended data register (D), extended link register (W), module access device (Un\G 3
and U3En\G0 to G4095), and link direct device (Jn\ ), add the processing time shown in (2) to that of the instruction.
• Since the processing time of an instruction varies depending on that of the cash function, both the minimum and
maximum values are described in the table.
A
(1) Table of the processing time of instructions other than subset instructions
(a) When using Q00UJCPU, Q00UCPU, Q01UCPU and Q02UCPU
Processing Time (µs) 5
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
ANB 6
ORB
MPS –– 0.120 0.080 0.060 0.040
MRD
MPP 7
When not executed
INV 0.120 0.080 0.060 0.040
When executed
MEP When not executed
0.120 0.080 0.060 0.040 8
MEF When executed
EGP When not executed
0.120 0.080 0.060 0.040
EGF When executed
PLS –– 1.800 1.900 1.800 1.900 1.800 1.900 1.300 1.600
Sequence PLF –– 1.800 1.900 1.800 1.900 1.800 1.900 1.600 1.700

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
instruction When not executed 0.240 0.160 0.120 0.080
FF
When executed 1.700 1.800 1.700 1.800 1.700 1.800 1.200 1.500
When not executed 0.240 0.160 0.120 0.080
DELTA
When executed 4.000 14.700 4.000 14.700 4.000 14.700 2.800 3.600
When not executed 0.240 0.160 0.120 0.800
SFT
When executed 1.800 12.600 1.800 12.600 1.800 12.600 1.600 6.600
MC –– 0.240 0.160 0.120 0.080
MCR –– 0.120 0.080 0.060 0.040
FEND Error check performed 250.000 250.000 250.000 250.000 250.000 250.000 175.000 252.000
END No error check performed 250.000 250.000 250.000 250.000 250.000 250.000 175.000 221.000
NOP
NOPLF –– 0.120 0.080 0.060 0.040
PAGE

801
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.100
LDE=
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.100
When not executed 0.360 0.240 0.180 0.120
Single
ANDE= When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.200 12.500
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 11.900
When not executed 0.360 0.240 0.180 0.120
Single
ORE= When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 10.800
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.500 9.800
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 7.700
LDE< >
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.600 8.200
When not executed 0.360 0.240 0.180 0.120
Single
ANDE< > When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.300 14.200
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 14.200
When not executed 0.360 0.240 0.180 0.120
Single
ORE< > When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 6.700
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 6.600
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 13.700
LDE>
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.600 13.700
When not executed 0.360 0.240 0.180 0.120
Single
ANDE> When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.300 8.100
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.200 8.100
When not executed 0.360 0.240 0.180 0.120
Single
ORE> When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 8.500
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 8.100
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 11.100
LDE<=
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 9.600
Basic
When not executed 0.360 0.240 0.180 0.120
instruction Single
ANDE<= When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.100 7.800
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 8.200
When not executed 0.360 0.240 0.180 0.120
Single
ORE<= When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.500 10.300
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 9.800
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 11.500
LDE<
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 10.900
When not executed 0.360 0.240 0.180 0.120
Single
ANDE< When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.300 9.200
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 9.400
When not executed 0.360 0.240 0.180 0.120
Single
ORE< When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 10.400
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.400 9.800
Single In conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 12.200
LDE>=
precision In non-conductive status 4.400 20.900 4.400 20.900 4.400 20.900 4.700 11.800
When not executed 0.360 0.240 0.180 0.120
Single
ANDE>= When In conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.100 6.700
precision
executed In non-conductive status 4.200 19.600 4.200 19.600 4.200 19.600 4.400 7.000
When not executed 0.360 0.240 0.180 0.120
Single
ORE>= When In conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.600 14.000
precision
executed In non-conductive status 4.200 17.400 4.200 17.400 4.200 17.400 4.500 14.300
Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 21.000
LDED=
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 21.900
When not executed 0.360 0.240 0.180 0.120
Double
ANDED= When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 3.800 17.800
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 18.100

802
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
When not executed 0.360 0.240 0.180 0.120
Double
ORED= When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.100 23.800
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.900 25.500
Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 23.500
2
LDED<>
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 22.600
When not executed 0.360 0.240 0.180 0.120
ANDED<>
Double
precision
When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 18.800 3
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 18.700
When not executed 0.360 0.240 0.180 0.120
Double
ORED<>
precision
When In conductive status
executed In non-conductive status
4.700
4.700
33.200
33.200
4.700
4.700
33.200
33.200
4.700
4.700
33.200
33.200
5.000
4.100
25.200
23.400
A
Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 25.100
LDED>
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 23.400
When not executed 0.360 0.240 0.180 0.120 5
Double
ANDED> When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 19.500
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.700

Double
When not executed 0.360 0.240 0.180 0.120
6
ORED> When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 24.200
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.900 25.800
Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 22.500
LDED<=
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 13.500
7
When not executed 0.360 0.240 0.180 0.120
Double
ANDED<= When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 19.600
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.700 8
When not executed 0.360 0.240 0.180 0.120
Basic Double
ORED<= When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 26.300
instruction precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.200
Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 5.100 25.000
LDED<

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 24.100
When not executed 0.360 0.240 0.180 0.120
Double
ANDED< When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.000 19.400
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.700
When not executed 0.360 0.240 0.180 0.120
Double
ORED< When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.100
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.100
Double In conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.200 13.100
LDED>=
precision In non-conductive status 4.700 37.400 4.700 37.400 4.700 37.400 4.300 13.100
When not executed 0.360 0.240 0.180 0.120
Double
ANDED>= When In conductive status 4.500 34.700 4.500 34.700 4.500 34.700 3.900 19.500
precision
executed In non-conductive status 4.500 34.700 4.500 34.700 4.500 34.700 4.100 19.800
When not executed 0.360 0.240 0.180 0.120
Double
ORED>= When In conductive status 4.700 33.200 4.700 33.200 4.700 33.200 5.000 25.100
precision
executed In non-conductive status 4.700 33.200 4.700 33.200 4.700 33.200 4.200 18.500
In conductive status 8.300 38.500 8.300 38.500 8.300 38.500 5.500 14.900
LD$=
In non-conductive status 8.300 38.500 8.300 38.500 8.300 38.500 5.500 15.600
When not executed 0.360 0.240 0.180 0.120
AND$= In conductive status 7.200 37.300 7.200 37.300 7.200 37.300 5.200 13.800
When executed
In non-conductive status 7.200 37.300 7.200 37.300 7.200 37.300 5.300 14.500
When not executed 0.360 0.240 0.180 0.120
OR$= In conductive status 7.500 36.600 7.500 36.600 7.500 36.600 5.500 14.900
When executed
In non-conductive status 7.500 36.600 7.500 36.600 7.500 36.600 5.300 14.600

803
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
In conductive status 8.300 39.300 8.300 39.300 8.300 39.300 5.600 15.200
LD$< >
In non-conductive status 8.300 39.300 8.300 39.300 8.300 39.300 5.600 15.400
When not executed 0.360 0.240 0.180 0.120
AND$< > In conductive status 8.000 38.200 8.000 38.200 8.000 38.200 4.300 21.500
When executed
In non-conductive status 8.000 38.200 8.000 38.200 8.000 38.200 4.500 23.400
When not executed 0.360 0.240 0.180 0.120
OR$< > In conductive status 8.300 37.300 8.300 37.300 8.300 37.300 5.400 17.700
When executed
In non-conductive status 8.300 37.300 8.300 37.300 8.300 37.300 5.300 19.400
In conductive status 8.300 41.600 8.300 41.600 8.300 41.600 6.400 19.200
LD$>
In non-conductive status 8.300 41.600 8.300 41.600 8.300 41.600 5.600 20.100
When not executed 0.360 0.240 0.180 0.120
AND$> In conductive status 8.000 38.100 8.000 38.100 8.000 38.100 4.500 15.400
When executed
In non-conductive status 8.000 38.100 8.000 38.100 8.000 38.100 4.600 15.300
When not executed 0.360 0.240 0.180 0.120
OR$> In conductive status 8.200 35.700 8.200 35.700 8.200 35.700 5.400 20.000
When executed
In non-conductive status 8.200 35.700 8.200 35.700 8.200 35.700 5.400 22.100
In conductive status 8.300 39.200 8.300 39.200 8.300 39.200 5.800 12.800
LD$<=
In non-conductive status 8.300 39.200 8.300 39.200 8.300 39.200 6.300 13.900
When not executed 0.360 0.240 0.180 0.120
Basic AND$<= In conductive status 7.100 36.500 7.100 36.500 7.100 36.500 6.000 16.000
When executed
instruction In non-conductive status 7.100 36.500 7.100 36.500 7.100 36.500 6.100 16.200
When not executed 0.360 0.240 0.180 0.120
OR$<= In conductive status 7.400 35.600 7.400 35.600 7.400 35.600 4.700 14.600
When executed
In non-conductive status 7.400 35.600 7.400 35.600 7.400 35.600 4.600 14.400
In conductive status 7.400 40.000 7.400 40.000 7.400 40.000 4.800 17.000
LD$<
In non-conductive status 7.400 40.000 7.400 40.000 7.400 40.000 5.500 18.000
When not executed 0.360 0.240 0.180 0.120
AND$< In conductive status 8.000 37.300 8.000 37.300 8.000 37.300 5.900 13.400
When executed
In non-conductive status 8.000 37.300 8.000 37.300 8.000 37.300 6.200 14.500
When not executed 0.360 0.240 0.180 0.120
OR$< In conductive status 8.300 35.600 8.300 35.600 8.300 35.600 6.200 18.700
When executed
In non-conductive status 8.300 35.600 8.300 35.600 8.300 35.600 5.400 19.700
In conductive status 7.400 38.300 7.400 38.300 7.400 38.300 4.800 10.000
LD$>=
In non-conductive status 7.400 38.300 7.400 38.300 7.400 38.300 5.500 11.200
When not executed 0.360 0.240 0.180 0.120
AND$>= In conductive status 7.200 37.300 7.200 37.300 7.200 37.300 4.400 21.600
When executed
In non-conductive status 7.200 37.300 7.200 37.300 7.200 37.300 4.500 21.800
When not executed 0.360 0.240 0.180 0.120
OR$>= In conductive status 8.200 36.400 8.200 36.400 8.200 36.400 5.400 15.400
When executed
In non-conductive status 8.200 36.400 8.200 36.400 8.200 36.400 5.300 15.300

804
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.600
BKCMP = S1 S2 D n
n = 96 64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.500
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.500
BKCMP<> S1 S2 D n
n = 96 66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.500
2
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 23.100
BKCMP> S1 S2 D n
n = 96 66.600 87.500 66.600 87.500 66.600 87.500 59.500 74.400

BKCMP<= S1 S2 D n
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.200 22.500 3
n = 96 64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.400
n=1 15.300 36.100 15.300 36.100 15.300 36.100 8.300 23.000
BKCMP< S1 S2 D n
n = 96
n=1
66.600
15.300
87.500
36.100
66.600
15.300
87.500
36.100
66.600
15.300
87.500
36.100
59.500
8.200
74.500
22.500
A
BKCMP>= S1 S2 D n
n = 96 64.500 85.500 64.500 85.500 64.500 85.500 57.400 72.400
n=1 15.800 36.300 15.800 36.300 15.800 36.300 9.350 29.000
DBKCMP = S1 S2 D n
n = 96 64.900 85.700 64.900 85.700 64.900 85.700 60.700 78.400 5
n=1 15.700 36.300 15.700 36.300 15.700 36.300 9.350 28.900
DBKCMP<> S1 S2 D n
n = 96 67.000 87.700 67.000 87.700 67.000 87.700 62.500 80.300

DBKCMP> S1 S2 D n
n=1 15.800 36.300 15.800 36.300 15.800 36.300 9.350 29.000
6
n = 96 67.000 87.700 67.000 87.700 67.000 87.700 62.600 80.300
n=1 15.700 36.300 15.700 36.300 15.700 36.300 9.350 29.000
DBKCMP<= S1 S2 D n
n = 96 64.800 85.700 64.800 85.700 64.800 85.700 60.800 78.400
n=1 15.800 36.300 15.800 36.300 15.800 36.300 9.350 29.000
7
DBKCMP< S1 S2 D n
n = 96 67.000 87.700 67.000 87.700 67.000 87.700 62.700 80.400
n=1 15.700 36.300 15.700 36.300 15.700 36.300 9.300 29.000
DBKCMP>= S1 S2 D n
n = 96 64.800 85.700 64.800 85.700 64.800 85.700 60.700 78.400 8
DB + S D When executed 5.750 13.300 5.750 13.300 5.750 13.300 4.900 7.500

DB + S1 S2 D When executed 5.650 13.200 5.650 13.200 5.650 13.200 5.200 11.000
Basic
instruction DB - S D When executed 5.750 12.700 5.750 12.700 5.750 12.700 4.900 10.200

DB - When executed 5.650 12.600 5.650 12.600 5.650 12.600 5.200 8.600

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
S1 S2 D

DB * S1 S2 D When executed 8.750 40.200 8.750 40.200 8.750 40.200 8.300 22.200

DB/ S1 S2 D When executed 5.750 21.500 5.750 21.500 5.750 21.500 6.100 19.200

Double S = 0, D =0 4.500 26.700 4.500 26.700 4.500 26.700 4.800 16.800

ED + S D
precision S = 21023, D = 21023 5.800 32.900 5.800 32.900 5.800 32.900 4.800 16.800

Double S1 = 0, S2 =0 5.450 35.400 5.450 35.400 5.450 35.400 7.100 20.100

ED + S1 S2 D
precision S1 = 21023, S2 =2 1023 6.750 41.400 6.750 41.400 6.750 41.400 7.100 20.100

Double S = 0, D =0 5.200 25.900 5.200 25.900 5.200 25.900 5.000 17.300

ED - S D
precision S =2 1023
, D =2 1023 6.000 27.700 6.000 27.700 6.000 27.700 5.000 17.300

Double S1 = 0, S2 =0 5.550 32.900 5.550 32.900 5.550 32.900 6.000 16.300

ED - S1 S2 D
precision S1 = 21023, S2 = 21023 5.750 33.900 5.750 33.900 5.750 33.900 6.000 16.300

Double S1 = 0, S2 =0 5.550 34.400 5.550 34.400 5.550 34.400 10.500 22.300

ED * S1 S2 D
precision S1 = 21023, S2 = 21023 5.950 39.100 5.950 39.100 5.950 39.100 10.500 22.300

Double
ED / S1 S2 D S1 = 21023, S2 = 21023 8.050 44.200 8.050 44.200 8.050 44.200 7.500 27.200
precision
n=1 13.500 28.500 13.500 28.500 13.500 28.500 12.100 19.700
BK + S1 S2 D n
n = 96 63.100 78.200 63.100 78.200 63.100 78.200 61.700 69.300
n=1 13.500 28.500 13.500 28.500 13.500 28.500 12.100 20.600
BK - S1 S2 D n
n = 96 63.100 78.200 63.100 78.200 63.100 78.200 61.700 70.200
n=1 10.100 24.200 10.100 24.200 10.100 24.200 7.050 19.200
DBK + S1 S2 D n
n = 96 59.800 73.900 59.800 73.900 59.800 73.900 59.400 68.900
n=1 10.100 24.200 10.100 24.200 10.100 24.200 7.050 19.900
DBK - S1 S2 D n
n = 96 59.800 73.900 59.800 73.900 59.800 73.900 59.400 69.600

805
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
$+ S D –– 15.400 64.300 15.400 64.300 15.400 64.300 14.400 34.000

$+ S1 S2 D –– 19.700 71.000 19.700 71.000 19.700 71.000 9.200 22.900

Double S =0 3.100 19.600 3.100 19.600 3.100 19.600 4.000 8.900

FLTD
precision S = 7FFFH 3.350 19.900 3.350 19.900 3.350 19.900 3.400 9.000

Double S =0 3.200 20.400 3.200 20.400 3.200 20.400 4.100 10.800

DFLTD
precision S = 7FFFFFFFH 3.450 20.500 3.450 20.500 3.450 20.500 3.600 10.800

Double S =0 3.200 22.900 3.200 22.900 3.200 22.900 3.500 9.300

INTD
precision S = 32766.5 4.100 34.300 4.100 34.300 4.100 34.300 5.100 19.500

Double S =0 3.200 23.000 3.200 23.000 3.200 23.000 2.600 6.800

DINTD
precision S = 1234567890.3 4.050 33.500 4.050 33.500 4.050 33.500 3.400 11.700

DBL When executed 3.300 5.900 3.300 5.900 3.300 5.900 2.700 3.800
WORD When executed 3.000 7.250 3.000 7.250 3.000 7.250 2.900 7.000
GRY When executed 3.350 7.500 3.350 7.500 3.350 7.500 2.700 6.100
DGRY When executed 3.000 7.200 3.000 7.200 3.000 7.200 2.900 4.600
GBIN When executed 4.600 9.700 4.600 9.700 4.600 9.700 4.000 8.200
DGBIN When executed 5.550 10.700 5.550 10.700 5.550 10.700 5.500 8.000
NEG When executed 3.300 6.850 3.300 6.850 3.300 6.850 2.400 4.100
DNEG When executed 3.050 5.700 3.050 5.700 3.050 5.700 2.500 4.300
Floating point = 0 3.100 7.350 3.100 7.350 3.100 7.350 2.500 3.400
ENEG
Floating point = -1.0 3.350 11.700 3.350 11.700 3.350 11.700 2.700 4.500
Floating point = 0 3.000 21.200 3.000 21.200 3.000 21.200 2.200 3.500
EDNEG
Floating point = -1.0 3.100 22.900 3.100 22.900 3.100 22.900 2.400 3.500
n=1 8.700 27.600 8.700 27.600 8.700 27.600 9.700 22.000
BKBCD S D n
n = 96 84.200 104.000 84.200 104.000 84.200 104.000 74.200 86.500
Basic n=1 8.450 28.100 8.450 28.100 8.450 28.100 8.900 16.300
instruction BKBIN S D n
n = 96 56.100 75.800 56.100 75.800 56.100 75.800 58.500 65.100
ECON –– 3.100 21.300 3.100 21.300 3.100 21.300 4.300 6.800
EDCON –– 5.050 24.000 5.050 24.000 5.050 24.000 2.800 5.400
EDMOV –– 2.900 22.900 2.900 22.900 2.900 22.900 3.200 7.800
Character string to be
6.250 30.100 6.250 30.100 6.250 30.100 4.500 13.900
transferred = 0
$MOV
Character string to be
15.500 39.300 15.500 39.300 15.500 39.300 15.400 17.500
transferred = 32
n=1 8.400 20.900 8.400 20.900 8.400 20.900 8.700 15.200
BXCH D1 D2 n
n = 96 67.100 79.900 67.100 79.900 67.100 79.900 67.200 74.000
SWAP –– 3.300 3.550 3.300 3.550 3.300 3.550 2.400 2.700
GOEND –– 0.550 0.550 0.550 0.500
DI –– 2.800 8.400 2.800 8.400 2.800 8.400 1.800 2.200
EI –– 4.300 12.300 4.300 12.300 4.300 12.300 3.100 3.800
IMASK –– 12.900 40.600 12.900 40.600 12.900 40.600 9.800 25.000
IRET –– 1.000 1.000 1.000 1.000
n=1 7.500 26.500 7.500 26.500 7.500 26.500 4.300 16.100
RFS X n
n = 96 11.400 30.400 11.400 30.400 11.400 30.400 11.400 23.700
n=1 7.300 26.300 7.300 26.300 7.300 26.300 3.800 10.000
RFS Y n
n = 96 10.900 29.900 10.900 29.900 10.900 29.900 8.500 15.200
UDCNT1 –– 1.500 7.100 1.500 7.100 1.500 7.100 1.000 2.000
UDCNT2 –– 1.500 6.300 1.500 6.300 1.500 6.300 1.000 4.000
TTMR –– 5.300 20.900 5.300 20.900 5.300 20.900 3.900 6.100
STMR –– 8.900 49.800 8.900 49.800 8.900 49.800 7.200 30.000
ROTC –– 52.300 52.600 52.300 52.600 52.300 52.600 15.200 16.100
RAMP –– 7.400 30.900 7.400 30.900 7.400 30.900 5.900 18.300
SPD –– 1.500 6.300 1.500 6.300 1.500 6.300 1.000 2.800

806
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
PLSY –– 6.400 7.100 6.400 7.100 6.400 7.100 3.500 4.700
Basic
PWM –– 3.900 4.600 3.900 4.600 3.900 4.600 3.400 3.400
instruction
MTR –– 10.100 61.400 10.100 61.400 10.100 61.400 20.500 28.400
n=1 13.600 28.500 13.600 28.500 13.600 28.500 12.100 20.100
2
BKAND S1 S2 D n
n = 96 63.200 78.200 63.200 78.200 63.200 78.200 57.400 63.200
n=1 13.500 28.500 13.500 28.500 13.500 28.500 7.700 13.200
BKOR S1 S2 D n
n = 96 63.100 78.200 63.100 78.200 63.100 78.200 57.400 62.800 3
n=1 13.600 28.300 13.600 28.300 13.600 28.300 7.800 13.200
BKXOR S1 S2 D n
n = 96 63.100 78.000 63.100 78.000 63.100 78.000 57.300 62.800

BKXNR S1 S2 D n
n=1
n = 96
13.500
63.100
28.300
78.000
13.500
63.100
28.300
78.000
13.500
63.100
28.300
78.000
7.800
57.400
14.100
62.900
A
n=1 5.050 21.100 5.050 21.100 5.050 21.100 3.700 6.300
BSFR D n
n = 96 9.000 34.800 9.000 34.800 9.000 34.800 10.200 12.800
n=1 4.800 19.100 4.800 19.100 4.800 19.100 4.500 8.900 5
BSFL D n
n = 96 8.550 34.300 8.550 34.300 8.550 34.300 10.100 14.300
n1 = 16 / n2 = 1 10.300 46.500 10.300 46.500 10.300 46.500 8.800 43.400
SFTBR n1 n2
6
D
n1 = 16 / n2 = 15 10.300 46.400 10.300 46.400 10.300 46.400 8.750 43.400
n1 = 16 / n2 = 1 10.500 49.800 10.500 49.800 10.500 49.800 8.050 45.100
SFTBL D n1 n2
n1 = 16 / n2 = 15 10.500 49.800 10.500 49.800 10.500 49.800 8.050 45.100
n1 = 16 / n2 = 1 7.950 24.000 7.950 24.000 7.950 24.000 6.500 22.800
SFTWR D n1 n2
n1 = 16 / n2 = 15 7.950 24.100 7.950 24.100 7.950 24.100 6.500 22.800
7
n1 = 16 / n2 = 1 8.700 23.600 8.700 23.600 8.700 23.600 7.350 23.600
SFTWL D n1 n2
n1 = 16 / n2 = 15 8.650 23.700 8.650 23.700 8.650 23.700 7.300 23.700

BSET D n
n=1 4.550 4.750 4.550 4.750 4.550 4.750 3.000 3.400 8
n = 15 4.550 4.750 4.550 4.750 4.550 4.750 3.000 3.500
n=1 4.600 4.750 4.600 4.750 4.600 4.750 3.000 3.400
BRST D n
n = 15 4.600 4.750 4.600 4.750 4.600 4.750 3.000 3.400
TEST When executed 7.250 13.200 7.250 13.200 7.250 13.200 4.400 6.900
Application

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
instruction DTEST When executed 6.950 12.900 6.950 12.900 6.950 12.900 4.500 7.000
n=1 7.350 11.600 7.350 11.600 7.350 11.600 4.300 5.200
BKRST D n
n = 96 10.100 22.600 10.100 22.600 10.100 22.600 6.500 13.200
All match 6.650 6.800 6.650 6.800 6.650 6.800 5.000 5.300
n=1
None match 6.650 6.800 6.650 6.800 6.650 6.800 5.000 5.300
SER S1 S2 D n
All match 34.000 42.300 34.000 42.300 34.000 42.300 32.300 35.900
n = 96
None match 34.000 42.300 34.000 42.300 34.000 42.300 32.400 35.900
All match 8.000 16.300 8.000 16.300 8.000 16.300 6.800 10.200
n=1
None match 8.000 16.300 8.000 16.300 8.000 16.300 6.800 10.200
DSER S1 S2 D n
All match 54.100 62.600 54.100 62.600 54.100 62.600 52.800 56.300
n = 96
None match 54.100 62.600 54.100 62.600 54.100 62.600 52.800 56.300

S =0 4.100 4.200 4.100 4.200 4.100 4.200 3.700 4.100

DSUM S D
S = FFFFFFFFH 4.100 4.200 4.100 4.200 4.100 4.200 3.800 4.100

n=2 8.850 23.000 8.850 23.000 8.850 23.000 6.000 16.400

DECO S D n
n=8 13.600 36.600 13.600 36.600 13.600 36.600 8.100 15.200
M1 = ON 7.650 11.900 7.650 11.900 7.650 11.900 5.300 6.300
n=2
M4 = ON 7.500 11.700 7.500 11.700 7.500 11.700 5.200 6.200
ENCO S D n
M1 = ON 14.600 27.800 14.600 27.800 14.600 27.800 10.400 17.900
n=8
M256 = ON 10.600 23.700 10.600 23.700 10.600 23.700 5.700 13.300
n=1 6.500 14.800 6.500 14.800 6.500 14.800 5.000 10.900
DIS S D n
n=4 6.900 15.200 6.900 15.200 6.900 15.200 5.400 11.300
n=1 6.800 15.100 6.800 15.100 6.800 15.100 5.500 8.900
UNI S D n
n=4 7.500 15.900 7.500 15.900 7.500 15.900 6.200 9.600
NDIS When executed 4.750 18.700 4.750 18.700 4.750 18.700 11.000 16.300
NUNI When executed 4.750 18.700 4.750 18.700 4.750 18.700 10.600 16.000

807
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
n=1 6.600 14.900 6.600 14.900 6.600 14.900 5.000 6.500
WTOB S D n
n = 96 37.700 46.100 37.700 46.100 37.700 46.100 36.000 38.400
n=1 7.350 15.600 7.350 15.600 7.350 15.600 5.100 6.100
BTOW S D n
n = 96 32.100 40.500 32.100 40.500 32.100 40.500 29.900 32.000
n=1 8.250 24.900 8.250 24.900 8.250 24.900 4.300 6.900
MAX S D n
n = 96 34.200 51.600 34.200 51.600 34.200 51.600 32.000 34.300
n=1 8.250 24.800 8.250 24.800 8.250 24.800 4.400 6.800
MIN S D n
n = 96 34.200 51.600 34.200 51.600 34.200 51.600 30.300 34.800
n=1 6.800 34.900 6.800 34.900 6.800 34.900 4.800 14.200
DMAX S D n
n = 96 60.300 89.200 60.300 89.200 60.300 89.200 56.400 68.000
n=1 7.600 35.700 7.600 35.700 7.600 35.700 4.800 9.300
DMIN S D n
n = 96 59.400 90.000 59.400 90.000 59.400 90.000 55.400 62.800

n = 1, S2 =1 9.400 28.900 9.400 28.900 9.400 28.900 6.200 24.900

SORT S1 n S2 D1 D2
n = 96, S2 = 16 31.500 74.000 31.500 74.000 31.500 74.000 27.500 70.100

n = 1, S2 =1 9.400 29.000 9.400 29.000 9.400 29.000 6.200 25.900

DSORT S1 n S2 D1 D2
n = 96, S2 = 16 37.800 81.000 37.800 81.000 37.800 81.000 33.100 78.900

n=1 6.700 15.000 6.700 15.000 6.700 15.000 4.800 6.200

WSUM S D n
n = 96 28.900 37.100 28.900 37.100 28.900 37.100 26.900 28.700
n=1 8.600 26.800 8.600 26.800 8.600 26.800 5.500 7.000
Application DWSUM n
S D
n = 96 56.200 74.700 56.200 74.700 56.200 74.700 53.000 56.300
instruction n=1 5.850 19.800 5.850 19.800 5.850 19.800 4.300 17.300
MEAN S D n
n = 96 17.300 38.200 17.300 38.200 17.300 38.200 16.000 35.500
n=1 6.900 23.300 6.900 23.300 6.900 23.300 5.750 21.900
DMEAN S D n
n = 96 29.400 49.900 29.400 49.900 29.400 49.900 29.200 48.600
NEXT –– 1.000 1.100 1.000 1.100 1.000 1.100 0.980 1.400
BREAK –– 4.700 25.000 4.700 25.000 4.700 25.000 21.300 17.900
Return to original program 4.100 19.500 4.100 19.500 4.100 19.500 2.000 3.000
RET
Return to other program 4.700 16.700 4.700 16.700 4.700 16.700 2.300 4.900
Internal file pointer 5.400 5.400 5.400 5.400 5.400 5.400 3.300 5.300
FCALL Pn
Common pointer 7.600 30.500 7.600 30.500 7.600 30.500 4.900 6.600

FCALL Pn S1 to S5 –– 50.400 62.700 50.400 62.700 50.400 62.700 19.800 23.700

ECALL * Pn
–– 105.000 214.000 105.000 214.000 105.000 214.000 75.700 134.000
*: Program name

ECALL * Pn S1 to S5
–– 164.000 271.000 164.000 271.000 164.000 271.000 109.000 173.000
*: Program name
EFCALL * Pn
–– 105.000 214.000 105.000 214.000 105.000 214.000 76.200 134.000
*: Program name

EFCALL * Pn S1 to S5
–– 164.000 271.000 164.000 271.000 164.000 271.000 90.500 170.000
*: Program name
XCALL –– 5.100 6.700 5.100 6.700 5.100 6.700 3.800 6.400

808
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
When selecting I/O refresh only 18.100 89.100 18.100 89.100 18.100 89.100 12.800 79.000
When selecting CC-Link refresh
33.300 132.000 33.300 132.000 33.300 132.000 24.900 119.000
only (master station side)
When selecting CC-Link refresh 2
33.300 132.000 33.300 132.000 33.300 132.000 24.900 119.000
only (local station side)
• When selecting MELSECNET/
H refresh only (Control station 3
side)
78.600 231.000 78.600 231.000 78.600 231.000 54.000 212.000
• When selecting CC-Link IE
Controller Network refresh only
(Control station side) A
• When selecting MELSECNET/
H refresh only (Normal station
side)
78.600 231.000 78.600 231.000 78.600 231.000 54.000 212.000 5
• When selecting CC-Link IE
Controller Network refresh only
(Normal station side)
COM When selecting CC-Link IE Field 6
CCOM Network refresh only (master 32.000 127.000 32.000 127.000 32.000 127.000 22.000 118.000
station side)
When selecting CC-Link IE Field 7
Network refresh only (local station 32.000 127.000 32.000 127.000 32.000 127.000 22.000 118.000
side)
When selecting intelli auto refresh
only
18.100 89.000 18.100 89.000 18.100 89.000 12.800 79.000 8
When selecting I/O outside the
15.700 71.600 15.700 71.600 15.700 71.600 8.600 76.500
Application group only (Input only)
instruction When selecting I/O outside the
40.200 152.000 40.200 152.000 40.200 152.000 26.300 135.000
group only (Output only)

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
When selecting I/O outside the
45.800 153.000 45.800 153.000 45.800 153.000 26.100 135.000
group only (Both I/O)
When selecting refresh of multiple
CPU high speed transmission –– –– –– –– –– –– –– ––
area only
When selecting communication
18.200 89.000 18.200 89.000 18.200 89.000 7.250 54.300
with external devices only
Number of data points = 0 6.100 14.200 6.100 14.200 6.100 14.200 3.700 10.100
FIFW
Number of data points = 96 6.100 14.200 6.100 14.200 6.100 14.200 3.800 5.200
Number of data points = 0 7.500 15.600 7.500 15.600 7.500 15.600 4.400 5.800
FIFR
Number of data points = 96 37.000 45.000 37.000 45.000 37.000 45.000 33.500 35.200
Number of data points = 0 7.600 15.600 7.600 15.600 7.600 15.600 4.400 10.800
FPOP
Number of data points = 96 7.600 15.600 7.600 15.600 7.600 15.600 4.400 10.800
Number of data points = 0 6.900 15.000 6.900 15.000 6.900 15.000 5.000 10.700
FINS
Number of data points = 96 36.600 44.700 36.600 44.700 36.600 44.700 4.400 10.900
Number of data points = 0 8.000 16.100 8.000 16.100 8.000 16.100 4.900 11.300
FDEL
Number of data points = 96 37.300 45.500 37.300 45.500 37.300 45.500 34.200 35.900
n3 = 1 17.400 74.700 17.400 74.700 17.400 74.700 12.100 71.300
FROM n1 n2 D n3
n3 = 1000 406.000 498.500 406.000 498.500 406.000 498.500 402.600 495.100
n3 = 1 19.600 85.600 19.600 85.600 19.600 85.600 14.600 81.800
DFRO n1 n2 D n3
n3 = 500 406.000 498.500 406.000 498.500 406.000 498.500 402.600 495.100
n3 = 1 16.400 69.600 16.400 69.600 16.400 69.600 11.700 63.400
TO n1 n2 S n3
n3 = 1000 381.300 471.200 381.300 471.200 381.300 471.200 375.900 464.300
n3 = 1 18.600 85.100 18.600 85.100 18.600 85.100 14.200 78.500
DTO n1 n2 S n3
n3 = 500 381.300 471.200 381.300 471.200 381.300 471.200 375.900 464.300

809
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
No display no display 1.500 7.100 1.500 7.100 1.500 7.100 5.100 5.100
LEDR LED instruction execution
38.900 109.000 38.900 109.000 38.900 109.000 35.700 89.200
no display
S =1 5.600 13.900 5.600 13.900 5.600 13.900 4.900 6.500
BINDA S D
S = -32768 7.800 16.200 7.800 16.200 7.800 16.200 7.200 8.700

S =1 6.200 14.500 6.200 14.500 6.200 14.500 5.700 7.100

DBINDA S D
S = -2147483648 11.000 19.200 11.000 19.200 11.000 19.200 10.400 12.200

S =1 5.050 13.400 5.050 13.400 5.050 13.400 4.400 5.900

BINHA S D
S = FFFFH 5.050 13.400 5.050 13.400 5.050 13.400 4.400 5.800

S =1 5.600 13.900 5.600 13.900 5.600 13.900 5.200 6.700

DBINHA S D
S = FFFFFFFFH 5.600 13.900 5.600 13.900 5.600 13.900 5.100 6.500

S =1 4.850 13.200 4.850 13.200 4.850 13.200 4.300 5.800

BCDDA S D
S = 9999 5.300 13.600 5.300 13.600 5.300 13.600 4.700 6.100

S =1 5.300 13.600 5.300 13.600 5.300 13.600 4.800 6.300

DBCDDA S D
S = 99999999 6.200 14.500 6.200 14.500 6.200 14.500 5.600 7.100

S =1 7.000 18.500 7.000 18.500 7.000 18.500 6.500 9.000

DABIN S D
S = -32768 6.950 18.500 6.950 18.500 6.950 18.500 6.300 8.900

S =1 9.450 21.000 9.450 21.000 9.450 21.000 9.400 12.000

DDABIN S D
S = -2147483648 9.450 21.000 9.450 21.000 9.450 21.000 9.100 11.600

S =1 5.650 17.100 5.650 17.100 5.650 17.100 4.900 7.500

HABIN S D
S = FFFFH 5.750 17.300 5.750 17.300 5.750 17.300 5.100 8.100
Application
S =1 6.800 18.200 6.800 18.200 6.800 18.200 6.000 8.500
instruction DHABIN S D
S = FFFFFFFFH 7.100 18.600 7.100 18.600 7.100 18.600 6.300 8.900

S =1 5.650 17.200 5.650 17.200 5.650 17.200 5.000 7.500

DABCD S D
S = 9999 5.700 17.200 5.700 17.200 5.700 17.200 5.000 7.500

S =1 6.850 18.300 6.850 18.300 6.850 18.300 6.200 8.800

DDABCD S D
S = 99999999 6.850 18.300 6.850 18.300 6.850 18.300 6.200 8.800

COMRD –– 185.000 188.000 185.000 188.000 185.000 188.000 97.300 97.400

1 character 4.700 16.200 4.700 16.200 4.700 16.200 4.100 6.600
LEN
96 characters 20.600 32.900 20.600 32.900 20.600 32.900 19.800 22.400
STR –– 9.800 36.500 9.800 36.500 9.800 36.500 6.900 14.400
DSTR –– 12.100 40.400 12.100 40.400 12.100 40.400 10.200 20.800
VAL –– 12.200 40.900 12.200 40.900 12.200 40.900 9.800 23.900
DVAL –– 19.400 45.600 19.400 45.600 19.400 45.600 14.000 33.100
ESTR –– 29.700 87.800 29.700 87.800 29.700 87.800 22.100 52.400
Decimal point format
23.900 70.400 23.900 70.400 23.900 70.400 23.300 36.500
all 2-digit specification
EVAL
Exponent format
23.700 70.300 23.700 70.300 23.700 70.300 23.300 36.400
all 6-digit specification
n=1 10.200 41.800 10.200 41.800 10.200 41.800 5.600 19.700
ASC S D n
n = 96 31.900 66.600 31.900 66.600 31.900 66.600 30.200 44.700
n=1 8.600 43.400 8.600 43.400 8.600 43.400 7.500 23.100
HEX S D n
n = 96 77.100 115.000 77.100 115.000 77.100 115.000 37.500 53.300
n=1 10.900 29.600 10.900 29.600 10.900 29.600 7.600 11.400
RIGHT S D n
n = 96 41.400 60.300 41.400 60.300 41.400 60.300 36.300 46.000
n=1 10.600 29.300 10.600 29.300 10.600 29.300 6.500 16.100
LEFT S D n
n = 96 41.300 60.200 41.300 60.200 41.300 60.200 36.200 46.200

810
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
MIDR –– 11.700 30.600 11.700 30.600 11.700 30.600 9.500 19.100
MIDW –– 12.400 24.000 12.400 24.000 12.400 24.000 10.300 18.200
No match 22.000 38.200 22.000 38.200 22.000 38.200 19.300 29.000
INSTR Head 13.300 29.600 13.300 29.600 13.300 29.600 10.300 20.000
2
Match
End 21.900 38.100 21.900 38.100 21.900 38.100 51.100 60.800
EMOD –– 11.600 24.000 11.600 24.000 11.600 24.000 10.300 15.300
EREXP –– 19.700 28.000 19.700 28.000 19.700 28.000 19.300 22.300 3
S = 128 / D = 40 / n = 1 47.000 102.000 47.000 102.000 47.000 102.000 44.300 96.700
STRINS S D n
S = 128 / D = 40 / n = 48 70.100 134.000 70.100 134.000 70.100 134.000 58.800 112.000

S = 128 / D = 40 / n = 1 46.400 93.600 46.400 93.600 46.400 93.600 39.000 78.100 A

STRDEL S D n
S = 128 / D = 40 / n = 48 44.500 70.600 44.500 70.600 44.500 70.600 36.000 69.200

SIN Single precision 6.400 13.900 6.400 13.900 6.400 13.900 4.500 9.900
COS Single precision 6.100 13.500 6.100 13.500 6.100 13.500 4.300 8.200 5
TAN Single precision 8.300 15.000 8.300 15.000 8.300 15.000 5.100 7.200
ASIN Single precision 7.300 15.600 7.300 15.600 7.300 15.600 6.100 13.700
ACOS Single precision 8.100 16.500 8.100 16.500 8.100 16.500 6.800 11.100 6
ATAN Single precision 5.350 12.000 5.350 12.000 5.350 12.000 4.000 6.900
SIND Double precision 13.400 51.300 13.400 51.300 13.400 51.300 9.600 26.000
COSD
TAND
Double precision
Double precision
14.700
17.400
51.700
54.400
14.700
17.400
51.700
54.400
14.700
17.400
51.700
54.400
10.000
11.400
26.900
25.300
7
ASIND Double precision 22.600 60.300 22.600 60.300 22.600 60.300 12.100 30.800
ACOSD Double precision 19.700 60.000 19.700 60.000 19.700 60.000 11.700 28.000
ATAND Double precision 15.000 51.800 15.000 51.800 15.000 51.800 9.700 22.000 8
RAD Single precision 3.200 10.300 3.200 10.300 3.200 10.300 2.500 4.800
RADD Double precision 5.200 43.100 5.200 43.100 5.200 43.100 4.100 16.400
Application
DEG Single precision 3.200 11.500 3.200 11.500 3.200 11.500 2.500 4.700
instruction
DEGD Double precision 5.150 43.800 5.150 43.800 5.150 43.800 5.000 18.100

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
SQR Single precision 3.900 12.300 3.900 12.300 3.900 12.300 3.500 9.300
SQRD Double precision 7.000 45.700 7.000 45.700 7.000 45.700 5.700 25.400

Single S = -10 6.350 13.800 6.350 13.800 6.350 13.800 4.000 13.000
EXP S D
precision S =1 6.350 13.800 6.350 13.800 6.350 13.800 4.000 13.000

Double S = -10 15.800 52.700 15.800 52.700 15.800 52.700 8.800 27.600
EXPD S D
precision S =1 15.400 52.500 15.400 52.500 15.400 52.500 8.500 27.300

Single S =1 5.800 14.900 5.800 14.900 5.800 14.900 4.100 8.100

LOG S D
precision S = 10 7.450 16.500 7.450 16.500 7.450 16.500 6.200 10.300

Double S =1 11.000 48.900 11.000 48.900 11.000 48.900 9.500 28.300

LOGD S D
precision S = 10 12.600 51.300 12.600 51.300 12.600 51.300 11.100 29.900

RND –– 1.950 5.450 1.950 5.450 1.950 5.450 1.200 2.300

SRND –– 2.750 4.550 2.750 4.550 2.750 4.550 1.400 2.400

S =0 2.500 6.800 2.500 6.800 2.500 6.800 1.800 3.300

BSQR S D
S = 9999 6.400 15.500 6.400 15.500 6.400 15.500 5.100 8.800

S =0 2.600 6.050 2.600 6.050 2.600 6.050 1.900 3.700

BDSQR S D
S = 99999999 8.450 17.600 8.450 17.600 8.450 17.600 7.500 10.900

BSIN –– 11.500 32.800 11.500 32.800 11.500 32.800 8.700 20.200

BCOS –– 10.400 32.500 10.400 32.500 10.400 32.500 7.800 14.400
BTAN –– 12.100 33.700 12.100 33.700 12.100 33.700 9.000 17.000
BASIN –– 13.300 32.800 13.300 32.800 13.300 32.800 12.200 15.100
BACOS –– 13.400 33.700 13.400 33.700 13.400 33.700 13.100 14.900
BATAN –– 12.600 31.400 12.600 31.400 12.600 31.400 11.400 15.700

811
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.

Single S1 = 12.3 E + 5
POW S1 S2 D 12.200 22.100 12.200 22.100 12.200 22.100 8.950 19.500
precision S2 = 3.45 E + 0

Double S1 = 12.3 E + 5
POWD S1 S2 D 27.300 61.000 27.300 61.000 27.300 61.000 19.400 55.200
precision S2 = 3.45 E + 0
LOG10 Single precision 8.200 16.500 8.200 16.500 8.200 16.500 5.950 14.800
LOG10D Double precision 15.100 48.000 15.100 48.000 15.100 48.000 12.400 46.500
LIMIT –– 5.350 5.500 5.350 5.500 5.350 5.500 5.200 5.400
DLIMIT –– 6.000 6.150 6.000 6.150 6.000 6.150 5.700 5.900
BAND –– 5.450 12.400 5.450 12.400 5.450 12.400 5.400 6.300
DBAND –– 6.050 11.900 6.050 11.900 6.050 11.900 5.800 6.900
ZONE –– 6.250 10.700 6.250 10.700 6.250 10.700 5.200 11.100
DZONE –– 6.000 11.900 6.000 11.900 6.000 11.900 5.700 10.800

Point No.1 < S1 <

14.900 50.100 14.900 50.100 14.900 50.100 14.700 48.000
SM750 Point No.2
= ON Point No.9 < S1 <
15.800 50.900 15.800 50.900 15.800 50.900 19.600 50.400
Point No.10
SCL S1 S2 D
Point No.1 < S1 <
13.900 53.100 13.900 53.100 13.900 53.100 13.700 51.000
SM750 Point No.2
= OFF Point No.9 < S1 <
16.600 56.600 16.600 56.600 16.600 56.600 20.400 56.200
Point No.10
Point No.1 < S1 <
13.400 52.400 13.400 52.400 13.400 52.400 12.800 50.300
Application SM750 Point No.2
instruction = ON Point No.9 < S1 <
14.200 54.100 14.200 54.100 14.200 54.100 17.300 53.500
Point No.10
DSCL S1 S2 D
Point No.1 < S1 <
12.300 53.200 12.300 53.200 12.300 53.200 11.500 51.100
SM750 Point No.2
= OFF Point No.9 < S1 <
15.000 57.600 15.000 57.600 15.000 57.600 18.100 57.100
Point No.10
Point No.1 < S1 <
14.200 53.300 14.200 53.300 14.200 53.300 13.200 51.200
SM750 Point No.2
= ON Point No.9 < S1 <
14.900 55.000 14.900 55.000 14.900 55.000 18.000 54.500
Point No.10
SCL2 S1 S2 D
Point No.1 < S1 <
15.000 53.500 15.000 53.500 15.000 53.500 14.000 51.300
SM750 Point No.2
= OFF Point No.9 < S1 <
16.300 56.400 16.300 56.400 16.300 56.400 19.300 55.800
Point No.10
Point No.1 < S1 <
13.400 52.700 13.400 52.700 13.400 52.700 13.100 50.500
SM750 Point No.2
= ON Point No.9 < S1 <
14.200 54.300 14.200 54.300 14.200 54.300 18.100 53.700
Point No.10
DSCL2 S1 S2 D
Point No.1 < S1 <
12.300 53.200 12.300 53.200 12.300 53.200 12.100 51.000
SM750 Point No.2
= OFF Point No.9 < S1 <
15.000 57.600 15.000 57.600 15.000 57.600 18.900 57.100
Point No.10

812
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
Standard RAM 6.800 26.900 6.800 26.900 6.800 26.900 3.000 16.400
RSET
SRAM card –– –– –– –– –– –– 3.000 16.400

QDRSET
SRAM card to standard RAM
Standard RAM to SRAM card
––
––
––
––
––
––
––
––
––
––
––
––
230.000 327.000
997.000 1066.000
2
SRAM card to standard ROM –– –– –– –– –– –– 525.000 690.000
QCDSET
Standard ROM to SRAM card –– –– –– –– –– –– 490.000 655.000
DATERD –– 5.600 27.800 5.600 27.800 5.600 27.800 5.100 14.700 3
DATEWR –– 7.800 42.100 7.800 42.100 7.800 42.100 7.100 23.000
No digit increase 14.200 41.200 14.200 41.200 14.200 41.200 6.500 13.100
DATE +
Digit increase 14.200 41.200 14.200 41.200 14.200 41.200 5.700 21.200
A
No digit increase 15.100 41.200 15.100 41.200 15.100 41.200 6.500 11.500
DATE -
Digit increase 15.100 41.200 15.100 41.200 15.100 41.200 5.700 17.200
SECOND –– 5.800 20.500 5.800 20.500 5.800 20.500 2.600 5.900
HOUR –– 6.200 22.500 6.200 22.500 6.200 22.500 3.000 5.300 5
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
date
In non-conductive
8.200 25.500 8.200 25.500 6.500 25.500 8.200 25.500
6
status
LDDT =
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
7
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
Application
Comparison
In conductive
8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
8
instruction status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT <>
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status

813
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT<> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT<> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT>
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
Application status
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 8.200 25.500 7.200 23.400
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 8.200 25.500 7.200 23.400
ANDDT> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 8.200 25.500 7.400 23.300
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 8.200 25.500 7.400 23.300
ORDT> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT<=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status

814
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
of specified
status
In non-conductive
2
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT<= status
In conductive
Comparison
of current
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
3
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed
In conductive
0.480 0.320 0.240 0.160
A
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In non-conductive
ORDT<=
date
status
8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
5
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
date
In non-conductive
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000 6
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
date
In non-conductive
8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
7
status
LDDT<
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
of current
status
8
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
Application status
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.400
status
LDDT>=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status

815
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.200 23.400
ANDDT>= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.200
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.400 23.300
ORDT>= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In non-conductive
date 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In non-conductive
date 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
Application status
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM<>
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status

816
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
of specified
status
In non-conductive
2
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM<> status
In conductive
Comparison
of current
status
6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
3
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed
In conductive
0.480 0.320 0.240 0.160
A
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In non-conductive
ORTM<>
clock
status
8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
5
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
clock
In non-conductive
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000 6
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
clock
In non-conductive
8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
7
status
LDTM>
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
of current
status
8
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
Application status
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM> status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM<=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status

817
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM<= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM<= status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM<
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
Application status
instruction When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.200
ORTM< status
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.000
status
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
of specified
In non-conductive
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.300 23.300
status
LDTM>=
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status

818
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max. 3
When not executed 0.480 0.320 0.240 0.160
In conductive
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
of specified
status
In non-conductive
2
clock 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
ANDTM>= status
In conductive
Comparison
of current
status
6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
3
In non-conductive
clock 6.500 23.100 6.500 23.100 6.500 23.100 5.600 21.900
status
When not executed
In conductive
0.480 0.320 0.240 0.160
A
Comparison 8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
status
of specified
In non-conductive
ORTM>=
clock
status
8.200 25.500 8.200 25.500 6.500 25.500 7.000 23.000
5
In conductive
Comparison 6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100
status
of current
clock
In non-conductive
status
6.500 23.100 6.500 23.100 6.500 23.100 5.900 22.100 6
S.DATERD –– 9.250 51.000 9.250 51.000 9.250 51.000 7.500 23.400
No digit increase 16.800 75.400 16.800 75.400 16.800 75.400 9.100 23.400
S.DATE +
Digit increase 16.800 75.400 16.800 75.400 16.800 75.400 8.900 22.200 7
No digit increase 17.600 75.300 17.600 75.300 17.600 75.300 9.000 22.200
S.DATE -
Digit increase 16.900 75.300 16.900 75.300 16.900 75.300 9.800 22.100
PSTOP –– 82.200 199.000 82.200 199.000 82.200 199.000 61.400 84.500 8
POFF –– 82.600 198.000 82.600 198.000 82.600 198.000 121.000 246.000
PSCAN –– 83.600 200.000 83.600 200.000 83.600 200.000 126.000 232.000
Application WDT –– 2.900 12.000 2.900 12.000 2.900 12.000 1.300 3.000
instruction
DUTY –– 7.700 27.500 7.700 27.500 7.700 27.500 4.900 24.300
TIMCHK –– 5.350 24.500 5.350 24.500 5.350 24.500 7.400 23.300

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
File register of standard RAM 4.100 4.200 4.100 4.200 4.100 4.200 2.400 2.600
ZRRDB
File register of SRAM card –– –– –– –– –– –– 2.500 2.800
File register of standard RAM 5.400 5.500 5.400 5.500 5.400 5.500 3.100 3.300
ZRWRB
File register of SRAM card –– –– –– –– –– –– 3.300 3.600
ADRSET –– 2.400 6.650 2.400 6.650 2.400 6.650 4.200 4.900
ZPUSH –– 9.200 20.500 9.200 20.500 9.200 20.500 6.900 14.000
ZPOP –– 9.000 15.500 9.000 15.500 9.000 15.500 7.500 12.500
UNIRD n1 n2 = 1 6.000 33.100 6.000 33.100 6.000 33.100 4.000 29.100
D n2 n2 = 16 16.500 43.600 16.500 43.600 16.500 43.600 12.500 37.600

TYPERD –– 48.50 141.30 43.50 139.90 43.40 139.80 32.40 134.20

TRACE Start 174.000 174.000 174.000 174.000 174.000 174.000 96.600 103.000
TRACER –– 5.100 15.500 5.100 15.500 5.100 15.500 3.800 13.600
When 1 point –– –– 12.200 34.900 12.200 34.900 9.400 31.300
standard
RAM is 1000 points –– –– 121.500 145.100 121.500 145.100 118.500 141.300
RBMOV S
used
D n When 1 point –– –– –– –– –– –– 9.400 31.400
SRAM
1000 points –– –– –– –– –– –– 178.500 201.300
card is used
SP.FWRIT
–– –– –– –– –– –– –– 9.200 12.100
E
SP.FREAD –– –– –– –– –– –– –– 489.000 544.000
SP.DEVST –– –– –– –– –– –– –– 87.000 144.000
S.DEVLD –– –– –– –– –– –– –– 127.000 140.000

819
 Processing Time (µs)
Category Instruction Condition (Device) Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When mounting CC-Link
29.400 91.700 29.400 91.700 29.400 91.700 20.600 55.000
module (master station side)
When mounting CC-Link
29.500 91.600 29.500 91.600 29.500 91.600 20.600 66.100
module (local station side)
• When selecting
MELSECNET/H refresh
only (control station side)
79.900 214.000 79.900 214.000 79.900 214.000 102.000 180.000
• When selecting CC-Link IE
Controller Network refresh
only (control station side)
• When selecting
S.ZCOM
Data link MELSECNET/H refresh
instruction only (normal station side)
79.900 214.000 79.900 214.000 79.900 214.000 55.600 168.100
• When selecting CC-Link IE
Controller Network refresh
only (normal station side)
When selecting CC-Link IE
Field Network refresh only 60.000 167.000 60.000 167.000 60.000 167.000 51.000 154.000
(master station side)
When selecting CC-Link IE
Field Network refresh only 60.000 167.000 60.000 167.000 60.000 167.000 51.000 154.000
(local station side)
S.RTREAD –– 12.600 65.000 12.600 65.000 12.600 65.000 8.700 60.500
S.RTWRITE –– 13.300 67.100 13.300 67.100 13.300 67.100 9.300 65.000
Writing to host n4 = 1 64.600 78.100 64.600 78.100 64.600 78.100 64.600 78.100
S.TO n1 n2 n3 n4 D CPU shared
n4 = 320 115.000 126.000 115.000 126.000 115.000 126.000 154.000 126.000
memory
Writing to host n3 = 1 12.700 62.200 12.700 62.200 12.700 62.200 8.300 58.200
TO n1 n2 S n3 CPU shared
n3 = 320 63.500 112.300 63.500 112.300 63.500 112.300 56.200 107.800
memory
Writing to host n3 = 1 13.500 62.300 13.500 62.300 13.500 62.300 8.600 58.300
DTO n1 n2 S n3 CPU shared
n3 = 320 112.900 160.800 112.900 160.800 112.900 160.800 106.800 157.300
memory
Multiple
Reading from n3 = 1 12.100 58.700 12.100 58.700 12.100 58.700 8.400 52.600
CPU
host CPU shared
dedicated n3 = 320 56.000 101.700 56.000 101.700 56.000 101.700 51.700 96.600
memory
instruction FROM n1 n2 D n3
Reading from n3 = 1 24.400 82.900 24.400 82.900 24.400 82.900 16.600 37.000
other CPU n3 = 320 152.000 243.000 152.000 243.000 152.000 243.000 153.000 185.000
shared memory n3 = 1000 418.000 518.000 418.000 518.000 418.000 518.000 432.000 485.000
Reading from n3 = 1 12.100 58.700 12.100 58.700 12.100 58.700 8.800 53.400
host CPU shared
n3 = 320 97.400 143.700 97.400 143.700 97.400 143.700 94.900 139.600
memory
DFRO n1 n2 D n3
Reading from n3 = 1 24.800 94.200 24.800 94.200 24.800 94.200 16.600 47.300
other CPU n3 = 320 276.000 367.000 276.000 367.000 276.000 367.000 278.000 339.000
shared memory n3 = 1000 799.000 892.000 799.000 892.000 799.000 892.000 841.000 892.000

Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
execution instruction.
Example WORDP instruction, TOP instruction etc.

820
 (b) When using Q03UD(E)JCPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU,
Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU, and Q100UDEHCPU
Processing Time (µs)
3
Instruc- Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Condition (Device)
tion UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
ANB 2
ORB
MPS –– 0.020 0.0095 0.0095 0.0095
MRD 3
MPP
When not executed
INV 0.020 0.0095 0.0095 0.0095
When executed
MEP When not executed A
0.020 0.0095 0.0095 0.0095
MEF When executed
EGP When not executed
0.020 0.0095 0.0095 0.0095
EGF When executed 5
PLS –– 1.300 1.600 0.890 1.100 0.890 1.100 0.890 1.100
PLF –– 1.500 1.600 0.940 1.200 0.940 1.200 0.940 1.200

FF
When not executed
When executed 1.200
0.040
1.500 0.790
0.0185
0.910 0.790
0.0185
0.910 0.790
0.0185
0.910
6
When not executed 0.040 0.0185 0.0185 0.0185
DELTA
When executed 2.800 3.600 2.400 3.200 2.400 3.200 2.400 3.200

SFT
When not executed 0.040 0.0185 0.0185 0.0185 7
When executed 1.600 3.300 1.100 2.700 1.100 2.700 1.100 2.700
MC –– 0.040 0.0185 0.0185 0.0185
MCR –– 0.040 0.0185 0.0185 0.0185
8
FEND Error check performed 108.000 130.000 75.800 89.300 75.800 89.300 75.800 89.300
END No error check performed 107.000 124.000 75.800 89.800 75.800 89.800 75.800 89.800
Sequence
NOP
instruction
NOPLF –– 0.020 0.0095 0.0095 0.0095
PAGE

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Single In conductive status 3.700 4.700 3.300 4.300
LDE= 0.0285 0.0285
precision In non-conductive status 3.800 5.000 3.400 4.500
When not executed 0.060 0.0285
Single
ANDE= When In conductive status 3.300 5.800 3.000 5.100 0.0285 0.0285
precision
executed In non-conductive status 3.500 5.600 3.000 5.200
When not executed 0.060 0.0285
Single
ORE= When In conductive status 3.600 4.500 3.200 4.200 0.0285 0.0285
precision
executed In non-conductive status 3.500 4.800 3.200 4.300
Single In conductive status 4.000 4.700 3.600 4.200
LDE< > 0.0285 0.0285
precision In non-conductive status 3.900 4.500 3.500 4.000
When not executed 0.060 0.0285
Single
ANDE< > When In conductive status 3.300 5.100 3.000 4.800 0.0285 0.0285
precision
executed In non-conductive status 3.500 5.000 3.100 4.600
When not executed 0.060 0.0285
Single
ORE< > When In conductive status 3.600 6.000 3.300 5.500 0.0285 0.0285
precision
executed In non-conductive status 3.500 5.800 3.100 5.300
Single In conductive status 3.800 5.000 3.300 4.600
LDE> 0.0285 0.0285
precision In non-conductive status 3.700 4.900 3.300 4.400
When not executed 0.060 0.0285
Single
ANDE> When In conductive status 3.500 4.700 3.100 4.200 0.0285 0.0285
precision
executed In non-conductive status 3.600 4.500 3.100 4.000

821
 Processing Time (µs)
Instruc- Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Condition (Device)
tion UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.060 0.0285
Single
ORE> When In conductive status 3.600 5.100 3.300 4.600 0.0285 0.0285
precision
executed In non-conductive status 3.500 4.800 3.200 4.500
Single In conductive status 3.800 5.600 3.400 5.200
LDE<= 0.0285 0.0285
precision In non-conductive status 3.800 5.600 3.400 5.100
When not executed 0.060 0.0285
Single
ANDE<= When In conductive status 3.200 4.600 2.800 4.200 0.0285 0.0285
precision
executed In non-conductive status 3.500 5.000 3.100 4.500
When not executed 0.060 0.0285
Single
ORE<= When In conductive status 3.700 5.800 3.400 5.400 0.0285 0.0285
precision
executed In non-conductive status 3.800 5.700 3.300 5.300
Single In conductive status 4.000 5.400 3.500 4.900
LDE< 0.0285 0.0285
precision In non-conductive status 4.000 5.200 3.500 4.900
When not executed 0.060 0.0285
Single
ANDE< When In conductive status 3.400 4.600 3.000 4.200 0.0285 0.0285
precision
executed In non-conductive status 3.500 4.900 3.100 4.400
When not executed 0.060 0.0285
Single
ORE< When In conductive status 3.600 5.200 3.300 4.900 0.0285 0.0285
precision
executed In non-conductive status 3.400 4.900 3.200 4.500
Single In conductive status 3.800 6.000 3.300 5.500
LDE>= 0.0285 0.0285
precision In non-conductive status 3.800 5.900 3.400 5.400
When not executed 0.060 0.0285
Single
ANDE>= When In conductive status 3.200 4.800 2.900 4.600 0.0285 0.0285
precision
executed In non-conductive status 3.500 5.400 3.100 5.100
When not executed 0.060 0.0285
Single
ORE>= When In conductive status 3.600 5.200 3.300 4.700 0.0285 0.0285
Basic precision
executed In non-conductive status 3.500 5.200 3.200 4.700
instruction
Double In conductive status 4.100 7.700 3.500 7.200 3.500 7.200 3.500 7.200
LDED=
precision In non-conductive status 4.300 8.100 3.800 7.400 3.800 7.400 3.800 7.400
When not executed 0.060 0.0285 0.0285 0.0285
Double
ANDED= When In conductive status 3.600 7.600 3.200 7.000 3.200 7.000 3.200 7.000
precision
executed In non-conductive status 3.900 7.700 3.400 7.400 3.400 7.400 3.400 7.400
When not executed 0.060 0.0285 0.0285 0.0285
Double
ORED= When In conductive status 3.800 8.800 3.400 8.300 3.400 8.300 3.400 8.300
precision
executed In non-conductive status 4.000 9.300 3.700 8.800 3.700 8.800 3.700 8.800
Double In conductive status 4.400 8.200 3.900 7.700 3.900 7.700 3.900 7.700
LDED<>
precision In non-conductive status 4.100 7.900 3.500 7.500 3.500 7.500 3.500 7.500
When not executed 0.060 0.0285 0.0285 0.0285
Double
ANDED<> When In conductive status 3.800 7.600 3.300 7.200 3.300 7.200 3.300 7.200
precision
executed In non-conductive status 3.800 7.700 3.400 7.300 3.400 7.300 3.400 7.300
When not executed 0.060 0.0285 0.0285 0.0285
Double
ORED<> When In conductive status 4.100 9.300 3.700 8.900 3.700 8.900 3.700 8.900
precision
executed In non-conductive status 3.800 8.900 3.400 8.400 3.400 8.400 3.400 8.400
Double In conductive status 4.300 8.100 3.800 7.500 3.800 7.500 3.800 7.500
LDED>
precision In non-conductive status 4.100 7.800 3.500 7.200 3.500 7.200 3.500 7.200
When not executed 0.060 0.0285 0.0285 0.0285
Double
ANDED> When In conductive status 3.800 7.700 3.300 7.300 3.300 7.300 3.300 7.300
precision
executed In non-conductive status 4.000 7.900 3.500 7.500 3.500 7.500 3.500 7.500
When not executed 0.060 0.0285 0.0285 0.0285
Double
ORED> When In conductive status 4.100 9.300 3.700 8.800 3.700 8.800 3.700 8.800
precision
executed In non-conductive status 4.100 9.300 3.700 8.800 3.700 8.800 3.700 8.800
Double In conductive status 4.000 8.000 3.500 7.400 3.500 7.400 3.500 7.400
LDED<=
precision In non-conductive status 4.100 9.400 3.600 8.800 3.600 8.800 3.600 8.800

822
 Processing Time (µs)
Instruc- Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Condition (Device)
tion UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.060 0.0285 0.0285 0.0285
Double
ANDED<= When In conductive status 3.800 7.700 3.300 7.200 3.300 7.200 3.300 7.200
precision
executed In non-conductive status 3.900 7.700 3.500 7.400 3.500 7.400 3.500 7.400 2
When not executed 0.060 0.0285 0.0285 0.0285
Double
ORED<= When In conductive status 4.100 9.600 3.700 9.200 3.700 9.200 3.700 9.200
precision
executed In non-conductive status 4.100 9.600 3.700 9.200 3.700 9.200 3.700 9.200 3
Double In conductive status 4.300 8.300 3.800 7.600 3.800 7.600 3.800 7.600
LDED<
precision In non-conductive status 3.700 7.900 3.500 7.400 3.500 7.400 3.500 7.400

ANDED<
Double
When
When not executed
In conductive status 3.800
0.060
7.800 3.300
0.0285
7.300 3.300
0.0285
7.300 3.300
0.0285
7.300
A
precision
executed In non-conductive status 3.900 7.900 3.400 3.900 3.400 3.900 3.400 3.900
When not executed 0.060 0.0285 0.0285 0.0285
ORED<
Double
precision
When In conductive status 4.100 9.600 3.700 9.200 3.700 9.200 3.700 9.200 5
executed In non-conductive status 4.000 9.600 3.700 9.200 3.700 9.200 3.700 9.200
Double In conductive status 4.100 9.600 3.600 9.000 3.600 9.000 3.600 9.000
LDED>=
precision In non-conductive status 4.100 9.600 3.600 8.900 3.600 8.900 3.600 8.900
6
When not executed 0.060 0.0285 0.0285 0.0285
Double
ANDED>= When In conductive status 3.800 7.900 3.400 7.400 3.400 7.400 3.400 7.400
precision
executed In non-conductive status 3.900 8.100 3.400 7.500 3.400 7.500 3.400 7.500
When not executed 0.060 0.0285 0.0285 0.0285 7
Double
ORED>= When In conductive status 4.100 9.600 3.700 9.200 3.700 9.200 3.700 9.200
precision
executed In non-conductive status 4.000 7.200 3.600 6.600 3.600 6.600 3.600 6.600

LD$=
In conductive status 5.300 8.900 4.700 8.100 4.700 8.100 4.700 8.100 8
In non-conductive status 4.700 9.000 4.200 8.200 4.200 8.200 4.200 8.200
When not executed 0.060 0.0285 0.0285 0.0285
AND$= In conductive status 4.400 6.800 3.900 6.400 3.900 6.400 3.900 6.400
When executed
Basic In non-conductive status 4.500 6.700 4.000 6.300 4.000 6.300 4.000 6.300
instruction When not executed

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
0.060 0.0285 0.0285 0.0285
OR$= In conductive status 5.100 8.200 4.200 7.600 4.200 7.600 4.200 7.600
When executed
In non-conductive status 5.000 8.100 4.000 7.200 4.000 7.200 4.000 7.200
In conductive status 4.800 8.100 4.300 7.500 4.300 7.500 4.300 7.500
LD$< >
In non-conductive status 4.700 8.400 4.200 7.800 4.200 7.800 4.200 7.800
When not executed 0.060 0.0285 0.0285 0.0285
AND$< > In conductive status 4.300 5.500 4.100 5.100 4.100 5.100 4.100 5.100
When executed
In non-conductive status 4.500 5.900 4.400 5.400 4.400 5.400 4.400 5.400
When not executed 0.060 0.0285 0.0285 0.0285
OR$< > In conductive status 5.200 7.300 4.100 6.700 4.100 6.700 4.100 6.700
When executed
In non-conductive status 5.100 7.200 4.100 6.700 4.100 6.700 4.100 6.700
In conductive status 4.800 7.200 4.300 6.700 4.300 6.700 4.300 6.700
LD$>
In non-conductive status 4.800 7.700 4.200 7.100 4.200 7.100 4.200 7.100
When not executed 0.060 0.0285 0.0285 0.0285
AND$> In conductive status 4.500 7.100 4.000 6.700 4.000 6.700 4.000 6.700
When executed
In non-conductive status 4.600 7.600 4.300 7.000 4.300 7.000 4.300 7.000
When not executed 0.060 0.0285 0.0285 0.0285
OR$> In conductive status 5.100 6.800 4.300 6.200 4.300 6.200 4.300 6.200
When executed
In non-conductive status 5.200 7.200 4.300 6.600 4.300 6.600 4.300 6.600
In conductive status 5.000 6.300 4.400 5.700 4.400 5.700 4.400 5.700
LD$<=
In non-conductive status 4.800 6.400 4.200 5.800 4.200 5.800 4.200 5.800
When not executed 0.060 0.0285 0.0285 0.0285
AND$<= In conductive status 4.600 7.600 4.100 7.200 4.100 7.200 4.100 7.200
When executed
In non-conductive status 4.700 7.700 4.200 7.300 4.200 7.300 4.200 7.300
When not executed 0.060 0.0285 0.0285 0.0285
OR$<= In conductive status 4.700 7.700 4.400 7.200 4.400 7.200 4.400 7.200
When executed
In non-conductive status 4.600 7.600 4.400 7.100 4.400 7.100 4.400 7.100

823
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
In conductive status 4.800 8.100 4.500 7.500 4.500 7.500 4.500 7.500
LD$<
In non-conductive status 5.000 8.300 4.500 7.900 4.500 7.900 4.500 7.900
When not executed 0.060 0.0285 0.0285 0.0285
AND$< When In conductive status 4.500 7.100 4.000 6.600 4.000 6.600 4.000 6.600
executed In non-conductive status 4.900 7.500 4.400 7.100 4.400 7.100 4.400 7.100
When not executed 0.060 0.0285 0.0285 0.0285
OR$< When In conductive status 5.100 7.800 4.100 7.200 4.100 7.200 4.100 7.200
executed In non-conductive status 5.000 8.100 4.100 7.600 4.100 7.600 4.100 7.600
In conductive status 4.800 6.700 4.500 6.200 4.500 6.200 4.500 6.200
LD$>=
In non-conductive status 5.000 6.700 4.400 6.300 4.400 6.300 4.400 6.300
When not executed 0.060 0.0285 0.0285 0.0285
AND$>= When In conductive status 4.400 6.800 4.100 6.300 4.100 6.300 4.100 6.300
executed In non-conductive status 4.500 7.000 4.200 6.600 4.200 6.600 4.200 6.600
When not executed 0.060 0.0285 0.0285 0.0285
OR$>= When In conductive status 5.400 6.600 4.100 5.800 4.100 5.800 4.100 5.800
executed In non-conductive status 5.300 6.300 4.100 5.700 4.100 5.700 4.100 5.700
BKCMP = n=1 8.200 10.700 7.500 10.000 7.500 10.000 7.500 10.000
S1 S2 D n n = 96 57.400 61.800 46.400 48.700 46.400 48.700 46.400 48.700

BKCMP<> n=1 8.200 10.700 7.500 10.000 7.500 10.000 7.500 10.000
S1 S2 D n n = 96 59.500 63.300 45.600 50.400 45.600 50.400 45.600 50.400

BKCMP> n=1 8.200 10.800 7.500 10.100 7.500 10.100 7.500 10.100
S1 S2 D n n = 96 59.500 63.400 47.700 50.500 47.700 50.500 47.700 50.500

BKCMP<= n=1 8.200 10.600 7.500 10.000 7.500 10.000 7.500 10.000

Basic
S1 S2 D n n = 96 57.400 61.700 46.400 49.000 46.400 49.000 46.400 49.000

instruction BKCMP< n=1 8.300 10.600 7.500 10.000 7.500 10.000 7.500 10.000
S1 S2 D n n = 96 59.500 63.600 47.600 50.500 47.600 50.500 47.600 50.500

BKCMP>= n=1 8.200 10.900 7.500 10.000 7.500 10.000 7.500 10.000
S1 S2 D n n = 96 57.400 62.000 46.400 48.900 46.400 48.900 46.400 48.900

DBKCMP = n=1 9.250 14.000 8.600 13.000 8.600 13.000 8.600 13.000
S1 S2 D n n = 96 60.700 67.500 47.900 52.800 47.900 52.800 47.900 52.800

DBKCMP<> n=1 9.250 14.000 8.600 13.000 8.600 13.000 8.600 13.000
S1 S2 D n n = 96 60.700 67.500 47.900 52.800 47.900 52.800 47.900 52.800

DBKCMP> n=1 9.250 14.000 8.600 13.000 8.600 13.000 8.600 13.000
S1 S2 D n n = 96 60.700 67.500 47.900 52.800 47.900 52.800 47.900 52.800

DBKCMP<= n=1 9.250 14.000 8.600 13.000 8.600 13.000 8.600 13.000
S1 S2 D n n = 96 60.700 67.500 47.900 52.800 47.900 52.800 47.900 52.800

DBKCMP< n=1 9.250 14.000 8.600 13.000 8.600 13.000 8.600 13.000
S1 S2 D n n = 96 60.700 67.500 47.900 52.800 47.900 52.800 47.900 52.800

DBKCMP>= n=1 9.250 14.000 8.600 13.000 8.600 13.000 8.600 13.000
S1 S2 D n n = 96 60.700 67.500 47.900 52.800 47.900 52.800 47.900 52.800

DB + S D When executed 4.900 7.000 4.600 6.400 4.600 6.400 4.600 6.400

DB + S1 S2 D When executed 5.200 7.300 4.800 6.700 4.800 6.700 4.800 6.700

DB - S D When executed 4.900 6.600 4.700 6.000 4.700 6.000 4.700 6.000

DB - S1 S2 D When executed 5.200 7.500 4.800 6.600 4.800 6.600 4.800 6.600

DB * S1 S2 D When executed 8.300 12.100 8.100 11.600 8.100 11.600 8.100 11.600

DB/ S1 S2 D When executed 6.100 9.100 5.800 8.800 5.800 8.800 5.800 8.800

824
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
ED + Double S = 0, D =0 4.800 8.000 4.300 7.200 4.300 7.200 4.300 7.200

S D precision S = 21023, D = 21023 4.800 8.000 4.300 7.200 4.300 7.200 4.300 7.200
2
ED + Double S1 = 0, S2 =0 5.500 9.800 4.800 9.200 4.800 9.200 4.800 9.200

S1 S2 D precision S1 = 21023, S2 = 21023 5.500 9.800 4.800 9.200 4.800 9.200 4.800 9.200

ED - Double S = 0, D =0 5.000 8.200 4.400 7.500 4.400 7.500 4.400 7.500 3

S D precision S =2 1023
, D =2 1023 5.000 8.200 4.400 7.500 4.400 7.500 4.400 7.500

ED - Double S1 = 0, S2 =0 4.400 8.100 3.800 7.500 3.800 7.500 3.800 7.500

S1 S2 D precision S1 = 21023, S2 = 21023 4.400 8.100 3.800 7.500 3.800 7.500 3.800 7.500 A
ED * Double S1 = 0, S2 =0 5.800 9.500 5.100 8.800 5.100 8.800 5.100 8.800

S1 S2 D precision = 21023, S2 =2 1023 5.800 9.500 5.100 8.800 5.100 8.800 5.100 8.800
5
S1

Double
ED / S1 S2 D S1 = 21023, S2 = 21023 6.600 10.600 5.900 10.000 5.900 10.000 5.900 10.000
precision
BK + n=1 9.100 11.200 8.500 10.600 8.500 10.600 8.500 10.600
S1 S2 D n n = 96 60.700 62.900 44.600 47.000 44.600 47.000 44.600 47.000 6
BK - n=1 9.700 12.000 8.900 11.300 8.900 11.300 8.900 11.300
S1 S2 D n n = 96 61.300 63.600 45.600 47.900 45.600 47.900 45.600 47.900

DBK + n=1 7.000 10.700 6.450 9.950 6.450 9.950 6.450 9.950 7
S1 S2 D n n = 96 59.400 63.100 43.700 47.500 43.700 47.500 43.700 47.500

DBK - n=1 7.000 10.700 6.450 9.950 6.450 9.950 6.450 9.950
S1 S2 D n n = 96 59.400 63.100 43.700 47.500 43.700 47.500 43.700 47.500 8
$+ S D –– 8.800 14.600 8.100 13.900 8.100 13.900 8.100 13.900

Basic $+ S1 S2 D –– 7.300 11.100 6.500 10.300 6.500 10.300 6.500 10.300

instruction Double S =0 2.300 5.000 1.800 4.700 1.800 4.700 1.800 4.700
FLTD

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
precision S = 7FFFH 2.500 5.200 2.200 4.800 2.200 4.800 2.200 4.800

Double S =0 2.400 5.200 2.000 4.900 2.000 4.900 2.000 4.900

DFLTD
precision S = 7FFFFFFFH 2.700 5.400 2.300 5.100 2.300 5.100 2.300 5.100

Double S =0 2.700 4.100 2.200 4.100 2.200 4.100 2.200 4.100

INTD
precision S = 32766.5 3.700 5.900 3.200 5.600 3.200 5.600 3.200 5.600

Double S =0 2.600 3.900 2.200 3.400 2.200 3.400 2.200 3.400

DINTD
precision S = 1234567890.3 3.400 5.600 3.000 5.100 3.000 5.100 3.000 5.100

DBL When executed 2.700 3.400 2.300 2.700 2.300 2.700 2.300 2.700
WORD When executed 2.900 4.300 2.600 3.600 2.600 3.600 2.600 3.600
GRY When executed 2.700 3.900 2.300 3.400 2.300 3.400 2.300 3.400
DGRY When executed 2.900 3.500 2.500 3.000 2.500 3.000 2.500 3.000
GBIN When executed 4.000 4.800 3.800 4.300 3.800 4.300 3.800 4.300
DGBIN When executed 5.500 6.100 5.000 5.900 5.000 5.900 5.000 5.900
NEG When executed 2.400 3.900 2.000 3.300 2.000 3.300 2.000 3.300
DNEG When executed 2.500 3.700 2.500 3.300 2.500 3.300 2.500 3.300
Floating point = 0 2.500 3.300 2.300 2.800 2.300 2.800 2.300 2.800
ENEG
Floating point = -1.0 2.700 4.500 2.500 3.900 2.500 3.900 2.500 3.900
Floating point = 0 2.200 3.500 1.800 3.100 1.800 3.100 1.800 3.100
EDNEG
Floating point = -1.0 2.400 3.500 1.900 3.000 1.900 3.000 1.900 3.000
n=1 6.600 8.900 5.900 8.200 5.900 8.200 5.900 8.200
BKBCD S D n
n = 96 71.300 74.100 61.000 63.400 61.000 63.400 61.000 63.400
n=1 6.500 9.800 5.600 9.300 5.600 9.300 5.600 9.300
BKBIN S D n
n = 96 56.300 59.500 49.200 52.500 49.200 52.500 49.200 52.500

825
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
ECON –– 2.600 5.400 2.100 4.500 2.100 4.500 2.100 4.500
EDCON –– 2.800 5.400 2.500 5.400 2.500 5.400 2.500 5.400
EDMOV –– 2.300 5.500 1.700 5.000 1.700 5.000 1.700 5.000
Character string to be
4.000 6.300 3.400 5.600 3.400 5.600 3.400 5.600
transferred = 0
$MOV
Character string to be
14.600 16.500 11.400 13.300 11.400 13.300 11.400 13.300
transferred = 32
n=1 6.200 7.900 5.500 7.300 5.500 7.300 5.500 7.300
BXCH D1 D2 n
n = 96 67.000 68.800 47.300 49.300 47.300 49.300 47.300 49.300
SWAP –– 2.400 2.700 1.900 2.200 1.900 2.200 1.900 2.200
GOEND –– 0.500 0.500 0.500 0.500
DI –– 1.800 2.200 1.500 1.800 1.500 1.800 1.500 1.800
EI –– 3.100 3.800 3.000 3.300 3.000 3.300 3.000 3.300
IMASK –– 9.800 13.300 7.200 10.500 7.200 10.500 7.200 10.500
Basic
IRET –– 1.000 1.000 1.000 1.000
instruction
n=1 4.200 5.900 3.700 5.600 3.700 5.600 3.700 5.600
RFS X n
n = 96 11.400 13.800 10.700 12.400 10.700 12.400 10.700 12.400
n=1 3.800 4.800 3.400 4.800 3.400 4.800 3.400 4.800
RFS Y n
n = 96 8.500 9.500 8.100 8.900 8.100 8.900 8.100 8.900
UDCNT1 –– 0.900 1.500 0.500 0.983 0.500 0.983 0.500 0.983
UDCNT2 –– 0.900 1.700 0.600 1.300 0.600 1.300 0.600 1.300
TTMR –– 3.900 6.100 3.400 5.400 3.400 5.400 3.400 5.400
STMR –– 6.800 13.500 5.800 12.500 5.800 12.500 5.800 12.500
ROTC –– 9.000 10.500 8.000 9.400 8.000 9.400 8.000 9.400
RAMP –– 5.900 8.800 5.200 8.400 5.200 8.400 5.200 8.400
SPD –– 0.900 1.900 0.500 1.400 0.500 1.400 0.500 1.400
PLSY –– 1.900 2.200 1.500 1.800 1.500 1.800 1.500 1.800
PWM –– 1.200 1.600 0.900 1.200 0.900 1.200 0.900 1.200
MTR –– 10.400 19.800 9.400 10.000 9.400 10.000 9.400 10.000
n=1 9.000 11.700 8.300 11.000 8.300 11.000 8.300 11.000
BKAND S1 S2 D n
n = 96 57.400 63.100 43.800 47.300 43.800 47.300 43.800 47.300
n=1 7.700 10.000 7.700 9.500 7.700 9.500 7.700 9.500
BKOR S1 S2 D n
n = 96 57.400 61.900 44.300 45.800 44.300 45.800 44.300 45.800
n=1 7.800 10.100 7.300 9.200 7.300 9.200 7.300 9.200
BKXOR S1 S2 D n
n = 96 57.300 61.500 43.800 45.800 43.800 45.800 43.800 45.800
n=1 7.800 9.600 7.600 8.900 7.600 8.900 7.600 8.900
BKXNR S1 S2 D n
n = 96 57.400 61.400 43.900 45.300 43.900 45.300 43.900 45.300
n=1 3.700 5.400 3.200 4.800 3.200 4.800 3.200 4.800
BSFR D n
n = 96 6.900 9.000 5.800 7.700 5.800 7.700 5.800 7.700
n=1 4.100 5.900 3.400 5.100 3.400 5.100 3.400 5.100
BSFL D n
Application n = 96 7.100 9.100 6.000 7.900 6.000 7.900 6.000 7.900
instruction n1 = 16 / n2 = 1 7.950 17.500 7.600 16.900 7.600 16.900 7.600 16.900
SFTBR D n1 n2
n1 = 16 / n2 = 15 7.950 17.500 7.550 16.900 7.550 16.900 7.550 16.900
n1 = 16 / n2 = 1 7.950 17.900 7.500 17.400 7.500 17.400 7.500 17.400
SFTBL D n1 n2
n1 = 16 / n2 = 15 7.900 17.800 7.500 17.300 7.500 17.300 7.500 17.300
n1 = 16 / n2 = 1 5.950 10.600 4.600 8.700 4.600 8.700 4.600 8.700
SFTWR D n1 n2
n1 = 16 / n2 = 15 5.900 10.600 4.600 8.700 4.600 8.700 4.600 8.700
n1 = 16 / n2 = 1 5.950 10.700 4.550 8.700 4.550 8.700 4.550 8.700
SFTWL D n1 n2
n1 = 16 / n2 = 15 5.950 10.700 4.600 8.800 4.600 8.800 4.600 8.800
n=1 3.000 3.400 2.500 2.800 2.500 2.800 2.500 2.800
BSET D n
n = 15 3.000 3.500 2.500 2.800 2.500 2.800 2.500 2.800
n=1 3.000 3.400 2.600 2.800 2.600 2.800 2.600 2.800
BRST D n
n = 15 3.000 3.400 2.500 2.800 2.500 2.800 2.500 2.800

826
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
TEST When executed 4.400 5.300 3.700 4.700 3.700 4.700 3.700 4.700
DTEST When executed 4.500 5.400 3.900 4.800 3.900 4.800 3.900 4.800
n=1 4.300 4.600 3.700 4.100 3.700 4.100 3.700 4.100 2
BKRST D n
n = 96 6.000 6.800 5.100 6.000 5.100 6.000 5.100 6.000
All match 4.900 5.300 4.200 4.600 4.200 4.600 4.200 4.600
n=1
SER S1 S2 D n
None match 5.000 5.300 4.200 4.600 4.200 4.600 4.200 4.600 3
All match 32.300 32.900 25.900 26.300 25.900 26.300 25.900 26.300
n = 96
None match 32.400 32.900 25.900 26.300 25.900 26.300 25.900 26.300

n=1
All match
None match
6.100
6.200
6.500
6.600
5.400
5.500
5.700
5.900
5.400
5.500
5.700
5.900
5.400
5.500
5.700
5.900
A
DSER S1 S2 D n
All match 52.800 54.200 41.200 41.800 41.200 41.800 41.200 41.800
n = 96
None match 52.800 54.200 41.200 41.800 41.200 41.800 41.200 41.800

S =0 3.700 4.100 3.300 3.600 3.300 3.600 3.300 3.600 5

DSUM S D
S = FFFFFFFFH 3.800 4.100 3.200 3.700 3.200 3.700 3.200 3.700

n=2 6.000 7.500 5.300 6.900 5.300 6.900 5.300 6.900

DECO S D n
n=8 8.100 9.300 6.800 7.800 6.800 7.800 6.800 7.800
6
M1 = ON 5.300 5.700 4.700 5.100 4.700 5.100 4.700 5.100
n=2
M4 = ON 5.200 5.700 4.600 5.000 4.600 5.000 4.600 5.000
ENCO S D n
n=8
M1 = ON 10.400 11.400 9.000 10.000 9.000 10.000 9.000 10.000 7
M256 = ON 5.700 6.800 5.100 6.100 5.100 6.100 5.100 6.100
n=1 4.400 5.300 3.800 4.600 3.800 4.600 3.800 4.600
DIS S D n
n=4
n=1
4.800
5.000
5.700
5.300
4.000
3.500
5.000
4.800
4.000
3.500
5.000
4.800
4.000
3.500
5.000
4.800
8
UNI S D n
n=4 5.600 6.000 4.000 5.100 4.000 5.100 4.000 5.100

Application NDIS When executed 11.000 13.100 11.000 13.200 11.000 13.200 11.000 13.200

instruction NUNI When executed 10.600 12.700 7.300 13.200 7.300 13.200 7.300 13.200
n=1 5.000 6.500 4.400 5.800 4.400 5.800 4.400 5.800

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
WTOB S D n
n = 96 36.000 38.400 28.200 29.300 28.200 29.300 28.200 29.300
n=1 5.100 6.100 4.600 5.500 4.600 5.500 4.600 5.500
BTOW S D n
n = 96 29.900 32.000 22.800 23.800 22.800 23.800 22.800 23.800
n=1 4.300 6.900 4.000 6.100 4.000 6.100 4.000 6.100
MAX S D n
n = 96 31.200 33.500 24.700 27.000 24.700 27.000 24.700 27.000
n=1 4.400 6.800 4.000 6.000 4.000 6.000 4.000 6.000
MIN S D n
n = 96 30.300 34.800 26.500 28.300 26.500 28.300 26.500 28.300
n=1 4.800 9.100 4.800 8.100 4.800 8.100 4.800 8.100
DMAX S D n
n = 96 56.400 62.200 47.100 49.600 47.100 49.600 47.100 49.600
n=1 4.800 6.800 4.300 5.900 4.300 5.900 4.300 5.900
DMIN S D n
n = 96 55.400 60.200 45.400 47.400 45.400 47.400 45.400 47.400

n = 1, S2 =1 6.200 9.300 5.600 8.800 5.600 8.800 5.600 8.800

SORT S1 n S2 D1 D2
n = 96, S2 = 16 28,200 38,500 22,200 32,200 22,200 32,200 22,200 32,200

n = 1, S2 =1 6.200 11,600 5.600 10,900 5.600 10,900 5.600 10,900

DSORT S1 n S2 D1 D2
n = 96, S2 = 16 34,700 45,300 26,700 36,900 26,700 36,900 26,700 36,900

n=1 4.800 6.200 4.200 5.500 4.200 5.500 4.200 5.500

WSUM S D n
n = 96 26.900 28.700 21.300 22.300 21.300 22.300 21.300 22.300
n=1 5.500 7.000 4.800 6.100 4.800 6.100 4.800 6.100
DWSUM S D n
n = 96 53.000 56.300 42.700 44.000 42.700 44.000 42.700 44.000
n=1 4.300 8.650 3.900 7.800 3.900 7.800 3.900 7.800
MEAN S D n
n = 96 16.000 21.400 12.900 18.000 12.900 18.000 12.900 18.000
n=1 5.700 10.600 5.300 9.950 5.300 9.950 5.300 9.950
DMEAN S D n
n = 96 29.200 35.200 23.000 28.800 23.000 28.800 23.000 28.800

827
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
NEXT –– 0.940 1.400 0.770 1.200 0.770 1.200 0.770 1.200
BREAK –– 10.400 5.500 9.100 5.000 9.100 5.000 9.100 5.000
Return to original program 2.000 3.000 1.600 2.600 1.600 2.600 1.600 2.600
RET
Return to other program 2.300 3.700 2.000 3.100 2.000 3.100 2.000 3.100
Internal file pointer 3.100 4.400 2.700 3.600 2.700 3.600 2.700 3.600
FCALL Pn
Common pointer 4.000 5.700 3.600 5.100 3.600 5.100 3.600 5.100

FCALL Pn S1 to S5 –– 19.300 21.500 16.500 18.600 16.500 18.600 16.500 18.600

Application ECALL * Pn
–– 70.300 82.300 65.900 77.600 65.900 77.600 65.900 77.600
instruction *: Program name
ECALL * Pn S1 to S5
–– 101.000 114.000 91.800 105.000 91.800 105.000 91.800 105.000
*: Program name
EFCALL * Pn
–– 70.700 82.800 66.200 78.100 66.200 78.100 66.200 78.100
*: Program name

EFCALL * Pn S1 to S5
–– 86.500 107.000 78.800 91.600 78.800 91.600 78.800 91.600
*: Program name
XCALL –– 3.800 5.700 3.700 5.200 3.700 5.200 3.700 5.200

828
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
When selecting I/O refresh
12.800 29.100 12.400 28.600 12.400 28.600 12.400 28.600
only
When selecting CC-Link 2
refresh only (master station 16.000 39.500 15.500 39.100 15.500 39.100 15.500 39.100
side)
When selecting CC-Link 3
refresh only (local station 16.100 39.500 15.500 39.100 15.500 39.100 15.500 39.100
side)
• When selecting
MELSECNET/H refresh A
only (Control station side)
34.700 70.400 34.400 69.800 34.400 69.800 34.400 69.800
• When selecting CC-Link IE
Controller Network refresh 5
only (Control station side)
• When selecting
MELSECNET/H refresh
only (Normal station side) 6
34.700 70.400 34.400 69.800 34.400 69.800 34.400 69.800
• When selecting CC-Link IE
Controller Network refresh
COM only (Normal station side) 7
CCOM When selecting CC-Link IE
Field Network refresh only 17.000 38.800 16.600 38.000 16.600 38.000 16.600 38.000
(master station side)
When selecting CC-Link IE 8
Application Field Network refresh only 17.000 38.800 16.600 38.000 16.600 38.000 16.600 38.000

instruction (local station side)

When selecting intelli auto
12.800 33.200 12.800 33.200 12.800 33.200 12.800 33.200
refresh only

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
When selecting I/O outside
7.900 21.100 7.700 20.700 7.700 20.700 7.700 20.700
the group only (Input only)
When selecting I/O outside
16.900 44.800 16.500 44.200 16.500 44.200 16.500 44.200
the group only (Output only)
When selecting I/O outside
22.600 52.600 22.400 52.600 22.400 52.600 22.400 52.600
the group only (Both I/O)
When selecting refresh of
multiple CPU high speed 13.000 33.800 12.700 33.200 12.700 33.200 12.700 33.200
transmission area only
When selecting
communication with external 7.250 18.800 7.100 18.500 7.100 18.500 7.100 18.500
devices only
Number of data points = 0 3.700 5.300 3.200 4.600 3.200 4.600 3.200 4.600
FIFW
Number of data points = 96 3.800 4.400 3.300 3.800 3.300 3.800 3.300 3.800
Number of data points = 01 4.300 5.000 3.800 4.400 3.800 4.400 3.800 4.400
FIFR
Number of data points = 96 33.500 35.500 24.800 25.700 24.800 25.700 24.800 25.700
Number of data points = 01 4.300 5.900 3.800 5.300 3.800 5.300 3.800 5.300
FPOP
Number of data points = 96 4.300 5.900 3.700 5.400 3.700 5.400 3.700 5.400
Number of data points = 0 4.800 5.900 3.700 5.300 3.700 5.300 3.700 5.300
FINS
Number of data points = 96 4.300 5.900 3.700 5.300 3.700 5.300 3.700 5.300
Number of data points =01 4.900 6.500 4.200 5.800 4.200 5.800 4.200 5.800
FDEL
Number of data points = 96 34.200 35.900 25.400 25.900 25.400 25.900 25.400 25.900

829
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
FROM n1 n2 n3 = 1 10.800 24.100 10.700 23.600 10.700 23.600 10.700 23.600
D n3 n3 = 1000 392.600 413.300 390.900 410.200 390.900 410.200 390.900 410.200

DFRO n1 n2 n3 = 1 13.600 27.700 12.600 26.700 12.600 26.700 12.600 26.700

D n3 n3 = 500 392.600 413.300 390.900 410.200 390.900 410.200 390.900 410.200

TO n1 n2 n3 = 1 10.200 21.900 9.600 21.300 9.600 21.300 9.600 21.300

S n3 n3 = 1000 373.700 394.100 372.500 390.800 372.500 390.800 372.500 390.800

DTO n1 n2 n3 = 1 13.000 26.700 12.000 25.700 12.000 25.700 12.000 25.700

S n3 n3 = 500 373.700 394.100 372.500 390.800 372.500 390.800 372.500 390.800

No display no display 2.400 2.600 1.900 2.000 1.900 2.000 1.900 2.000
LEDR LED instruction execution
28.100 39.400 24.400 35.800 24.400 35.800 24.400 35.800
no display
BINDA S =1 4.900 6.500 4.300 5.600 4.300 5.600 4.300 5.600

S D 7.200 8.700 6.500 8.000 6.500 8.000 6.500 8.000

S = -32768
DBINDA S =1 5.700 7.100 4.900 6.300 4.900 6.300 4.900 6.300

S D 10.400 12.000 9.600 11.000 9.600 11.000 9.600 11.000

S = -2147483648
S =1 4.400 5.900 3.800 5.200 3.800 5.200 3.800 5.200
BINHA S D
S = FFFFH 4.400 5.800 3.700 5.200 3.700 5.200 3.700 5.200

S =1 5.200 6.700 4.600 6.000 4.600 6.000 4.600 6.000

DBINHA S D
S = FFFFFFFFH 5.100 6.500 4.600 6.000 4.600 6.000 4.600 6.000

Application S =1 4.300 5.800 3.600 5.000 3.600 5.000 3.600 5.000

instruction BCDDA S D
S = 9999 4.700 6.100 4.100 5.400 4.100 5.400 4.100 5.400

S =1 4.800 6.300 4.000 5.500 4.000 5.500 4.000 5.500

DBCDDA S D
S = 99999999 5.600 7.100 4.900 6.300 4.900 6.300 4.900 6.300

S =1 6.500 8.500 5.800 7.800 5.800 7.800 5.800 7.800

DABIN S D
S = -32768 6.300 8.300 5.600 7.700 5.600 7.700 5.600 7.700

S =1 9.400 11.500 8.500 10.500 8.500 10.500 8.500 10.500

DDABIN S D
S = -2147483648 9.100 11.200 8.100 10.200 8.100 10.200 8.100 10.200

S =1 4.900 7.100 4.400 6.400 4.400 6.400 4.400 6.400

HABIN S D
S = FFFFH 5.100 7.300 4.600 6.500 4.600 6.500 4.600 6.500

S =1 6.000 8.100 5.300 7.300 5.300 7.300 5.300 7.300

DHABIN S D
S = FFFFFFFFH 6.300 8.500 5.600 7.700 5.600 7.700 5.600 7.700

S =1 5.000 7.100 4.400 6.300 4.400 6.300 4.400 6.300

DABCD S D
S = 9999 5.000 7.100 4.300 6.300 4.300 6.300 4.300 6.300

S =1 6.200 8.300 5.500 7.400 5.500 7.400 5.500 7.400

DDABCD S D
S = 99999999 6.200 8.300 5.500 7.500 5.500 7.500 5.500 7.500

COMRD –– 51.600 52.400 50.900 51.200 50.900 51.200 50.900 51.200

1 character 4.100 6.200 3.600 5.500 3.600 5.500 3.600 5.500
LEN
96 characters 19.800 22.200 16.800 18.700 16.800 18.700 16.800 18.700
STR –– 6.900 11.100 6.600 10.400 6.600 10.400 6.600 10.400

830
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
DSTR –– 10.200 12.500 9.600 11.500 9.600 11.500 9.600 11.500
VAL –– 9.800 14.200 8.900 13.000 8.900 13.000 8.900 13.000
DVAL –– 14.000 18.700 12.700 16.800 12.700 16.800 12.700 16.800 2
ESTR –– 18.700 24.100 17.900 23.100 17.900 23.100 17.900 23.100
Decimal point format
3
23.300 30.400 22.800 29.000 22.800 29.000 22.800 29.000
all 2-digit specification
EVAL
Exponent format
23.300 30.500 22.500 29.000 22.500 29.000 22.500 29.000
all 6-digit specification
n=1
ASC S D n
n = 96
5.600
28.700
9.000
32.100
5.400
25.200
8.300
28.400
5.400
25.200
8.300
28.400
5.400
25.200
8.300
28.400
A
n=1 6.000 9.700 5.400 9.000 5.400 9.000 5.400 9.000
HEX S D n
n = 96 35.600 39.800 31.300 35.000 31.300 35.000 31.300 35.000

RIGHT S D n
n=1 7.600 9.400 6.600 7.300 6.600 7.300 6.600 7.300 5
n = 96 36.300 40.000 29.200 31.600 29.200 31.600 29.200 31.600
n=1 6.500 8.900 5.900 8.200 5.900 8.200 5.900 8.200
LEFT S D n

MIDR
n = 96
––
36.200
9.500
39.700
12.100
29.200
8.100
31.500
10.300
29.200
8.100
31.500
10.300
29.200
8.100
31.500
10.300
6
MIDW –– 10.300 12.000 8.800 10.200 8.800 10.200 8.800 10.200
No match 19.300 21.800 16.600 18.400 16.600 18.400 16.600 18.400
INSTR Head 10.300 12.800 9.100 10.900 9.100 10.900 9.100 10.900 7
Match
End 51.100 54.200 42.700 44.900 42.700 44.900 42.700 44.900
EMOD –– 10.300 11.800 9.600 11.000 9.600 11.000 9.600 11.000
EREXP –– 19.300 21.000 18.800 20.100 18.800 20.100 18.800 20.100 8
S = 128 / D = 40 /
41.100 54.200 35.300 47.600 35.300 47.600 35.300 47.600
Application n=1
instruction STRINS S D n
S = 128 / D = 40 /
56.700 81.400 48.600 61.700 48.600 61.700 48.600 61.700
n = 48

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
S = 128 / D = 40 /
39.000 49.500 34.800 44.600 34.800 44.600 34.800 44.600
n=1
STRDEL S D n
S = 128 / D = 40 /
36.000 45.200 29.200 38.100 29.200 38.100 29.200 38.100
n = 48
SIN Single precision 4.500 6.200 4.100 5.700 4.100 5.700 4.100 5.700
COS Single precision 4.300 6.000 4.000 5.600 4.000 5.600 4.000 5.600
TAN Single precision 5.100 7.200 5.100 6.700 5.100 6.700 5.100 6.700
ASIN Single precision 6.100 8.900 5.900 8.500 5.900 8.500 5.900 8.500
ACOS Single precision 6.800 9.300 6.700 8.900 6.700 8.900 6.700 8.900
ATAN Single precision 4.000 6.500 3.900 6.000 3.900 6.000 3.900 6.000
SIND Double precision 8.800 14.300 8.500 13.800 8.500 13.800 8.500 13.800
COSD Double precision 9.300 15.100 8.800 14.600 8.800 14.600 8.800 14.600
TAND Double precision 11.200 16.900 10.800 16.500 10.800 16.500 10.800 16.500
ASIND Double precision 12.000 17.100 11.600 16.600 11.600 16.600 11.600 16.600
ACOSD Double precision 11.700 16.500 11.200 16.200 11.200 16.200 11.200 16.200
ATAND Double precision 9.500 14.200 9.100 13.800 9.100 13.800 9.100 13.800
RAD Single precision 2.500 4.800 2.100 4.300 2.100 4.300 2.100 4.300
RADD Double precision 4.000 9.600 3.600 9.200 3.600 9.200 3.600 9.200
DEG Single precision 2.500 4.700 2.200 4.400 2.200 4.400 2.200 4.400
DEGD Double precision 4.300 9.000 3.800 9.000 3.800 9.000 3.800 9.000
SQR Single precision 3.000 4.600 2.600 4.300 2.600 4.300 2.600 4.300
SQRD Double precision 5.600 11.500 5.200 11.000 5.200 11.000 5.200 11.000

831
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.

Single S = -10 4.000 6.100 3.800 5.500 3.800 5.500 3.800 5.500
EXP S D
precision S =1 4.000 6.100 3.800 5.600 3.800 5.600 3.800 5.600

Double S = -10 8.700 13.900 8.200 13.500 8.200 13.500 8.200 13.500
EXPD S D
precision S =1 8.400 13.600 8.000 13.200 8.000 13.200 8.000 13.200

Single S =1 4.100 6.900 3.800 6.400 3.800 6.400 3.800 6.400

LOG S D
precision S = 10 5.600 8.200 5.200 7.700 5.200 7.700 5.200 7.700

Double S =1 8.100 13.000 7.700 12.500 7.700 12.500 7.700 12.500

LOGD S D
precision S = 10 9.700 14.800 9.200 14.300 9.200 14.300 9.200 14.300

RND –– 1.200 2.300 0.800 1.800 0.800 1.800 0.800 1.800

SRND –– 1.400 2.400 1.100 2.000 1.100 2.000 1.100 2.000

S =0 1.800 3.300 1.600 2.800 1.600 2.800 1.600 2.800

BSQR S D
S = 9999 5.100 8.800 5.100 8.000 5.100 8.000 5.100 8.000

S =0 1.900 3.400 1.500 3.000 1.500 3.000 1.500 3.000

BDSQR S D
S = 99999999 7.500 10.200 7.500 9.900 7.500 9.900 7.500 9.900
Application BSIN –– 8.600 15.100 8.100 14.500 8.100 14.500 8.100 14.500
instruction BCOS –– 7.800 14.400 7.800 13.700 7.800 13.700 7.800 13.700
BTAN –– 9.000 13.800 9.000 13.300 9.000 13.300 9.000 13.300
BASIN –– 10.600 13.400 10.100 12.800 10.100 12.800 10.100 12.800
BACOS –– 11.600 14.400 11.100 14.100 11.100 14.100 11.100 14.100
BATAN –– 9.800 11.700 9.100 10.900 9.100 10.900 9.100 10.900

Single S1 = 12.3 E + 5
POW S1 S2 D
precision S2 = 3.45 E + 0
8.750 11.400 8.400 10.900 8.400 10.900 8.400 10.900
Double S1 = 12.3 E + 5
POWD S1 S2 D
precision S2 = 3.45 E + 0
LOG10 Single precision
18.600 27.200 18.200 26.500 18.200 26.500 18.200 26.500
LOG10D Double precision
LIMIT –– 5.900 8.550 5.700 8.050 5.700 8.050 5.700 8.050
DLIMIT –– 11.500 19.400 11.100 18.600 11.100 18.600 11.100 18.600
BAND –– 2.800 3.100 2.400 2.700 2.400 2.700 2.400 2.700
DBAND –– 3.200 3.500 2.800 3.000 2.800 3.000 2.800 3.000
ZONE –– 3.000 4.300 2.700 3.800 2.700 3.800 2.700 3.800
DZONE –– 3.600 5.100 3.300 4.600 3.300 4.600 3.300 4.600

832
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
Point No.1

2
< S1 < 13.200 23.600 12.300 22.500 12.300 22.500 12.300 22.500
SM750 Point No.2
= ON Point No.9
< S1 < 13.300 23.600 12.600 22.700 12.600 22.700 12.600 22.700
Point No.10 3
SCL S1 S2 D
Point No.1
< S1 < 12.000 23.100 11.400 22.200 11.400 22.200 11.400 22.200
SM750 Point No.2 A
= OFF Point No.9
< S1 < 14.100 25.300 12.800 23.900 12.800 23.900 12.800 23.900
Point No.10 5
Point No.1
< S1 < 12.800 23.800 11.900 23.000 11.900 23.000 11.900 23.000
SM750
= ON
Point No.2
Point No.9
6
< S1 < 12.900 23.900 12.100 23.000 12.100 23.000 12.100 23.000
Point No.10
DSCL S1 S2 D
Point No.1 7
< S1 < 11.500 22.400 10.900 21.500 10.900 21.500 10.900 21.500
SM750 Point No.2
= OFF Point No.9 8
< S1 < 13.800 24.900 12.700 23.600 12.700 23.600 12.700 23.600
Application Point No.10
instruction Point No.1
< S1 < 12.700 24.200 11.900 23.300 11.900 23.300 11.900 23.300

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
SM750 Point No.2
= ON Point No.9
< S1 < 12.900 24.600 12.100 23.300 12.100 23.300 12.100 23.300
Point No.10
SCL2 S1 S2 D
Point No.1
< S1 < 12.300 23.400 11.500 22.600 11.500 22.600 11.500 22.600
SM750 Point No.2
= OFF Point No.9
< S1 < 13.700 25.000 12.600 23.900 12.600 23.900 12.600 23.900
Point No.10
Point No.1
< S1 < 12.600 23.800 11.800 22.900 11.800 22.900 11.800 22.900
SM750 Point No.2
= ON Point No.9
< S1 < 13.000 23.900 12.200 22.800 12.200 22.800 12.200 22.800
Point No.10
DSCL2 S1 S2 D
Point No.1
< S1 < 11.500 22.400 11.000 21.400 11.000 21.400 11.000 21.400
SM750 Point No.2
= OFF Point No.9
< S1 < 13.900 24.900 12.800 23.600 12.800 23.600 12.800 23.600
Point No.10

833
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
Standard RAM 3.000 6.300 2.700 5.900 2.700 5.900 2.700 5.900
RSET
SRAM card 3.000 6.400 2.600 5.800 2.600 5.800 2.600 5.800
SRAM card to standard RAM 120.000 134.000 115.000 134.000 115.000 134.000 115.000 134.000
QDRSET
Standard RAM to SRAM card 533.000 560.000 520.000 553.000 520.000 553.000 520.000 553.000
SRAM card to standard ROM 306.000 346.000 305.000 346.000 305.000 346.000 305.000 346.000
QCDSET
Standard ROM to SRAM card 311.000 342.000 300.000 334.000 300.000 334.000 300.000 334.000
DATERD –– 3.200 5.000 2.500 4.200 2.500 4.200 2.500 4.200
DATEWR –– 4.900 9.700 4.100 8.900 4.100 8.900 4.100 8.900
No digit increase 5.100 8.000 4.700 6.600 4.700 6.600 4.700 6.600
DATE +
Digit increase 5.700 8.000 4.600 6.500 4.600 6.500 4.600 6.500
No digit increase 5.800 8.500 4.600 7.000 4.600 7.000 4.600 7.000
DATE -
Digit increase 5.700 7.400 4.600 6.500 4.600 6.500 4.600 6.500
SECOND –– 2.600 3.900 2.200 3.400 2.200 3.400 2.200 3.400
HOUR –– 2.900 4.800 2.400 4.300 2.400 4.300 2.400 4.300
Comparison In conductive status 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900
of specified
date In non-conductive status 7.400 11.600 6.800 10.900 6.800 10.900 6.800 10.900
LDDT =
Comparison In conductive status 5.900 10.000 5.500 9.700 5.500 9.700 5.500 9.700
of current
date In non-conductive status 5.900 10.100 5.500 9.700 5.500 9.700 5.500 9.700

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700
of specified
ANDDT= date In non-conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700

Comparison In conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300
of current
Application date In non-conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300

instruction When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
ORDT= date In non-conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800

Comparison In conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600
of current
date In non-conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600

Comparison In conductive status 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900
of specified
date In non-conductive status 7.400 11.600 6.800 10.900 6.800 10.900 6.800 10.900
LDDT <>
Comparison In conductive status 5.900 10.000 5.500 9.700 5.500 9.700 5.500 9.700
of current
date In non-conductive status 5.900 10.100 5.500 9.700 5.500 9.700 5.500 9.700

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700
of specified
ANDDT<> date In non-conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700

Comparison In conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300
of current
date In non-conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
ORDT<> date In non-conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800

Comparison In conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600
of current
date In non-conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600

834
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
Comparison In conductive status 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900
of specified
date In non-conductive status 7.400 11.600 6.800 10.900 6.800 10.900 6.800 10.900 2
LDDT>
Comparison In conductive status 5.900 10.000 5.500 9.700 5.500 9.700 5.500 9.700
of current
date In non-conductive status 5.900 10.100 5.500 9.700 5.500 9.700 5.500 9.700
3
When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700

ANDDT>
of specified
In non-conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700
A
date
Comparison In conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300
of current
date In non-conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300 5
When not executed 0.008 0.038 0.038 0.038
Comparison In conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified 6
ORDT> date In non-conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800

Comparison In conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600
of current
date In non-conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600 7
Comparison In conductive status 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900
of specified

LDDT<=
date In non-conductive status 7.400 11.600 6.800 10.900 6.800 10.900 6.800 10.900 8
Comparison In conductive status 5.900 10.000 5.500 9.700 5.500 9.700 5.500 9.700
of current
date In non-conductive status 5.900 10.100 5.500 9.700 5.500 9.700 5.500 9.700
Application
instruction When not executed 0.008 0.038 0.038 0.038

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Comparison In conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700
of specified
ANDDT<= date In non-conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700

Comparison In conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300
of current
date In non-conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
ORDT<= date In non-conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800

Comparison In conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600
of current
date In non-conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600

Comparison In conductive status 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900
of specified
date In non-conductive status 7.400 11.600 6.800 10.900 6.800 10.900 6.800 10.900
LDDT<
Comparison In conductive status 5.900 10.000 5.500 9.700 5.500 9.700 5.500 9.700
of current
date In non-conductive status 5.900 10.100 5.500 9.700 5.500 9.700 5.500 9.700

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700
of specified
ANDDT< date In non-conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700

Comparison In conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300
of current
date In non-conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300

835
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.008 0.038 0.038 0.038
Comparison In conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
ORDT< date In non-conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800

Comparison In conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600
of current
date In non-conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600

Comparison In conductive status 7.400 11.400 6.800 10.900 6.800 10.900 6.800 10.900
of specified
date In non-conductive status 7.400 11.600 6.800 10.900 6.800 10.900 6.800 10.900
LDDT>=
Comparison In conductive status 5.900 10.000 5.500 9.700 5.500 9.700 5.500 9.700
of current
date In non-conductive status 5.900 10.100 5.500 9.700 5.500 9.700 5.500 9.700

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700
of specified
ANDDT>= date In non-conductive status 7.200 11.400 6.500 10.700 6.500 10.700 6.500 10.700

Comparison In conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300
of current
date In non-conductive status 5.700 9.900 5.300 9.300 5.300 9.300 5.300 9.300

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
ORDT>= date In non-conductive status 7.400 11.500 6.700 10.800 6.700 10.800 6.700 10.800

Comparison In conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600
of current
Application In non-conductive status 5.900 10.000 5.400 9.600 5.400 9.600 5.400 9.600
date
instruction
Comparison In conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
clock In non-conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
LDTM=
Comparison In conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500
of current
clock In non-conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800
of specified
ANDTM= clock In non-conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800

Comparison In conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500
of current
clock In non-conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800
of specified
ORTM= clock In non-conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800

Comparison
of current In conductive status 5.900 9.900 5.300 9.500 5.300 9.500 5.300 9.500
clock
Comparison In conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
clock In non-conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
LDTM<>
Comparison In conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500
of current
clock In non-conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500

836
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.008 0.038 0.038 0.038
Comparison
of specified
In conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800
2
ANDTM<> clock In non-conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800

Comparison In conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500
of current
In non-conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500
3
clock
When not executed 0.008 0.038 0.038 0.038
Comparison
of specified
In conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800
A
ORTM<> clock In non-conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800

Comparison In conductive status 5.900 9.900 5.300 9.500 5.300 9.500 5.300 9.500
of current 5
clock In non-conductive status 5.900 9.900 5.300 9.500 5.300 9.500 5.300 9.500

Comparison In conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
clock In non-conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800 6
LDTM>
Comparison In conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500
of current
clock In non-conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500
7
When not executed 0.008 0.038 0.038 0.038
Comparison In conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800

Application
ANDTM>
of specified
clock In non-conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800 8
instruction
Comparison In conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500
of current
clock In non-conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500

When not executed 0.008 0.038 0.038 0.038

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Comparison In conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800
of specified
ORTM> clock In non-conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800

Comparison In conductive status 5.900 9.900 5.300 9.500 5.300 9.500 5.300 9.500
of current
clock In non-conductive status 5.900 9.900 5.300 9.500 5.300 9.500 5.300 9.500

Comparison In conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
clock In non-conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
LDTM<=
Comparison In conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500
of current
clock In non-conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500

When not executed 0.008 0.038 0.038 0.038

Comparison In conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800
of specified
ANDTM<= clock In non-conductive status 7.000 11.500 6.300 10.800 6.300 10.800 6.300 10.800

Comparison In conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500
of current
clock In non-conductive status 5.500 9.900 5.100 9.500 5.100 9.500 5.100 9.500

837
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When not executed 0.008 0.038 0.038 0.038
Comparison In conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800
of specified
ORTM<= clock In non-conductive status 7.300 11.500 6.600 10.800 6.600 10.800 6.600 10.800

Comparison In conductive status 5.900 9.900 5.300 9.500 5.300 9.500 5.300 9.500
of current
clock In non-conductive status 5.900 9.900 5.300 9.500 5.300 9.500 5.300 9.500

Comparison In conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
clock In non-conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
LDTM<
Comparison In conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500
of current
clock In non-conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500

When not executed 0.480 0.320 0.240 0.240

Comparison In conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500
of specified
ANDTM< clock In non-conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500

Comparison In conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100
of current
clock In non-conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100

When not executed 0.480 0.320 0.240 0.240

Comparison In conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500
of specified
ORTM< clock In non-conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500

Comparison In conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100
Application of current
instruction clock In non-conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100

Comparison In conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
of specified
clock In non-conductive status 7.300 11.500 6.700 10.800 6.700 10.800 6.700 10.800
LDTM<
Comparison In conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500
of current
clock In non-conductive status 5.800 9.900 5.400 9.500 5.400 9.500 5.400 9.500

When not executed 0.480 0.320 0.240 0.240

Comparison In conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500
of specified
ANDTM< clock In non-conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500

Comparison In conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100
of current
clock In non-conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100

When not executed 0.480 0.320 0.240 0.240

Comparison In conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500
of specified
ORTM< clock In non-conductive status 8.200 25.500 8.200 25.500 6.500 25.500 6.500 25.500

Comparison In conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100
of current
clock In non-conductive status 6.500 23.100 6.500 23.100 6.500 23.100 6.500 23.100

S.DATERD –– 9.250 51.000 9.250 51.000 9.250 51.000 9.250 51.000

No digit increase 16.800 75.400 16.800 75.400 16.800 75.400 16.800 75.400
S.DATE +
Digit increase 16.800 75.400 16.800 75.400 16.800 75.400 16.800 75.400
No digit increase 17.600 75.300 17.600 75.300 17.600 75.300 17.600 75.300
S.DATE -
Digit increase 16.900 75.300 16.900 75.300 16.900 75.300 16.900 75.300

838
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
PSTOP –– 82.200 199.000 82.200 199.000 82.200 199.000 82.200 199.000
POFF –– 82.600 198.000 82.600 198.000 82.600 198.000 82.600 198.000
PSCAN –– 83.600 200.000 83.600 200.000 83.600 200.000 83.600 200.000 2
WDT –– 2.900 12.000 2.900 12.000 2.900 12.000 2.900 12.000
DUTY –– 7.700 27.500 7.700 27.500 7.700 27.500 7.700 27.500
TIMCHK –– 5.350 24.500 5.350 24.500 5.350 24.500 5.350 24.500 3
File register of standard RAM 4.100 4.200 4.100 4.200 4.100 4.200 4.100 4.200
ZRRDB
File register of SRAM card –– –– –– –– –– –– –– ––

ZRWRB
File register of standard RAM
File register of SRAM card
5.400
––
5.500
––
5.400
––
5.500
––
5.400
––
5.500
––
5.400
––
5.500
––
A
ADRSET –– 2.400 6.650 2.400 6.650 2.400 6.650 2.400 6.650
ZPUSH –– 9.200 20.500 9.200 20.500 9.200 20.500 9.200 20.500
Application ZPOP –– 9.000 15.500 9.000 15.500 9.000 15.500 9.000 15.500 5
instruction n2 = 1 4.000 8.400 3.700 8.000 3.700 8.000 3.700 8.000
UNIRD n1 D n2
n2 = 16 12.500 17.000 12.200 16.600 12.200 16.600 12.200 16.600
TYPERD 29.800 53.000 29.500 52.300 29.500 52.300 29.500 52.300
6
TRACE Start 46.600 48.300 43.800 44.700 43.800 44.700 43.800 44.700
TRACER –– 3.300 6.800 2.600 6.000 2.600 6.000 2.600 6.000
When standard 1 point 11.300 16.800 9.200 15.100 9.200 15.100 9.200 15.100
RAM is used 1000 points 120.700 127.100 61.000 68.600 61.000 68.600 61.000 68.600 7
RBMOV S D n
When SRAM 1 point 11.200 16.700 9.400 15.600 9.400 15.600 9.400 15.600
card is used 1000 points 180.700 187.100 165.000 172.600 165.000 172.600 165.000 172.600
SP.FWRITE –– 6.700 11.100 6.000 10.400 6.000 10.400 6.000 10.400 8
SP.FREAD –– 5.900 11.000 5.400 10.500 5.400 10.500 5.400 10.500
SP.DEVST –– 4.500 36.500 4.000 34.500 4.000 34.500 4.000 34.500
S.DEVLD –– 11.000 17.800 10.000 17.000 10.000 17.000 10.000 17.000

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME

839
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU
Min. Max. Min. Max. Min. Max. Min. Max.
When mounting CC-Link
19.600 26.500 19.300 26.000 19.300 26.000 19.300 26.000
module (Master station side)
When mounting CC-Link
19.600 26.500 19.100 26.200 19.100 26.200 19.100 26.200
module (Local station side)
• When selecting
MELSECNET/H refresh
only (control station side)
• When selecting CC-Link 53.500 73.500 53.000 72.700 53.000 72.700 53.000 72.700
IE Controller Network
refresh only (control
station side)
• When selecting
S.ZCOM
MELSECNET/H refresh
only (normal station side)
• When selecting CC-Link 29.800 61.100 29.800 60.800 29.800 60.800 29.800 60.800
IE Controller Network
refresh only (normal
station side)
When selecting CC-Link IE
Field Network refresh only 31.500 60.000 31.000 58.000 31.000 58.000 31.000 58.000
(master station side)
When selecting CC-Link IE
Field Network refresh only 31.500 60.000 31.000 58.000 31.000 58.000 31.000 58.000
(local station side)
Data link S.RTREAD –– 8.200 20.500 7.400 19.000 7.400 19.000 7.400 19.000
instruction S.RTWRITE –– 8.700 21.500 8.300 19.800 8.300 19.800 8.300 19.800
When the refresh device as
the write target exists at 85.300 99.400 84.800 97.500 84.800 97.500 84.800 97.500
Transfer 1
S.REFDVWRB
When the refresh device as
the write target exists at 515.700 528.500 501.600 518.200 501.600 518.200 501.600 518.200
Transfer 256
When the refresh device as
the write target exists at 85.000 99.300 84.600 97.400 84.600 97.400 84.600 97.400
Transfer 1
S.REFDVWRW
When the refresh device as
the write target exists at 527.000 539.500 517.300 529.000 517.300 529.000 517.300 529.000
Transfer 256
When the refresh device as
the read target exists at 83.100 99.100 82.000 97.200 82.000 97.200 82.000 97.200
Transfer 1
S.REFDVRDB
When the refresh device as
the read target exists at 514.600 527.700 499.800 517.400 499.800 517.400 499.800 517.400
Transfer 256
When the refresh device as
the read target exists at 83.100 99.100 82.000 97.200 82.000 97.200 82.000 97.200
Transfer 1
S.REFDVRDW
When the refresh device as
the read target exists at 526.100 539.400 517.400 528.900 517.400 528.900 517.400 528.900
Transfer 256

840
 Processing Time (µs)
Q03 Q04/Q06 Q10/Q13/Q20/ Q50/Q100
Category Instruction Condition (Device)
UD(E)CPU UD(E)HCPU Q26UD(E)HCPU UDEHCPU 3
Min. Max. Min. Max. Min. Max. Min. Max.
Writing to host n4 = 1 34.700 34.900 33.500 34.400 33.500 34.400 33.500 34.400
S.TO
CPU shared
n1 n2 n3 n4 D
memory
n4 = 320 85.900 87.600 75.200 75.500 75.200 75.500 75.200 75.500 2
Writing to host n3 = 1 4.700 23.800 5.200 23.300 5.200 23.300 5.200 23.300
TO
CPU shared
n1 n2 n3 n3 = 320 57.500 76.200 47.100 64.500 47.100 64.500 47.100 64.500
3
S
memory
Writing to host n3 = 1 5.300 23.800 5.800 23.300 5.800 23.300 5.800 23.300
DTO
CPU shared
n1 n2 S n3 n3 = 320 111.300 128.400 91.500 108.500 91.500 108.500 91.500 108.500
memory
Multiple
Reading from n3 = 1 5.000 23.800 4.300 23.300 4.300 23.300 4.300 23.300 A
CPU
host CPU
dedicated n3 = 320 51.400 65.600 44.400 60.700 44.400 60.700 44.400 60.700
FROM shared memory
instruction
n1 n2 D n3 Reading from n3 = 1 11.600 17.700 10.600 13.900 10.600 13.900 10.600 13.900 5
other CPU n3 = 320 142.000 160.000 142.000 149.000 142.000 149.000 142.000 149.000
shared memory n3 = 1000 431.000 463.000 422.000 448.000 422.000 448.000 422.000 448.000
Reading from n3 = 1
6
5.200 23.800 5.600 23.300 5.600 23.300 5.600 23.300
host CPU
n3 = 320 96.400 113.200 83.600 100.800 83.600 100.800 83.600 100.800
DFRO shared memory
n1 n2 D n3 Reading from n3 = 1 12.900 20.800 12.200 17.100 12.200 17.100 12.200 17.100
other CPU n3 = 320 277.000 299.000 274.000 291.000 274.000 291.000 274.000 291.000 7
shared memory n3 = 1000 838.000 860.000 835.000 857.000 835.000 857.000 835.000 857.000
n=1 34.700 34.900 33.500 34.400 33.500 34.400 33.500 34.400
D.DDWR
n S1 S2 D1 D2
Writes devices
n=16
n=96
85.900
5.600
87.600
10.200
75.200
3.300
75.500
9.900
75.200
3.300
75.500
9.900
75.200
3.300
75.500
9.900
8
Multiple to another CPU. n=1 36.700 42.400 34.300 39.200 34.300 39.200 34.300 39.200
DP.DDWR
CPU n=16 5.000 12.100 3.100 10.500 3.100 10.500 3.100 10.500
n S1 S2 D1 D2
high-speed n=96 59.100 66.800 55.300 65.100 55.300 65.100 55.300 65.100
transmission n=1 3.300 12.700 2.400 9.600 2.400 9.600 2.400 9.600
D.DDRD

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
dedicated n=16 50.900 64.400 45.200 48.200 45.200 48.200 45.200 48.200
n S1 S2 D1 D2 Reads devices
instruction n=96 11.600 17.700 10.600 13.900 10.600 13.900 10.600 13.900
from another
n=1 142.000 160.000 142.000 149.000 142.000 149.000 142.000 149.000
DP.DDRD CPU.
n=16 431.000 463.000 422.000 448.000 422.000 448.000 422.000 448.000
n S1 S2 D1 D2
n=96 6.700 12.600 2.800 9.900 2.800 9.900 2.800 9.900

Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
execution instruction.
Example WORDP instruction, TOP instruction etc.

841
 (c) When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU and, Q26UDVCPU
Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
ANB
ORB
MPS –– 0.0019 0.0078 0.0019 0.0078 0.0019 0.0078
MRD
MPP
When not executed 0.0019 0.0078 0.0019 0.0078 0.0019 0.0078
INV
When executed 0.0019 0.0078 0.0019 0.0078 0.0019 0.0078
MEP When not executed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
MEF When executed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
EGP When not executed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
EGF When executed 0.0039 0.0078 0.0039 0.0078 0.0039 0.0078
PLS –– 0.0078 0.015 0.0078 0.015 0.0078 0.015
Sequence PLF –– 0.0078 0.015 0.0078 0.015 0.0078 0.015
instruction When not executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
FF
When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
When not executed 0.012 0.012 0.012
DELTA
When executed 1.600 5.600 1.600 5.600 1.600 5.600
When not executed 0.012 0.012 0.012
SFT
When executed 1.100 5.000 1.100 5.000 1.100 5.000
MC –– 0.0078 0.015 0.0078 0.015 0.0078 0.015
MCR –– 0.0078 0.015 0.0078 0.015 0.0078 0.015
FEND Error check performed 60.000 60.000 60.000 60.000 60.000 60.000
END No error check performed 60.000 60.000 60.000 60.000 60.000 60.000
NOP
NOPLF –– 0.0019 0.0078 0.0019 0.0078 0.0019 0.0078
PAGE
Single In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDE=
precision In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.012 0.012 0.012
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ANDE= When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ORE= When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
Basic status
instruction Single In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDE< >
precision In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ANDE< > When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ORE< > When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status

842
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
Single In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDE>
precision In non-conductive status
When not executed
0.0098
0.0078
0.023
0.023
0.0098
0.0078
0.023
0.023
0.0098
0.0078
0.023
0.023
2
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ANDE>
precision
When
executed
In non- 3
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive A
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ORE> When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023 5
status
Single In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDE<=
precision In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023 6
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ANDE<= When
precision
executed
In non-
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
7
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
8
Single status
ORE<= When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
Basic status
instruction Single In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
LDE<
precision In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ANDE< When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ORE< When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status
Single In conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
LDE>=
precision In non-conductive status 0.0098 0.023 0.0098 0.023 0.0098 0.023
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ANDE>= When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status
When not executed 0.0078 0.023 0.0078 0.023 0.0078 0.023
In conductive
0.0098 0.023 0.0098 0.023 0.0098 0.023
Single status
ORE>= When
precision In non-
executed
conductive 0.0098 0.023 0.0098 0.023 0.0098 0.023
status

843
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
Double In conductive status 1.800 6.900 1.800 6.900 1.800 6.900
LDED=
precision In non-conductive status 1.800 7.100 1.800 7.100 1.800 7.100
When not executed 0.018 0.018 0.018
In conductive
1.700 6.600 1.700 6.600 1.700 6.600
Double status
ANDED= When
precision In non-
executed
conductive 1.700 6.600 1.700 6.600 1.700 6.600
status
When not executed 0.018 0.018 0.018
In conductive
1.700 7.100 1.700 7.100 1.700 7.100
Double status
ORED= When
precision In non-
executed
conductive 1.800 7.100 1.800 7.100 1.800 7.100
status
Double In conductive status 1.800 7.100 1.800 7.100 1.800 7.100
LDED< >
precision In non-conductive status 1.800 6.900 1.800 6.900 1.800 6.900
When not executed 0.018 0.018 0.018
In conductive
1.700 6.200 1.700 6.200 1.700 6.200
Double status
ANDED< > When
precision In non-
executed
conductive 1.700 6.600 1.700 6.600 1.700 6.600
status
When not executed 0.018 0.018 0.018
In conductive
1.800 6.500 1.800 6.500 1.800 6.500
Double status
ORED< > When
precision In non-
executed
conductive 1.800 6.700 1.800 6.700 1.800 6.700
Basic status
instruction Double In conductive status 1.800 7.300 1.800 7.300 1.800 7.300
LDED>
precision In non-conductive status 1.800 7.200 1.800 7.200 1.800 7.200
When not executed 0.018 0.018 0.018
In conductive
1.700 6.700 1.700 6.700 1.700 6.700
Double status
ANDED> When
precision In non-
executed
conductive 1.700 6.800 1.700 6.800 1.700 6.800
status
When not executed 0.018 0.018 0.018
In conductive
1.700 6.700 1.700 6.700 1.700 6.700
Double status
ORED> When
precision In non-
executed
conductive 1.800 7.200 1.800 7.200 1.800 7.200
status
Double In conductive status 1.800 7.100 1.800 7.100 1.800 7.100
LDED<=
precision In non-conductive status 1.700 7.100 1.700 7.100 1.700 7.100
When not executed 0.018 0.018 0.018
In conductive
1.700 6.700 1.700 6.700 1.700 6.700
Double status
ANDED<= When
precision In non-
executed
conductive 1.800 6.500 1.800 6.500 1.800 6.500
status
When not executed 0.018 0.018 0.018
In conductive
1.700 6.700 1.700 6.700 1.700 6.700
Double status
ORED<= When
precision In non-
executed
conductive 1.800 6.500 1.800 6.500 1.800 6.500
status

844
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
Double In conductive status 1.800 7.100 1.800 7.100 1.800 7.100
LDED<
precision In non-conductive status
When not executed
1.800 7.100
0.018
1.800 7.100
0.018
1.800 7.100
0.018
2
In conductive
1.700 6.700 1.700 6.700 1.700 6.700
Double status
ANDED<
precision
When
executed
In non- 3
conductive 1.700 6.400 1.700 6.400 1.700 6.400
status
When not executed 0.018 0.018 0.018
In conductive A
1.700 7.100 1.700 7.100 1.700 7.100
Double status
ORED< When
precision In non-
executed
conductive 1.700 7.100 1.700 7.100 1.700 7.100 5
status
Double In conductive status 1.800 7.100 1.800 7.100 1.800 7.100
LDED>=
precision In non-conductive status 1.800 7.100 1.800 7.100 1.800 7.100
When not executed 0.018 0.018 0.018 6
In conductive
1.700 6.400 1.700 6.400 1.700 6.400
Double status
ANDED>= When
precision
executed
In non-
conductive 1.700 6.400 1.700 6.400 1.700 6.400
7
status
When not executed 0.018 0.018 0.018
In conductive
1.700 7.100 1.700 7.100 1.700 7.100
8
Double status
ORED>= When
precision In non-
executed
conductive 1.700 7.100 1.700 7.100 1.700 7.100
Basic status
instruction In conductive status 1.400 3.800 1.400 3.800 1.400 3.800

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
LD$=
In non-conductive status 1.400 3.800 1.300 3.800 1.300 3.800
When not executed 0.018 0.018 0.018
In conductive
1.300 3.700 1.300 3.800 1.300 3.800
status
AND$=
When executed In non-
conductive 1.400 3.900 1.400 3.900 1.400 3.900
status
When not executed 0.018 0.018 0.018
In conductive
1.300 3.900 1.400 3.900 1.400 3.900
status
OR$=
When executed In non-
conductive 1.300 3.800 1.300 3.800 1.300 3.800
status
In conductive status 1.400 3.800 1.400 3.800 1.400 3.800
LD$< >
In non-conductive status 1.400 3.800 1.400 3.800 1.400 3.800
When not executed 0.018 0.018 0.018
In conductive
1.300 3.700 1.300 3.700 1.300 3.700
status
AND$< >
When executed In non-
conductive 1.400 3.900 1.400 3.900 1.400 3.900
status
When not executed 0.018 0.018 0.018
In conductive
1.300 3.900 1.300 3.900 1.300 3.900
status
OR$< >
When executed In non-
conductive 1.300 3.800 1.300 3.800 1.300 3.800
status

845
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
In conductive status 1.400 3.800 1.400 3.800 1.400 3.800
LD$>
In non-conductive status 1.300 3.800 1.300 3.800 1.300 3.800
When not executed 0.018 0.018 0.018
In conductive
1.300 3.800 1.300 3.800 1.300 3.800
status
AND$>
When executed In non-
conductive 1.300 3.900 1.300 3.900 1.300 3.900
status
When not executed 0.018 0.018 0.018
In conductive
1.300 3.900 1.300 3.900 1.300 3.900
status
OR$>
When executed In non-
conductive 1.300 3.700 1.300 3.700 1.300 3.700
status
In conductive status 1.400 3.900 1.400 3.900 1.400 3.900
LD$<=
In non-conductive status 1.400 3.800 1.400 3.800 1.400 3.800
When not executed 0.018 0.018 0.018
In conductive
1.300 3.800 1.300 3.800 1.300 3.800
status
AND$<=
When executed In non-
conductive 1.400 3.900 1.400 3.900 1.400 3.900
status
When not executed 0.018 0.018 0.018
In conductive
1.400 3.900 1.400 3.900 1.400 3.900
status
OR$<=
When executed In non-
conductive 1.300 3.700 1.300 3.700 1.300 3.700
Basic status
instruction In conductive status 1.400 3.900 1.400 3.900 1.400 3.900
LD$<
In non-conductive status 1.400 3.800 1.400 3.800 1.400 3.800
When not executed 0.018 0.018 0.018
In conductive
1.300 3.700 1.300 3.700 1.300 3.700
status
AND$<
When executed In non-
conductive 1.400 3.900 1.400 3.900 1.400 3.900
status
When not executed 0.018 0.018 0.018
In conductive
1.300 3.900 1.300 3.900 1.300 3.900
status
OR$<
When executed In non-
conductive 1.300 3.800 1.300 3.800 1.300 3.800
status
In conductive status 1.400 3.800 1.400 3.800 1.400 3.800
LD$>=
In non-conductive status 1.300 3.800 1.300 3.800 1.300 3.800
When not executed 0.018 0.018 0.018
In conductive
1.300 3.700 1.300 3.700 1.300 3.700
status
AND$>=
When executed In non-
conductive 1.300 3.900 1.300 3.900 1.300 3.900
status
When not executed 0.018 0.018 0.018
In conductive
1.300 3.800 1.300 3.800 1.300 3.800
status
OR$>=
When executed In non-
conductive 1.300 3.800 1.300 3.800 1.300 3.800
status

846
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
BKCMP = n=1 3.200 20.600 3.200 20.600 3.200 20.600
S1 S2 D n n=96 16.800 34.000 16.800 34.000 16.800 34.000 2
BKCMP<> n=1 3.200 20.600 3.200 20.600 3.200 20.600
S1 S2 D n n=96 16.800 34.000 16.800 34.000 16.800 34.000
BKCMP> n=1 3.200 20.800 3.200 20.800 3.200 20.800
3
S1 S2 D n n=96 16.700 34.400 16.700 34.400 16.700 34.400
BKCMP<= n=1 3.200 21.000 3.200 21.000 3.200 21.000
n=96 16.600 34.300 16.600 34.300 16.600 34.300
S1 S2 D

BKCMP<
n
n=1 3.200 21.000 3.200 21.000 3.200 21.000
A
S1 S2 D n n=96 16.800 34.400 16.800 34.400 16.800 34.400
BKCMP>= n=1 3.200 20.600 3.200 20.600 3.200 20.600
S1 S2 D n n=96 16.800 34.000 16.800 34.000 16.800 34.000
5
DBKCMP = n=1 3.500 22.200 3.500 22.200 3.500 22.200
S1 S2 D n n=96 17.100 35.700 17.100 35.700 17.100 35.700
DBKCMP<> n=1 3.500 22.700 3.500 22.700 3.500 22.700 6
S1 S2 D n n=96 17.000 36.300 17.000 36.300 17.000 36.300
DBKCMP> n=1 3.500 22.700 3.500 22.700 3.500 22.700
S1 S2 D n n=96 17.100 36.300 17.100 36.300 17.100 36.300 7
DBKCMP<= n=1 3.500 22.600 3.500 22.600 3.500 22.600
S1 S2 D n n=96 17.000 36.000 17.000 36.000 17.000 36.000
DBKCMP< n=1 3.500 22.700 3.500 22.700 3.500 22.700 8
S1 S2 D n n=96 17.100 36.500 17.100 36.500 17.100 36.500
DBKCMP>= n=1 3.500 22.700 3.500 22.700 3.500 22.700
S1 S2 D n n=96 16.900 36.000 16.900 36.000 16.900 36.000
Basic
instruction DB + S D When executed 2.000 8.400 2.000 8.400 2.000 8.400

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
DB + S1 S2 D When executed 2.200 8.400 2.200 8.400 2.200 8.400
DB - S D When executed 2.000 8.200 2.000 8.200 2.000 8.200
DB - S1 S2 D When executed 2.200 8.600 2.200 8.600 2.200 8.600
DB * S1 S2 D When executed 2.700 12.200 2.700 12.200 2.700 12.200
DB/ S1 S2 D When executed 2.500 11.100 2.500 11.100 2.500 11.100
ED + Double S = 0, D =0 1.700 6.800 1.700 6.800 1.700 6.800
S D precision S =2 1023
, D =2 1023 2.000 9.300 2.000 9.300 2.000 9.300
ED + Double S1 = 0, S2 =0 1.900 8.400 1.900 8.400 1.900 8.400
S1 S2 D precision S1 = 21023, S2 =2 1023 2.100 10.500 2.100 10.500 2.100 10.500
ED - Double S = 0, D =0 1.700 8.000 1.700 8.000 1.700 8.000
S D precision S = 21023, D = 21023 1.800 8.100 1.800 8.100 1.800 8.100
ED - Double S1 = 0, S2 =0 1.900 8.100 1.900 8.100 1.900 8.100
S1 S2 D precision S1 = 21023, S2 =2 1023 1.900 8.400 1.900 8.400 1.900 8.400
ED * Double S1 = 0, S2 =0 1.900 8.700 1.900 8.700 1.900 8.700
S1 S2 D precision S1 = 21023, S2 = 21023 2.200 10.800 2.200 10.800 2.200 10.800
Double
ED / S1 S2 D S1 = 21023, S2 = 21023 2.200 10.800 2.200 10.800 2.200 10.800
precision
BK + n=1 2.900 14.500 2.900 14.500 2.900 14.500
S1 S2 D n n=96 17.000 28.700 17.000 28.700 17.000 28.700
BK - n=1 2.800 14.200 2.800 14.200 2.800 14.200
S1 S2 D n n=96 17.000 28.400 17.000 28.400 17.000 28.400
DBK + n=1 3.000 16.300 3.000 16.300 3.000 16.300
S1 S2 D n n=96 17.100 30.500 17.100 30.500 17.100 30.500

847
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
DBK - n=1 3.000 16.300 3.000 16.300 3.000 16.300
S1 S2 D n n=96 17.100 30.500 17.100 30.500 17.100 30.500

$+ S D –– 1.900 6.200 1.900 6.200 1.900 6.200

$+ S1 S2 D –– 2.300 7.800 2.300 7.800 2.300 7.800

Double S =0 1.400 4.500 1.400 4.500 1.400 4.500

FLTD
precision S = 7FFFH 1.400 4.400 1.400 4.400 1.400 4.400

Double S =0 1.400 4.300 1.400 4.300 1.400 4.300

DFLTD
precision S = 7FFFFFFFH 1.400 4.500 1.400 4.500 1.400 4.500

Double S =0 1.400 5.300 1.400 5.300 1.400 5.300

INTD
precision S = 32766.5 1.400 6.700 1.400 6.700 1.400 6.700
Double S =0 1.400 5.300 1.400 5.300 1.400 5.300
DINTD
precision S = 1234567890.3 1.500 6.500 1.500 6.500 1.500 6.500
DBL When executed 0.0039 0.015 0.0039 0.015 0.0039 0.015
WORD When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
GRY When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
DGRY When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
GBIN When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
DGBIN When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
NEG When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
DNEG When executed 0.0078 0.015 0.0078 0.015 0.0078 0.015
Floating point = 0 1.200 2.800 1.200 2.800 1.200 2.800
ENEG
Floating point = -1.0 1.300 3.300 1.300 3.300 1.300 3.300
Floating point = 0 1.300 5.500 1.300 5.500 1.300 5.500
EDNEG
Floating point = -1.0 1.300 6.200 1.300 6.200 1.300 6.200
BKBCD S D n=1 2.200 12.800 2.200 12.800 2.200 12.800
Basic n n=96 23.400 34.100 23.400 34.100 23.400 34.100
instruction n=1 2.100 11.700 2.100 11.700 2.100 11.700
BKBIN S D n
n=96 16.600 26.200 16.600 26.200 16.600 26.200
ECON –– 1.500 6.300 1.500 6.300 1.500 6.300
EDCON –– 1.600 5.300 1.600 5.300 1.600 5.300
EDMOV –– 0.0078 0.015 0.0078 0.015 0.0078 0.015
Character string to be transferred = 0 1.800 13.500 1.800 13.500 1.800 13.500
$MOV
Character string to be transferred = 32 3.900 15.400 3.900 15.400 3.900 15.400
n=1 2.100 10.300 2.100 10.300 2.100 10.300
BXCH D1 D2 n
n=96 16.200 24.400 16.200 24.400 16.200 24.400
SWAP –– 1.200 2.200 1.200 2.200 1.200 2.200
GOEND –– 0.580 2.100 0.580 2.100 0.580 2.100
DI –– 2.200 3.400 2.200 3.400 2.200 3.400
EI –– 3.100 6.400 3.100 6.400 3.100 6.400
IMASK –– 4.100 8.000 4.100 8.000 4.100 8.000
IRET –– 1.000 2.900 1.000 2.900 1.000 2.900
n=1 2.200 10.100 2.200 10.100 2.200 10.100
RFS X n
n=96 3.600 12.200 3.600 12.200 3.600 12.200
n=1 2.100 10.800 2.100 10.800 2.100 10.800
RFS Y n
n=96 3.600 13.200 3.600 13.200 3.600 13.200
UDCNT1 –– 1.000 1.700 1.000 1.700 1.000 1.700
UDCNT2 –– 1.000 2.000 1.000 2.000 1.000 2.000
TTMR –– 1.800 8.000 1.800 8.000 1.800 8.000
STMR –– 2.800 11.300 2.800 11.300 2.800 11.300
ROTC –– 5.400 9.700 5.400 9.700 5.400 9.700
RAMP –– 3.100 12.000 3.100 12.000 3.100 12.000
SPD –– 1.000 1.800 1.000 1.800 1.000 1.800
PLSY –– 1.100 2.100 1.100 2.100 1.100 2.100
PWM –– 1.100 1.600 1.100 1.600 1.100 1.600
MTR –– 3.000 14.500 3.000 14.500 3.000 14.500

848
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
BKAND S1 S2 n=1 2.800 14.700 2.800 14.700 2.800 14.700

D n n=96 17.000 28.800 17.000 28.800 17.000 28.800 2

BKOR S1 S2 n=1 2.900 14.300 2.900 14.300 2.900 14.300

D n n=96 17.000 28.400 17.000 28.400 17.000 28.400

BKXOR S1 S2 n=1 2.800 14.600 2.800 14.600 2.800 14.600 3

D n n=96 17.000 28.700 17.000 28.700 17.000 28.700

BKXNR n=1 2.900 14.600 2.900 14.600 2.900 14.600

A
S1 S2

D n n=96 17.400 29.100 17.400 29.100 17.400 29.100

n=1 1.700 5.300 1.700 5.300 1.700 5.300
BSFR D n
n=96 2.300 9.600 2.300 9.600 2.300 9.600

BSFL D n
n=1 1.700 5.300 1.700 5.300 1.700 5.300 5
n=96 2.300 9.300 2.300 9.300 2.300 9.300
SFTBR D n1 n1 = 16 / n2 = 1 3.300 16.200 3.300 16.200 3.300 16.200
n2 n1 = 16 / n2 = 15 3.300 16.100 3.300 16.100 3.300 16.100
6
SFTBL D n1 n1 = 16 / n2 = 1 3.300 16.000 3.300 16.000 3.300 16.000
n2 n1 = 16 / n2 = 15 3.300 16.000 3.300 16.000 3.300 16.000

SFTWR D n1 n1 = 16 / n2 = 1
n1 = 16 / n2 = 15
2.000
2.000
11.900
11.900
2.000
2.000
11.900
11.900
2.000
2.000
11.900
11.900
7
n2
SFTWL D n1 n1 = 16 / n2 = 1 2.000 11.900 2.000 11.900 2.000 11.900
n1 = 16 / n2 = 15 2.100 11.700 2.100 11.700 2.100 11.700
n2
n=1 0.0039 0.015 0.0039 0.015 0.0039 0.015
8
BSET D n
n=15 0.0039 0.015 0.0039 0.015 0.0039 0.015
Application n=1 0.0039 0.015 0.0039 0.015 0.0039 0.015
BRST D n
instruction n=15 0.0039 0.015 0.0039 0.015 0.0039 0.015
TEST When executed 0.012 0.031 0.012 0.031 0.012 0.031

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
DTEST When executed 0.019 0.031 0.019 0.031 0.019 0.031
n=1 1.700 9.200 1.700 9.200 1.700 9.200
BKRST D n
n=96 2.000 11.500 2.000 11.500 2.000 11.500
All match 2.700 8.000 2.700 8.000 2.700 8.000
n=1
SER S1 S2 D None match 2.700 8.000 2.700 8.000 2.700 8.000
n All match 9.600 18.100 9.600 18.100 9.600 18.100
n=96
None match 9.600 18.100 9.600 18.100 9.600 18.100
All match 2.800 10.600 2.800 10.600 2.800 10.600
n=1
DSER S1 S2 None match 2.800 10.600 2.800 10.600 2.800 10.600
D n All match 14.400 22.000 14.400 22.000 14.400 22.000
n=96
None match 14.400 21.900 14.400 21.900 14.400 21.900
S =0 1.600 2.700 1.600 2.700 1.600 2.700
DSUM S D
S = FFFFFFFFH 1.600 2.800 1.600 2.800 1.600 2.800
n=2 2.600 12.800 2.600 12.800 2.600 12.800
DECO S D n
n=8 3.000 15.400 3.000 15.400 3.000 15.400
M1 = ON 2.400 8.600 2.400 8.600 2.400 8.600
n=2
M4 = ON 2.400 8.600 2.400 8.600 2.400 8.600
ENCO S D n
M1 = ON 3.800 13.400 3.800 13.400 3.800 13.400
n=8
M256 = ON 2.600 11.400 2.600 11.400 2.600 11.400
n=1 1.900 6.500 1.900 6.500 1.900 6.500
DIS S D n
n=4 2.000 6.700 2.000 6.700 2.000 6.700
n=1 2.200 6.700 2.200 6.700 2.200 6.700
UNI S D n
n=4 2.500 7.000 2.500 7.000 2.500 7.000
NDIS When executed 3.200 12.300 3.200 12.300 3.200 12.300
NUNI When executed 3.200 12.400 3.200 12.400 3.200 12.400

849
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
n=1 2.100 7.300 2.100 7.300 2.100 7.300
WTOB S D n
n=96 12.500 17.700 12.500 17.700 12.500 17.700
n=1 2.000 7.000 2.000 7.000 2.000 7.000
BTOW S D n
n=96 9.300 14.000 9.300 14.000 9.300 14.000
n=1 2.000 6.400 2.000 6.400 2.000 6.400
MAX S D n
n=96 9.100 13.700 9.100 13.700 9.100 13.700
n=1 2.000 7.100 2.000 7.100 2.000 7.100
MIN S D n
n=96 9.100 14.200 9.100 14.200 9.100 14.200
n=1 2.200 11.000 2.200 11.000 2.200 11.000
DMAX S D n
n=96 16.900 26.000 16.900 26.000 16.900 26.000
n=1 2.300 11.000 2.300 11.000 2.300 11.000
DMIN S D n
n=96 6.900 26.000 6.900 26.000 6.900 26.000
SORT S1 n S2 n = 1, S2 =1 3.000 7.700 3.000 7.700 3.000 7.700
D1 D2 n = 96, S2 = 16 8.100 17.500 8.100 17.500 8.100 17.500

DSORT S1 n n = 1, S2 =1 3.100 8.800 3.100 8.800 3.100 8.800

S2 D1 D2 n = 96, S2 = 16 9.800 20.300 9.800 20.300 9.800 20.300

WSUM S D n=1 1.400 5.700 1.400 5.700 1.400 5.700

n n=96 6.200 10.600 6.200 10.600 6.200 10.600

DWSUM S n=1 2.300 11.400 2.300 11.400 2.300 11.400

D n n=96 8.600 18.600 8.600 18.600 8.600 18.600

n=1 2.100 6.800 2.100 6.800 2.100 6.800
MEAN S D n
n=96 3.900 10.100 3.900 10.100 3.900 10.100
Application DMEAN S D n=1 2.400 11.100 2.400 11.100 2.400 11.100
instruction n n=96 8.700 16.100 8.700 16.100 8.700 16.100
NEXT –– 0.044 0.044 0.044
BREAK –– 2.300 7.800 2.300 7.800 2.300 7.800
Return to original program 0.200 0.200 0.200 0.200 0.200 0.200
RET
Return to other program 2.000 5.700 2.000 5.700 2.000 5.700
Internal file pointer 0.800 0.800 0.800 0.800 0.800 0.800
FCALL Pn
Common pointer 4.800 21.700 4.800 21.700 4.800 21.700
FCALL Pn S1
–– 13.700 38.600 13.700 38.600 13.700 38.600
to S5
ECALL * Pn
*: Program –– 46.100 78.700 46.100 78.700 46.100 78.700
name
ECALL * Pn
S1 to S5
–– 59.000 97.700 59.000 97.700 59.000 97.700
*: Program
name
EFCALL * Pn
*: Program –– 48.500 90.200 48.500 90.200 48.500 90.200
name
EFCALL * Pn
S1 to S5
–– 65.700 108.900 65.700 108.900 65.700 108.900
*: Program
name
XCALL –– 2.500 8.800 2.500 8.800 2.500 8.800

850
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
When selecting I/O refresh only 3.100 9.900 3.100 9.900 3.100 9.900
When selecting CC-Link refresh only
(master station side)
5.900 21.400 5.900 21.400 5.900 21.400 2
When selecting CC-Link refresh only
5.900 21.400 5.900 21.400 5.900 21.400
(local station side)
• When selecting MELSECNET/H 3
refresh only (Control station side)
• When selecting CC-Link IE Controller 13.900 42.900 13.900 42.900 13.900 42.900
Network refresh only (Control station
side)
A
• When selecting MELSECNET/H
refresh only (Normal station side)
• When selecting CC-Link IE Controller 13.900 37.600 13.900 37.600 13.900 37.600 5
Network refresh only (Normal station
side)
COM
When selecting CC-Link IE Field
CCOM
Network refresh only (master station 9.800 32.200 9.800 32.200 9.800 32.200 6
side)
When selecting CC-Link IE Field
9.800 35.700 9.800 35.700 9.800 35.700
Network refresh only (local station side)
When selecting intelli auto refresh only 5.300 15.100 5.300 15.100 5.300 15.100
7
When selecting I/O outside the group
2.100 10.900 2.100 10.900 2.100 10.900
only (Input only)
When selecting I/O outside the group
7.500 30.500 7.500 30.500 7.500 30.500
8
only (Output only)
When selecting I/O outside the group
7.200 30.100 7.200 30.100 7.200 30.100
only (Both I/O)
Application When selecting refresh of multiple CPU
instruction 2.000 9.400 2.000 9.400 2.000 9.400
high speed transmission area only

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
When selecting communication with
7.100 28.200 7.100 28.200 7.100 28.200
external devices only
Number of data points = 0 1.900 6.000 1.900 6.000 1.900 6.000
FIFW
Number of data points = 96 1.900 6.000 1.900 6.000 1.900 6.000
Number of data points = 1 2.000 6.500 2.000 6.500 2.000 6.500
FIFR
Number of data points = 96 7.100 12.200 7.100 12.200 7.100 12.200
Number of data points = 1 2.100 6.200 2.100 6.200 2.100 6.200
FPOP
Number of data points = 96 2.100 6.200 2.100 6.200 2.100 6.200
Number of data points = 0 2.200 7.500 2.200 7.500 2.200 7.500
FINS
Number of data points = 96 2.200 7.500 2.200 7.500 2.200 7.500
Number of data points = 1 2.400 7.100 2.400 7.100 2.400 7.100
FDEL
Number of data points = 96 7.500 12.800 7.500 12.800 7.500 12.800
FROM n1 n2 n3 = 1 5.900 21.400 5.900 21.400 5.900 21.400
D n3 n3 = 1000 366.700 383.200 366.700 383.200 366.700 383.200
DFRO n1 n2 n3 = 1 6.500 22.900 6.500 22.900 6.500 22.900
D n3 n3 = 500 366.700 405.100 366.700 405.100 366.700 405.100
TO n1 n2 n3 = 1 5.100 19.100 5.100 19.100 5.100 19.100
S n3 n3 = 1000 355.700 370.400 355.700 370.400 355.700 370.400
DTO n1 n2 n3 = 1 6.900 21.700 6.900 21.700 6.900 21.700
S n3 n3 = 500 355.700 370.200 355.700 370.200 355.700 370.200
No display no display 0.900 3.000 0.900 3.000 0.900 3.000
LEDR LED instruction execution
8.700 26.600 8.700 26.600 8.700 26.600
no display
BINDA S =1 1.900 7.600 1.900 7.600 1.900 7.600
S D S = -32768 2.200 7.800 2.200 7.800 2.200 7.800

851
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
DBINDA S =1 1.900 7.600 1.900 7.600 1.900 7.600
S D S = -2147483648 2.300 8.000 2.300 8.000 2.300 8.000
S =1 1.800 7.200 1.800 7.200 1.800 7.200
BINHA S D
S = FFFFH 1.800 7.300 1.800 7.300 1.800 7.300
S =1 1.800 7.100 1.800 7.100 1.800 7.100
DBINHA S D
S = FFFFFFFFH 1.800 6.800 1.800 6.800 1.800 6.800
S =1 1.800 7.600 1.800 7.600 1.800 7.600
BCDDA S D
S = 9999 1.800 7.700 1.800 7.700 1.800 7.700

DBCDDA S S =1 1.700 7.200 1.700 7.200 1.700 7.200

D S = 99999999 1.900 7.400 1.900 7.400 1.900 7.400
S =1 1.900 9.800 1.900 9.800 1.900 9.800
DABIN S D
S = -32768 1.900 9.800 1.900 9.800 1.900 9.800
S =1 2.400 12.300 2.400 12.300 2.400 12.300
DDABIN S D
S = -2147483648 2.400 12.400 2.400 12.400 2.400 12.400
S =1 1.900 10.000 1.900 10.000 1.900 10.000
HABIN S D
S = FFFFH 1.900 10.100 1.900 10.100 1.900 10.100
S =1 2.100 9.900 2.100 9.900 2.100 9.900
DHABIN S D
S = FFFFFFFFH 2.200 9.800 2.200 9.800 2.200 9.800
S =1 1.800 9.100 1.800 9.100 1.800 9.100
DABCD S D
S = 9999 1.800 9.100 1.800 9.100 1.800 9.100

DDABCD S S =1 2.100 10.100 2.100 10.100 2.100 10.100

D S = 99999999 2.100 10.100 2.100 10.100 2.100 10.100
Application
instruction COMRD –– 23.000 31.300 23.000 31.300 23.000 31.300
1 character 1.200 3.400 1.200 3.400 1.200 3.400
LEN
96 characters 8.900 11.100 8.900 11.100 8.900 11.100
STR –– 2.600 11.600 2.600 11.600 2.600 11.600
DSTR –– 2.900 11.600 2.900 11.600 2.900 11.600
VAL –– 3.700 14.100 3.700 14.100 3.700 14.100
DVAL –– 4.400 160.000 4.400 160.000 4.400 160.000
ESTR –– 4.200 23.700 4.200 23.700 4.200 23.700
In conductive
2.600 14.700 2.600 14.700 2.600 14.700
status
Comparison of
In non-
specified date
conductive 2.600 14.300 2.600 14.300 2.600 14.300
status
LDTM=
In conductive
4.900 21.600 4.900 21.600 4.900 21.600
status
Comparison of current
In non-
date
conductive 4.800 22.500 4.800 22.500 4.800 22.500
status
When not executed 0.018 0.018 0.018
In conductive
2.500 14.400 2.500 14.400 2.500 14.400
status
Comparison of
In non-
specified date
conductive 2.600 14.100 2.600 14.100 2.600 14.100
ANDTM= status
In conductive
4.700 21.600 4.700 21.600 4.700 21.600
status
Comparison of current
In non-
date
conductive 4.800 22.200 4.800 22.200 4.800 22.200
status

852
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
When not executed 0.018 0.018 0.018
In conductive
status
2.600 14.800 2.600 14.800 2.600 14.800 2
Comparison of
In non-
specified date
conductive 2.600 14.300 2.600 14.300 2.600 14.300
ORTM= status 3
In conductive
4.900 21.900 4.900 21.900 4.900 21.900
status
Comparison of current
In non-
date
conductive 4.700 22.000 4.700 22.000 4.700 22.000
A
status
In conductive
2.600 14.400 2.600 14.400 2.600 14.400
Comparison of
status 5
In non-
specified date
conductive 2.600 14.700 2.600 14.700 2.600 14.700
status
LDTM<>
In conductive
4.800 22.300 4.800 22.300 4.800 22.300
6
status
Comparison of current
In non-
date
conductive
status
4.800 21.800 4.800 21.800 4.800 21.800
7
When not executed 0.018 0.018 0.018
In conductive

Comparison of
status
2.600 14.200 2.600 14.200 2.600 14.200
8
In non-
specified date
conductive 2.600 14.600 2.600 14.600 2.600 14.600
Application
ANDTM<> status
instruction
In conductive
4.600 22.200 4.600 22.200 4.600 22.200
status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Comparison of current
In non-
date
conductive 4.800 21.600 4.800 21.600 4.800 21.600
status
When not executed 0.018 0.018 0.018
In conductive
2.600 15.000 2.600 15.000 2.600 15.000
status
Comparison of
In non-
specified date
conductive 2.600 14.900 2.600 14.900 2.600 14.900
ORTM<> status
In conductive
4.800 22.300 4.800 22.300 4.800 22.300
status
Comparison of current
In non-
date
conductive 4.700 21.500 4.700 21.500 4.700 21.500
status
In conductive
2.600 14.300 2.600 14.300 2.600 14.300
status
Comparison of
In non-
specified date
conductive 2.600 14.300 2.600 14.300 2.600 14.300
status
LDTM>
In conductive
4.800 22.400 4.800 22.400 4.800 22.400
status
Comparison of current
In non-
date
conductive 4.800 21.700 4.800 21.700 4.800 21.700
status

853
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
When not executed 0.018 0.018 0.018
In conductive
2.500 14.500 2.500 14.500 2.500 14.500
status
Comparison of
In non-
specified date
conductive 2.600 14.900 2.600 14.900 2.600 14.900
ANDTM> status
In conductive
4.600 22.000 4.600 22.000 4.600 22.000
status
Comparison of current
In non-
date
conductive 4.800 21.800 4.800 21.800 4.800 21.800
status
When not executed 0.018 0.018 0.018
In conductive
2.600 14.400 2.600 14.400 2.600 14.400
status
Comparison of
In non-
specified date
conductive 2.500 14.400 2.500 14.400 2.500 14.400
ORTM> status
In conductive
4.800 22.700 4.800 22.700 4.800 22.700
status
Comparison of current
In non-
date
conductive 4.700 21.800 4.700 21.800 4.700 21.800
status
In conductive
2.600 14.400 2.600 14.400 2.600 14.400
status
Comparison of
In non-
specified date
conductive 2.600 14.400 2.600 14.400 2.600 14.400
Application status
LDTM<=
instruction In conductive
4.800 22.200 4.800 22.200 4.800 22.200
status
Comparison of current
In non-
date
conductive 4.800 22.100 4.800 22.100 4.800 22.100
status
When not executed 0.018 0.018 0.018
In conductive
2.600 14.400 2.600 14.400 2.600 14.400
status
Comparison of
In non-
specified date
conductive 2.600 14.500 2.600 14.500 2.600 14.500
ANDTM<= status
In conductive
4.600 21.800 4.600 21.800 4.600 21.800
status
Comparison of current
In non-
date
conductive 4.700 22.400 4.700 22.400 4.700 22.400
status
When not executed 0.018 0.018 0.018
In conductive
2.600 14.800 2.600 14.800 2.600 14.800
status
Comparison of
In non-
specified date
conductive 2.500 14.600 2.500 14.600 2.500 14.600
ORTM<= status
In conductive
4.800 22.700 4.800 22.700 4.800 22.700
status
Comparison of current
In non-
date
conductive 4.700 22.400 4.700 22.400 4.700 22.400
status

854
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
In conductive
2.600 14.500 2.600 14.500 2.600 14.500
Comparison of
status
In non-
2
specified date
conductive 2.600 14.500 2.600 14.500 2.600 14.500
status
LDTM<
In conductive
4.800 21.900 4.800 21.900 4.800 21.900
3
status
Comparison of current
In non-
date
conductive 4.800 22.200 4.800 22.200 4.800 22.200
status
A
When not executed 0.018 0.018 0.018
In conductive
2.500 14.500 2.500 14.500 2.500 14.500
Comparison of
status 5
In non-
specified date
conductive 2.600 14.600 2.600 14.600 2.600 14.600
ANDTM< status
In conductive
4.600 21.900 4.600 21.900 4.600 21.900
6
status
Comparison of current
In non-
date
conductive
status
4.700 22.200 4.700 22.200 4.700 22.200
7
When not executed 0.018 0.018 0.018
In conductive

Comparison of
status
2.600 14.800 2.600 14.800 2.600 14.800
8
In non-
specified date
conductive 2.500 14.500 2.500 14.500 2.500 14.500
Application
ORTM< status
instruction
In conductive
4.800 22.400 4.800 22.400 4.800 22.400
status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Comparison of current
In non-
date
conductive 4.700 22.200 4.700 22.200 4.700 22.200
status
In conductive
2.600 14.500 2.600 14.500 2.600 14.500
status
Comparison of
In non-
specified date
conductive 2.600 14.400 2.600 14.400 2.600 14.400
status
LDTM>=
In conductive
4.800 22.300 4.800 22.300 4.800 22.300
status
Comparison of current
In non-
date
conductive 4.800 22.200 4.800 22.200 4.800 22.200
status
When not executed 0.018 0.018 0.018
In conductive
2.600 14.500 2.600 14.500 2.600 14.500
status
Comparison of
In non-
specified date
conductive 2.600 14.600 2.600 14.600 2.600 14.600
ANDTM>= status
In conductive
4.600 22.000 4.600 22.000 4.600 22.000
status
Comparison of current
In non-
date
conductive 4.700 21.900 4.700 21.900 4.700 21.900
status

855
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
When not executed 0.018 0.018 0.018
In conductive
2.600 14.800 2.600 14.800 2.600 14.800
status
Comparison of
In non-
specified date
conductive 2.500 14.500 2.500 14.500 2.500 14.500
ORTM>= status
In conductive
4.800 22.600 4.800 22.600 4.800 22.600
status
Comparison of current
In non-
date
conductive 4.700 22.100 4.700 22.100 4.700 22.100
status
In conductive
2.700 14.900 2.700 14.900 2.700 14.900
status
Comparison of
In non-
specified date
conductive 2.600 14.500 2.600 14.500 2.600 14.500
status
LDDT=
In conductive
4.800 22.600 4.800 22.600 4.800 22.600
status
Comparison of current
In non-
date
conductive 4.800 22.200 4.800 22.200 4.800 22.200
status
When not executed 0.018 0.018 0.018
In conductive
2.500 14.700 2.500 14.700 2.500 14.700
status
Comparison of
In non-
specified date
conductive 2.500 15.200 2.500 15.200 2.500 15.200
Application
ANDDT= status
instruction
In conductive
4.600 22.400 4.600 22.400 4.600 22.400
status
Comparison of current
In non-
date
conductive 4.700 22.600 4.700 22.600 4.700 22.600
status
When not executed 0.018 0.018 0.018
In conductive
2.600 15.700 2.600 15.700 2.600 15.700
status
Comparison of
In non-
specified date
conductive 2.600 15.000 2.600 15.000 2.600 15.000
ORDT= status
In conductive
4.700 23.300 4.700 23.300 4.700 23.300
status
Comparison of current
In non-
date
conductive 4.700 22.500 4.700 22.500 4.700 22.500
status
In conductive
2.700 14.700 2.700 14.700 2.700 14.700
status
Comparison of
In non-
specified date
conductive 2.700 14.900 2.700 14.900 2.700 14.900
status
LDDT<>
In conductive
4.800 22.600 4.800 22.600 4.800 22.600
status
Comparison of current
In non-
date
conductive 4.800 22.800 4.800 22.800 4.800 22.800
status

856
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
When not executed 0.018 0.018 0.018
In conductive
status
2.600 15.100 2.600 15.100 2.600 15.100 2
Comparison of
In non-
specified date
conductive 2.700 15.400 2.700 15.400 2.700 15.400
ANDDT<> status 3
In conductive
4.600 22.100 4.600 22.100 4.600 22.100
status
Comparison of current
In non-
date
conductive 4.700 22.500 4.700 22.500 4.700 22.500
A
status
When not executed 0.018 0.018 0.018
In conductive
2.700 15.100 2.700 15.100 2.700 15.100 5
status
Comparison of
In non-
specified date
conductive 2.600 15.100 2.600 15.100 2.600 15.100
ORDT<> status 6
In conductive
4.800 22.600 4.800 22.600 4.800 22.600
status
Comparison of current
date
In non-
conductive 4.700 22.800 4.700 22.800 4.700 22.800
7
status
In conductive

Comparison of
status
2.700 14.700 2.700 14.700 2.700 14.700
8
In non-
specified date
conductive 2.700 14.500 2.700 14.500 2.700 14.500
Application status
LDDT>
instruction In conductive
4.800 22.400 4.800 22.400 4.800 22.400
status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Comparison of current
In non-
date
conductive 4.800 21.800 4.800 21.800 4.800 21.800
status
When not executed 0.018 0.018 0.018
In conductive
2.600 15.000 2.600 15.000 2.600 15.000
status
Comparison of
In non-
specified date
conductive 2.700 15.100 2.700 15.100 2.700 15.100
ANDDT> status
In conductive
4.600 22.100 4.600 22.100 4.600 22.100
status
Comparison of current
In non-
date
conductive 4.500 22.000 4.500 22.000 4.500 22.000
status
When not executed 0.018 0.018 0.018
In conductive
2.700 15.300 2.700 15.300 2.700 15.300
status
Comparison of
In non-
specified date
conductive 2.600 15.000 2.600 15.000 2.600 15.000
ORDT> status
In conductive
4.800 21.500 4.800 21.500 4.800 21.500
status
Comparison of current
In non-
date
conductive 4.700 22.400 4.700 22.400 4.700 22.400
status

857
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
In conductive
2.700 14.500 2.700 14.500 2.700 14.500
status
Comparison of
In non-
specified date
conductive 2.700 14.500 2.700 14.500 2.700 14.500
status
LDDT<=
In conductive
4.800 22.600 4.800 22.600 4.800 22.600
status
Comparison of current
In non-
date
conductive 4.800 22.600 4.800 22.600 4.800 22.600
status
When not executed 0.018 0.018 0.018
In conductive
2.400 14.500 2.400 14.500 2.400 14.500
status
Comparison of
In non-
specified date
conductive 2.700 15.000 2.700 15.000 2.700 15.000
ANDDT<= status
In conductive
4.700 21.600 4.700 21.600 4.700 21.600
status
Comparison of current
In non-
date
conductive 4.700 22.400 4.700 22.400 4.700 22.400
status
When not executed 0.018 0.018 0.018
In conductive
2.700 15.300 2.700 15.300 2.700 15.300
status
Comparison of
In non-
specified date
conductive 2.600 15.200 2.600 15.200 2.600 15.200
Application
ORDT<= status
instruction
In conductive
4.800 22.500 4.800 22.500 4.800 22.500
status
Comparison of current
In non-
date
conductive 4.800 21.700 4.800 21.700 4.800 21.700
status
In conductive
2.700 14.500 2.700 14.500 2.700 14.500
status
Comparison of
In non-
specified date
conductive 2.700 14.300 2.700 14.300 2.700 14.300
status
LDDT<
In conductive
4.800 22.700 4.800 22.700 4.800 22.700
status
Comparison of current
In non-
date
conductive 4.800 22.500 4.800 22.500 4.800 22.500
status
When not executed 0.018 0.018 0.018
In conductive
2.600 14.800 2.600 14.800 2.600 14.800
status
Comparison of
In non-
specified date
conductive 2.600 14.900 2.600 14.900 2.600 14.900
ANDDT< status
In conductive
4.600 22.200 4.600 22.200 4.600 22.200
status
Comparison of current
In non-
date
conductive 4.700 22.100 4.700 22.100 4.700 22.100
status

858
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
When not executed 0.018 0.018 0.018
In conductive
status
2.700 15.500 2.700 15.500 2.700 15.500 2
Comparison of
In non-
specified date
conductive 2.600 15.000 2.600 15.000 2.600 15.000
ORDT< status 3
In conductive
4.800 23.000 4.800 23.000 4.800 23.000
status
Comparison of current
In non-
date
conductive 4.700 22.600 4.700 22.600 4.700 22.600
A
status
In conductive
2.700 14.700 2.700 14.700 2.700 14.700
Comparison of
status 5
In non-
specified date
conductive 2.700 14.700 2.700 14.700 2.700 14.700
status
LDDT>=
In conductive
4.800 22.600 4.800 22.600 4.800 22.600
6
status
Comparison of current
In non-
date
conductive
status
4.800 22.900 4.800 22.900 4.800 22.900
7
When not executed 0.018 0.018 0.018
In conductive

Comparison of
status
2.600 15.000 2.600 15.000 2.600 15.000
8
In non-
specified date
conductive 2.700 15.000 2.700 15.000 2.700 15.000
ANDDT>= status
Application In conductive
4.600 22.100 4.600 22.100 4.600 22.100
instruction status

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Comparison of current
In non-
date
conductive 4.700 22.700 4.700 22.700 4.700 22.700
status
When not executed 0.018 0.018 0.018
In conductive
2.700 15.300 2.700 15.300 2.700 15.300
status
Comparison of
In non-
specified date
conductive 2.600 15.000 2.600 15.000 2.600 15.000
ORDT>= status
In conductive
4.800 22.500 4.800 22.500 4.800 22.500
status
Comparison of current
In non-
date
conductive 4.700 22.700 4.700 22.700 4.700 22.700
status
Decimal point format all 2-digit
5.600 16.000 5.600 16.000 5.600 16.000
EVAL specification
Exponent format all 6-digit specification 2.100 16.300 2.100 16.300 2.100 16.300
n=1 8.100 11.000 8.100 11.000 8.100 11.000
ASC S D n
n=96 3.400 14.900 3.400 14.900 3.400 14.900
n=1 15.100 11.700 15.100 11.700 15.100 11.700
HEX S D n
n=96 3.300 17.700 3.300 17.700 3.300 17.700
RIGHT S D n=1 15.100 15.400 15.100 15.400 15.100 15.400
n n=96 4.000 25.500 4.000 25.500 4.000 25.500
n=1 4.500 16.000 4.500 16.000 4.500 16.000
LEFT S D n
n=96 7.300 25.700 7.300 25.700 7.300 25.700
MIDR –– 4.700 18.600 4.700 18.600 4.700 18.600
MIDW –– 7.300 17.000 7.300 17.000 7.300 17.000

859
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
No match 2.900 19.200 2.900 19.200 2.900 19.200
INSTR Head 2.800 16.900 2.800 16.900 2.800 16.900
Match
End 16.900 19.400 16.900 19.400 16.900 19.400
EMOD –– 19.900 12.100 19.900 12.100 19.900 12.100
EREXP –– 15.300 13.800 15.300 13.800 15.300 13.800
STRINS S D S = 128 / D = 40 / n = 1 16.900 30.000 16.900 30.000 16.900 30.000
n S = 128 / D = 40 / n = 48 19.900 32.500 19.900 32.500 19.900 32.500

STRDEL S S = 128 / D = 40 / n = 1 15.300 25.600 15.300 25.600 15.300 25.600

D n S = 128 / D = 40 / n = 48 13.200 23.500 13.200 23.500 13.200 23.500
SIN Single precision 1.600 6.700 1.600 6.700 1.600 6.700
COS Single precision 1.600 6.700 1.600 6.700 1.600 6.700
TAN Single precision 1.700 6.600 1.700 6.600 1.700 6.600
ASIN Single precision 1.500 6.700 1.500 6.700 1.500 6.700
ACOS Single precision 1.500 6.700 1.500 6.700 1.500 6.700
ATAN Single precision 1.500 5.200 1.500 5.200 1.500 5.200
SIND Double precision 2.600 20.500 2.600 20.500 2.600 20.500
COSD Double precision 2.500 19.900 2.500 19.900 2.500 19.900
TAND Double precision 3.000 22.700 3.000 22.700 3.000 22.700
ASIND Double precision 2.600 18.100 2.600 18.100 2.600 18.100
ACOSD Double precision 2.400 16.400 2.400 16.400 2.400 16.400
ATAND Double precision 2.300 16.400 2.300 16.400 2.300 16.400
RAD Single precision 1.300 3.500 1.300 3.500 1.300 3.500
RADD Double precision 1.400 3.600 1.400 3.600 1.400 3.600
DEG Single precision 1.800 11.500 1.800 11.500 1.800 11.500
DEGD Double precision 1.800 11.500 1.800 11.500 1.800 11.500
SQR Single precision 1.300 4.200 1.300 4.200 1.300 4.200
SQRD Double precision 1.900 11.500 1.900 11.500 1.900 11.500
Application 1.700 8.100 1.700 8.100 1.700 8.100
S = -10
instruction EXP S D Single precision
S =1 1.700 8.100 1.700 8.100 1.700 8.100
S = -10 2.300 17.400 2.300 17.400 2.300 17.400
EXPD S D Double precision
S =1 2.200 17.400 2.200 17.400 2.200 17.400
S =1 1.500 5.900 1.500 5.900 1.500 5.900
LOG S D Single precision
S = 10 1.600 7.000 1.600 7.000 1.600 7.000
S =1 1.900 13.400 1.900 13.400 1.900 13.400
LOGD S D Double precision
S = 10 2.400 17.400 2.400 17.400 2.400 17.400
RND –– 0.800 2.200 0.800 2.200 0.800 2.200
SRND –– 1.100 2.000 1.100 2.000 1.100 2.000
S =0 1.400 3.000 1.400 3.000 1.400 3.000
BSQR S D
S = 9999 2.000 9.600 2.000 9.600 2.000 9.600
S =0 1.100 2.200 1.100 2.200 1.100 2.200
BDSQR S D
S = 99999999 1.900 8.300 1.900 8.300 1.900 8.300
BSIN –– 2.300 14.700 2.300 14.700 2.300 14.700
BCOS –– 2.300 14.900 2.300 14.900 2.300 14.900
BTAN –– 2.500 15.600 2.500 15.600 2.500 15.600
BASIN –– 2.200 11.800 2.200 11.800 2.200 11.800
BACOS –– 2.200 12.200 2.200 12.200 2.200 12.200
BATAN –– 2.300 12.500 2.300 12.500 2.300 12.500
S1 = 12.3 E + 5
POW S1 S2 D Single precision 3.300 13.600 3.300 13.600 3.300 13.600
S2 = 3.45 E + 0
POWD S1 S2 S1 = 12.3 E + 5
Double precision 4.400 26.600 4.400 26.600 4.400 26.600
D S2 = 3.45 E + 0
LOG10 –– 1.900 6.800 1.900 6.800 1.900 6.800

860
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
LOG10D –– 2.500 19.000 2.500 19.000 2.500 19.000
LIMIT
DLIMIT
––
––
0.700
0.700
1.300
1.300
0.700
0.700
1.300
1.300
0.700
0.700
1.300
1.300
2
BAND –– 2.000 4.000 2.000 4.000 2.000 4.000
DBAND –– 2.000 4.000 2.000 4.000 2.000 4.000
ZONE –– 2.000 3.700 2.000 3.700 2.000 3.700 3
DZONE –– 2.000 3.500 2.000 3.500 2.000 3.500
Point No.1 < S1 <
3.200 14.100 3.200 14.100 3.200 14.100
SM750 =
ON
Point No.2
Point No.9 < S1 <
A
3.200 14.200 3.200 14.200 3.200 14.200
Point No.10
SCL S1 S2 D
Point No.1 < <
5
S1
2.900 12.700 2.900 12.700 2.900 12.700
SM750 = Point No.2
OFF Point No.9 < S1 <
3.400 12.700 3.400 12.700 3.400 12.700
Point No.10
Point No.1 < S1 <
3.200 14.500 3.200 14.500 3.200 14.500
6
SM750 = Point No.2
ON Point No.9 < S1 <
3.200 14.700 3.200 14.700 3.200 14.700
DSCL S1 S2 Point No.10 7
D Point No.1 < S1 <
2.700 12.200 2.700 12.200 2.700 12.200
SM750 = Point No.2
OFF Point No.9 < S1 <
3.300 12.100 3.300 12.100 3.300 12.100 8
Point No.10
Point No.1 < S1 <
3.200 14.000 3.200 14.000 3.200 14.000
SM750 = Point No.2
ON Point No.9 < S1 <
Application 3.200 14.200 3.200 14.200 3.200 14.200
SCL2 Point No.10

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
S1 S2
instruction
D Point No.1 < S1 <
2.900 12.300 2.900 12.300 2.900 12.300
SM750 = Point No.2
OFF Point No.9 < S1 <
3.300 12.400 3.300 12.400 3.300 12.400
Point No.10
Point No.1 < S1 <
3.200 13.900 3.200 13.900 3.200 13.900
SM750 = Point No.2
ON Point No.9 < S1 <
3.200 13.900 3.200 13.900 3.200 13.900
DSCL2 S1 S2 Point No.10
D Point No.1 < S1 <
2.700 12.200 2.700 12.200 2.700 12.200
SM750 = Point No.2
OFF Point No.9 < S1 <
3.300 12.200 3.300 12.200 3.300 12.200
Point No.10
Standard RAM 1.600 9.300 1.600 9.300 1.600 9.300
RSET
Extended SRAM cassette 1.600 8.300 1.600 8.300 1.600 8.300
Extended SRAM cassette to standard RAM 51.800 88.600 51.800 88.600 51.800 88.600
QDRSET
Standard RAM to extended SRAM cassette 53.300 88.600 53.300 88.600 53.300 88.600
Extended SRAM cassette to standard ROM 930.000 1008.000 930.000 1008.000 930.000 1008.000
QCDSET
Standard ROM to extended SRAM cassette 56.000 68.000 56.000 68.000 56.000 68.000
No digit increase 2.400 8.500 2.400 8.500 2.400 8.500
DATE +
Digit increase 2.400 8.500 2.400 8.500 2.400 8.500
No digit increase 2.400 8.500 2.400 8.500 2.400 8.500
DATE -
Digit increase 2.500 8.400 2.500 8.400 2.500 8.400
SECOND –– 1.600 5.200 1.600 5.200 1.600 5.200
HOUR –– 1.500 5.400 1.500 5.400 1.500 5.400
DATERD –– 2.500 13.900 2.500 13.900 2.500 13.900
DATEWR –– 4.100 19.100 4.100 19.100 4.100 19.100
S.DATERD –– 4.400 19.500 4.400 19.500 4.400 19.500

861
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Min. Max. Min. Max. Min. Max.
No digit increase 3.400 14.800 3.400 14.800 3.400 14.800
S.DATE+
Digit increase 3.500 14.500 3.500 14.500 3.500 14.500
No digit increase 3.400 15.800 3.400 15.800 3.400 15.800
S.DATE -
Digit increase 3.400 15.500 3.400 15.500 3.400 15.500
PSTOP –– 35.600 68.400 35.600 68.400 35.600 68.400
POFF –– 35.400 66.800 35.400 66.800 35.400 66.800
PSCAN –– 36.700 69.100 36.700 69.100 36.700 69.100
WDT –– 1.000 3.300 1.000 3.300 1.000 3.300
DUTY –– 2.500 9.700 2.500 9.700 2.500 9.700
TIMCHK –– 2.500 6.900 2.500 6.900 2.500 6.900
File register of standard RAM 1.600 3.500 1.600 3.500 1.600 3.500
ZRRDB
File register of extended SRAM cassette 1.600 3.500 1.600 3.500 1.600 3.500
File register of standard RAM 1.700 4.100 1.700 4.100 1.700 4.100
ZRWRB
File register of extended SRAM cassette 1.700 4.100 1.700 4.100 1.700 4.100
ADRSET –– 1.400 3.800 1.400 3.800 1.400 3.800
Application ZPUSH –– 3.100 7.000 3.100 7.000 3.100 7.000
instruction ZPOP –– 3.000 3.900 3.000 3.900 3.000 3.900
UNIRD n1 D n2 = 1 2.100 10.100 2.100 10.100 2.100 10.100
n2 n2 = 16 4.200 12.600 4.200 12.600 4.200 12.600
TYPERD –– 16.100 36.800 16.100 36.800 16.100 36.800
TRACE Start 32.200 46.200 32.200 46.200 32.200 46.200
TRACER –– 2.600 8.800 2.600 8.800 2.600 8.800
When standard RAM is used : 1 point 3.500 21.400 3.500 21.400 3.500 21.400
When standard RAM is used : 1000 point 42.200 58.000 42.200 58.000 42.200 58.000
RBMOV S D When extended SRAM cassette is used :
3.600 19.600 3.600 19.600 3.600 19.600
n 1 point
When extended SRAM cassette is used :
102.200 118.000 102.200 118.000 102.200 118.000
1000 point
SP.FREAD –– 3.500 39.400 3.500 39.400 3.500 39.400
SP.FWRITE –– 3.500 39.500 3.500 39.500 3.500 39.500
SP.DEVST –– 25.900 37.600 25.900 37.600 25.900 37.600
S.DEVLD –– 3.700 20.000 3.700 20.000 3.700 20.000
When mounting CC-Link module
7.100 25.000 7.100 25.000 7.100 25.000
(Master station side)
When mounting CC-Link module (Local
7.100 25.200 7.100 25.200 7.100 25.200
station side)
• When selecting MELSECNET/H
refresh only (control station side)
• When selecting CC-Link IE Controller 18.400 48.300 18.400 48.300 18.400 48.300
Network refresh only (control station
side)
S.ZCOM • When selecting MELSECNET/H
Data link
refresh only (normal station side)
instruction
• When selecting CC-Link IE Controller 18.400 43.500 18.400 43.500 18.400 43.500
Network refresh only (normal station
side)
When selecting CC-Link IE Field
Network refresh only (master station 12.000 38.500 12.000 38.500 12.000 38.500
side)
When selecting CC-Link IE Field
11.900 41.900 11.900 41.900 11.900 41.900
Network refresh only (local station side)
S.RTREAD –– 2.900 15.400 2.900 15.400 2.900 15.400
S.RTWRITE –– 3.100 15.600 3.100 15.600 3.100 15.600

862
 Processing Time (µs)
Q06UDVCPU,
Category Instruction Condition (Device) Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU 3
Min. Max. Min. Max. Min. Max.
S.TO n4 = 1 14.700 30.000 14.700 30.000 14.700 30.000
Writing to host CPU
n1 n2 n3 n4
shared memory n4 = 320 48.700 62.900 48.700 62.900 48.700 62.900 2
D

TO Writing to host CPU n3 = 1 3.700 18.200 3.700 18.200 3.700 18.200

shared memory n3 = 320 36.500 50.800 36.500 50.800 36.500 50.800
n1 n2
DTO
S n3
Writing to host CPU n3 = 1 3.700 18.600 3.700 18.600 3.700 18.600
3
n1 n2 S n3 shared memory n3 = 320 68.700 82.700 68.700 82.700 68.700 82.700
Multiple CPU
Reading from host n3 = 1 3.700 17.500 3.700 17.500 3.700 17.500
dedicated
FROM CPU shared memory n3 = 320 27.400 41.000 27.400 41.000 27.400 41.000 A
instruction
n3 = 1 5.100 28.000 5.100 28.000 5.100 28.000
n1 n2 D n3 Reading from other
n3 = 320 125.600 152.100 125.600 152.100 125.600 152.100
CPU shared memory

Reading from host

n3 = 1000
n3 = 1
386.000
3.700
413.900
17.500
386.000
3.700
413.900
17.500
386.000
3.700
413.900
17.500
5
DFRO CPU shared memory n3 = 320 51.500 65.000 51.500 65.000 51.500 65.000
n3 = 1 5.700 30.300 5.700 30.300 5.700 30.300
Reading from other
n1 n2 D n3
CPU shared memory
n3 = 320 246.700 272.000 246.700 272.000 246.700 272.000 6
n3 = 1000 764.500 792.800 764.500 792.800 764.500 792.800
n=1 34.000 82.000 34.000 82.000 34.000 82.000
D.DDWR
n=16 37.000 84.000 37.000 84.000 37.000 84.000
n S1 S2 D1 D2
Writes devices to n=96*1 52.000 98.000 52.000 98.000 52.000 98.000 7
another CPU. n=1 34.000 82.000 34.000 82.000 34.000 82.000
Multiple CPU DP.DDWR
n=16 37.000 84.000 37.000 84.000 37.000 84.000
high-speed
transmission
n S1 S2 D1 D2
n=96*1 52.000 98.000 52.000 98.000 52.000 98.000 8
n=1 34.000 81.000 34.000 81.000 34.000 81.000
dedicated D.DDRD
n=16 34.000 81.000 34.000 81.000 34.000 81.000
instruction n S1 S2 D1 D2
Reads devices from n=96*1 34.000 81.000 34.000 81.000 34.000 81.000
another CPU. n=1 34.000 81.000 34.000 81.000 34.000 81.000
DP.DDRD
n=16 34.000 81.000 34.000 81.000 34.000 81.000

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
n S1 S2 D1 D2
n=96*1 34.000 81.000 34.000 81.000 34.000 81.000

Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
execution instruction.
Example WORDP instruction, TOP instruction etc.

863
(2) Table of the time to be added when file register, extended data register, extended link register, module access device,
and link direct device are used
(a) When using Q00UJCPU, Q00UCPUI, Q01UCPU and Q02UCPU
Device Processing Time (µs)
Device name Data Specification
Q00UJCPU Q00UCPU Q01UCPU Q02UCPU
Location
Source 0.100 0.100 0.100 0.100
Bit
Destination 0.100 0.100 0.100 0.100
When standard Source 0.100 0.100 0.100 0.100
Word
RAM is used Destination 0.100 0.100 0.100 0.100
Source 0.100 0.100 0.100 0.200
Double word
Destination 0.100 0.100 0.100 0.200
Source –– –– –– 0.220
Bit
When SRAM Destination –– –– –– 0.180
card is used Source –– –– –– 0.220
File register (R) Word
(Q2MEM-1MBS, Destination –– –– –– 0.180
Q2MEM-2MBS) Source –– –– –– 0.440
Double word
Destination –– –– –– 0.380
Source –– –– –– 0.160
Bit
When SRAM Destination –– –– –– 0.140
card is used Source –– –– –– 0.160
Word
(Q3MEM-4MBS, Destination –– –– –– 0.140
Q3MEM-8MBS) Source –– –– –– 0.320
Double word
Destination –– –– –– 0.300
Source 0.120 0.120 0.120 0.120
Bit
Destination 0.120 0.120 0.120 0.120
When standard Source 0.120 0.120 0.120 0.120
Word
RAM is used Destination 0.120 0.120 0.120 0.120
Source 0.120 0.120 0.120 0.220
Double word
Destination 0.120 0.120 0.120 0.220
Source –– –– –– 0.240
Bit
When SRAM Destination –– –– –– 0.200
card is used Source –– –– –– 0.240
File register (ZR) Word
(Q2MEM-1MBS, Destination –– –– –– 0.200
Q2MEM-2MBS) Source –– –– –– 0.460
Double word
Destination –– –– –– 0.400
Source –– –– –– 0.180
Bit
When SRAM Destination –– –– –– 0.160
card is used Source –– –– –– 0.180
Word
(Q3MEM-4MBS, Destination –– –– –– 0.160
Q3MEM-8MBS) Source –– –– –– 0.340
Double word
Destination –– –– –– 0.320
Source –– –– –– 12.000
Bit
Destination –– –– –– 17.300
Module access device Source –– –– –– 9.700
Word
(Un\G , U3En\G0 to G4095) Destination –– –– –– 33.000
Source –– –– –– 24.200
Double word
Destination –– –– –– 34.800
Source 70.900 70.900 70.900 46.200
Bit
Destination 120.100 120.100 120.100 75.000
Link direct device Source 68.400 68.400 68.400 44.800
Word
(Jn\ ) Destination 53.700 53.700 53.700 33.600
Source 75.600 75.600 75.600 60.300
Double word
Destination 58.900 58.900 58.900 41.900

864
 (b) When using Q03UD(E)CPU, Q04UD(E)HCPU, Q06UD(E)HCPU, Q10UD(E)HCPU, Q13UD(E)HCPU,
Q20UD(E)HCPU, Q26UD(E)HCPU, Q50UDEHCPU and Q100UDEHCPU

Device name data

Device
Specification
Processing Time (µs)
3
Q03UD(E) Q04/Q06UD(E)H Q10/Q13/Q20/ Q50/Q100UDEH
Location CPU CPU Q26UD(E)HCPU CPU
Source 0.100 0.048 0.048 0.048
Bit
Destination 0.100 0.038 0.038 0.038 2
When standard Source 0.100 0.048 0.048 0.048
Word
RAM is used Destination 0.100 0.038 0.038 0.038
Double Source 0.200 0.095 0.095 0.095 3
word Destination 0.200 0.086 0.086 0.086
Source 0.220 0.200 0.200 0.200
Bit
Destination 0.180 0.162 0.162 0.162
When SRAM
card is used Source 0.220 0.200 0.200 0.200
A
File register (R) Word
(Q2MEM-1MBS, Destination 0.180 0.162 0.162 0.162
Q2MEM-2MBS) Double Source 0.440 0.399 0.399 0.399
word Destination 0.380 0.361 0.361 0.361 5
Source 0.160 0.152 0.152 0.152
Bit
When SRAM Destination 0.140 0.133 0.133 0.133
card is used
(Q3MEM-4MBS,
Word
Source
Destination
0.160
0.140
0.152
0.133
0.152
0.133
0.152
0.133
6
Q3MEM-8MBS) Double Source 0.320 0.304 0.304 0.304
word Destination 0.300 0.295 0.295 0.295
Source 0.120 0.057 0.057 0.057 7
Bit
Destination 0.120 0.048 0.048 0.048
When standard Source 0.120 0.057 0.057 0.057
Word
RAM is used Destination 0.120 0.048 0.048 0.048 8
Double Source 0.220 0.105 0.105 0.105
word Destination 0.220 0.095 0.095 0.095
File register Source 0.240 0.209 0.209 0.209
Bit
(ZR)/ When SRAM Destination 0.200 0.171 0.171 0.171
Extended data card is used Source 0.240 0.209 0.209 0.209

Appendix 1.4Operation Processing Time of Universal Model QCPU

Appendix 1OPERATION PROCESSING TIME
Word
register (D)/ (Q2MEM-1MBS, Destination 0.200 0.171 0.171 0.171
Extended link Q2MEM-2MBS) Double Source 0.460 0.409 0.409 0.409
register (W) word Destination 0.400 0.371 0.371 0.371
Source 0.180 0.162 0.162 0.162
Bit
When SRAM Destination 0.160 0.143 0.143 0.143
card is used Source 0.180 0.162 0.162 0.162
Word
(Q3MEM-4MBS, Destination 0.160 0.143 0.143 0.143
Q3MEM-8MBS) Double Source 0.340 0.314 0.314 0.314
word Destination 0.320 0.304 0.304 0.304
Source 11.700 11.200 11.200 11.200
Bit
Destination 15.400 15.300 15.300 15.300
Module access device Source 9.460 9.410 9.410 9.410
Word
(Un\G , U3En\G0 to G4095) Destination 19.000 19.000 19.000 19.000
Double Source 11.000 10.900 10.900 10.900
word Destination 18.800 18.700 18.700 18.700
Source 32.700 31.300 31.300 31.300
Bit
Destination 52.300 51.800 51.800 51.800
Link direct device Source 30.600 30.100 30.100 30.100
Word
(Jn\ ) Destination 28.900 28.400 28.400 28.400
Double Source 38.900 38.400 38.400 38.400
word Destination 34.800 34.300 34.300 34.300

865
 (c) When using Q03UDVCPU, Q04UDVCPU, Q06UDVCPU, Q13UDVCPU and, Q26UDVCPU
Processing Time (µs)
Device Specification Q06UDVCPU,
Device name data
Location Q03UDVCPU Q04UDVCPU Q13UDVCPU,
Q26UDVCPU
Source 0.074 0.043 0.043
Bit
Destination 0.023 0.023 0.023
When the extended
Source 0.074 0.043 0.043
SRAM cassette is not Word
Destination 0.023 0.023 0.023
used
Double Source 0.148 0.085 0.085
word Destination 0.044 0.044 0.044
File register (R)
Source 0.099 0.099 0.099
Bit
Destination 0.028 0.028 0.028
When the extended Source 0.099 0.099 0.099
Word
SRAM cassette is used Destination 0.028 0.028 0.028
Double Source 0.198 0.198 0.198
word Destination 0.054 0.054 0.054
Source 0.074 0.043 0.043
Bit
Destination 0.023 0.023 0.023
When the extended
Source 0.074 0.043 0.043
SRAM cassette is not Word
Destination 0.023 0.023 0.023
File register (ZR)/ used
Double Source 0.148 0.085 0.085
Extended data
word Destination 0.044 0.044 0.044
register (D)/
Source 0.099 0.099 0.099
Extended link Bit
Destination 0.028 0.028 0.028
register (W)
When the extended Source 0.099 0.099 0.099
Word
SRAM cassette is used Destination 0.028 0.028 0.028
Double Source 0.198 0.198 0.198
word Destination 0.054 0.054 0.054
Source 8.200 8.200 8.200
Bit
Destination 11.800 11.800 11.800
Module access device Source 9.410 9.410 9.410
Word
(Un\G , U3En\G0 to G4095) Destination 9.400 9.400 9.400
Double Source 10.900 10.900 10.900
word Destination 18.700 18.700 18.700
Source 16.200 16.200 16.200
Bit
Destination 27.400 27.400 27.400
Link direct device Source 19.800 19.800 19.800
Word
(Jn\ ) Destination 17.400 17.400 17.400
Double Source 18.200 18.200 18.200
word Destination 17.400 17.400 17.400

866
Appendix 1.5 Operation Processing Time of LCPU

The processing time for the individual instructions are shown in the table on the following pages.
3
Operation processing times can vary substantially depending on the nature of the sources and destinations of the instructions,
and the values contained in the following tables should therefore be taken as a set of general guidelines to processing time
rather than as being strictly accurate.
2

Appendix 1.5.1 Subset instruction processing time 3

The following describes the subset instruction processing time.

A
(1) The processing time shown in "(1) Subset instruction processing time table" applies when the device used in an
instruction meets the device condition for subset processing (For device condition triggering subset processing, refer

(2)
to Page 109, Section 3.5.1).
When using a file resister (R, ZR), extended data register (D), and extended link register (W), add the processing time
5
shown in (2) to that of the instruction.
(3) When using an F,T(ST),C device with an OUT/SET/RST instruction, add the processing time for each instruction, with

(4)
reference to the adding time in (3).
Since the processing time of an instruction varies depending on that of the cash function, both the minimum and 6
maximum values are described in the table.

(1) Subset instruction processing time table 7

(a) When using L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT,
and L26CPU-PBT
8
Processing Time (µs)
L06CPU, L06CPU-P,
L02SCPU, L02CPU,
Category Instruction Condition (Device) L26CPU, L26CPU-P,
L02SCPU-P L02CPU-P
L26CPU-BT, L26CPU-PBT
Min. Max. Min. Max. Min. Max.

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
LD
LDI
AND
ANI
OR
ORI
When executed 0.060 0.040 0.0095
LDP
LDF
ANDP
ANDF
ORP
ORF
Sequence
LDPI
instruction When executed 0.180 0.120 0.0285
LDFI
ANDPI
ANDFI
When executed 0.240 0.160 0.038
ORPI
ORFI
When not changed
OUT 0.060 0.040 0.0095
When changed
When not changed
OUTH 0.060 0.040 0.0095
When changed
When not executed
SET
When When not changed 0.060 0.040 0.0095
RST
executed When changed

867
 Processing Time (µs)
L06CPU, L06CPU-P,
L02SCPU, L02CPU,
Category Instruction Condition (Device) L26CPU, L26CPU-P,
L02SCPU-P L02CPU-P
L26CPU-BT, L26CPU-PBT
Min. Max. Min. Max. Min. Max.
In conductive status
LD= 0.180 0.120 0.0285
In non-conductive status
When not executed
AND= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
OR= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
In conductive status
LD<> 0.180 0.120 0.0285
In non-conductive status
When not executed
AND<> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
OR<> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
In conductive status
LD> 0.180 0.120 0.0285
In non-conductive status
When not executed
AND> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
OR> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
In conductive status
LD<= 0.180 0.120 0.0285
In non-conductive status
Basic
When not executed
instruction
AND<= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
OR<= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
In conductive status
LD< 0.180 0.120 0.0285
In non-conductive status
When not executed
AND< When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
OR< When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
In conductive status
LD>= 0.180 0.120 0.0285
In non-conductive status
When not executed
AND>= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
OR>= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
In conductive status
LDD= 0.180 0.120 0.0285
In non-conductive status
When not executed
ANDD= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status

868
 Processing Time (µs)
L06CPU, L06CPU-P,
L02SCPU, L02CPU,
Category Instruction Condition (Device) L26CPU, L26CPU-P,
L02SCPU-P L02CPU-P
L26CPU-BT, L26CPU-PBT
3
Min. Max. Min. Max. Min. Max.
When not executed
ORD= When In conductive status 0.180 0.120 0.0285 2
executed In non-conductive status
In conductive status
LDD<> 0.180 0.120 0.0285
In non-conductive status
When not executed
3
ANDD<> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed A
ORD<> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status

LDD>
In conductive status
0.180 0.120 0.0285 5
In non-conductive status
When not executed
ANDD> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
6
When not executed
ORD> When In conductive status 0.180 0.120 0.0285
executed In non-conductive status 7
In conductive status
LDD<= 0.180 0.120 0.0285
In non-conductive status

ANDD<= When
When not executed
In conductive status 0.180 0.120 0.0285
8
executed In non-conductive status
When not executed
ORD<= When In conductive status 0.180 0.120 0.0285
Basic
executed In non-conductive status

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
instruction
In conductive status
LDD< 0.180 0.120 0.0285
In non-conductive status
When not executed
ANDD< When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
ORD< When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
In conductive status
LDD>= 0.180 0.120 0.0285
In non-conductive status
When not executed
ANDD>= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
When not executed
ORD>= When In conductive status 0.180 0.120 0.0285
executed In non-conductive status
+ S D When executed 0.180 0.120 0.0285

+ S1 S2 D When executed 0.240 0.160 0.038

- S D When executed 0.180 0.120 0.0285

- S1 S2 D When executed 0.240 0.160 0.038

D+ S D When executed 0.180 0.120 0.0285

D+ S1 S2 D When executed 0.240 0.160 0.038

D- S D When executed 0.180 0.120 0.0285

D- S1 S2 D When executed 0.240 0.160 0.038

869
 Processing Time (µs)
L06CPU, L06CPU-P,
L02SCPU, L02CPU,
Category Instruction Condition (Device) L26CPU, L26CPU-P,
L02SCPU-P L02CPU-P
L26CPU-BT, L26CPU-PBT
Min. Max. Min. Max. Min. Max.
* S1 S2 D When executed 0.240 0.180 0.057

/ S1 S2 D When executed 0.340 0.280 0.105

D* S1 S2 D When executed 0.320 0.260 0.095

D/ S1 S2 D When executed 0.460 0.400 0.162

B+ S D When executed 3.100 12.300 3.100 6.800 2.900 4.100

B+ S1 S2 D When executed 5.900 13.500 4.800 8.900 4.200 5.900

B- S D When executed 3.100 12.300 3.100 6.800 2.900 4.100

B- S1 S2 D When executed 5.900 13.600 4.800 8.900 4.200 4.600

B* S1 S2 D When executed 3.700 12.100 3.900 7.400 3.400 4.800

B/ S1 S2 D When executed 4.000 14.000 3.900 8.500 3.700 5.200

Single S = 0, D =0 0.240 0.180 0.057

E+ S D
precision S = 2127, D = 2127 0.240 0.180 0.057

Single S1 = 0, S2 =0 0.300 0.220 0.0665

E+ S1 S2 D
precision S1 = 2127, S2 = 2127 0.300 0.220 0.0665

Single S = 0, D =0 0.240 0.180 0.057

E- S D
precision S = 2127, D = 2127 0.240 0.180 0.057

Single S1 = 0, S2 =0 0.300 0.220 0.0665

E- S1 S2 D
precision S1 = 2127, S2 =2 127 0.300 0.220 0.0665

Single S1 = 0, S2 =0 0.240 0.180 0.057

E* S1 S2 D
precision S1 = 2127, S2 = 2127 0.240 0.180 0.057
Single
E/ S1 S2 D S1 = 2127, S2 = 2127 4.900 18.900 3.900 8.500 0.285*1
Basic precision
instruction INC When executed 0.120 0.080 0.019
DINC When executed 0.120 0.080 0.019
DEC When executed 0.120 0.080 0.019
DDEC When executed 0.120 0.080 0.019
BCD When executed 0.200 0.160 0.057
DBCD When executed 0.280 0.240 0.095
BIN When executed 0.140 0.100 0.0285
DBIN When executed 0.140 0.100 0.0285

Single S =0 0.180 0.100 0.0475

FLT
precision S = 7FFFH 0.180 0.140 0.0475

Single S =0 0.180 0.140 0.0475

DFLT
precision S = 7FFFFFFFH 0.180 0.140 0.0475

Single S =0 0.180 0.140 0.0475

INT
precision S = 32766.5 0.180 0.140 0.0475

Single S =0 0.180 0.140 0.0475

DINT
precision S = 1234567890.3 0.180 0.140 0.0475
MOV –– 0.120 0.080 0.019
DMOV –– 0.120 0.080 0.019
EMOV –– 0.120 0.080 0.019
CML –– 0.120 0.080 0.019
DCML –– 0.120 0.080 0.019
n=1 4.200 4.600 3.600 4.100 2.900 3.200
SM237=ON
n=96 4.850 5.150 4.500 4.700 3.400 3.700
BMOV
n=1 6.800 11.300 5.000 7.400 3.900 5.100
SM237=OFF
n=96 7.450 11.900 6.000 7.900 4.400 5.700

870
 Processing Time (µs)
L06CPU, L06CPU-P,
L02SCPU, L02CPU,
Category Instruction Condition (Device) L26CPU, L26CPU-P,
L02SCPU-P L02CPU-P
L26CPU-BT, L26CPU-PBT
3
Min. Max. Min. Max. Min. Max.
n=1 4.100 4.600 5.900 6.800 2.800 3.200

FMOV
SM237=ON
n=96 4.800 5.200 6.300 11.000 3.000 5.200 2
n=1 4.600 8.250 7.000 8.000 3.400 3.800
SM237=OFF
n=96 6.150 10.600 5.200 6.900 3.600 5.800
XCH
DXCH
––
––
2.250
2.400
8.100
8.200
2.100
2.200
4.100
4.200
1.800
2.100
2.300
2.900
3
Basic
n=1 2.700 2.800 2.000 3.200 1.750 1.750
instruction SM237=ON
n=96 6.500 6.800 5.600 6.100 3.650 4.150
DFMOV
SM237=OFF
n=1 4.000 8.150 2.900 4.600 2.250 3.150 A
n=96 8.000 12.200 6.100 8.200 4.200 5.500
CJ –– 3.500 10.100 2.100 2.900 1.100 2.400
SCJ –– 3.500 10.100 2.100 2.900 1.100 2.400 5
JMP –– 3.500 10.100 2.100 2.900 1.100 2.400
WAND S D When executed 0.180 0.120 0.0285

WAND S1 S2
When executed 0.240 0.160 0.038 6
D

DAND S D When executed 0.180 0.120 0.0285

DAND S1 S2
When executed 0.240 0.160 0.038
7
D

WOR S D When executed 0.180 0.120 0.0285

WOR S1 S2 8
When executed 0.240 0.160 0.038
D

DOR S D When executed 0.180 0.120 0.0285

DOR S1 S2
When executed 0.240 0.160 0.038

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
D

WXOR S D When executed 0.180 0.120 0.0285

WXOR S1 S2
When executed 0.240 0.160 0.038
D

Application DXOR S D When executed 0.180 0.120 0.0285

instruction DXOR S1 S2
When executed 0.240 0.160 0.038
D

WXNR S D When executed 0.180 0.120 0.0285

WXNR S1 S2
When executed 0.240 0.160 0.038
D

DXNR S D When executed 0.180 0.120 0.0285

DXNR S1 S2
When executed 0.240 0.160 0.038
D

n=1 2.250 10.800 2.200 4.900 1.700 2.500

ROR D n
n = 15 2.350 10.800 2.200 4.900 1.700 2.500
n=1 2.250 10.800 2.100 4.800 1.700 3.200
RCR D n
n = 15 2.250 10.800 2.100 4.800 1.700 3.200
n=1 2.350 10.800 2.100 4.800 1.800 3.200
ROL D n
n = 15 2.350 10.800 2.100 4.800 1.800 3.200
n=1 2.300 11.500 2.100 5.200 1.800 2.200
RCL D n
n = 15 2.300 11.500 2.100 5.200 1.800 2.200
n=1 2.350 11.500 2.200 5.200 1.900 2.700
DROR D n
n = 31 2.350 11.500 2.200 5.200 1.900 2.700

871
 Processing Time (µs)
L06CPU, L06CPU-P,
L02SCPU, L02CPU,
Category Instruction Condition (Device) L26CPU, L26CPU-P,
L02SCPU-P L02CPU-P
L26CPU-BT, L26CPU-PBT
Min. Max. Min. Max. Min. Max.
n=1 2.350 13.300 2.200 5.900 1.900 4.200
DRCR D n
n = 31 2.350 14.900 2.200 5.900 1.900 4.200
n=1 2.350 10.800 2.200 4.900 1.800 3.300
DROL D n
n = 31 2.350 10.800 2.200 4.900 1.800 3.300
n=1 2.350 13.300 2.200 5.900 1.900 3.800
DRCL D n
n = 31 2.350 13.300 2.200 5.900 1.900 3.800
n=1 2.350 9.900 2.200 4.600 1.700 2.600
SFR D n
n = 15 2.350 9.900 2.200 4.600 1.700 2.600
n=1 2.350 9.850 2.200 4.600 1.800 2.700
SFL D n
n = 15 2.350 9.850 2.200 4.600 1.800 2.700
n=1 3.250 15.500 2.200 6.100 2.200 4.300
Application DSFR D n
n = 96 32.600 45.000 33.400 38.100 23.900 26.100
instruction
n=1 3.200 15.500 2.200 6.100 2.100 4.000
DSFL D n
n = 96 32.600 45.100 33.500 38.000 23.700 25.800
S =0 3.100 8.950 3.000 4.800 2.900 3.600
SUM
S = FFFFH 3.000 8.850 3.000 4.900 2.900 3.600
SEG When executed 2.100 7.700 1.700 3.600 1.500 2.100
FOR –– 1.500 7.500 1.300 3.200 0.870 2.100
Internal file pointer 4.800 5.400 2.600 4.000 2.300 3.600
CALL Pn
Common pointer 7.100 30.500 4.600 13.500 3.200 4.900
CALL Pn S1
–– 50.200 62.000 31.200 36.000 26.100 29.300
to S5

*1 For the L06CPU and L06CPU-P, the minimum value is 3.900 µs and the maximum value is 4.900 µs.

Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
execution instruction.
Example MOVP instruction, WANDP instruction etc.

872
(2) Table of the time to be added when file register, extended data register, and extended link register are used
(a) When using L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT,
and L26CPU-PBT 3
Processing Time (µs)
L06CPU,

Device name Data

Device
Specification L02SCPU, L02CPU,
L06CPU-P,
L26CPU,
2
Location L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 3
Source 0.100 0.100 0.048
Bit
Destination 0.220 0.220 0.038

File register (R)

When standard RAM
is used
Word
Source
Destination
0.100
0.100
0.100
0.100
0.048
0.038
A
Source 0.200 0.200 0.095
Double word
Destination 0.200 0.200 0.086

Bit
Source 0.160 0.140 0.057 5
File register (ZR), Destination 0.320 0.280 0.048
Extended data When standard RAM Source 0.160 0.140 0.057
Word
register (D), Extended is used Destination 0.160 0.140 0.048 6
link register (W) Source 0.260 0.240 0.105
Double word
Destination 0.260 0.240 0.095

7
(3) Table of the time to be added when F/T(ST)/C device is used in OUT/SET/RST instruction
(a) When using L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT,
and L26CPU-PBT 8
Processing Time (µs)
L06CPU,
L06CPU-P,
Instruction Device
Condition L02SCPU, L02CPU, L26CPU,
name name
L02SCPU-P L02CPU-P L26CPU-P,

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
L26CPU-BT,
L26CPU-PBT
When not executed 2.900 2.000 1.570
F When displayed 116.000 53.100 38.090
When executed
Display completed 116.000 53.000 37.980
OUT
When not executed 0.180 0.120 0.030
T(ST), C After time up 0.180 0.120 0.030
When executed
When added 0.180 0.120 0.030
When not executed 0.060 0.040 0.010
SET F When displayed 116.000 52.000 40.600
When executed
Display completed 116.000 43.600 37.900
When not executed 0.060 0.040 0.010
F When displayed 55.800 45.700 36.600
When executed
RST Display completed 29.200 19.000 16.190
When not executed 0.180 0.120 0.030
T(ST), C
When executed 0.180 0.120 0.030

873
 Appendix 1.5.2 Processing time of instructions other than subset instruction
The following table shows the processing time of instructions other than subset instructions.

• The processing time shown in "(1) Table of the processing time of instructions other than subset instructions" applies
when the device used in an instruction does not meet the device condition for subset processing (For device condition
that does not trigger subset processing, refer to Page 109, Section 3.5.1).
For instructions not shown in the following table, refer to "(1) Subset instruction processing time table" in Page 873,
Appendix 1.5.1(2).
• When using file register (R, ZR), extended data register (D), extended link register (W), module access device (Un/G ),
and link direct device (Jn/ ), add the processing time shown in (2) to that of the instruction.
• Since the processing time of an instruction varies depending on that of the cash function, both the minimum and
maximum values are described in the table.

(1) Table of the processing time of instructions other than subset instructions
(a) When using L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT,
and L26CPU-PBT
Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
ANB
ORB
MPS –– 0.060 0.040 0.0095
MRD
MPP
When not executed
INV 0.060 0.040 0.0095
When executed
MEP When not executed
0.060 0.040 0.0095
MEF When executed
EGP When not executed
0.060 0.040 0.0095
EGF When executed
PLS –– 1.800 1.900 1.600 1.700 0.890 1.200
PLF –– 1.800 1.900 1.600 1.700 0.890 1.200
Sequence
When not executed 0.120 0.080 0.0185
instruction FF
When executed 1.700 1.800 1.500 1.500 0.790 0.910
When not executed 0.120 0.080 0.0185
DELTA
When executed 4.000 14.700 2.700 6.800 2.400 3.200
When not executed 0.120 0.080 0.0185
SFT
When executed 1.800 12.600 1.700 4.300 1.100 2.700
MC –– 0.120 0.080 0.0185
MCR –– 0.060 0.040 0.0185
FEND Error check performed 250.000 250.000 170.000 210.000 130.000 170.000
END No error check performed 250.000 250.000 170.000 210.000 130.000 170.000
STOP –– –– –– ––
NOP
NOPLF –– 0.060 0.040 0.0095
PAGE

874
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
Single In conductive status 4.400 20.900 3.900 10.000 0.0285
LDE=
precision In non-conductive status 4.400 20.900 3.900 10.000 0.0285
When not executed 0.180 0.120 0.0285
3
In conductive
Single 4.200 19.600 3.400 9.300 0.0285
ANDE= When status
precision
executed In non-conductive
4.200 19.600 3.400 9.300 0.0285
A
status
When not executed 0.180 0.120 0.0285

ORE=
Single
When
In conductive
status
4.200 17.400 3.500 8.500 0.0285 5
precision
executed In non-conductive
4.200 17.400 3.500 8.500 0.0285
status

LDE< >
Single In conductive status 4.400 20.900 3.900 10.000 0.0285 6
precision In non-conductive status 4.400 20.900 3.900 10.000 0.0285
When not executed 0.180 0.120 0.0285

ANDE< >
Single
When
In conductive
status
4.200 19.600 3.400 9.300 0.0285 7
precision
executed In non-conductive
4.200 19.600 3.400 9.300 0.0285
status
When not executed 0.180 0.120 0.0285 8
In conductive
Single 4.200 17.400 3.500 8.500 0.0285
ORE< > When status
precision
executed In non-conductive
4.200 17.400 3.500 8.500 0.0285
status

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
Basic Single In conductive status 4.400 20.900 3.900 10.000 0.0285
LDE>
instruction precision In non-conductive status 4.400 20.900 3.900 10.000 0.0285
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 19.600 3.400 9.300 0.0285
ANDE> When status
precision
executed In non-conductive
4.200 19.600 3.400 9.300 0.0285
status
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 17.400 3.500 8.500 0.0285
ORE> When status
precision
executed In non-conductive
4.200 17.400 3.500 8.500 0.0285
status
Single In conductive status 4.400 20.900 3.900 10.000 0.0285
LDE<=
precision In non-conductive status 4.400 20.900 3.900 10.000 0.0285
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 19.600 3.400 9.300 0.0285
ANDE<= When status
precision
executed In non-conductive
4.200 19.600 3.400 9.300 0.0285
status
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 17.400 3.500 8.500 0.0285
ORE<= When status
precision
executed In non-conductive
4.200 17.400 3.500 8.500 0.0285
status
Single In conductive status 4.400 20.900 3.900 10.000 0.0285
LDE<
precision In non-conductive status 4.400 20.900 3.900 10.000 0.0285

875
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 19.600 3.400 9.300 0.0285
ANDE< When status
precision
executed In non-conductive
4.200 19.600 3.400 9.300 0.0285
status
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 17.400 3.500 8.500 0.0285
ORE< When status
precision
executed In non-conductive
4.200 17.400 3.500 8.500 0.0285
status
Single In conductive status 4.400 20.900 3.900 10.000 0.0285
LDE>=
precision In non-conductive status 4.400 20.900 3.900 10.000 0.0285
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 19.600 3.400 9.300 0.0285
ANDE>= When status
precision
executed In non-conductive
4.200 19.600 3.400 9.300 0.0285
status
When not executed 0.180 0.120 0.0285
In conductive
Single 4.200 17.400 3.500 8.500 0.0285
ORE>= When status
precision
executed In non-conductive
4.200 17.400 3.500 8.500 0.0285
status
Double In conductive status 4.700 37.400 4.800 16.000 3.500 9.000
LDED=
Basic precision In non-conductive status 4.700 37.400 4.800 16.000 3.500 9.000
instruction When not executed 0.180 0.120 0.0285
In conductive
Double 4.500 34.700 4.400 15.100 3.200 7.500
ANDED= When status
precision
executed In non-conductive
4.500 34.700 4.400 15.100 3.200 7.500
status
When not executed 0.180 0.120 0.0285
In conductive
Double 4.700 33.200 4.500 14.900 3.400 9.200
ORED= When status
precision
executed In non-conductive
4.700 33.200 4.500 14.900 3.400 9.200
status
Double In conductive status 4.700 37.400 4.800 16.000 3.500 9.000
LDED<>
precision In non-conductive status 4.700 37.400 4.800 16.000 3.500 9.000
When not executed 0.180 0.120 0.0285
In conductive
Double 4.500 34.700 4.400 15.100 3.200 7.500
ANDED<> When status
precision
executed In non-conductive
4.500 34.700 4.400 15.100 3.200 7.500
status
When not executed 0.180 0.120 0.0285
In conductive
Double 4.700 33.200 4.500 14.900 3.400 9.200
ORED<> When status
precision
executed In non-conductive
4.700 33.200 4.500 14.900 3.400 9.200
status
Double In conductive status 4.700 37.400 4.800 16.000 3.500 9.000
LDED>
precision In non-conductive status 4.700 37.400 4.800 16.000 3.500 9.000

876
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
When not executed 0.180 0.120 0.0285
In conductive
ANDED>
Double
When status
4.500 34.700 4.400 15.100 3.200 7.500 3
precision
executed In non-conductive
4.500 34.700 4.400 15.100 3.200 7.500
status
When not executed 0.180 0.120 0.0285 A
In conductive
Double 4.700 33.200 4.500 14.900 3.400 9.200
ORED> When status
precision
executed In non-conductive
status
4.700 33.200 4.500 14.900 3.400 9.200 5
Double In conductive status 4.700 37.400 4.800 16.000 3.500 9.000
LDED<=
precision In non-conductive status 4.700 37.400 4.800 16.000 3.500 9.000
When not executed 0.180 0.120 0.0285 6
In conductive
Double 4.500 34.700 4.400 15.100 3.200 7.500
ANDED<= When status
precision
executed In non-conductive
status
4.500 34.700 4.400 15.100 3.200 7.500 7
When not executed 0.180 0.120 0.0285
In conductive
ORED<=
Double
precision
When status
4.700 33.200 4.500 14.900 3.400 9.200
8
executed In non-conductive
4.700 33.200 4.500 14.900 3.400 9.200
status
Double In conductive status 4.700 37.400 4.800 16.000 3.500 9.000
LDED<
Basic precision In non-conductive status 4.700 37.400 4.800 16.000 3.500 9.000

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
instruction When not executed 0.180 0.120 0.0285
In conductive
Double 4.500 34.700 4.400 15.100 3.200 7.500
ANDED< When status
precision
executed In non-conductive
4.500 34.700 4.400 15.100 3.200 7.500
status
When not executed 0.180 0.120 0.0285
In conductive
Double 4.700 33.200 4.500 14.900 3.400 9.200
ORED< When status
precision
executed In non-conductive
4.700 33.200 4.500 14.900 3.400 9.200
status
Double In conductive status 4.700 37.400 4.800 16.000 3.500 9.000
LDED>=
precision In non-conductive status 4.700 37.400 4.800 16.000 3.500 9.000
When not executed 0.180 0.120 0.0285
In conductive
Double 4.500 34.700 4.400 15.100 3.200 7.500
ANDED>= When status
precision
executed In non-conductive
4.500 34.700 4.400 15.100 3.200 7.500
status
When not executed 0.180 0.120 0.0285
In conductive
Double 4.700 33.200 4.500 14.900 3.400 9.200
ORED>= When status
precision
executed In non-conductive
4.700 33.200 4.500 14.900 3.400 9.200
status
In conductive status 8.300 38.500 5.600 17.100 4.200 8.200
LD$=
In non-conductive status 8.300 38.500 5.600 17.100 4.200 8.200

877
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
When not executed 0.180 0.120 0.0285
In conductive
7.200 37.300 5.300 16.400 3.900 7.300
AND$= status
When executed
In non-conductive
7.200 37.300 5.300 16.400 3.900 7.300
status
When not executed 0.180 0.120 0.0285
In conductive
7.500 36.600 5.200 15.700 4.000 7.600
OR$= status
When executed
In non-conductive
7.500 36.600 5.200 15.700 4.000 7.600
status
In conductive status 8.300 39.300 5.600 17.100 4.200 8.200
LD$< >
In non-conductive status 8.300 39.300 5.600 17.100 4.200 8.200
When not executed 0.180 0.120 0.0285
In conductive
8.000 38.200 5.300 16.400 3.900 7.300
AND$< > status
When executed
In non-conductive
8.000 38.200 5.300 16.400 3.900 7.300
status
When not executed 0.180 0.120 0.0285
In conductive
8.300 37.300 5.200 15.700 4.000 7.600
OR$< > status
When executed
In non-conductive
8.300 37.300 5.200 15.700 4.000 7.600
status
In conductive status 8.300 41.600 5.600 17.100 4.200 8.200
Basic LD$>
In non-conductive status 8.300 41.600 5.600 17.100 4.200 8.200
instruction
When not executed 0.180 0.120 0.0285
In conductive
8.000 38.100 5.300 16.400 3.900 7.300
AND$> status
When executed
In non-conductive
8.000 38.100 5.300 16.400 3.900 7.300
status
When not executed 0.180 0.120 0.0285
In conductive
8.200 35.700 5.200 15.700 4.000 7.600
OR$> status
When executed
In non-conductive
8.200 35.700 5.200 15.700 4.000 7.600
status
In conductive status 8.300 39.200 5.600 17.100 4.200 8.200
LD$<=
In non-conductive status 8.300 39.200 5.600 17.100 4.200 8.200
When not executed 0.180 0.120 0.0285
In conductive
7.100 36.500 5.300 16.400 3.900 7.300
AND$<= status
When executed
In non-conductive
7.100 36.500 5.300 16.400 3.900 7.300
status
When not executed 0.180 0.120 0.0285
In conductive
7.400 35.600 5.200 15.700 4.000 7.600
OR$<= status
When executed
In non-conductive
7.400 35.600 5.200 15.700 4.000 7.600
status
In conductive status 7.400 40.000 5.600 17.100 4.200 8.200
LD$<
In non-conductive status 7.400 40.000 5.600 17.100 4.200 8.200

878
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
When not executed 0.180 0.120 0.0285
In conductive
AND$< status
8.000 37.300 5.300 16.400 3.900 7.300 3
When executed
In non-conductive
8.000 37.300 5.300 16.400 3.900 7.300
status
When not executed 0.180 0.120 0.0285 A
In conductive
8.300 35.600 5.200 15.700 4.000 7.600
OR$< status
When executed
In non-conductive
status
8.300 35.600 5.200 15.700 4.000 7.600 5
In conductive status 7.400 38.300 5.600 17.100 4.200 8.200
LD$>=
In non-conductive status 7.400 38.300 5.600 17.100 4.200 8.200
When not executed 0.180 0.120 0.0285 6
In conductive
7.200 37.300 5.300 16.400 3.900 7.300
AND$>= status
When executed
In non-conductive
status
7.200 37.300 5.300 16.400 3.900 7.300 7
When not executed 0.180 0.120 0.0285
In conductive
OR$>=
When executed
status
8.200 36.400 5.200 15.700 4.000 7.600
8
In non-conductive
8.200 8.200 5.200 15.700 4.000 7.600
status
BKCMP = S1 n=1 15.300 36.100 9.200 15.600 7.500 10.100

S2 D n n = 96 64.500 85.500 60.700 69.100 45.600 50.500

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
Basic n=1 15.300 36.100 9.200 15.600 7.500 10.100
BKCMP<> S1
instruction
S2 D n n = 96 66.600 87.500 60.700 69.100 45.600 50.500

BKCMP> S1 n=1 15.300 36.100 9.200 15.600 7.500 10.100

S2 D n n = 96 66.600 87.500 60.700 69.100 45.600 50.500

BKCMP<= S1 n=1 15.300 36.100 9.200 15.600 7.500 10.100

S2 D n n = 96 64.500 85.500 60.700 69.100 45.600 50.500

BKCMP< S1 n=1 15.300 36.100 9.200 15.600 7.500 10.100

S2 D n n = 96 66.600 87.500 60.700 69.100 45.600 50.500

BKCMP>= S1 n=1 15.300 36.100 9.200 15.600 7.500 10.100

S2 D n n = 96 64.500 85.500 60.700 69.100 45.600 50.500

DBKCMP = n=1 15.800 36.300 9.700 16.400 8.600 13.000
S1 S2 D n n = 96 64.900 85.700 61.200 69.900 47.900 52.800
DBKCMP<> n=1 15.700 36.300 9.700 16.400 8.600 13.000
S1 S2 D n n = 96 67.000 87.700 61.200 69.900 47.900 52.800

DBKCMP> S1 n=1 15.800 36.300 9.700 16.400 8.600 13.000

S2 D n n = 96 67.000 87.700 61.200 69.900 47.900 52.800

DBKCMP<= n=1 15.700 36.300 9.700 16.400 8.600 13.000
S1 S2 D n n = 96 64.800 85.700 61.200 69.900 47.900 52.800

DBKCMP< S1 n=1 15.800 36.300 9.700 16.400 8.600 13.000

S2 D n n = 96 67.000 87.700 61.200 69.900 47.900 52.800

DBKCMP>= n=1 15.700 36.300 9.700 16.400 8.600 13.000
S1 S2 D n n = 96 64.800 85.700 61.200 69.900 47.900 52.800

879
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
DB + S D When executed 5.750 13.300 4.800 8.400 4.600 6.400

DB + S1 S2
When executed 5.650 13.200 5.100 8.700 4.800 6.700
D

DB - S D When executed 5.750 12.700 4.800 8.400 4.600 6.400

DB - S1 S2 D When executed 5.650 12.600 5.100 8.700 4.800 6.700

DB * S1 S2 D When executed 8.750 40.200 8.700 18.900 8.100 11.600

DB/ S1 S2 D When executed 5.750 21.500 6.100 9.100 5.800 8.800

Double S = 0, D =0 4.500 26.700 4.800 8.000 4.300 7.200

ED + S D
precision S = 21023, D = 21023 5.800 32.900 5.400 14.900 4.300 7.200

ED + S1 S2 Double S1 = 0, S2 =0 5.450 35.400 5.500 9.800 4.800 9.200

D precision S1 = 21023, S2 = 21023 6.750 41.400 6.100 17.800 4.800 9.200

Double S = 0, D =0 5.200 25.900 4.400 10.800 4.400 7.500

ED - S D
precision S = 21023, D = 21023 6.000 27.700 5.400 15.500 4.400 7.500

Double S1 = 0, S2 =0 5.550 32.900 4.700 13.900 3.800 7.500

ED - S1 S2 D
precision S1 = 21023, S2 = 21023 5.750 33.900 5.700 17.200 3.800 7.500

Double S1 = 0, S2 =0 5.500 34.400 5.800 9.500 5.100 8.800

ED * S1 S2 D
precision S1 = 21023, S2 =2 1023 5.950 39.100 5.900 17.600 5.100 8.800
Double
ED / S1 S2 D S1 = 21023, S2 = 21023 8.050 44.200 7.300 18.700 5.900 10.000
precision
BK + S1 S2 D n=1 13.500 28.500 9.100 11.200 8.500 10.600
Basic
n n = 96 63.100 78.200 60.500 66.200 44.600 47.900
instruction
BK - S1 S2 D n=1 13.500 28.500 9.700 12.000 8.900 11.300
n n = 96 63.100 78.200 60.500 66.200 44.600 47.900

DBK + S1 S2 n=1 10.100 24.200 7.500 12.400 6.450 9.950

D n n = 96 59.800 73.900 59.900 65.200 43.700 47.500

DBK - S1 S2 n=1 10.100 24.200 7.500 12.400 6.450 9.950

D n n = 96 59.800 73.900 59.900 65.200 43.700 47.500

$+ S D –– 15.400 64.300 11.200 24.700 8.100 13.900

$+ S1 S2 D –– 19.700 71.000 7.900 16.600 6.500 10.300

Double S =0 3.100 19.600 2.800 9.400 1.800 4.700

FLTD
precision S = 7FFFH 3.350 19.900 3.300 9.600 2.200 4.800

Double S =0 3.200 20.400 2.900 9.100 2.000 4.900

DFLTD
precision S = 7FFFFFFFH 3.450 20.500 3.400 9.300 2.300 5.100

Double S =0 3.200 22.900 3.500 8.700 2.200 4.100

INTD
precision S = 32766.5 4.100 34.300 4.100 12.900 3.200 5.600

Double S =0 3.200 23.000 3.200 9.500 2.200 3.400

DINTD
precision S = 1234567890.3 4.050 33.500 4.100 13.400 3.000 5.100
DBL When executed 3.300 5.900 2.500 4.400 2.300 2.700
WORD When executed 3.000 7.250 2.800 3.900 2.600 3.600
GRY When executed 3.350 7.500 2.700 4.300 2.300 3.000
DGRY When executed 3.000 7.200 2.700 4.300 2.300 3.000
GBIN When executed 4.600 9.700 4.000 6.400 3.800 4.300

880
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
DGBIN When executed 5.550 10.700 5.000 6.900 5.000 5.900
NEG When executed 3.300 6.850 2.100 4.400 2.000 3.300
DNEG When executed 3.050 5.700 2.500 3.700 2.500 3.300
3
Floating point = 0 3.100 7.350 2.500 3.300 2.300 2.800
ENEG
Floating point = -1.0 3.350 11.700 2.800 5.600 2.500 3.900

EDNEG
Floating point = 0 3.000 21.200 3.000 8.800 1.800 3.100 A
Floating point = -1.0 3.100 22.900 2.700 9.400 1.900 3.000
BKBCD S D n=1 8.700 27.600 6.000 13.400 5.900 8.200
n n = 96 84.200 104.000 83.300 91.400 61.000 63.400 5
BKBIN S D n=1 8.450 28.100 6.500 9.800 5.600 9.300
n n = 96 56.100 75.800 55.400 62.900 49.200 52.500
ECON –– 3.100 21.300 3.000 9.800 2.100 4.500 6
EDCON –– 5.050 24.000 3.300 10.300 2.500 5.400
EDMOV –– 2.900 22.900 2.700 8.500 1.700 5.000
Character string to be transferred = 0 6.250 30.100 4.400 12.300 3.400 5.600
$MOV
Character string to be transferred = 32 15.500 39.300 14.000 21.900 11.400 13.300 7
BXCH D1 D2 n=1 8.400 20.900 6.200 7.900 5.500 7.300

n n = 96 67.100 79.900 67.300 71.400 47.300 49.300

Basic
SWAP –– 3.300 3.550 2.400 2.700 1.900 2.200 8
instruction
GOEND –– 0.550 0.700 0.500
DI –– 2.800 8.400 2.100 4.000 1.500 1.800
EI –– 4.300 12.300 3.600 6.300 3.000 3.300
IMASK –– 12.900 40.600 11.800 20.500 7.200 10.500

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
IRET –– 1.000 1.400 1.000
n=1 7.500 26.500 5.900 12.500 3.700 5.600
RFS X n
n = 96 11.400 30.400 12.900 19.300 10.700 12.400
n=1 7.300 26.300 5.100 11.500 3.400 4.800
RFS Y n
n = 96 10.900 29.900 8.600 15.300 8.100 8.900
UDCNT1 –– 1.500 7.100 6.200 16.400 5.100 12.300
UDCNT2 –– 1.500 6.300 6.300 16.800 5.400 12.500
TTMR –– 5.300 20.900 4.500 9.500 3.400 5.400
STMR –– 8.900 49.800 7.800 21.400 5.800 12.500
ROTC –– 52.300 52.600 20.900 21.500 8.000 9.400
RAMP –– 7.400 30.900 6.700 14.600 5.200 8.400
SPD –– 1.500 6.300 5.400 14.800 4.900 11.200
PLSY –– 6.400 7.100 10.500 10.500 7.900 7.900
PWM –– 3.900 4.600 10.100 10.100 7.500 7.500
MTR –– 10.100 61.400 14.700 25.100 9.400 10.000

881
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
BKAND S1 S2 n=1 13.600 28.500 9.000 11.700 8.300 11.000

D n n = 96 63.200 78.200 60.600 66.400 43.800 47.300

BKOR S1 S2 n=1 13.500 28.500 7.900 14.000 7.700 9.500

D n n = 96 63.100 78.200 60.700 66.500 44.300 45.800

BKXOR S1 S2 n=1 13.600 28.300 8.800 13.800 7.300 9.200

D n n = 96 63.100 78.000 61.300 66.300 43.800 45.800

BKXNR S1 S2 n=1 13.500 28.300 8.400 13.900 7.600 8.900

D n n = 96 63.100 78.000 60.900 66.700 43.900 45.300

n=1 5.050 21.100 3.600 9.500 3.200 4.800
BSFR D n
n = 96 9.000 34.800 6.500 15.900 5.800 7.700
n=1 4.800 19.100 3.600 9.300 3.400 5.100
BSFL D n
n = 96 8.550 34.300 6.300 15.800 6.000 7.900
SFTBR D n1 n1 = 16 / n2 = 1 10.300 46.500 8.100 21.000 7.500 17.400
n2 n1 = 16 / n2 = 15 10.300 46.500 8.100 22.100 7.500 17.300

SFTBL D n1 n1 = 16 / n2 = 1 10.500 49.800 8.100 21.000 7.500 17.400

n2 n1 = 16 / n2 = 15 10.500 49.800 8.100 22.100 7.500 17.300

SFTWR D n1 n1 = 16 / n2 = 1 7.950 24.000 6.200 13.100 4.500 8.700

Application n2 n1 = 16 / n2 = 15 7.950 24.000 6.100 13.100 4.600 8.800

instruction SFTWL D n1 n1 = 16 / n2 = 1 8.700 23.600 6.200 13.100 4.500 8.700
n2 n1 = 16 / n2 = 15 8.650 23.700 6.100 13.100 4.600 8.800
n=1 4.550 4.750 2.800 3.100 2.500 2.800
BSET D n
n = 15 4.550 4.750 2.800 3.100 2.500 2.800
n=1 4.600 4.750 2.800 3.100 2.500 2.800
BRST D n
n = 15 4.600 4.750 2.800 3.100 2.500 2.800
TEST When executed 7.250 13.200 4.700 6.100 3.700 4.800
DTEST When executed 6.950 12.900 4.700 6.100 3.700 4.800
n=1 7.350 11.600 4.300 5.700 3.700 4.100
BKRST S n
n = 96 10.100 22.600 6.200 10.000 5.100 6.000
All match 6.650 6.800 4.800 5.300 4.200 4.600
n=1
SER S1 S2 D None match 6.650 6.800 4.700 5.300 4.200 4.600
n All match 34.000 42.300 33.200 35.900 25.900 26.300
n = 96
None match 34.000 42.300 33.200 35.900 25.900 26.300
All match 8.000 16.300 6.500 9.000 5.400 5.700
n=1
DSER S1 S2 None match 8.000 16.300 6.500 9.000 5.500 5.900
D n All match 54.100 62.600 54.800 57.500 41.200 41.800
n = 96
None match 54.100 62.600 54.700 57.500 41.200 41.800
S =0 4.100 4.200 3.400 3.700 3.200 3.700
DSUM S D
S = FFFFFFFFH 4.100 4.200 3.400 3.700 3.200 3.700

882
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
DECO S D n=2 8.850 23.000 6.000 10.700 5.300 6.900
n n=8 13.600 36.600 9.500 16.700 6.800 7.800
3
M1 = ON 7.650 11.900 5.400 6.900 4.700 5.100
n=2
ENCO S D M4 = ON 7.500 11.700 5.300 6.600 4.600 5.000
n M1 = ON 14.600 27.800 10.700 14.000 9.000 10.000
n=8
M256 = ON 10.600 23.700 7.000 11.100 5.100 6.100 A
n=1 6.500 14.800 4.600 7.000 3.800 4.600
DIS S D n
n=4 6.900 15.200 4.900 7.300 4.000 5.000

UNI S D n
n=1 6.800 15.100 5.000 7.300 3.500 4.800 5
n=4 7.500 15.900 5.700 8.300 4.000 5.100
NDIS When executed 4.750 18.700 11.200 15.200 11.000 13.200
NUNI When executed
n=1
4.750
6.600
18.700
14.900
10.600
5.400
12.700
8.100
7.300
4.400
13.200
5.800
6
WTOB S D

n n = 96 37.700 46.100 38.400 40.900 28.200 29.300

n=1 7.350 15.600 5.300 8.200 4.600 5.500
BTOW
n
S D

n = 96 32.100 40.500 31.700 34.200 22.800 23.800

7
n=1 8.250 24.900 5.400 11.900 4.000 6.100
MAX S D n
n = 96 34.200 51.600 34.200 41.100 24.700 27.000
n=1 8.250 24.800 6.100 12.000 4.000 6.000 8
MIN S D n
n = 96 34.200 51.600 32.900 39.300 26.500 28.300
DMAX S D n=1 6.800 34.900 6.000 14.800 4.800 8.100
n n = 96 60.300 89.200 61.100 69.500 47.100 49.600
n=1 7.600 35.700 6.000 14.800 4.300 5.900

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
DMIN S D n
n = 96 59.400 90.000 57.000 67.000 45.400 47.400
Application
instruction SORT S1 n S2 n = 1, S2 =1 9.400 28.900 6.800 13.700 5.600 8.800
D1 D2 n = 96, S2 = 16 31.500 74.000 31,300 46,800 24,300 34,400

DSORT S1 n n = 1, S2 =1 9.400 29.000 6.800 14.300 5.600 10,900

S2 D1 D2 n = 96, S2 = 16 37.800 81.000 34,900 49,700 26,200 36,700

WSUM S D n=1 6.700 15.000 5.000 7.300 4.200 5.500

n n = 96 28.900 37.100 28.100 30.700 21.300 22.300

DWSUM S n=1 8.600 26.800 6.100 11.300 4.800 6.100

D n n = 96 56.200 74.700 56.200 62.100 42.700 44.000

MEAN S D n=1 5.850 19.800 4.400 10.400 3.900 7.800

n n = 96 17.300 38.200 16.100 24.500 12.900 18.000

DMEAN S n=1 6.900 23.300 6.000 12.500 5.300 9.950

D n n = 96 29.400 49.900 34.000 42.000 23.000 28.800

NEXT –– 1.000 1.100 0.940 1.400 0.770 1.200
BREAK –– 4.700 25.000 3.500 10.200 3.100 7.600
Return to original program 4.100 19.500 2.900 8.800 1.600 2.600
RET
Return to other program 4.700 16.700 3.200 10.500 2.000 3.100
Internal file pointer 5.400 5.400 3.600 3.800 2.700 3.600
FCALL Pn
Common pointer 7.600 30.500 5.300 13.500 3.600 5.100
FCALL Pn S1
–– 50.400 62.700 20.900 30.300 16.500 18.600
to S5

ECALL * Pn
*: Program –– 105.000 214.000 72.700 109.000 65.900 77.600
name

883
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
ECALL * Pn
S1 to S5
–– 164.000 271.000 101.400 141.400 91.800 105.000
*: Program
name
EFCALL * Pn
*: Program –– 105.000 214.000 72.800 109.600 66.200 78.100
name
EFCALL * Pn
S1 to S5
–– 164.000 271.000 101.900 141.500 78.800 91.600
*: Program
name
XCALL –– 5.100 6.700 5.200 14.600 3.700 5.200
When selecting I/O refresh only 18.100 89.100 8.400 14.600 12.600 17.200
When selecting CC-Link refresh only
33.300 132.000 10.500 29.400 10.100 22.000
(Master station side)
When selecting CC-Link refresh only
33.300 132.000 10.500 29.400 10.100 22.000
(Local station side)
When selecting CC-Link IE Field Network
32.000 127.000 17.000 49.500 16.600 38.000
COM refresh only (master station side)
CCOM When selecting CC-Link IE Field Network
32.000 127.000 17.000 49.500 16.600 38.000
refresh only (local station side)
When selecting intelli auto refresh only 18.100 89.000 7.900 14.400 7.400 11.900
When selecting communications with
–– –– 29.700 79.900 26.800 60.700
display unit
Application When selecting communication with
instruction 21.300 89.000 9.500 32.800 9.200 25.200
external devices only
Number of data points = 0 6.100 14.200 4.200 6.700 3.200 4.600
FIFW
Number of data points = 96 6.100 14.200 4.400 6.800 3.300 3.800
Number of data points = 1 7.500 15.600 5.100 7.400 3.800 4.400
FIFR
Number of data points = 96 37.000 45.000 36.100 38.800 24.800 25.700
Number of data points = 1 7.600 15.600 4.900 7.500 3.800 5.300
FPOP
Number of data points = 96 7.600 15.600 5.000 7.500 3.700 5.400
Number of data points = 0 6.900 15.000 5.400 7.500 3.700 5.300
FINS
Number of data points = 96 36.600 44.700 5.000 7.400 3.700 5.300
Number of data points = 1 8.000 16.100 5.700 8.300 4.200 5.800
FDEL
Number of data points = 96 37.300 45.500 36.900 39.300 25.400 25.900
FROM n1 n2 n3 = 1 17.400 74.700 11.600 31.000 10.700 23.600
D n3 n3 = 1000 406.000 498.500 403.900 432.900 390.900 410.200
DFRO n1 n2 n3 = 1 19.600 85.600 13.300 35.400 12.600 26.700
D n3 n3 = 500 406.000 498.500 405.000 434.600 390.900 410.200

TO n1 n2 S n3 = 1 16.400 69.600 11.200 28.400 9.600 21.300

n3 n3 = 1000 381.300 471.200 381.500 410.900 372.500 390.800

DTO n1 n2 S n3 = 1 18.600 85.100 12.500 33.900 12.000 25.700

n3 n3 = 500 381.300 471.200 379.800 410.400 372.500 390.800
No display no display 1.500 7.100 2.400 2.600 1.900 2.000
LEDR
LED instruction execution no display 38.900 109.000 32.700 50.600 24.400 35.800
S =1 5.600 13.900 5.000 7.300 4.300 5.600
BINDA S D
S = -32768 7.800 16.200 7.400 9.800 6.500 8.000

884
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
DBINDA S S =1 6.200 14.500 5.600 8.300 4.900 6.300
D S = -2147483648 11.000 19.200 10.500 12.900 9.600 11.000 3
S =1 5.050 13.400 4.500 6.900 3.700 5.200
BINHA S D
S = FFFFH 5.050 13.400 4.500 6.900 3.700 5.200

DBINHA S S =1 5.600 13.900 5.000 7.600 4.600 6.000 A

D S = FFFFFFFFH 5.600 13.900 5.000 7.600 4.600 6.000

BCDDA S D
S =1 5.600 13.900 5.000 7.300 4.300 5.600
5
S = 9999 7.800 16.200 7.400 9.800 6.500 8.000

DBCDDA S S =1 6.200 14.500 5.600 8.300 4.900 6.300

D S = 99999999 11.000 19.200 10.500 12.900 9.600 11.000 6
S =1 7.000 18.500 5.800 10.100 5.600 7.800
DABIN S D
S = -32768 6.950 18.500 5.800 10.100 5.600 7.800

DDABIN S S =1 9.450 21.000 8.300 12.600 8.100 10.500

7
D S = -2147483648 9.450 21.000 8.300 12.600 8.100 10.500

HABIN S D
S =1 5.650 17.100 4.500 8.800 4.400 6.500
8
S = FFFFH 5.750 17.300 4.500 8.800 4.400 6.500

DHABIN S S =1 6.800 18.200 5.500 10.000 5.300 7.700

D S = FFFFFFFFH 7.100 18.600 5.500 10.000 5.300 7.700

5.650 17.200 4.500 8.700 4.300 6.300

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
Application
S =1
DABCD S D
instruction S = 9999 5.700 17.200 4.500 8.700 4.300 6.300

DDABCD S S =1 6.850 18.300 5.500 9.800 5.500 7.500

D S = 99999999 6.850 18.300 5.500 9.800 5.500 7.500
COMRD –– 185.000 188.000 65.700 65.700 50.900 51.200
1 character 4.700 16.200 3.900 7.800 3.600 5.500
LEN
96 characters 20.600 32.900 19.700 23.900 16.800 18.700
STR –– 9.800 36.500 7.500 16.700 6.600 10.400
DSTR –– 12.100 40.400 10.200 19.700 9.600 11.500
VAL –– 12.200 40.900 9.800 19.900 8.900 13.000
DVAL –– 19.400 45.600 12.700 23.900 12.700 16.800
ESTR –– 29.700 87.800 21.200 43.400 17.900 23.100
Decimal point format all 2-digit
23.900 70.400 28.300 41.000 22.500 29.00
EVAL specification
Exponent format all 6-digit specification 23.700 70.300 28.300 41.000 22.500 29.00
n=1 10.200 41.800 6.200 17.100 5.400 8.300
ASC S D n
n = 96 31.900 66.600 30.300 42.100 25.200 28.400
n=1 8.600 43.400 5.400 16.000 5.400 9.000
HEX S D n
n = 96 77.100 115.000 42.400 54.900 31.300 35.000
RIGHT S D n=1 10.900 29.600 7.400 13.900 6.600 7.300
n n = 96 41.400 60.300 39.300 45.800 29.200 31.600
n=1 10.600 29.300 6.900 13.400 5.900 8.200
LEFT S D n
n = 96 41.300 60.200 39.300 45.800 29.200 31.500
MIDR –– 11.700 30.600 10.200 16.500 8.100 10.300
MIDW –– 12.400 24.000 10.700 14.900 8.800 10.200

885
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
No match 22.000 38.200 20.000 25.600 16.600 18.400
INSTR Head 13.300 29.600 11.000 16.500 9.100 10.900
Match
End 21.900 38.100 53.900 60.000 42.700 44.900
EMOD –– 11.600 24.000 11.200 15.100 9.600 11.000
EREXP –– 19.700 28.000 20.400 22.900 18.800 20.100
STRINS S S = 128 / D = 40 / n = 1 47.000 102.000 45.300 63.400 35.300 47.600
D n S = 128 / D = 40 / n = 48 70.100 134.000 63.200 81.900 48.600 61.700

STRDEL S S = 128 / D = 40 / n = 1 46.400 93.600 39.000 53.500 34.800 44.600

D n S = 128 / D = 40 / n = 48 44.500 70.600 40.800 50.400 29.200 38.100
SIN Single precision 6.400 13.900 5.000 8.400 4.100 5.700
COS Single precision 6.100 13.500 5.200 8.000 4.000 5.600
TAN Single precision 8.300 15.000 6.100 9.200 5.100 6.700
ASIN Single precision 7.300 15.600 6.900 10.900 5.900 8.500
ACOS Single precision 8.100 16.500 7.800 11.000 6.700 8.900
ATAN Single precision 5.350 12.000 4.700 7.300 3.900 6.000
SIND Double precision 13.400 51.300 9.400 22.300 8.500 13.800
COSD Double precision 14.700 51.700 10.000 22.300 8.800 14.600
TAND Double precision 17.400 54.400 12.200 24.900 10.800 16.500
ASIND Double precision 22.600 60.300 12.800 25.900 11.600 16.600
ACOSD Double precision 19.700 60.000 12.600 25.900 11.200 16.200
ATAND Double precision 15.000 51.800 10.500 22.900 9.100 13.800
RAD Single precision 3.200 10.300 3.000 6.400 2.100 4.300
RADD Double precision 5.200 43.100 5.200 16.900 3.600 9.200
Application
DEG Single precision 3.200 11.500 2.900 6.600 2.200 4.400
instruction
DEGD Double precision 5.150 43.800 5.200 16.800 3.800 9.000
SQR Single precision 3.900 12.300 3.600 7.200 2.600 4.300
SQRD Double precision 7.000 45.700 6.200 19.100 5.200 11.000

Single S = -10 6.350 13.800 4.700 7.500 3.800 5.600

EXP S D
precision S =1 6.350 13.800 4.700 7.500 3.800 5.600

Double S = -10 15.800 52.700 9.300 22.100 8.000 13.500

EXPD S D
precision S =1 15.400 52.500 9.300 22.100 8.000 13.500

Single S =1 5.800 14.900 4.700 8.800 3.800 6.400

LOG S D
precision S = 10 7.450 16.500 6.300 10.400 5.200 7.700

Double S =1 11.000 48.900 8.600 21.100 7.700 12.500

LOGD S D
precision S = 10 12.600 51.300 10.200 23.000 9.200 14.300
RND –– 1.950 5.450 1.500 2.500 0.800 1.800
SRND –– 2.750 4.550 1.800 2.900 1.100 2.000
S =0 2.500 6.800 2.700 4.400 1.500 3.000
BSQR S D
S = 9999 6.400 15.500 6.100 12.500 5.100 8.000
S =0 2.600 6.050 2.700 4.400 1.500 3.000
BDSQR S D
S = 99999999 8.450 17.600 8.500 15.200 7.500 9.900
BSIN –– 11.500 32.800 9.500 21.500 8.100 14.500
BCOS –– 10.400 32.500 9.500 21.400 7.800 13.700
BTAN –– 12.100 33.700 10.400 22.600 9.000 13.300
BASIN –– 13.300 32.800 11.800 23.600 10.100 12.800
BACOS –– 13.400 33.700 13.100 23.700 11.100 14.100

886
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
BATAN –– 12.600 31.400 11.100 21.500 9.100 10.900
POW S1 S2 Single
precision
S1 = 12.3E+5
12.200 22.100 9.600 13.300 8.400 10.900 3
D S2 = 3.45E+0
POWD S1 S2 Double S1 = 12.3E+5
27.300 61.000 18.900 30.600 18.200 26.500
D precision S2 = 3.45E+0 A
LOG10 Single precision 8.200 16.500 6.000 9.600 5.700 8.050
LOG10D Double precision 15.100 48.000 11.900 22.900 11.100 18.600
LIMIT
DLIMIT
––
––
5.350
6.000
5.500
6.150
4.000
4.400
4.000
4.400
2.400
2.800
2.700
3.000
5
BAND –– 5.450 12.400 4.500 6.600 2.700 3.800
DBAND –– 6.050 11.900 4.800 6.900 3.300 4.600
ZONE –– 6.250 10.700 4.200 6.100 2.600 4.300 6
DZONE –– 6.000 11.900 4.700 6.900 3.000 4.600
Comparis In conductive status 8.200 25.500 7.700 14.200 6.800 10.900
on of
specified In non-conductive status 8.200 25.500 7.700 14.200 6.800 10.900
7
date
LDDT =
Comparis In conductive status 6.500 23.100 6.400 12.800 5.500 9.700
on of 8
current In non-conductive status 6.500 23.100 6.400 12.800 5.500 9.700
date
When not executed 0.240 0.160 0.038
Application Comparis In conductive status 8.200 25.500 7.300 14.000 6.500 10.700
instruction

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
on of
specified In non-conductive status 8.200 25.500 7.300 14.000 6.500 10.700
ANDDT= date
Comparis In conductive status 6.500 23.100 6.100 12.700 5.300 9.300
on of
current In non-conductive status 6.500 23.100 6.100 12.700 5.300 9.300
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.400 14.400 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.400 14.400 6.700 10.800
ORDT= date
Comparis In conductive status 6.500 23.100 6.000 12.800 5.400 9.600
on of
current In non-conductive status 6.500 23.100 6.000 12.800 5.400 9.600
date
Comparis In conductive status 8.200 25.500 7.700 14.200 6.800 10.900
on of
specified In non-conductive status 8.200 25.500 7.700 14.200 6.800 10.900
date
LDDT <>
Comparis In conductive status 6.500 23.100 6.400 12.800 5.500 9.700
on of
current In non-conductive status 6.500 23.100 6.400 12.800 5.500 9.700
date

887
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.000 6.500 10.700
on of
specified In non-conductive status 8.200 25.500 7.300 14.000 6.500 10.700
ANDDT<> date
Comparis In conductive status 6.500 23.100 6.100 12.700 5.300 9.300
on of
current In non-conductive status 6.500 23.100 6.100 12.700 5.300 9.300
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.400 14.400 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.400 14.400 6.700 10.800
ORDT<> date
Comparis In conductive status 6.500 23.100 6.000 12.800 5.400 9.600
on of
current In non-conductive status 6.500 23.100 6.000 12.800 5.400 9.600
date
Comparis In conductive status 8.200 25.500 7.700 14.200 6.800 10.900
on of
specified In non-conductive status 8.200 25.500 7.700 14.200 6.800 10.900
date
LDDT>
Comparis In conductive status 6.500 23.100 6.400 12.800 5.500 9.700
on of
current In non-conductive status 6.500 23.100 6.400 12.800 5.500 9.700
Application date
instruction When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.000 6.500 10.700
on of
specified In non-conductive status 8.200 25.500 7.300 14.000 6.500 10.700
ANDDT> date
Comparis In conductive status 6.500 23.100 6.100 12.700 5.300 9.300
on of
current In non-conductive status 6.500 23.100 6.100 12.700 5.300 9.300
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.400 14.400 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.400 14.400 6.700 10.800
ORDT> date
Comparis In conductive status 6.500 23.100 6.000 12.800 5.400 9.600
on of
current In non-conductive status 6.500 23.100 6.000 12.800 5.400 9.600
date
Comparis In conductive status 8.200 25.500 7.700 14.200 6.800 10.900
on of
specified In non-conductive status 8.200 25.500 7.700 14.200 6.800 10.900
date
LDDT<=
Comparis In conductive status 6.500 23.100 6.400 12.800 5.500 9.700
on of
current In non-conductive status 6.500 23.100 6.400 12.800 5.500 9.700
date

888
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.000 6.500 10.700
on of
3
specified In non-conductive status 8.200 25.500 7.300 14.000 6.500 10.700
ANDDT<= date
Comparis In conductive status 6.500 23.100 6.100 12.700 5.300 9.300 A
on of
current In non-conductive status 6.500 23.100 6.100 12.700 5.300 9.300
date
When not executed 0.240 0.160 0.038
5
Comparis In conductive status 8.200 25.500 7.400 14.400 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.400 14.400 6.700 10.800 6
ORDT<= date
Comparis In conductive status 6.500 23.100 6.000 12.800 5.400 9.600
on of
current In non-conductive status 6.500 23.100 6.000 12.800 5.400 9.600
7
date
Comparis In conductive status 8.200 25.500 7.700 14.200 6.800 10.900
on of 8
specified In non-conductive status 8.200 25.500 7.700 14.200 6.800 10.900
date
LDDT<
Comparis In conductive status 6.500 23.100 6.400 12.800 5.500 9.700
on of
current In non-conductive status 6.500 23.100 6.400 12.800 5.500 9.700

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
Application date
instruction When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.000 6.500 10.700
on of
specified In non-conductive status 8.200 25.500 7.300 14.000 6.500 10.700
ANDDT< date
Comparis In conductive status 6.500 23.100 6.100 12.700 5.300 9.300
on of
current In non-conductive status 6.500 23.100 6.100 12.700 5.300 9.300
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.400 14.400 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.400 14.400 6.700 10.800
ORDT< date
Comparis In conductive status 6.500 23.100 6.000 12.800 5.400 9.600
on of
current In non-conductive status 6.500 23.100 6.000 12.800 5.400 9.600
date
Comparis In conductive status 8.200 25.500 7.700 14.200 6.800 10.900
on of
specified In non-conductive status 8.200 25.500 7.700 14.200 6.800 10.900
date
LDDT>=
Comparis In conductive status 6.500 23.100 6.400 12.800 5.500 9.700
on of
current In non-conductive status 6.500 23.100 6.400 12.800 5.500 9.700
date

889
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.000 6.500 10.700
on of
specified In non-conductive status 8.200 25.500 7.300 14.000 6.500 10.700
ANDDT>= date
Comparis In conductive status 6.500 23.100 6.100 12.700 5.300 9.300
on of
current In non-conductive status 6.500 23.100 6.100 12.700 5.300 9.300
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.400 14.400 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.400 14.400 6.700 10.800
ORDT>= date
Comparis In conductive status 6.500 23.100 6.000 12.800 5.400 9.600
on of
current In non-conductive status 6.500 23.100 6.000 12.800 5.400 9.600
date
Comparis In conductive status 8.200 25.500 7.600 14.000 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.600 14.000 6.700 10.800
date
LDTM=
Comparis In conductive status 6.500 23.100 6.200 12.700 5.400 9.500
on of
current In non-conductive status 6.500 23.100 6.200 12.700 5.400 9.500
Application date
instruction When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.200 13.900 6.300 10.800
on of
specified In non-conductive status 8.200 25.500 7.200 13.900 6.300 10.800
ANDTM= date
Comparis In conductive status 6.500 23.100 5.900 12.500 5.100 9.500
on of
current In non-conductive status 6.500 23.100 5.900 12.500 5.100 9.500
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.100 6.600 10.800
on of
specified In non-conductive status 8.200 25.500 7.300 14.100 6.600 10.800
ORTM= date
Comparis In conductive status 6.500 23.100 6.000 12.700 5.300 9.500
on of
current In non-conductive status 6.500 23.100 6.000 12.700 5.300 9.500
date
Comparis In conductive status 8.200 25.500 7.600 14.000 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.600 14.000 6.700 10.800
date
LDTM<>
Comparis In conductive status 6.500 23.100 6.200 12.700 5.400 9.500
on of
current In non-conductive status 6.500 23.100 6.200 12.700 5.400 9.500
date

890
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.200 13.900 6.300 10.800
on of
3
specified In non-conductive status 8.200 25.500 7.200 13.900 6.300 10.800
ANDTM<> date
Comparis In conductive status 6.500 23.100 5.900 12.500 5.100 9.500 A
on of
current In non-conductive status 6.500 23.100 5.900 12.500 5.100 9.500
date
When not executed 0.240 0.160 0.038
5
Comparis In conductive status 8.200 25.500 7.300 14.100 6.600 10.800
on of
specified In non-conductive status 8.200 25.500 7.300 14.100 6.600 10.800 6
ORTM<> date
Comparis In conductive status 6.500 23.100 6.000 12.700 5.300 9.500
on of
current In non-conductive status 6.500 23.100 6.000 12.700 5.300 9.500
7
date
Comparis In conductive status 8.200 25.500 7.600 14.000 6.700 10.800
on of 8
specified In non-conductive status 8.200 25.500 7.600 14.000 6.700 10.800
date
LDTM>
Comparis In conductive status 6.500 23.100 6.200 12.700 5.400 9.500
on of
current In non-conductive status 6.500 23.100 6.200 12.700 5.400 9.500

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
Application date
instruction When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.200 13.900 6.300 10.800
on of
specified In non-conductive status 8.200 25.500 7.200 13.900 6.300 10.800
ANDTM> date
Comparis In conductive status 6.500 23.100 5.900 12.500 5.100 9.500
on of
current In non-conductive status 6.500 23.100 5.900 12.500 5.100 9.500
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.100 6.600 10.800
on of
specified In non-conductive status 8.200 25.500 7.300 14.100 6.600 10.800
ORTM> date
Comparis In conductive status 6.500 23.100 6.000 12.700 5.300 9.500
on of
current In non-conductive status 6.500 23.100 6.000 12.700 5.300 9.500
date
Comparis In conductive status 8.200 25.500 7.600 14.000 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.600 14.000 6.700 10.800
date
LDTM<=
Comparis In conductive status 6.500 23.100 6.200 12.700 5.400 9.500
on of
current In non-conductive status 6.500 23.100 6.200 12.700 5.400 9.500
date

891
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.200 13.900 6.300 10.800
on of
specified In non-conductive status 8.200 25.500 7.200 13.900 6.300 10.800
ANDTM<= date
Comparis In conductive status 6.500 23.100 5.900 12.500 5.100 9.500
on of
current In non-conductive status 6.500 23.100 5.900 12.500 5.100 9.500
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.100 6.600 10.800
on of
specified In non-conductive status 8.200 25.500 7.300 14.100 6.600 10.800
ORTM<= date
Comparis In conductive status 6.500 23.100 6.000 12.700 5.300 9.500
on of
current In non-conductive status 6.500 23.100 6.000 12.700 5.300 9.500
date
Comparis In conductive status 8.200 25.500 7.600 14.000 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.600 14.000 6.700 10.800
date
LDTM<
Comparis In conductive status 6.500 23.100 6.200 12.700 5.400 9.500
on of
current In non-conductive status 6.500 23.100 6.200 12.700 5.400 9.500
Application date
instruction When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.200 13.900 6.300 10.800
on of
specified In non-conductive status 8.200 25.500 7.200 13.900 6.300 10.800
ANDTM< date
Comparis In conductive status 6.500 23.100 5.900 12.500 5.100 9.500
on of
current In non-conductive status 6.500 23.100 5.900 12.500 5.100 9.500
date
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.300 14.100 6.600 10.800
on of
specified In non-conductive status 8.200 25.500 7.300 14.100 6.600 10.800
ORTM< date
Comparis In conductive status 6.500 23.100 6.000 12.700 5.300 9.500
on of
current In non-conductive status 6.500 23.100 6.000 12.700 5.300 9.500
date
Comparis In conductive status 8.200 25.500 7.600 14.000 6.700 10.800
on of
specified In non-conductive status 8.200 25.500 7.600 14.000 6.700 10.800
date
LDTM>=
Comparis In conductive status 6.500 23.100 6.200 12.700 5.400 9.500
on of
current In non-conductive status 6.500 23.100 6.200 12.700 5.400 9.500
date

892
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
When not executed 0.240 0.160 0.038
Comparis In conductive status 8.200 25.500 7.200 13.900 6.300 10.800
on of
3
specified In non-conductive status 8.200 25.500 7.200 13.900 6.300 10.800
ANDTM>= date
Comparis In conductive status 6.500 23.100 5.900 12.500 5.100 9.500 A
on of
current In non-conductive status 6.500 23.100 5.900 12.500 5.100 9.500
date
When not executed 0.240 0.160 0.038
5
Comparis In conductive status 8.200 25.500 7.300 14.100 6.600 10.800
on of
specified In non-conductive status 8.200 25.500 7.300 14.100 6.600 10.800 6
ORTM>= date
Comparis In conductive status 6.500 23.100 6.000 12.700 5.300 9.500
on of
current In non-conductive status 6.500 23.100 6.000 12.700 5.300 9.500
7
date
SM750 = Point No.1 < S1 < Point No.2 14.900 50.100 12.500 29.200 11.900 23.000
ON Point No.9 < S1 < Point No.10 15.800 50.900 13.200 29.100 12.100 23.000 8
SCL S1 S2 D
SM750 = Point No.1 < S1 < Point No.2 13.900 53.100 12.100 28.900 10.900 22.200
OFF Point No.9 < S1 < Point No.10 16.600 56.600 13.900 30.900 12.700 23.900

SM750 = Point No.1 < S1 < Point No.2 13.400 52.400 12.500 29.200 11.900 23.000

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
Application DSCL S1 S2 ON Point No.9 < S1 < Point No.10 14.200 54.100 13.200 29.100 12.100 23.000
instruction
D SM750 = Point No.1 < S1 < Point No.2 12.300 53.200 12.100 28.900 10.900 22.200
OFF Point No.9 < S1 < Point No.10 15.000 57.600 13.900 30.900 12.700 23.900

SM750 = Point No.1 < S1 < Point No.2 14.200 53.300 13.400 29.700 11.800 23.300

SCL2 S1 S2 ON Point No.9 < S1 < Point No.10 14.900 55.000 12.900 29.500 12.100 23.300
D SM750 = Point No.1 < S1 < Point No.2 15.000 53.500 12.200 29.100 11.000 22.600
OFF Point No.9 < S1 < Point No.10 16.300 56.400 13.900 30.700 12.600 23.900

SM750 = Point No.1 < S1 < Point No.2 13.400 52.700 13.400 29.700 11.800 23.300

DSCL2 S1 S2 ON Point No.9 < S1 < Point No.10 14.200 54.300 12.900 29.500 12.100 23.300
D SM750 = Point No.1 < S1 < Point No.2 12.300 53.200 12.200 29.100 11.000 22.600
OFF Point No.9 < S1 < Point No.10 15.000 57.600 13.900 30.700 12.600 23.900
RSET Standard RAM 6.800 26.900 3.500 11.100 2.700 5.900
No digit increase 15.100 41.200 9.000 17.900 4.600 7.000
DATE -
Digit increase 15.100 41.200 10.000 19.200 4.600 6.500
SECOND –– 5.800 20.500 4.600 9.800 2.200 3.400
HOUR –– 6.200 22.500 4.600 10.300 2.400 4.300
SD memory card to standard ROM –– –– 690.800 736.470 1146.900 1179.500
QCDSET
Standard ROM to SD memory card –– –– 6981.400 7232.070 5613.900 5653.500
DATERD –– 5.600 27.800 4.600 11.200 2.500 4.200
DATEWR –– 7.800 42.100 6.500 19.300 4.100 8.900
No digit increase 14.200 41.200 10.000 19.400 4.700 6.600
DATE +
Digit increase 14.200 41.200 9.900 19.700 4.600 6.500
S.DATERD –– 9.250 51.000 7.800 22.500 4.800 7.100

893
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Min. Max. Min. Max. Min. Max.
No digit increase 16.800 75.400 15.100 34.100 7.400 10.000
S.DATE +
Digit increase 16.800 75.400 15.000 34.100 7.400 10.000
No digit increase 17.600 75.300 13.700 33.600 7.400 10.300
S.DATE -
Digit increase 16.900 75.300 13.700 33.600 7.500 10.200
PSTOP –– 82.200 199.000 67.600 104.100 56.600 79.800
POFF –– 82.600 198.000 66.800 103.600 57.200 79.800
PSCAN –– 83.600 200.000 67.900 104.800 60.100 79.900
WDT –– 2.900 12.000 1.600 4.800 1.100 2.400
DUTY –– 7.700 27.500 4.900 10.100 4.800 9.600
TIMCHK –– 5.350 24.500 4.100 9.100 3.500 4.700
File register of standard RAM 4.100 4.200 2.900 3.300 1.800 2.100
ZRRDB
File register of SRAM card –– –– –– –– –– ––
File register of standard RAM 5.400 5.500 3.600 3.800 2.400 2.700
ZRWRB
Application File register of SRAM card –– –– –– –– –– ––
instruction ADRSET –– 2.400 6.650 2.200 4.800 2.100 2.600
ZPUSH –– 9.200 20.500 8.000 12.000 5.800 7.500
ZPOP –– 9.000 15.5000 8.200 10.900 5.800 6.400
UNIRD n1 D n2 = 1 6.000 33.100 5.000 14.100 3.700 8.000
n2 n2 = 16 16.500 43.600 13.600 22.600 12.200 16.600
TYPERD –– 43.400 139.800 32.100 67.600 29.500 52.500
TRACE Start 174.000 174.000 58.100 58.100 43.800 44.700
TRACER –– 5.100 15.500 6.100 6.100 4.500 4.500
Number of displayed characters = 1 –– –– 7.300 17.000 7.000 13.500
UMSG
Number of displayed characters = 32 –– –– 16.500 26.300 14.300 21.300
SP.FWRITE –– –– –– 81.000 81.800 63.500 64.100
SP.FREAD –– –– –– 81.100 81.700 61.600 62.500
SP.DEVST –– 125.000 125.000 50.100 50.100 39.400 39.400
S.DEVLD –– 18.300 36.700 12.000 27.600 10.000 17.000

894
 Processing Time (µs)
L06CPU,
L06CPU-P,
L02SCPU, L02CPU, L26CPU,
3
Category Instruction Condition (Device)
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT 2
Min. Max. Min. Max. Min. Max.
When mounting CC-Link module (master
29.400 91.700 23.700 48.500 19.300 26.000
station side)
When mounting CC-Link module (local
3
29.500 91.600 23.700 48.500 19.100 26.200
station side)
S.ZCOM
When selecting CC-Link IE Field Network
79.900 214.000 31.500 72.000 31.000 58.000
refresh only (master station side) A
When selecting CC-Link IE Field Network
79.900 214.000 31.500 72.000 31.000 58.000
refresh only (local station side)
S.RTREAD
S.RTWRITE
––
––
12.600
13.300
65.000
67.100
8.500
9.000
27.000
28.000
7.400
8.300
19.000
19.800
5
When the refresh device as the write
–– –– 90.100 98.400 98.200 118.100
S.REFDVWR target exists at Transfer 1
Data link B When the refresh device as the write
–– –– 546.600 559.800 577.900 596.400
6
instruction target exists at Transfer 256
When the refresh device as the write
–– –– 88.600 97.700 97.200 116.800
S.REFDVWR
W
target exists at Transfer 1
When the refresh device as the write
7
–– –– 544.900 554.100 588.500 606.400
target exists at Transfer 256
When the refresh device as the read
S.REFDVRD target exists at Transfer 1
–– –– 89.500 97.900 96.000 117.300
8
B When the refresh device as the read
–– –– 545.800 559.000 577.000 595.500
target exists at Transfer 256
When the refresh device as the read
–– –– 88.500 97.700 95.800 116.800
S.REFDVRD target exists at Transfer 1

Appendix 1.5Operation Processing Time of LCPU

Appendix 1OPERATION PROCESSING TIME
W When the refresh device as the read
–– –– 545.100 554.000 589.600 606.100
target exists at Transfer 256
Communic
ation
protocol S(P).CPRTCL ― 138.000 192.600 68.600 83.100 50.700 60.300
function
instruction

Remark
For the instructions for which a leading edge instruction ( P) is not described, the processing time is the same as an ON
execution instruction.
Example WORDP instruction, TOP instruction etc.

895
(2) Table of the time to be added when file register, extended data register, extended link register, module access device,
and link direct device are used
(a) When using L02SCPU, L02SCPU-P, L02CPU, L02CPU-P, L06CPU, L06CPU-P, L26CPU, L26CPU-P, L26CPU-BT,
and L26CPU-PBT
Processing Time (µs)
L06CPU,
L06CPU-P,
Device Specification
Device name Data L02SCPU, L02CPU, L26CPU,
Location
L02SCPU-P L02CPU-P L26CPU-P,
L26CPU-BT,
L26CPU-PBT
Source 0.100 0.100 0.048
Bit
Destination 0.220 0.220 0.038
When standard Source 0.100 0.100 0.048
File register (R) Word
RAM is used Destination 0.100 0.100 0.038
Source 0.200 0.200 0.095
Double word
Destination 0.200 0.200 0.086
Source 0.160 0.140 0.057
File register (ZR), Bit
Destination 0.320 0.280 0.048
Extended data
When standard Source 0.160 0.140 0.057
register (D), Word
RAM is used Destination 0.160 0.140 0.048
Extended link
Source 0.260 0.240 0.105
register (W) Double word
Destination 0.260 0.240 0.095
Source 15.000 11.700 11.200
Bit
Destination 21.300 15.400 15.300
Source 10.600 9.460 9.410
Module access device (Un\G ) Word
Destination 33.000 19.000 19.000
Source 24.200 11.000 10.900
Double word
Destination 34.800 18.800 18.700
Source 70.900 41.600 37.900
Bit
Destination 120.100 63.200 58.100
Source 68.400 40.700 37.500
Link direct device (Jn\ ) Word
Destination 53.700 31.700 30.800
Source 75.600 49.400 43.400
Double word
Destination 58.900 39.600 37.300

896
Appendix 2 CPU PERFORMANCE COMPARISON
3
Appendix 2.1 Comparison of Q, LCPU with AnNCPU, AnACPU, and
AnUCPU 2
Appendix 2.1.1 Usable devices
Device name QCPU LCPU AnUCPU AnACPU AnNCPU
3
Q02, Q02H, Q06H,
Q12H, Q25H, Q02PH,
Q06PH, Q12PH,
Q25PH, Q12PRH,
A
L02SCPU,
Q25PRH, Q03UD(E),
L02SCPU-P,
Q03UDV,
L02CPU,
Q04UD(E)H, A2U:
Q00J: Q00UJ: Q04UDV,
L02CPU-P:
1024 points
512 points
A1N: 256 points
5
256 points 256 points Q06UD(E)H, A2U-S1: A2A: 512 points
A2N: 512 points
Q00: Q00U: Q06UDV, 1024 points A2A-S1:
Number of I/O points*9 L06CPU, A2N-S1:
1024 points 1024 points Q10UD(E)H, A3U: 1024 points
Q01: Q01U: Q13UD(E)H,
L06CPU-P,
L26CPU,
2048 points A3A: 2048 points
1024 points
A3N: 2048 points
6
1024 points 1024 points Q13UDV, A4U:
L26CPU-P,
Q20UD(E)H, 4096 points
L26CPU-BT,
Q26UD(E)H,
L26CPU-PBT:
Q26UDV, Q50UDEH,
Q100UDEH:
4096 points 7
40096 points

Number of I/O device

Q02U: 2048 points
Same with I/O devices points of each
8
*1
2048 points 8192 points*1 8192 points*1 8192 points
points*8 CPU
Internal relay 8192 points*1 8192 points*1
Total 2048 points
*1 *1
Latch relay 2048 points 8192 points 8192 points*1 Total 8192 points
Sequence

Appendix 2.1Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU

Appendix 2CPU PERFORMANCE COMPARISON
Step –– –– ––
program
relay
SFC 2048 points*6 8192 points 8192 points ––
Annunciator 1024 points*1 2048 points*1 2048 points*1 2048 points 2048 points 256 points
Edge relay 1024 points*1 2048 points*1 2048 points*1 ––
Link relay 2048 points*1 8192 points*1 8192 points*1 8192 points 4096 points 1024 points
Link special relay 1024 points 2048 points 2048 points 56 points
Timer 512 points*1 2048 points*1 2048 points*1
Total 2048 points Total 256 points
Retentive timers 0 points*1 0 points*1
Counter 512 points*1 1024 points*1 1024 points*1 1024 points 256 points
Data register *1 *1 *1 8192 points 6144 points 1024 points
11136 points 12288 points 12288 points
Link register 2048 points*1 8192 points*1 8192 points*1 8192 points 4096 points 1024 points
Link special register 1024 points 2048 points 2048 points 56 points
16 points
Function input 16 points (FX0 to FXF)*7 ––
(FX0 to FXF)*7
16 points
Function output 16 points (FY0 to FYF)*7 ––
(FY0 to FYF)*7
Special relay 1000 points 2048 points 2048 points 256 points
5 points
Function register 5 points (FD0 to FD4) ––
(FD0 to FD4)
Special register 1000 points 2048 points 2048 points 256 points
Designated by
Link direct device Designated by J \ ––
J \
Intelligent function Designated by
Designated by U \G ––
module device U \G

897
 Device name QCPU LCPU AnUCPU AnACPU AnNCPU
Other than Universal model QCPU:
10 points 16 points (Z0 to Z15) 20 points
Index Z 7 points (Z, Z1 to Z6) 1 point (Z)
(Z0 to Z9) Universal model QCPU: 20 points (Z0 to Z19)
register (Z0 to Z19)
V*2 –– –– 7 points (V, V1 to V6) 1 point (V)
32768 points/ 32768 points/
32768 points/block
File register block*5 block 8192 points/block(R0 to R8191)
(R0 to R32767)*10
(R0 to R32767) (R0 to R32767)

Accumulator*3 –– –– 2 points
Nesting 15 points 15 points 8 points
Pointer 300 points 512 points 4096 points 4096 points 256 points
Interrupt pointers 128 points 128 points 256 points 256 points 32 points
SFC blocks 126*6 320 points 320 points ––
SFC transition devices –– 512 points 512 points ––
Decimal constants K - 2147483648 to K2147483647
Hexadecimal constants H0 to HFFFFFFFF
Real number
E ± 1.17550-38 to E ± 3.40282+38 ––
constants*6
Character string "QnACPU", "ABCD"*4 ––

*1: The number of device points can be changed at the parameters.

*2: CPU uses V as an edge relay.
*3: Instructions that used accumulators with the AnNCPU, AnACPU, and AnUCPU have different formats with the QCPU.
*4: Can only be used by the $MOV instruction with the Q00JCPU, Q00CPU, and Q01CPU.
*5: The Q00JCPU does not have file registers.
*6: Applicable to products with the first 5 digits of the serial number 04122 or higher (Q00JCPU, Q00CPU, and QCPU).
*7: Each 5 points of FX0 to FX4 and FY0 to FY4 can be used on the programs.
*8: The number of points that can be used on the programs
*9: The number of accessible points to actual I/O modules
*10: The Q00UJCPU does not have file registers.

Appendix 2.1.2 I/O control mode

I/O control mode QCPU LCPU AnUCPU AnACPU AnNCPU

Refresh mode *2

Partial refresh instructions

Direct Dedicated instruction*1 –– –– ––
I/O method Direct access input –– –– ––
Direct access output –– –– ––
Direct mode –– –– –– –– *2

Symbol in table : Usable, ––: Unusable

*1: The DOUT, DSET, and SRST instructions are direct output dedicated instructions.
There are no dedicated instructions for direct input.
*2: Switching between the refresh mode and direct mode is conducted with an AnNCPU DIP switch.

898
 Appendix 2.1.3 Data that can be used by instructions

Setting Data QCPU LCPU AnUCPU AnACPU AnNCPU 3

Bit device

Bit data
Word device (Bit specification (Bit specification –– –– –– 2
required) required)

Word data
Bit device (Digit specification (Digit specification (Digit specification (Digit specification (Digit specification
required) required) required) required) required)
3
Word device

Bit device (Digit specification (Digit specification (Digit specification (Digit specification (Digit specification
A
Double word data
required) required) required) required) required)
Word device
Real number data *1 –– 5
Character string data *2 –– –– ––
Symbols in table : Usable, –– : Unusable
*1: Applicable to products with the first 5 digits of the serial number 04122 or higher (Q00JCPU, Q00CPU, and Q01CPU). 6
*2: Usable with only the MOV instruction for the Q00JCPU, Q00CPU, and Q01CPU.

Appendix 2.1Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU

Appendix 2CPU PERFORMANCE COMPARISON

899
 Appendix 2.1.4 Timer comparison

Function QCPU/LCPU AnUCPU AnACPU AnNCPU

100ms (default value)
Measurement Change of measurement unit at the parameter is
Fixed at 100ms
unit enabled.
Low speed timer QCPU/LCPU: 1 to 1000ms (1ms unit)

Designation K100 K100

method T0 T0

10ms (default value)

Change of measurement unit at the parameter is
Measurement enabled.
Fixed at 10ms
unit QnUCPU/LCPU: 0.01 to 100ms (0.01ms unit)
QCPU(Other than QnUCPU)
: 0.1 to 100ms (0.1ms unit)
High speed timer
High speed timer specification
K100
H K100 T200
Designation T0
method
High speed timer setting:
High speed timer setting:
Conducted at parameters
Conducted by sequence program
Measurement
Same measurement unit as low speed timer Fixed at 100ms
unit
Retentive timers
Designation K100 K100
method ST0 T0

Measurement
Same measurement unit as high speed timer
unit
High speed timer specification
High speed H K100 None
retentive timer Designation ST0
method
High speed timer setting:
Conducted by sequence program
Setting range for set values 1 to 32767 1 to 32767
Processing for set value 0 Momentarily ON No maximum (does not time out)
Contact Enabled (only Z0 and Z1 are usable) Enabled Disabled
Coil Enabled (only Z0 and Z1 are usable) Disabled Disabled
Index modification
Set value *1 Disabled Disabled
Enabled (Z0 to Z15 are usable)
Present value Enabled (Z0 to Z15 are usable)*1 Enabled Enabled
Update processing for present
value When OUT Tn instruction is executed When END processing is done
Contact ON/OFF processing
*1: The Q00J/Q00/Q01CPU can use Z0 to Z9.
The Universal model QCPU/LCPU can use Z0 to Z19.
(1) Cautions on using timers
QCPU, LCPU updates the present value of timers and turns ON/OFF the contacts of them at the execution of OUT T
instruction.
Therefore, if "Present value Set value" when the timer coil is turned ON, the contact of that timer is turned ON.
When creating a program in which the operation of the timer contact triggers the operation of another timer, create the
program for the timer that operates later first.
In the following cases, all timers go ON at the same scan if the program is created in the order the timers operate.
• With high speed timers, if the set value is smaller than a scan time.
• With slow timers, if "1" is set.

900
 Example

• For timers T0 to T2, the program is created in the order the timer operates later.
3
T1 K1
T2 T2 timer starts measurement from the next scan after turning the contact of T1 ON.

T0 K1 2
T1 T1 timer starts measurement from the next scan after turning the contact of T0 ON.

X0 K1
T0 T0 timer starts measurement when X0 is turned ON. 3

• For timers T0 to T2, the program is created in the order of timer operation. A
X0 K1
T0 T0 timer starts measurement when X0 is turned ON.
5
T0 K1
T1

T1 K1
Contacts of T1 and T2 timers are turned ON when contact of T0 is turned ON.
6
T2

Appendix 2.1.5 Comparison of counters 7

Function QCPU/LCPU AnUCPU AnACPU AnNCPU

K100 K100 8
Designation method C0 C0

Contact • Enabled (only Z0 and Z1 are usable) • Enabled • Disabled

Coil • Enabled (only Z0 and Z1 are usable) • Disabled • Disabled
Index modification
Set value • Disabled • Disabled • Disabled

Appendix 2.1Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU

Appendix 2CPU PERFORMANCE COMPARISON
Present value • Enabled (Z0 to Z15 are usable)*1 • Enabled • Enabled
Update processing for present value
• When OUT Cn instruction is executed • When END processing is done
Contact ON/OFF processing
*1: The Q00J/Q00/Q01CPU can use Z0 to Z9.
The Universal model QCPU/LCPU can use Z0 to Z19.

Appendix 2.1.6 Comparison of display instructions

Instruction QCPU/LCPU AnUCPU AnACPU AnNCPU

• When SM701 is OFF: Output continued until • When M9049 is OFF: Output continued until
PR*1 00H encountered 00H encountered
• When SM701 is ON: 16 characters output • When M9049 is ON: 16 characters output
• When SM701 is OFF: 32-character comment
output
PRC*1 16-character comment output
• When SM701 is ON: Upper 16 characters
output
*1: Unusable for the Q00J/Q00/Q01CPU.

901
 Appendix 2.1.7 Instructions whose designation format has been changed
(Except dedicated instructions for AnACPU and AnUCPU)
Because the QCPU, LCPU does not have accumulators (A0, A1), the format of AnUCPU, AnACPU and AnNCPU instructions
that used accumulators has been changed.

QCPU/LCPU AnUCPU/AnACPU/AnNCPU
Function
Instruction Format Remarks Instruction Format Remarks
• Rotation data are set at
ROR D n • D : Rotation data ROR n A0.
16-bit • Rotation data are set at
• D : Rotation data
rotation to right A0.
RCR D n • SM700 is used for RCR n • M9012 is used for
carry flag.
carry flag.
• Rotation data are set at
ROL D n • D : Rotation data ROL n A0.
16-bit • Rotation data are set at
• D : Rotation data
rotation to left A0.
RCL D n • SM700 is used for RCL n • M9012 is used for
carry flag.
carry flag.
• Rotation data are set at
DROR D n • D : Rotation data DROR n A0 and A1.
32-bit • Rotation data are set at
• D : Rotation data
rotation to right A0 and A1.
DRCR D n • SM700 is used for DRCR n • M9012 is used for
carry flag.
carry flag.
• Rotation data are set at
DROL D n • D : Rotation data DROL n A0 and A1.
32-bit • Rotation data are set at
• D : Rotation data
rotation to left A0 and A1.
DRCL D n • SM700 is used for DRCL n • M9012 is used for
carry flag.
carry flag.
• Search results are
• Search results are
16-bit data search SER S1 S2 D n stored at the D and SER S1 S2 n stored at A0 and A1.
D+1 devices.
• Search results are
• Search results are
32-bit data search DSER S1 S2 D n stored at the D and DSER S1 S2 n stored at A0 and A1.
D+1 devices.
16-bit • Check results are • Check results are
data bit check SUM S D stored at the D device. SUM S stored at A0.
16-bit • Check results are • Check results are
data bit check DSUM S D stored at the D device. DSUM S stored at A0.
• Dedicated instruction is • Only when M9052 is
Partial refresh RFS D n SEG D n
added. ON
8-character ASCII
$MOV (Character string) D –– ASC (Character string) D ––
conversion
• No dedicated
Carry flag set SET SM700 STC ––
instruction
• No dedicated
Carry flag reset RST SM700 CLC ––
instruction
• Dedicated instruction is • P255: END instruction
Jump to END instruction GOEND CJ P255
added. designation

CHKST • The CHKST instruction CJ Pn

CHK instruction*1 ––
is added.
CHK P254 CHK
*1: Unusable for the Q00J/Q00/Q01CPU/Universal model QCPU/LCPU.

902
 Appendix 2.1.8 AnACPU and AnUCPU dedicated instructions
(1) Method of expression of dedicated instructions
Dedicated instructions based on the LEDA, LEDB, LEDC, SUB, and LEDR instructions, that are used with the AnACPU
3
or AnUCPU have been changed for the same format as the basic instructions and the application instructions for the
QCPU, LCPU.
The instructions that cannot be converted due to the absence of the corresponding instructions in the QCPU, LCPU are
2
converted into OUT SM1255/OUT SM999 (for the Q00J/Q00/Q01CPU).
The instructions that have been converted into OUT SM1255/OUT SM999 should be replaced by other instructions or
deleted.
3
QCPU AnUCPU/AnACPU

Command A
LEDA(B) Instruction name

LEDC/SUB S
Command
LEDC/SUB D
5
Instruction name S D n
LEDC/SUB n

LEDR 6
: S, D, and n indicate data used by instructions.

7
(2) Dedicated instructions whose names have been changed
Dedicated instructions for the AnUCPU or AnACPU which have the same instruction name as is used for basic
instructions and application instructions have undergone name changes in the QCPU, LCPU. 8
Function QCPU/LCPU AnUCPU/AnACPU
Floating point addition E+ ADD
Floating point subtraction E- SUB
Floating point multiplication E* MUL

Appendix 2.1Comparison of Q, LCPU with AnNCPU, AnACPU, and AnUCPU

Appendix 2CPU PERFORMANCE COMPARISON
Floating point division E/ DIV
Data dissociation NDIS DIS
Data association NUNI UNI
Updating check patterns CHKCIR*1, CHKEND*1 CHK, CHKEND

*1: Not available on Q00J/Q00/Q01CPU/Universal model QCPU/LCPU.

903
Appendix 3 APPLICATION PROGRAM EXAMPLES

Appendix 3.1 Concept of Programs which Perform Operations of a nth

power of X, a nth root X

(1) Concept of programs which perform operations of Xn

Xn can be operated using e(nlogeX).
For example, the operation of 101.2 is e(1.2 loge10), which is represented in the form of a sequence program as shown
below.

Converts 10 into a real number format data

and stores the result in D0 and D1.
Executes Loge10 operation and stores the
result in D2 and D3.
Converts 12 into a real number format data
and stores the result into D4 and D5.
Divides D4 and D5 (12) by D0 and D1 (10),
and stores the result (1, 2) in D6 and D7 (1, 2).
Multiplies D2 and D3 (Loge10) by D6 and
D7 (1, 2) and stores the result in D8 and D9.
Executes Loge(D8, D9) operation and stores
the result in D10 and D11.

n
(2) Concept of program which performs operation of X
1
n
X can be operated using e( n logeX) .
3 ( 13 log e10)
For example, the operation of 10 is e , which is represented in the form of a sequence program as shown
below.

Converts 10 into a real number format data

and stores the result in D20 and D21.
Executes Loge10 operation and stores the
result in D22 and D23.
Converts 3 into a real number type data
and stores the result in D24 and D25.
Divides D22 and D23 (Loge10) by D24 and
D25 (3) and stores the result in D26 and D27.
Executes Loge(D26, D27) operation and
stores the result in D28 and D29.

904
 A
3

Appendix 3APPLICATION PROGRAM EXAMPLES

Appendix 3.1Concept of Programs which Perform Operations of a nth power of X, a nth root X

905
Memo
 INDEX
0 to 9 BCD 8-digit multiplication and division operations
......................................... 215
16-bit BIN data decrement . . . . . . . . . . . . . . . . . . . . 237 BCD 8-digit square roots . . . . . . . . . . . . . . . . . . . . . 555
16-bit BIN data increment . . . . . . . . . . . . . . . . . . . . . 237 BCD type arc cosine operation . . . . . . . . . . . . . . . . 564
16-bit data check. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 BCD type arc sine operations . . . . . . . . . . . . . . . . . 562
16-bit data exchanges. . . . . . . . . . . . . . . . . . . . . . . . 281 BCD type arc tangent operations . . . . . . . . . . . . . . . 566
16-bit data exclusive NOR operations. . . . . . . . . . . . 335 BCD type COS operations . . . . . . . . . . . . . . . . . . . . 559
16-bit data negation transfer . . . . . . . . . . . . . . . . . . . 271 BCD type SIN operation. . . . . . . . . . . . . . . . . . . . . . 557
16-bit data search . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 BCD type TAN operation . . . . . . . . . . . . . . . . . . . . . 561
16-bit data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 265 BIN 16 bit-data sort operations . . . . . . . . . . . . . . . . 388
16-bit exclusive OR operations . . . . . . . . . . . . . . . . . 329 BIN 16-bit addition and subtraction operations . . . . 197
1-bit shift to left of n-bit data . . . . . . . . . . . . . . . . . . . 352 BIN 16-bit block data comparisons . . . . . . . . . . . . . 191
1-bit shift to right of n-bit data . . . . . . . . . . . . . . . . . . 352 BIN 16-bit data block addition and subtraction
1-word shift to left of n-word data . . . . . . . . . . . . . . . 357 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229
1-word shift to right of n-word data . . . . . . . . . . . . . . 357 BIN 16-bit data comparisons . . . . . . . . . . . . . . . . . . 181
32-bit BIN data decrement . . . . . . . . . . . . . . . . . . . . 238 BIN 16-bit dead band controls . . . . . . . . . . . . . . . . . 570
32-bit BIN data increment . . . . . . . . . . . . . . . . . . . . . 238 BIN 16-bit multiplication and division operations . . . 203
32-bit data check. . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 BIN 32 bit-data sort operations . . . . . . . . . . . . . . . . 388
32-bit data exchanges. . . . . . . . . . . . . . . . . . . . . . . . 281 BIN 32-bit addition and subtraction operations . . . . 200
32-bit data exclusive NOR operations. . . . . . . . . . . . 335 BIN 32-bit block data comparisons . . . . . . . . . . . . . 193
32-bit data negation transfer . . . . . . . . . . . . . . . . . . . 271 BIN 32-bit data block addition and subtraction
32-bit data search . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
32-bit data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . 265 BIN 32-bit data comparisons . . . . . . . . . . . . . . . . . . 182
32-bit exclusive OR operations . . . . . . . . . . . . . . . . . 329 BIN 32-bit dead band controls . . . . . . . . . . . . . . . . . 570
4-bit dissociation of 16-bit data . . . . . . . . . . . . . . . . . 375 BIN 32-bit multiplication and division operations . . . 205
4-bit linking of 16-bit data . . . . . . . . . . . . . . . . . . . . . 376 Bit device output inversion . . . . . . . . . . . . . . . . . . . . 163
7-segment decode . . . . . . . . . . . . . . . . . . . . . . . . . . 373 Bit device shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
Bit processing instructions . . . . . . . . . . . . . . . . . . . . 362
A Bit reset for word devices. . . . . . . . . . . . . . . . . . . . . 362
Bit set for word devices . . . . . . . . . . . . . . . . . . . . . . 362
Addition and subtraction of floating-point data Bit tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363
(Double precision). . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Block 16-bit data exchanges . . . . . . . . . . . . . . . . . . 282
Addition and subtraction of floating-point data Block 16-bit data transfer . . . . . . . . . . . . . . . . . . . . . 274
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Block exclusive NOR operations . . . . . . . . . . . . . . . 339
AnACPU and AnUCPU dedicated instructions . . . . . 903 Block exclusive OR operations . . . . . . . . . . . . . . . . 333
Annunciator output . . . . . . . . . . . . . . . . . . . . . . . . . . 154 Block logical products . . . . . . . . . . . . . . . . . . . . . . . 321
Arc cosine operation on floating-point data Block logical sum operations . . . . . . . . . . . . . . . . . . 327
(Double precision). . . . . . . . . . . . . . . . . . . . . . . . . . . 528 Block switching method . . . . . . . . . . . . . . . . . . . . . . 128
Arc cosine operation on floating-point data Buffer memory access instruction . . . . . . . . . . . . . . 439
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 527
Arc sine operation on floating-point data
(Double precision). . . . . . . . . . . . . . . . . . . . . . . . . . . 525 C
Arc sine operation on floating-point data Calculation of averages for 16-bit data . . . . . . . . . . 393
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 Calculation of averages for 32-bit data . . . . . . . . . . 393
Arc tangent operation on floating-point data Calculation of totals for 16-bit data. . . . . . . . . . . . . . 391
(Double precision). . . . . . . . . . . . . . . . . . . . . . . . . . . 532 Calculation of totals for 32-bit data. . . . . . . . . . . . . . 392
Arc tangent operation on floating-point data Changing check format of CHK . . . . . . . . . . . . . . . . 457
(Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Character string data comparisons . . . . . . . . . . . . . 188
Arithmetic Operation Instructions . . . . . . . . . . . . . . . 197 Character string length detection . . . . . . . . . . . . . . . 476
Association Instructions . . . . . . . . . . . . . . . . . . . . . . 139 Character string processing instructions . . . . . . . . . 460
Character string search . . . . . . . . . . . . . . . . . . . . . . 504
B Character string transfer . . . . . . . . . . . . . . . . . . . . . 269
Clock data addition operation. . . . . . . . . . . . . . . . . . 590
Basic model QCPU . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Clock data subtraction operation . . . . . . . . . . . . . . . 592
Batch recovery of index register . . . . . . . . . . . . . . . . 632 Clock instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . 587
Batch reset of bit devices . . . . . . . . . . . . . . . . . . . . . 365 Common logarithm operation on floating-point data
Batch save of index register . . . . . . . . . . . . . . . . . . . 632 (Double precision) . . . . . . . . . . . . . . . . . . . . . . . . . . 553
BCD 4-digit addition and subtraction operations. . . . 207 Common logarithm operation on floating-point data
BCD 4-digit multiplication and division operations . . 213 (Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 552
BCD 4-digit square roots. . . . . . . . . . . . . . . . . . . . . . 555 Comparison Operation Instructions . . . . . . . . . . . . . 181
BCD 8-digit addition and subtraction operations. . . . 210

906
Complement of 2 of BIN 16-bit data (sign inversion) Conversion from floating-point data to BIN 16-bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 data (Double precision). . . . . . . . . . . . . . . . . . . . . . . 249
Complement of 2 of BIN 32-bit data (sign inversion) Conversion from floating-point data to BIN 16-bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 data (Single precision) . . . . . . . . . . . . . . . . . . . . . . . 247
Conditions for Execution of Instructions . . . . . . . . . 117 Conversion from floating-point data to BIN 32-bit
Configuration of Instructions . . . . . . . . . . . . . . . . . . . 87 data (Double precision). . . . . . . . . . . . . . . . . . . . . . . 249
Contact Instructions . . . . . . . . . . . . . . . . . . . . . . . . . 132 Conversion from floating-point data to BIN 32-bit
Conversion from ASCII to hexadecimal BIN . . . . . . 496 data (Single precision) . . . . . . . . . . . . . . . . . . . . . . . 247
Conversion from BCD 4-digit data to BIN data . . . . 242 Conversion from floating-point data to character
Conversion from BCD 4-digit data to decimal ASCII string data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 Conversion from floating-point radian to angle
Conversion from BCD 8-digit data to BIN data . . . . 242 (Double precision). . . . . . . . . . . . . . . . . . . . . . . . . . . 537
Conversion from BCD 8-digit data to decimal ASCII Conversion from floating-point radian to angle
data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 (Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 536
Conversion from BIN 16-bit data to character string Conversion from Gray code to BIN 16-bit data. . . . . 254
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 Conversion from Gray code to BIN 32-bit data. . . . . 254
Conversion from BIN 16-bit data to decimal ASCII Conversion from hexadecimal ASCII to BIN 16-bit
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 I
Conversion from BIN 16-bit data to floating-point Conversion from hexadecimal ASCII to BIN 32-bit
data (Double precision) . . . . . . . . . . . . . . . . . . . . . . 246 data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470
Conversion from BIN 16-bit data to floating-point Conversion from hexadecimal BIN to ASCII. . . . . . . 494
data (Single precision) . . . . . . . . . . . . . . . . . . . . . . . 244 Conversion from Single precision to Double precision
Conversion from BIN 16-bit data to Gray code . . . . 253 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
Conversion from BIN 16-bit data to hexadecimal COS operation on floating-point data
ASCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 (Double precision). . . . . . . . . . . . . . . . . . . . . . . . . . . 518
Conversion from BIN 16-bit to BIN 32-bit data . . . . 251 COS operation on floating-point data
Conversion from BIN 32-bit data to character string (Single precision) . . . . . . . . . . . . . . . . . . . . . . . . . . . 517
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Conversion from BIN 32-bit data to decimal ASCII Counter 1-phase input up or down . . . . . . . . . . . . . . 298
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 Counter 2-phase input up or down . . . . . . . . . . . . . . 300
Conversion from BIN 32-bit data to floating-point Counting Step Number . . . . . . . . . . . . . . . . . . . . . . . 118
data (Double precision) . . . . . . . . . . . . . . . . . . . . . . 246 CPU module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Conversion from BIN 32-bit data to floating-point CPU performance comparison
data (Single precision) . . . . . . . . . . . . . . . . . . . . . . . 244 counters. . . . . . . . . . . . . . . . . . . . . .