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Practica 4-Constraints y Codigo

This document describes a VHDL code for a 7-segment display controller. It defines entities, ports, signals and processes for a 4-digit 7-segment display. Frequency divider processes generate 1Hz and 250Hz signals to multiplex the display. A state machine cycles through states to display the characters "ARBO" on the 4 digits. The anode and cathode signals are defined to drive the display segments.

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SEBASTIAN PLASCENCIA LOPEZ
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40 views4 pages

Practica 4-Constraints y Codigo

This document describes a VHDL code for a 7-segment display controller. It defines entities, ports, signals and processes for a 4-digit 7-segment display. Frequency divider processes generate 1Hz and 250Hz signals to multiplex the display. A state machine cycles through states to display the characters "ARBO" on the 4 digits. The anode and cathode signals are defined to drive the display segments.

Uploaded by

SEBASTIAN PLASCENCIA LOPEZ
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd
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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cartel is
Port (clk,rst: in STD_LOGIC;
led: out std_logic;
anodos: out std_logic_vector (3 DOWNTO 0);
seg: out std_logic_vector (6 DOWNTO 0));
end cartel;

architecture funcional of cartel is


signal aux1hz: std_logic:='0';
signal aux250hz: std_logic:='0';
signal anodo: std_logic_vector (1 downto 0):="00"; --Anodo actual
signal catA: std_logic_vector (2 downto 0):="110"; --Configuracion de catodos
display
signal catB: std_logic_vector (2 downto 0):="110";
signal catC: std_logic_vector (2 downto 0):="110";
signal catD: std_logic_vector (2 downto 0):="110";
signal segA: std_logic_vector (2 downto 0);
type estados is (s0,s1,s2,s3,s4,s5,s6,s7,s8,s9);
signal edo_presente, edo_futuro: estados;
begin

--Divisor de Frecuencia de 1 Hz
process(clk, rst)
variable cuenta1hz: integer range 1 to 500;
begin
if(rst='1')then
aux1hz<='0';
cuenta1hz:=1;
else
if rising_edge (clk) then
if (cuenta1hz=500) then
aux1hz<= not (aux1hz);
cuenta1hz:=1;
else
cuenta1hz:= cuenta1hz +1;
end if;
end if;
end if;
led<= aux1hz;
end process;

--Divisor de Frecuencia de 250 Hz


process(clk, rst)
variable cuenta250hz: integer range 1 to 200000;
begin
if rising_edge (clk) then
if (cuenta250hz=200000) then
aux250hz<= not (aux250hz);
cuenta250hz:=1;
else
cuenta250hz:= cuenta250hz +1;
end if;
end if;
end process;
--Estado PresenteA
process(aux1hz, rst)
begin
if (rst='1') then
edo_presente <=s9;
elsif (falling_edge (aux1hz)) then
edo_presente <= edo_futuro;
end if;
end process;

--Estado Futuro
process(edo_presente, rst)
begin
case edo_presente is
when s0 =>
edo_futuro <= s1;
catA<="110"; --espacio
catB<="110"; --espacio
catC<="110"; --espacio
catD<="110"; --espacio

when s1 =>
edo_futuro <= s2;
catA<="001"; --A
catB<="110"; --espacio
catC<="110"; --espacio
catD<="110"; --espacio

when s2 =>
edo_futuro <= s3;
catA<="010"; --r
catB<="001"; --A
catC<="110"; --espacio
catD<="110"; --espacio

when s3 =>
edo_futuro <= s4;
catA<="011"; --b
catB<="010"; --r
catC<="001"; --A
catD<="110"; --espacio

when s4 =>
edo_futuro <= s5;
catA<="100"; --o
catB<="011"; --b
catC<="010"; --r
catD<="001"; --A

when s5 =>
edo_futuro <= s6;
catA<="101"; --l
catB<="100"; --o
catC<="011"; --b
catD<="010"; --r

when s6 =>
edo_futuro <= s7;
catA<="110"; --espacio
catB<="101"; --l
catC<="100"; --o
catD<="011"; --b

when s7 =>
edo_futuro <= s8;
catA<="001"; --A
catB<="110"; --espacio
catC<="101"; --l
catD<="100"; --o

when s8 =>
edo_futuro <= s3;
catA<="010"; --r
catB<="001"; --A
catC<="110"; --espacio
catD<="101"; --l

when s9 =>
edo_futuro <= s1;
catA<="000"; --0
catB<="000"; --0
catC<="000"; --0
catD<="000"; --0
end case;
end process;

--Multiplexacion
process(aux250hz, anodo, catA, catB, catC, catD)
begin
if falling_edge (aux250hz) then
anodo <= anodo +1;
else
anodo<= anodo;
end if;
if(anodo="00")then
anodos<="1110";
segA<=catA;
elsif (anodo="01")then
anodos<="1101";
segA<=catB;
elsif (anodo="10")then
anodos<="1011";
segA<=catC;elsif (anodo="11")then
anodos<="0111";
else
anodos<="0000";
segA<=catB;
end if;
end process;

--Decodificador
process(segA)
begin
case segA is
when "000"=>seg<= "0000001"; --0
when "001"=>seg<= "1001000"; --H
when "010"=>seg<= "1100010"; --O
when "011"=>seg<= "1110001"; --L
when "100"=>seg<= "0001000"; --A
when others =>seg<="1111111";-- espacio
end case;
end process;
end funcional;

-------------------------------------------------
Anodos

set_property PACKAGE_PIN U2 [get_ports{seg[0]}]


set_property IOSTANDARD LVCMOS33 [get_ports{seg[0]}]

set_property PACKAGE_PIN U4 [get_ports{seg[1]}]


set_property IOSTANDARD LVCMOS33 [get_ports{seg[1]}]

set_property PACKAGE_PIN V4 [get_ports{seg[2]}]


set_property IOSTANDARD LVCMOS33 [get_ports{seg[2]}]

set_property PACKAGE_PIN W4 [get_ports{seg[3]}]


set_property IOSTANDARD LVCMOS33 [get_ports{seg[3]}]

--------------------------------------

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