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CS405 Computer System Architecture, December 2019

This document appears to be an exam for a computer architecture course. It contains: 1) Four parts (A, B, C, D) with multiple choice and long answer questions. 2) Part A has 10 short answer questions worth 4 marks each on topics like pipelining, Amdahl's law, cache coherence protocols. 3) Parts B, C and D have longer answer questions worth 9 and 12 marks on topics such as parallelism, memory hierarchies, pipelining hazards, out-of-order execution, and interconnection networks. 4) The questions assess understanding of fundamental computer architecture concepts as well as the ability to analyze examples and problems.

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Karthika
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64 views

CS405 Computer System Architecture, December 2019

This document appears to be an exam for a computer architecture course. It contains: 1) Four parts (A, B, C, D) with multiple choice and long answer questions. 2) Part A has 10 short answer questions worth 4 marks each on topics like pipelining, Amdahl's law, cache coherence protocols. 3) Parts B, C and D have longer answer questions worth 9 and 12 marks on topics such as parallelism, memory hierarchies, pipelining hazards, out-of-order execution, and interconnection networks. 4) The questions assess understanding of fundamental computer architecture concepts as well as the ability to analyze examples and problems.

Uploaded by

Karthika
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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C G192056

RegNo-:

SEVENTH

Max. Marks: 100 Duration: 3 Hours

PART A
Answer all questions, each carries 4 marks. Marks
A 400MFIz processor was used to execute a program with 150000 floating point (4)
instructions with clock cvcle count of l. Determine the execution time and MIPS
rate for this program.

State Amdahl's law. Write an expression for the overall speed up. (4)
Distinguish between scalar RISC and super-scalar RISC in terms of instruction (4)
issue, pipeline architecture and performance.

4 Discuss the schematic representation of a generalized multiprocessor system. (4)


5 Explain chained cache coherence protocol. (4)
6 Consider the execution of a program of 15,00,000 instructions by a linear pipeline (4)
processor with a clock rate of 1000 MHz. Assume that the instruction pipeline has
five stages and that one instruction is issued per cycle. The penalties due to branch
instruction and out-of-order execution are ignored.
a) Calculate the speedup factor in using this pipeline to execute the program as
compared with the use of an equivalent non-pipelined processor with an

equal amount of flow-through delay.


b) Find out the efficiency and throughput of this pipelined processor.
7 Write short notes on internal data forwarding. (4)
8 Explain Goodman's write once protocol with transition diagram. (4)
9 List any two advantages and disadvantages of Scalable Coherence Interface(SCl). (4)
l0 What are the four context switching policies adopted by multithreaded (4)
architectures?

PART B
Answer any twofull questions, eoch conies 9 marks.
ll a) Discuss the Bemstein's conditions for checking the parallelism among a set of (3)
processes.

b) Analyze the data dependences among the following statements and construct a (6)

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G192056 Pages:3
in them'
dependency graph. Also detect the parallelism embedded

Rl , M(100) / Rl <- MemorY(I0O) /


S1 : Load
S2 MoveR2,Rl lF.2-- (Rl )/
S3 IncRl /Rl <-(Rl )+1/
S4 Add R2 . Rl lF.2 ,- (R2 ) + (Rl) /
55 : Store M(100), Rl/Memory(lO0) <- (R1) /
the data transfers (5)
a) Define the inclusion property of a memory hierarchy. Illustrate
12 between adjacent levels of a memory hierarchy'
64Kbytes and (4)
b) consider a two-level memory hierarchy, Ml and M2 of sizes
4Mbytes respectively, with access time tl
:20ns andt2:200ns and costs cl and
: $0.0005/byte respectively. The cache hit ratio hl : 0'95 at
c2 are$0.01/byte,-c2

the first level. Find the effective access time and total cost of
this memory system'

13 Differentiate between the following with necessary diagrams:


(4)
a) UMA and NUMA multiprocessor models'
(5)
b) RISC and CISC
PART C
Answer any twofutt questions, each canies 9 marks'
(4)
14 a) Explain the different levels of hierarchy of bus systems.
b) Define the write-invalidate snoopy bus protocol for maintaining cache coherence' (5)
and write-back cache
Show the different possible state transitions for write-through
using the write-invalidate protocol'
Consider the five-stage pipelined processor specified by the
following reservation
15
table and answer the following: (S indicate the stages)

1 2 3 4 5 6

s1 X X

S2 X X

S3 X

S4 X X

(i) List the set of forbidden latencies and the collision vector. Q)

(ii) Draw the state transition diagram showing all possible initial sequences
without (3)
causing a collision in the pipeline.

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C G192056 Pages:3
(iii) List all the simple and greedy cycles from the state diagram. (2)
(iv) Determine the minimal average latency (MAL). (2)
16 a) Explain the three major operational characteristics of a multiprocessor (3)
interconnection network.
b) Analyse and compare the communication latencies of Store-and Forward and (3)
Wormhole routing schemes.
c) Consider a l6-node hypercube network. Based on the E-cube routing algorithm, (3)
show how to route a message from node (0lll) to node (1101). All intermediate
nodes must be identified on the routing path.

PART D
Answer ony tnoTott questions, each curries 12 marks.
17 a) Which are the three logic hazards possible in an instruction pipeline? Define each. (6)
Write the necessary conditions for each to occur.
b) Explain the in-order and out-of-order pipeline scheduling policies for a superscalar (6)
machine with an example.
l8 a) Explain the importance of Tomasulo's algorithm for dynamic instruction (8)
scheduling.
b) What do you mean by Release Consistency (RC) memory model? Give the (4)
conditions to ensure RC.
19 a) Explain the effect of branching in instruction pipelining. Find the execution time (6)
and throughput of the pipeline for n instructions by considering the effect of
branching. How branch penalty is reduced using delayed branch strategy.
b) Explain any two latency hiding techniques used in distributed shared memory (6)
multi computers.
****

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