Chapter 9-Verilog Behavioral Modeling
Chapter 9-Verilog Behavioral Modeling
Chapter 9
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Procedural Blocks
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Example - always
In an always block, when the trigger event occurs, the code inside
begin and end is executed; then once again the always block waits for
next event triggering. This process of waiting and executing on event is
repeated till simulation stops.
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Procedural Assignment Statements
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Example-Bad Procedural Assignment
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Example-Good Procedural Assignment
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Procedural Assignment Groups
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Example - "begin-end"
begin-end: clk gets 0 after 1 time unit, reset gets 0 after 11 time units,
enable after 16 time units, data after 19 units. All the statements are executed
sequentially.
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Example - "fork-join"
fork-join: clk gets its value after 1 time unit, reset after 10 time units,
enable after 5 time units, data after 3 time units. All the statements are
executed in parallel.
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Sequential Statement Groups
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Example - Sequential
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Parallel Statement Groups
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Example - Parallel
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Example - Mixing "begin-end" and
"fork - join"
Block name
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Blocking and Nonblocking
Assignment
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Example - Blocking and Nonblocking
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The Conditional Statement if-else
• The if - else statement controls the execution of other
statements. In programming language like C, if - else
controls the flow of program. When more than one
statement needs to be executed for an if condition, then we
need to use begin and end as seen in earlier examples.
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Example- simple if
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Example- if-else
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Example- nested-if-else-if
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Example- nested-if-else-if (cont.)
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The Case Statement
• The case statement compares an expression to a series of
cases and executes the statement or statement group
associated with the first matching case:
Case statement supports single or multiple statements.
Group multiple statements using begin and end keywords.
• Syntax of a case statement look as shown below.
case()
< case1 > : < statement >
< case2 > : < statement >
.....
default : < statement >
endcase
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Example- case
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Example- case without default
The example above shows how to specify multiple case items as a single case item.
The Verilog case statement does an identity comparison (like the === operator); one can
use the case statement to check for logic x and z values as shown in the example below.
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Example- case with x and z
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Looping Statements
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The forever Statement
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The repeat Statement
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Example- repeat
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The while Loop Statement
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Example- while
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The for Loop Statement
• The for loop is the same as the for loop used in any other
programming language.
• Executes an < initial assignment > once at the start of the loop.
• Executes the loop as long as an < expression > evaluates as
true.
• Executes a < step assignment > at the end of each pass
through the loop.
• syntax:
for (< initial assignment >; < expression >; < step assignment >) < statement >
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Example - for
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Continuous Assignment Statements
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Example - One bit Adder
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Example - Tri-state buffer
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Propagation Delay
• Continuous assignments may have a delay specified; only
one delay for all transitions may be specified. A
minimum:typical:maximum delay range may be specified.
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Procedural Block Control
• Procedural blocks become active at simulation time zero. Use level
sensitive event controls to control the execution of a procedure.
Any change in either d or enable satisfies the event control and allows the
execution of the statements in the procedure. The procedure is sensitive to any
change in d or enable. 41
Combo Logic using Procedural Coding
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Example - One bit Adder
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Example - 4-bit Adder
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Example - Ways to avoid Latches -
Cover all conditions
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Example - Ways to avoid Latches -
Snit the variables to zero
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Sequential Logic using Procedural Coding
• To model sequential logic, a procedure block must be
sensitive to positive edge or negative edge of clock. To
model asynchronous reset, procedure block must be
sensitive to both clock and reset. All the assignments to
sequential logic should be made through nonblocking
assignments.
• Sometimes it's tempting to have multiple edge triggering
variables in the sensitive list: this is fine for simulation. But
for synthesis this does not make sense, as in real life, flip-
flop can have only one clock, one reset and one preset (i.e.
posedge clk or posedge reset or posedge preset).
• One common mistake the new beginner makes is using
clock as the enable input to flip-flop. This is fine for
simulation, but for synthesis, this is not right.
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Example - Bad coding
Using two clocks
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Example - D Flip-flop with async reset
and async preset
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Example - D Flip-flop with sync reset
and sync preset
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A procedure can't trigger itself
• One cannot trigger the block with a variable that block assigns value
or drives.
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Example – Multiple Blocks
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Named Blocks
• Blocks can be named by adding : block_name after the
keyword begin. Named blocks can be disabled using the
'disable' statement.
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Example - Named Blocks
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The End