University of Tikrit

College of Engineering

Electrical Engineering Department

Microprocessor 8086 / 8086

By
Abdulmuttalib A. Hussein Aldouri
8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Main Structural Component of a Computer System

The main elements associated with a computer system are as follows:
1. Central Processing Unit (CPU)
2. Main Memory
3. Secondary Storage Devices
4. Input and Output (I/O) Devices
5. Busses

The Processor (CPU)

The CPU or processor acts as the controller of all actions or services provided
by the system. It is the Brain and the Heart of the Computer. The operations of
a CPU can be reduced into the following :
1. Fetch the next instruction from memory.
2. Decode the instruction.
3. Execute the instruction.
4. Store the result of the instruction into main memory.

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In general, the CPU has three main units: (See the figure below)
 Arithmetic and Logic Unit (ALU): Performs arithmetic and logical
operations. For example, it can add together two binary numbers either
from memory or from some of the CPU registers.
 Control Unit: controls the action of the other computer components so
that instructions are executed in the correct sequence.
 Registers - Temporary storage inside CPU. Registers can be read and
written at high speed as they are inside the CPU.

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Memory
The memory in a computer system is of two fundamental types:
 Main Memory: used to store information for immediate access by the
CPU. Main Memory is also referred to as Primary Storage or Main Store.
 Closely connected to the processor.
 The contents are quickly and easily changed.
 Stores the programs that the processor is actively working with.
Main memory includes:
 Random Access memory (RAM): for temporary storage.
 Read-only memory (ROM): for permanent storage.

 Secondary Storage Devices: devices provide permanent storage of large

amounts of data. Secondary storage is also called: secondary memory,
external memory. This storage may consist of magnetic tapes, magnetic
disk, optical memory device.
 Connected to main memory through the bus and a controller.
 The contents are easily changed, but this is very slow compared
main memory.
 Used for permanent storage of programs and data.

Input/Output Devices
Input/output devices provide an interface between the computer and the
user. There is at least one input device (e.g. keyboard, mouse, measuring device
such as a temperature sensor) and at least one output device (e.g. printer, screen,
control device such as an actuator). Input and output devices like keyboards and
printers, together with the external storage devices, are referred to as peripherals.

System Bus
There are three types of busses:
1. Address Buss: A unidirectional lines determine the size of memory
addressable by the processor.
2. Data Bus : A bi-directional lines indicate the size of the data transferred
between the processor and memory or I/O device.
3. Control Bus: consists of a set of control signals indicates the type of
action taking place on the system bus.

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Evolution of Intel Microprocessor

Intel (Integrate electronics) was the first corporation in manufacturing
Microprocessors starting with 4004µP to Pentium µP. Processor vary in their
speed, capacity of memory, register width, and address & data bus size, a brief
description of various Intel processor is explained in the table below.
Address Bus
Size of Data

Width (bit)
Register
Size of
Bus

µP Memory Size Clock Rate

4004 4 12 4 4 Kbyte 0.2 MHz

8008 8 14 8 16 Kbyte 0.2 MHz
8080 8 16 8 64 Kbyte 2 MHz
8085 8 16 8 64 Kbyte 3 MHz
8086 16 20 16 1 Mbyte 5 MHz
8088 8 20 16 1 Mbyte 5 MHz
‫) ال تىجد عملياث الضزب والقسمت ويبدأ وجىد هاتيه العمليتيه‬4004-8085( ‫في المعالجاث االربعت‬
8887µP ‫ لذلك يزبط معه‬integer numbers ‫ لكنه يتعامل مع االعداد الصحيحت فقط‬8086µP ‫في‬
floating numbers ‫الذي يتعامل مع االعداد الحقيقيت‬
80186 16 28 16 1 Mbyte 6 MHz
80286 16 24 16 16 Mbyte 8 MHz
floating numbers ‫ الذي يتعامل مع االعداد الحقيقيت‬88287µP ‫يزبط معه‬
80386 32 32 32 4 Gbyte 16 MHz
floating numbers ‫ الذي يتعامل مع االعداد الحقيقيت‬88387µP ‫يزبط معه‬
80486 32 32 32 4 Gbyte + 8 Kbyte cache 50 MHz
‫ لكنهما يصنعان‬، floating numbers ‫ الذي يتعامل مع االعداد الحقيقيت‬88487µP ‫يزبط معه‬
‫قطعت واحدة‬
Pentium 64 32 32 4 Gbyte + 8 Kbyte cache 100 MHz
Pentium 64 Gbyte + 8K L1 cache
64 36 32 180M Hz
Pro +256K L2 cache
Pentium 64 Gbyte + 32K L1 cache 233 - 450
64 36 32
II +512K L2 cache MHz
Pentium 64 Gbyte + 32K L1 cache
64 36 32 1GHz
III +512K L2 cache
Pentium 64 Gbyte + 32K L1 cache
64 36 32 1.3 GHz
IV +512K L2 cache

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Intel's 8086 Microprocessor

The 8086µP is manufactured using High performance Metal-Oxide
Semiconductor (HMOS) technology. It has approximately 29000 transistors and
housed in a 40-pin package.

Internal Architecture of 8086µP

The architecture of 8086µP is shown in figure below . It has two separate
functional units : Bus Interface Unit (BIU) and Execution Unit (EU). The
8086µP architecture employs parallel processing—i.e., both the units (BIU and
EU) work at the same time. Parallel processing makes the fetch and execution of
instructions independent operations. This results in efficient use of the system
bus and higher performance for 8086µP systems.
 The BIU has segment registers, instruction pointer, address generation
and bus control logic block, instruction queue.
The main jobs performed by BIU are:
1. The BIU performs all bus operations such as instruction fetching,
reading and writing operands for memory and calculating the addresses
of the memory operands.
2. Input/output of data from/to input/output peripherals.
 The EU has general purpose registers, ALU, control unit, instruction
register, flags (or status) register.
The main jobs performed by the execution unit EU are:
1. Decoding/execution of instructions.
2. It accepts instructions from the instruction queue and data from the
general purpose registers or memory.
3. EU tests the status of flags in the control register and updates them
when executing instructions.

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Pipelining is a process that allows the CPU (Microprocessor) to fetch and

execute instructions at the same time. Intel Co. implemented the concept of
pipelining by splitting the internal architecture of the 8088/8086µP into two
units that works simultaneously:

Q: Explain the operations of instructions queue in BIU.

Ans. The instruction queue is 6-bytes in length, operates on FIFO (first-in first-
out) basis. It receives the instruction codes from memory. BIU fetches the
instructions for the instructions queue from memory.

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Types of Buses in the 8086µP

A bus is a number of wires organized to provide a means of communication
among different elements in a microcomputer system. There are three types of
buses:
1. Address Bus : A 20-bit unidirectional lines used hold the address of a
memory location. The address bus allows the processor to access 1 Mbyte
of memory (Memory size = 220 =1048576 bytes = 1 Mbyte).
2. Data Bus : A 16-bit bidirectional lines used for transferring data between
the microprocessor and memory or the peripheral devices.
3. Control Bus : It contains lines that select the memory or I/O and cause
them to perform a read or write operation.

Internal Registers of 8086µP

There are fourteen 16-bit registers. The different groups are:
 The data group (general purpose registers) consists of AX (accumulator),
BX (base), CX (count) and DX (data).
 Pointer group consists of SP (Stack pointer), BP (Base pointer), IP
(Instruction pointer).
 Index group consists of SI (Source Index), and DI (Destination index).
 Segment group consists of CS (Code Segment), DS (Data Segment) ,
SS(Stack Segment) and ES (Extra Segment),.
 16-bit flags (status) register.
Figure below shows the registers placed in the different groups.

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General Purpose Data Registers

Figure below shows the four data registers with their dedicated functions.

15 87 0

Pointers and Index Group

The pointer registers are SP (Stack Pointer), BP (Base pointer) and IP
(Instruction Pointer) while the index registers are SI (Source Index) and DI
(Destination Index). All the five are 16-bit registers and are used to store offset
(effective address) of memory locations relative to segment registers.

Segment Registers : there are four segment registers, they are:

1. Code Segment (CS): The CS register is used for addressing a memory
location in the Code Segment of the memory, where the executable program
is stored.
2. Data Segment (DS): The DS contains most data used by program. Data are
accessed in the Data Segment by an offset address or the content of other
register that holds the offset address.
3. Stack Segment (SS): SS defines the area of memory used for the stack.
4. Extra Segment (ES): ES is additional data segment that is used by some of
the string instructions to hold the destination data.

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The Flags Register

It is a 16-bit register, also called Program Status Word (PSW). Seven bits
remain unused while the rest nine are used. Six are status flags and three are
control flags.
 The control flags can be set/reset by the programmer.
1. DF (Direction Flag) : controls the direction of operation of string
instructions. (DF=0 Ascending order DF=1 Descending order)
2. IF (Interrupt Flag): controls the interrupt operation in 8086µP.
(IF=0 Disable interrupt IF=1 Enable interrupt)
3. TF (Trap Flag): controls the operation of the microprocessor.
(TF=0 Normal operation TF=1 Single Step operation)
 The status flags are set/reset depending on the results of some arithmetic or
logical operations during program execution.
1. CF (Carry Flag) is set (CF=1) if there is a carry out of the MSB
position resulting from an addition operation or subtraction.
2. AF (Auxiliary Carry Flag) AF is set if there is a carry out of bit 3
resulting from an addition operation.

3. SF (Sign Flag) set to 1 when result is negative. When result is positive

it is set to 0.
4. ZF (Zero Flag) is set (ZF=1) when result of an arithmetic or logical
operation is zero. For non-zero result this flag is reset (ZF=0).
5. PF (Parity Flag) this flag is set to 1 when there is even number of one
bits in result, and to 0 when there is odd number of one bits.
6. OF (Overflow Flag) set to 1 when there is a signed overflow. For
example, when you multiply FFH by 11H (result is not one byte).

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Memory Organization
8086/8088µP, via its 20-bit address bus, can address 220 = 1,048,576 bytes
or (1 Mbyte) of memory locations. Thus the memory space of 8086µP is
1,048,576 bytes or 524,288 words. The memory map of 8086µP as shown,
where the whole memory space starting from 00000H to FFFFFH.
The 8086µP operate in the Real mode memory addressing. Real mode
operation allows the microprocessor to address only the first 1 Mbyte of
memory. Even though the 8086 has a 1 Mbyte address space, not all this
memory is active at one time. Actually, the 1 Mbytes of memory are partitioned
into 64 Kbyte (65,536) segments. The 8086µP allows four memory segments.
The figure shows these memory segments.

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Software Model of 8086µP

What is important to the programmer is to know the various registers
within the 8086µP and to understand their purpose, functions, operating
capabilities, and limitations. The figure below illustrates the software
architecture of the 8086µP.

Physical Address Generation

Logical address, segment address and physical address are explained as follows:
 The logical address, also known as the effective address or offset address
is contained in the registers IP, BP, SP, BX, SI or DI.
 The 16-bit content of one of the four segment registers (CS, DS, ES, SS)
is known as the base segment address.
 Offset and base segment address are combined to form a 20-bit physical
address (also called real address) that is used to access the memory.

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The 20-bit physical address is generated by combining the offset (residing in

BX, BP, IP, SP, SI or DI) and the content of one of the segment registers CS,
DS, ES or SS. The process of combination is as follows:
The content of the segment register is internally appended with 0H (0000B) on
its right most end to form a 20-bit memory address—this 20-bit address points
to the start of the segment. The offset is then added to the above to get the
physical address.

Physical Address = Segment Register : Offset (Effective Address)

= (Segment Register)0H + Offset (Effective Address)

For example if (DS)=2000H and the Logical address is 1234H then the physical
address is: PA = (2000)*10 + 1234H = 20000H + 1234H = 21234H

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Addressing Modes of 8086µP

The general form of an Assembly language instruction is :

Destination(D) Source(S)
Operation ,
reg. / mem. reg. / mem.
An instruction consists of an op-code and operands. The operand may reside in
the accumulator, or in a general purpose register or in a memory location.
Examples:
MOV AX , BX ; copy the content of BX to AX.
ADD AL , 12H ; add 12H to AL and store the result in AL.
An addressing mode is a method of specifying an operand. The following are
the different addressing modes of 8086µP:
1. Register Addressing Mode: The operands both are registers (8-bit or 16-
bit). Some examples are:
MOV AX , BX
ADD AL , BH
2. Immediate Addressing Mode: The source can be either 8-bit or 16-bit
number and the destination is a register . Some examples are:
MOV AL , 83H
ADD BX , 1284H
3. Memory Addressing Mode: One of the operands is a memory location. The
different memory addressing modes are:
a) Direct Addressing Mode: The effective address of the specified memory
location is given directly between [ ] brackets, for example: (DS)=1000H
MOV AL , [3000H]
Note: The default
{ } { } segment register is DS

PA = (DS)0H + 3000H = 10000H + 3000H = 13000H

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b) Register Indirect Addressing Mode: The effective address is located in

any of the following registers : BP, BX , SI and DI.
[ ] 𝑪𝑺 𝑩𝑿
𝑷𝑨 {𝑫𝑺} {𝑩𝑷}
[ ] 𝑺𝑺 𝑺𝑰
𝑬𝑺 𝑫𝑰
For example if (SI)=2000H, and (DS)=1000H, then the instruction
MOV BX , [SI] copies the word 2030H from locations 12000H and
12001H to BX.
PA=(DS)0H + [2000H] = 10000H + 2000H = 12000H

SI

c) Register Relative Addressing Mode: The effective address can be found

as follows:
 Based with displacement (Based-Relative) addressing mode.

 Indexed with displacement(Indexed-Relative) addressing mode.

{ } { } { }

For example if (BP)=1000H , (SS)=0100H , (AL)=FFH and a

displacement of 100H then the instruction MOV [BP+100H] , AL copies
the content of AL into memory location 02100H.
PA = (100)0H + [1000H + 100H] = 2100H
Note: the diagram is left as a H.W for the student

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d) Based-Indexed Addressing Mode : The effective address can be found

as follows:
[ ]

{ } { } { }

For example if (BX) = 2000H , (DI) = 0030H and (DS) = 1000H then the
instruction MOV CX , [BX + DI] load the register CX with 1040H form
memory locations 12030H and 12031H.
PA = 10000 + [2000H + 0030H] = 12030H

0030H

e) Based-Indexed with Displacement Mode : The effective address can be

found as follows:
[ ]

{ } { } { } { }

For example if (BP) = 0100H , (SI) = 0200H , (SS) = 2000H and a

displacement of 10H then the instruction MOV AL , [BP+SI+10H] load
the register AL with 50H form memory location 20310H.
PA = (2000)0H + [0100H + 0200H + 10H] = 20310H

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MOV AL , [BP + SI + 10H]

BP

SS
(SS) x 10H

The table below shows the operand that stores the effective address and the
default segment register used to form the physical address

Addressing Mode Operand Default Segment

Direct [offset] DS
Register Indirect [BX] or [SI] or [DI] DS
[BP] SS
Based Relative [BX + disp] DS
[BP + disp] SS
Indexed Relative [SI + disp] DS
[DI + disp] DS
Based-Indexed [BX + SI or DI + disp] DS
Relative [BP + SI or DI + disp] SS

Note:
1. CS : IP together determine the address of the first instruction to execute.
In this way the first instruction in CS being execution, if the first
instruction is two byte long, the processor increment IP by 2 to indicate
the next instruction.
2. Segment override prefix means that we can use any segment register to
form the physical address as follows:
MOV AX , ES : [2000H]
ADD SS : [BX+SI] , DX
AND CS : [BP] , AL
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Unsigned and Signed Integer Numbers

1. Unsigned integer numbers: each type of integer can be either byte-wide or

word-wide. This data type can be used to represent decimal numbers in the
range 0 through 255. The unsigned word integer can be used to represent
decimal numbers in the range 0 through 65535.

2. Signed integer numbers: each type of integer can be either byte-wide or

word-wide. They are similar to unsigned integer numbers except the most
significant bit MSB in signed integer data type is a sign bit. This data type
represents decimal numbers in the range -128 to +127. The signed word
integer represents decimal numbers in the range –32768 to +32767.

Note: Negative integers are stored in 2's complement form.

-1H = FFH (byte) , -2H = FEH (byte)

-1H = FFFFH (word) , -2H = FFFEH (word)

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Instruction Set of 8086µP

There are 117 basic instructions in the instruction set of 8086µP. The instruction
set of 8086µP can be divided into the following groups :
1. Data Transfer Instructions 2. Arithmetic and Logic Instructions
3.Shift and Rotate Instructions 4. Flag Control Instructions
5. Compare Instructions 6. Jump Instructions
7. Loop Instructions 8. Stack Instructions 
9.Strings Instructions 10. Subroutines Instructions
Data Transfer Instructions
The data transfer instructions include:
1. MOV (byte or word) Instruction. 2. XCHG (Exchange byte or word)
3. XLAT (Translate byte) 4. LEA (Load effective address )
5. LDS (Load register and DS) 6. LES (Load register and ES)

The MOV Instruction:

The MOV instruction is used to transfer (copy) a byte or word of data

from a source operand to a destination operand. The general form of MOV
instruction is as shown below:

The allowed operands for the source and destination are listed below:
Examples :
MOV AX , BX
MOV AL , FFH
MOV [BX] , CX
MOV [SI] , FF87H
MOV BH , [PB+DI]
MOV DS , AX
MOV AL , 'A'
MOV [BX] , [SI] is not allowed, why?
MOV DS , FA34H is not allowed, why?
MOV DS , CS is not allowed, why?
MOV CS, AX is not allowed, why?

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The Exchange XCHG Instruction

The XCHG (exchange) instruction exchanges the contents of a register a
memory with the contents of any other register or memory. The general form of
this instruction is as shown below:

The allowed operands for the source and destination are listed below:
Example
(AX)=1000H and (BX)=2000H
XCHG AX , BX
After execution :
(AX)=2000H and (BX)=1000H

H.W. Repeat the example by using MOV instructions only.

The XLAT Instruction

This instruction used to simplify implementation of the lookup table operation.
The general form of this instruction is as shown below:

Ex: Assume (DS) = 1000H, (BX)=1000H, and (AL)=05H. Execution of XLAT

replaces the contents of AL by the contents of memory location with physical
address : PA = (DS)0 + (BX) + (AL) = 10000H + 1000H + 05H = 11005H
Thus: (AL) = 6DH (the old byte 05H in AL is replaced by 6DH)

AX

BX

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Load-Effective Address (LEA, LDS, and LES) Instructions:

These instructions load a segment and general purpose registers with an address
directly from memory. The general forms of these instructions are as shown
below:
Mnemonic Meaning Format Operation Flags Affected
LEA Load effective address LEA Reg16 , EA EA → (Reg16) None
[PA] → (Reg16)
LDS Load register and DS LDS Reg16 , EA None
[PA+2] → (DS)
[PA] → (Reg16)
LES Load register and ES LES Reg16 , EA None
[PA+2] → (ES)

Ex: What does BX contain after executing: LEA BX , [SI+100H] If

(SI)=1000H
Ans. The effective address EA=1000H + 100H = 1100H → (BX) = 1100H

Ex : If (SI)=1000H and (DS)=1000H , what do the registers BX and DS

contain after execution LDS BX , [SI] instruction?
Ans.
PA = 10000H + 1000H = 11000H
The execution of LDS BX , [SI] loads BX from addresses 11000H and 11001H
and DS from addresses 11002H and 11003H.
(BX) = 127AH and (DS) = 3000H

BX

SI

Note : All data transfer instructions do not affect the status flags.

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Arithmetic and Logic Group

The arithmetic group includes instructions for the addition, subtraction,
multiplication, division as well as increment and decrement operations.
Addition and Subtraction Instructions

The allowed operands: Examples

ADD AL , BL
ADD AX , DI
ADC DX , 1234H
SUB AX , [BX]
SBB [BX+DI] , CL
INC AL
DEC [DI]
Ex: Write an ALP that subtracts Ex: Write a piece of code to add
1234H existing in DX from the two 32-bit numbers stored at
word beginning at memory 82000H and 84000H and store the
location 64200. result at 86000H.
Ans. : Ans. :
MOV AX , 6000H MOV AX , 8000H
MOV DS , AX MOV DS , AX
MOV BX , 4200H MOV AX , [2000]
MOV DX , 1234H MOV DX , [2002]
SUB [BX] , DX ADD AX , [4000]
HLT ADC DX , [4002]
MOV [6000] , AX
MOV [6002] , DX
HTL

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Multiplication and Division Instructions:

The 8086µP has instructions for multiplication and division of binary,
BCD numbers, and signed or unsigned integers. Multiplication and division are
performed on bytes or on words.

The allowed operand: Examples

Source MUL BL
DIV [SI]
IMUL BX
IDIV [DI+1000H]

Ex: Write an ALP for dividing Ex : If (AL) = -1 and (BL) = -2 ,

1234H by 34H. what is the result of Executing :
Ans. 1. MUL BL
MOV AX, 1234H 2. IMUL BL
MOV CL, 34H Ans.
DIV CL The 2'complement of -1 = FFH
HLT The 2'complement of -2 = FEH
After Execution : (AX)= 2059H 1. (AX) = FF*FE = FD02H
Quotient in AL = 59H and 2. (AX) = -1H* -2H = 0002H
Remainder in AH = 20H.

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CBW(Convert Signed Byte to Word) & CWD(Convert Signed Word to

Double Word) instructions:
The division instruction can also be used to divide a sign 8-bit dividend in AL
by an 8-bit divisor. For this purpose we use (CBW) instruction. When (CBW)
instruction is executed the value of AX register is as shown below:
AH=0 if the number is positive & AH=1 if the number is negative.

Ex: What is the result of executing the following piece of code?

MOV AL , A1H
CBW
CWD

The first instruction loads AL with

(AL)=A116=101000012
Executing the second instruction gives:
(AH)=111111112 = FF16
(AX)=11111111101000012= FFA116
Executing the third instruction gives:
(AX)=FFA116
(DX)=FFFF16

Ex: Write an ALP that divide a signed byte stored in 5600AH by the
content of BL.
Ans.
MOV AX , 5000H
MOV DS , AX
MOV SI , 6000H
MOV AL , [SI + 0AH]
CBW
IDIV BL
MOV [SI + 0AH] , AX
HLT

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Ex : Write an ALP to evaluate x(y + z) where x = 10H, y = 20H and z = 30H

and store the result in a memory location 54000H.

MOV AX , 5000H
MOV DS , AX
MOV AL , 20H
MOV CL , 30H
ADD AL , CL
MOV CL , 10H
MUL CL
MOV SI , 4000H
MOV [SI] , AX
HLT
Ex: Write an ALP to multiply the word 1234H by the double word
12345678H. Store the result in locations starting in 54000H.

MOV AX , 1234H
MOV BX , 5678H
MOV CX , 1234H
MUL BX
MOV SI , AX
MOV DI , DX
MOV AX , 1234H
MUL CX
ADC AX , DI
ADC DX , 0000H
MOV BX , 5000H
MOV DS , BX
MOV [4000H], SI
MOV [4002H],AX
MOV [4004H],DX
HLT

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Logical Instructions:
This group includes AND, OR, XOR and NOT instructions. These
instructions perform logic operations. They are used to clear , set, and
complement certain bits in a register or a memory location.

NOT Instruction gives the 1's complement of the operand (X = X)

NEG Instruction gives the 2's complement of the operand (X=X+1)
The allowed operands Examples
AND AL , BL
(AND, OR , XOR) AND AX , [BX]
OR [SI+1000] , CL
XOR AX , AX
NOT and NEG NOT DL
NOT [2000]

Note: After executing AND , OR, or XOR instructions CF and OF are both 0.
PF, SF, and ZF are updated . AF is undefined.

Ex : Write an ALP to clear bits 0 to 5, set bits 6 to 10 and complement bits

11 to 15 in a memory location 34000H.
Ans.
MOV AX , 3000H
MOV DS , AX
AND [4000] , FFC0H
OR [4000] , 07C0H
XOR [4000] , F800H
HLT

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Shift Instructions:
Shift instructions can perform two basic types of shift operations: the
logical shift and the arithmetic shift. Also, each of these operations can be
performed to the right or to the left. They have the ability to shift the contents of
either an internal register or a storage location in memory.

SHL D,1 Shift D (Reg. / Mem.)

SHL D , CL to left either by 1 bit or
SAL D,1 by number of bits
SAL D , CL stored in CL .
SHR D , 1 Shift D (Reg. / Mem.)
SHR D , CL to right either by 1 bit
or by number of bits
stored in CL .
SAR D , 1 Shift D (Reg. / Mem.)
SAR D , CL either by 1 bit or by
number of bits stored
in CL .

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex: If (AX)=1234H , then, executing: SHL AX , 1

(AX) = 2468H & (CF)=0

Ex: If (CL)=2 and (AX)= 1234AH. Then, executing: SAR AX , CL leads to:
(AX)=048EH & (CF)=0

Rotate (ROL, ROR, RCL, and, RCR ) Instructions:

Rotate instructions, are similar to the shift instructions. The operation of
these instructions is described below. They have the ability to rotate the contents
of either an internal register or a storage location in memory.

ROL D , 1 Rotate D (Reg./Mem.) left

ROL D , CL out of carry either by 1 bit
or No. of bits stored in CL .

ROR D , 1 Rotate D (Reg./Mem.) right

ROR D , CL out of carry either by 1 bit
or No. of bits stored in CL .

RCL D , 1 Rotate D (Reg./Mem.) left

RCL D , CL through carry either by 1
bit or No. of bits in CL .

RCR D , 1 The same operation of RCL

RCR D , CL but to the right.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex : If (CL) =0416 and AX=1234A16. Determine the new contents of AX and the
carry flag after executing the instructions:
a) ROL AX, 1 b) ROR AX, CL
Ans.
a) (AX) = 2468H and (CF) = 0

b) (AX) = 4123H and (CF)=1

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Flags Control Instructions

The flag control instruction affect the state of the flags directly, these
instructions and their operation are listed below:

LAHF instruction : Load (copy to) AH with the low byte the flag register.
(AH) ← (Low byte of flag register)
SAHF instruction : Store (copy) AH register to low byte of flag register.
(Low byte of flag register) ← (AH)
Ex: Write an ALP that complements the first byte of flags register.
LAHF
XOR AH , 0FFH
SAHF
HLT

Compare CMP and TEST Instructions

The following are the characteristics of CMP instruction:
 Can compare two 8-bit or two 16-bit numbers.
 Operands many reside in memory, a register in the CPU or be a part of an
instruction.
 CMP is a subtraction method, it uses 2’s complement .
 Result of CMP is not saved in the destination operand.
 Results of comparison is reflected in the six status flags: CF, AF, OF, PF,
SF and ZF.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Examples

CMP AX , BX
CMP DL , CL
CMP AL , [BX]
CMP CX , 1234h
CMP [SI+100H] , 1234H

The TEST Instruction

This instruction ANDs the contents of a source byte or word with the
contents of specified destination word. Flags are updated but neither operand is
changed. TEST instruction is often used to set flags before a condition jump
instruction.

Mnemonic Meaning Format Operation Flags Affected

TEST test TEST D , S (D) . (S) PF , ZF , SF

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Program Control Instructions

Branch Instructions (Jump)
There are two basic types of jump:
 The Intra-segment jump is a jump within the current code segment. It is
achieved by only modifying the value of IP.
 The Inter-segment jump is a jump from one segment to another, both CS
and IP values are to be modified.

Unconditional and Conditional Jump

 Unconditional Jump (JMP)

Specifies a new value of IP with an 8-bit immediate operand.

Specifies a new value of IP with a 16-bit immediate operand.
Specifies a new value of IP and A new segment.
Specifies a new value of IP with the content of a 16-bit memory operand.
Specifies a new value of IP with the content of a 16-bit Reg. operand.
Specifies a new value of IP with the content of a 32-bit memory operand.

 Short-label , Near-label , Memptr16 or Regptr16 types of operands

represent intra-segment jump.
 Far-label and Memptr32 represent inter-segment jump.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Conditional Jump

Cond. Unsigned Signed

JE : Jump Equal JE : Jump Equal
= ZF = 1 ZF = 1
JZ : Jump Zero JZ : Jump Zero
JNZ : Jump Not Zero JNZ : Jump Not Zero
≠ ZF = 0 ZF = 0
JNE : Jump Not Equal JNE : Jump Not Equal
JA : Jump above
CF = 0 JG : Jump Greater ZF = 0
> JNBE : Jump if Non Below
and ZF = 0 and SF = OF
Nor Equal
JB : Jump Below
< JNAE : Jump Non Above CF = 1 JL : Jump Less SF ≠ OF
nor Equal
JAE : Jump Above or Equal JGE : Jump Greater or
≥ CF = 0 SF = OF
JNB : Jump Non Below Equal
JBE : Jump Below or Equal CF = 1 JLE : Jump Less or Equal SF ≠ OF
≤
JNA : Jump Non Above or ZF = 1 or ZF = 1

JC : Jump if Carry CF=1

Carry
JNC: Jump if No Carry CF=0
JZ: Jump if Zero ZF=1
Zero
JNZ: Jump if No Zero ZF=0
JPE : Jump if Parity Even PF=1
Parity
JPO: Jump if Parity Odd PF=0
JS: Jump if Signed (if negative) SF = 1
Sign
JNS: Jump if Not Signed (if positive) SF = 0
JO: Jump if Overflow OF = 1
Overflow
JNO: Jump if Not Overflow OF = 0

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex: Write a piece of code that transfers a block of 256 bytes stored at
locations starting at 34000H to locations starting at 36000H.
Ans.
MOV AX , 3000H 360FF ← 340FF
MOV DS , AX ←
MOV BX , 0000H ←
.
MOV CX , 100H
.
NEXT: MOV AL , [BX + 4000H] .
MOV [BX + 6000H] , AL .
INC BX .
DEC CX 36001 ← 34001
JNZ NEXT 36000 ← 34000
HLT
Ex : Write an ALP that adds an array of integers of size 256 byte stored at
locations starting at 54000H with another array starting at address 56000H,
store the result at locations starting at 58000H.
Ans.
MOV AX , 5000H 540FF 560FF 580FF
MOV DS , AX . .
MOV BX , 0000H . .
MOV CX , 100H . .
NEXT: MOV AL , [BX + 4000H] . + . =
. .
ADD AL , [BX + 6000H]
. .
MOV [BX + 8000H] , AL . .
INC BX 54001 56001 58001
DEC CX 54000 56000 58000
JNZ NEXT
HLT
Ex: Write an ALP to find the absolute subtraction of two arrays of size
1024 bytes starting at 82000H and 84000H respectively. Store the results at
locations starting at 86000H.
Ans.
MOV AX , 8000H
MOV DS , AX
XOR SI , SI
MOV CX , 400H
NEXT: MOV AL , [SI + 2000H]
CMP AL , [SI + 4000H]
JB N1
SUB AL , [SI + 4000H]
JMP N2
N1: MOV BL , [SI + 4000H]

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

XCHG AL , BL
SUB AL , BL
N2: MOV [SI + 6000H] , AL
INC SI
DEC CX
JNZ NEXT
HLT
Ex: Write an ALP that counts the number of 1’s in a byte stored in 54000H
and stores the result in 54001H
Ans.
XOR BL , BL ; clear BL to keep the number of 1s
MOV CL , 8 ; rotate total of 8 times
MOV AX , 5000H
MOV DS , AX
MOV SI , 4000H
MOV AL , [SI]
AGAIN: ROL AL,1 ; rotate it once
JNC NEXT ; check for 1
INC BL ; if CF=1 then add one to count
NEXT: DEC CL ; go through this 8 times
JNZ AGAIN ; if not finished go back
INC SI
MOV [SI] , BL
HLT
Ex : Write a piece of code to find the number of negative integers in an
array of size 1024 byte contain signed numbers stored at addresses starting
at 21000H, store the result in a location 51000H.
Ans.
MOV AX , 2000H
MOV DS , AX
MOV CX , 400H
MOV DL , 00H
MOV SI , 0000H
AGAIN: MOV AL , [SI+1000H]
ROL AL , 1
JNC NEXT
INC DX
NEXT: INC SI
DEC CX
JNZ AGAIN
MOV AX , 5000H
MOV [1000H] , DX
HLT

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex: Write an ALP to find the maximum byte of a block of 256 bytes
starting at 53000H. Store the result at 56000H.

MOV AX , 5000H
MOV DS , AX
MOV SI , 3000 H
MOV CX , 0100 H
MOV AH , 00 H
NEXT: CMP AH , [SI]
JAE PASS
MOV AH, [SI]
PASS: INC SI
DEC CX
JNZ NEXT
MOV DI , 6000
MOV [DI] , AH
HLT

Ex : Write a program finds the factorial of 08H .

Ans.
MOV BX , 08
MOV AX , 0001
LOOP: MUL BX
DEC BX
JNZ LOOP
HLT

H.W :
 Write a piece of code to find the number of odd integers in an array
of size 1024 byte stored at addresses starting at 21000H, store the
result in location 51000H.
 Write a piece of code that exchanges a block of 256 bytes stored at
locations starting at 34000H with another block starting at 36000H.
 By using XCHG instruction.
 By using MOV instruction.
 Write an ALP to find the 2’s complement of a block of 100 bytes
starting at 53000H and store the result in
 Write an ALP to find the minimum value of a byte from a block of
256 bytes starting at 53000H. Store the result at 56000H.
 Write an ALP to find the sum of the following series:
Sum=1 + 2 + 3 + 4 + ………………………..+ 100

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Branch Program Structure IF – THEN – ELSE

The High–level language IF–THEN–ELSE structure is expressed by the
following assembly structure:
CMP AX , BX
JNE NEQUAL
--- --- ; Next instruction if (AX) = (BX)
..
NEQUAL: --- --- ; Next instruction if (AX) ≠ (BX)
..
--- ---

Loop Program Structures WHILE – LOOP

A typical WHILE – LOOP shown in the following flow chart can be expressed
by the following assembly structure:

count= final;
while (count !=0)
{
Loop program statements;
--count;
}
….. // next statement

MOV CL , COUNT ; Set loop repeat count

AGAIN: JZ NEXT ; Loop is complete if CL=0 (ZF=1)
--- --- ; First instruction of the loop
--- --- ; Second instruction of the loop
...
--- --- ; last instruction of the loop
DEC CL ; Decrement repeat count by 1
JMP AGAIN ; Repeat from AGAIN
NEXT: --- --- ; First instruction executed after the loop
is complete

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Loop Instructions
There are three loop instructions. They can be used in place of certain
conditional jump instructions. These instructions give the programmer a
flexibility in writing programs in a simpler manner. The different loop
instructions and the operations they perform are listed below:

CX = CX - 1
NEXT

CX ≠ 0 ? Yes

No

Ex: Write a piece of code that transfers a block of 256 bytes stored at
locations starting at 34000H to locations starting at 36000H.
Ans.
MOV AX , 3000H
MOV DS , AX
MOV BX , 0000H
MOV CX , 100H
NEXT: MOV AL , [BX + 4000H]
MOV [BX + 6000H] , AL
INC BX
LOOP NEXT
HLT

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex: Write an ALP to find the maximum byte from a block of 256 bytes
starting at 53000H.
Ans.
MOV AX , 5000H
MOV DS , AX
LEA SI , [3000H]
MOV CX , 0100H
MOV AH , 00H
AGAIN: CMP AH , [SI]
JAE NEXT
MOV AH , [SI]
NEXT: INC SI
LOOPNE AGAIN
MOV [SI] , AH
HLT
Ex : Write an ALP that counts the number of letters M in a string of size
256 bytes starts at 5F600H.
MOV AX , 5000H
MOV DS , AX
LEA SI , [F600H]
MOV CX , 100H
MOV DL , 00H
MOV AL , 4DH ; 4D is the ASCII code of the letter M
AGAIN: CMP AL , [SI]
JNE NEXT
INC DL
NEXT: INC SI
LOOP AGAIN
HLT
Ex: Write an ALP to find the average of an array of size 256 bytes of
unsigned integers starting at 6A000H.
MOV AX , 6000H
MOV DS , AX
XOR BX , BX
XOR AX , AX
MOV CX , 100H
AGAIN: ADD AL , [BX+2000H] H.W: Repeat the previous example
ADC AH , 00H if the array has signed integers
NEXT: INC BX
LOOP AGAIN
XOR DX , DX
DIV BX
HLT

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Stack Instructions
The stack in the 8086/8088 µPs, like that in many microprocessors, is a region
of memory that can store information temporarily (‫ )بصىرة مؤقتت‬during the
execution of the program. It is called a stack, because you "stack" things on it.
The stack is a Last-In-First-Out, (LIFO) structure so the last thing stored in
the stack is the first thing retrieved. The philosophy is that you retrieve (‫)يستزجع‬
(pop) data in the opposite order of storing (push) it .
In the 8086/8088µP, the stack pointer is SS:SP (physical address) , which is a 16
bit pointer into a 20 bit address space.
 In a POP operation, the data is retrieved (POPed) from that address
(SS : SP). The SP register is incremented by 2.
(Low byte of the operand) ← SS : SP
(High byte of the operand) ← SS : (SP) + 1
(SP)← (SP) + 2
 In a PUSH operation, the data of the source is stored (pushed) at address
(SS : SP). The SP register is decremented 2.
SS: (SP) – 1 ← (High byte of the operand)
SS: (SP) – 2 ← (Low byte of the operand)
(SP) ← (SP) – 2
 POPF retrieves a word from the stack and places it into the flags register
and increments the stack pointer SP by 2.
(Low Byte of Flags Reg.) ← SS : SP
(High Byte of Flags Reg.) ← SS : (SP) + 1
(SP) ← (SP) + 2
 PUSHF pushes the contents of the flags register onto the stack at address
(SS : SP) and decrements the stack pointer SP by 2.
SS : (SP) – 1 ← (High Byte of Flags Reg.)
SS : (SP) – 2 ← (Low Byte of Flags Reg.)
(SP) ← (SP) – 2

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Note: PUSHF / POPF have no operands

The figure below shows that if (SS) = 3000H , (SP) = 0042H, so the execution
of POP CX loads CX by the word 4050H form the stack segment. The SP is
incremented by 2.

The figure below shows the Execution of PUSH CX if (SS) = 3000H , (SP) =
0034H and (CX)=2030H. This instruction copies the contents of CX in locations
30033H and 30032H in stack segment. The SP is decremented by 2.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

String Instructions
1. MOVS ( MOVSB / MOVSW ) MOVES STRING BYTE OR STRING
WORD: This instruction copies a byte or a word from location in the data
segment to a location in the extra segment. The offset of the source in the data
segment must be in the SI register. The offset of the destination in the extra
segment must be in the DI register. For multiple-byte or multiple-word
moves, the number of elements to be moved is put in the CX
register(counter). If DF is 0, then SI and DI will incremented by 1 after a byte
move and by 2 after a word move. If DF is 1, then SI and DI will be
decremented by 1 after a byte move and by 2 after a word move. MOVS does
not affect any flag.
MOVSB MOVSW
DF=0 DF=1 DF=0 DF=1
(ES:DI) ← (DS:SI) (ES:DI) ← (DS:SI) (ES:DI) ← (DS:SI) (ES:DI) ← (DS:SI)
SI ← SI + 1 SI ← SI - 1 SI ← SI + 2 SI ← SI - 2
DI ← DI + 1 DI ← DI - 1 DI ← DI + 2 DI ← DI - 2
2. LODS ( LODSB / LODSW ) LOAD STRING BYTE INTO AL OR
STRING WORD INTO AX :This instruction copies a byte or a word from a
string location pointed to by SI to AL or to AX. If DF is 0, SI will be
automatically incremented (by 1 for a byte string, and 2 for a word string) to
point to the next element of the string. If DF is 1, SI will be automatically
decremented (by 1 for a byte string, and 2 for a word string) to point to the
previous element of the string. LODS does not affect any flag.
LODSB LODSW
DF=0 DF=1 DF=0 DF=1
(AL) ← (DS:SI) (AL) ← (DS:SI) (AX) ← (DS:SI) (AX) ← (DS:SI)
SI ← SI + 1 SI ← SI - 1 SI ← SI + 2 SI ← SI - 2

3. STOS ( STOSB / STOSW ) STORE STRING BYTE OR STRING

WORD: This instruction copies a byte from AL or a word from AX to a
memory location in the extra segment pointed to by DI. If DF is 0, then DI
will automatically incremented by 1 for a byte string and by 2 for a word
string. If DI is 1, DI will be automatically decremented by 1 for a byte string
and by 2 for a word string. STOS does not affect any flag.

STOSB STOSW
DF=0 DF=1 DF=0 DF=1
(ES:DI) ← (AL) (ES:DI) ← (AL) (ES:DI) ← (AX) (ES:DI) ← (AX)
DI ← DI + 1 DI ← DI - 1 DI ← DI + 2 DI ← DI - 2

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

4. CMPS ( CMPSB / CMPSW ) COMPARE STRING BYTE OR STRING

WORD : This instruction can be used to compare a byte / word in the
source string with a byte / word in the destination string. SI stores the offset
of the byte or word in the source string, and DI stores the offset of the byte
or word in the destination string. The AF, CF, OF, PF, SF, and ZF flags are
affected by the comparison, but the two operands are not affected. If DF is 1,
then SI and DI will automatically be decremented by 1 for a byte string and
by 2 for a word string. If DF is 0, then SI and DI will automatically be
incremented by 1 for byte strings and by 2 for word strings.
CMPSB CMPSW
DF=0 DF=1 DF=0 DF=1
(DS:SI) - (ES:DI) (DS:SI) - (ES:DI) (DS:SI) - (ES:DI) (DS:SI) - (ES:DI)
SI ← SI + 1 SI ← SI - 1 SI ← SI + 2 SI ← SI - 2
DI ← DI + 1 DI ← DI - 1 DI ← DI + 2 DI ← DI - 2

5. SCAS ( SCASB / SCASW ) SCAN A STRING BYTE OR A STRING

WORD : This instruction compares a byte in AL or a word in AX with a
byte or a word in Extra-segment , DI must contain the effective address. If
DF is 0, then DI will be incremented by 1 for byte strings and by 2 for word
strings. If DF is 0, then DI will be decremented by 1 for byte strings and by
2 for word strings. SCAS affects AF, CF, OF, PF, SF, and ZF, but it does not
change either the operand in AL / AX or the operand in the string.
SCASB SCASW
DF=0 DF=1 DF=0 DF=1
(AL) - (ES:DI) (AL) - (ES:DI) (AX) - (ES:DI) (AX) - (ES:DI)
DI ← DI + 1 DI ← DI - 1 DI ← DI + 2 DI ← DI - 2

The following table summarizes all the string instructions:

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex: Write a piece of code that transfers a block of 256 bytes stored at
locations starting at 34000H to locations starting at 36000H.
Ans.
MOV AX , 3000H
MOV DS , AX
MOV ES , AX
MOV SI , 4000H
MOV DI , 6000H H.W : Repeat by using MOVSW
MOV CX , 100H
CLD
NEXT: MOVSB
LOOP NEXT
HLT
Ex: Write an ALP to initialize a block of memory starting at 8A000H with
English alphabet (A to Z) using string instructions.
Ans.
MOV AX , 8000H
MOV ES , AX
MOV AL , 'A'
MOV DI , A000H
MOV CX , 18H
CLD
AGAIN: STOSB
INC AL
LOOP AGAIN
HLT
Ex: Write an ALP that scans the byte 05H in a block of memory of size 16
starting at 2A000H, if is found loads BL with 01H otherwise load BL with
00H.
MOV AX, 2000H
MOV ES, AX
MOV AL, 05
MOV DI, 0A000H
MOV CL, 10H
MOV BL , 00H
CLD
AGAIN: SCASB
LOOPNE AGAIN
JNE END
MOV BL , 01H
END: HLT

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

6. REP & (REPE / REPZ) & (REPNE / REPNZ)

REPEAT STRING INSTRUCTION UNTIL SPECIFIED
CONDITIONS EXIST:
REP (Repeat) is written before one of the string instructions. It will cause
the CX register to be decremented and the string instruction to be repeated
until CX = 0. The instruction REP MOVSB, for example, will continue to
copy string bytes until the number of bytes into CX has been copied.
REPE and REPZ (Repeat if Equal and Repeat if Zero) : They will cause
the string instruction to be repeated as long as the compared bytes or words
are equal (ZF = 1) and CX is not equal to zero. In other words, there are two
conditions that will stop the repetition: CX = 0 or string bytes or words not
equal.
REPNE and REPNZ (Repeat if Not Equal and Repeat if Not Zero)
respectively. They are often used with the Compare String instruction or
with the Scan String instruction. They will cause the string instruction to be
repeated as long as the compared bytes or words are not equal (ZF = 0) and
CX is not yet counted down to zero.

Ex: Write an ALP that loads a block of memory of size 256 starting at
7A000H with a value 55H by repeating the STOSB instruction.
Ans.
MOV AX, 7000H
MOV ES, AX
MOV DI, 0A000H H.W Repeat by using MOV instruction
MOV AL, 55H
MOV CX, 100H
CLD
REP STOSB
HLT

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex : Two arrays of size 1Kbyte stored at 21000H and 52000H respectively.

Write a piece of code to store 01H in AH if they are equal or 00H if they are
not equal.
Ans.
MOV AX , 2000H
MOV DS , AX
MOV AX , 5000H
MOV ES , AX
MOV SI , 1000H
MOV DI , 2000H H.W. : Repeat using CMPSW
MOV AH , 00H
CLD
MOV CX , 400H
REPE CMPSB
JNE END
MOV AH , 01H
END: HLT
Ex: Describe what happen as the following sequence of instruction is
executed.
Ans.
CLD
MOV AX , 5000H
MOV DS , AX Ans.
MOV AX , 5000H This program is used to transfer 32 bytes
MOV ES , AX
form locations starting at 52000H to
MOV CX , 20H
MOV SI , 2000H another locations starting at 54000H.
MOV DI , 4000H
REP MOVSB
HLT

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Subroutines
A subroutine is a special program that performs a certain task(‫)مهمت او وظيفت معينت‬
and is called for execution from any point in the main program. A subroutine is
also known as a procedure. A return instruction must be included at the end of
the subroutine to return execution to the main program.

CALL Instruction (call a procedure)

The CALL instruction is used to transfer execution to a subprogram or a
procedure. There two basic type of calls :
1. near call is a call to a procedure, which is in the same code segment as the
CALL instruction. When the 8086 executes a near CALL instruction, it
decrements the stack pointer by 2 and copies the offset of the next
instruction after the CALL into the stack.
2. far call is a call to a procedure, which is in a different segment. When the
8086 executes a far call, it decrements the SP by 2 and copies the content
of the CS register to the stack. It then decrements the SP by 2 again and
copies the offset of the instruction after the CALL instruction to the stack.

A RET instruction at the end of the procedure will return execution to the next
instruction after the CALL instruction by restoring the saved values IP (in the
case of near call) or CS and IP (in the case of far call) from the stack.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Ex: Write an ALP to calculate the combinations from the following

formula, store the result in AX.

Ans.
MOV CL , n ; n is positive integer less than or equal to 08H
MOV CH , m ; m is positive integer less than or equal to 08H
CMP CL , CH
JC STOP
MOV BL , CL
CALL FACT
MOV SI , AX
MOV BL , CH
CALL FACT
MOV DI , AX
SUB CL , CH
MOV BL , CL
CALL FACT
MUL DI
MOV CX , AX
MOV AX , SI
XOR DX , DX
DIV CX
STOP: HLT

; Subroutine finds the factorial

FACT: MOV AX , 0001H
CMP BL , 00H
JE END
MOV BH , 00H
AGAIN: MUL BX
DEC BX
JNZ AGAIN
END: RET

If n = 06H and m = 04H then after execution (AX) = 000FH

If n = 08H and m = 04H then after execution (AX) = 0046H
If n = 06H and m = 06H then after execution (AX) = 0001H

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Ex: Write an ALP to find the sum of the following series:

Sum= 11 + 22 + 33 + 44 + 55 + 66
Ans.

MOV BX ,0000H
MOV SI , 0001H
XOR DI , DI
NEXT: CALL SUBR
ADD BX , AX
ADC DI , 0000H
INC SI
CMP SI , 0007H
JNZ NEXT
HLT

; Subroutine finds the power

SUBR: MOV CX ,SI
MOV AX , 0001H
AGAIN: MUL SI
DEC CX
JNZ AGAIN
RET

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Input / Output (IN / OUT) Instructions

 The IN instruction copies data from a port to the AL or AX register. If an 8-
bit is read, the data will go to AL. If a 16-bit is read, the data will go to AX.
The IN instruction does not change any flag. The general form is :
IN AL / AX , (input port)
 The OUT instruction copies a byte from AL or a word from AX to the
specified port. The OUT instruction does not affect any flag. The general
form is :
OUT (output port) , AL / AX

The IN / OUT instructions has two possible formats:

 Fixed (Direct) Port : the 8-bit address of a port is specified directly in the
instruction. With this form 256 possible ports can be addressed.
IN AL , 0C8H ; Input a byte from port 0C8H to AL
OUT 34H , AX ; Output a word from AX to 34H port
 Variable (Indirect) Port : the port address is loaded into the DX register
before the IN instruction is executed. Since DX is a 16-bit register, the
port address can be any number between 0000H and FFFFH. Therefore,
up to 65,536 ports are addressable in this mode.
MOV DX , 0FF78H ; Initialize DX with a port address
IN AX , DX ; Input a word from the port 0FF78H to AX
OUT DX , AL ; Output a byte from AL to the port 0FF78H

Note : The variable-port IN / OUT instructions has advantage that the port
address can be computed or dynamically determined in the program. Suppose,
for example, that an 8086-based computer needs to input data from 10 terminals,
each having its own port address. Instead of having a separate procedure to input
data from each port, you can write one generalized input procedure and simply
pass the address of the desired port to the procedure in DX.

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Ex: Write a piece of code to send 55H to output port device which its
address is F300H.
MOV AL , 55H
MOV DX , F300H
OUT DX , AL
Ex: Write a piece of code to input the contents of the byte-wide input port
at A000H of the I/O address space into BL.
MOV DX, 0A000h
IN AL, DX
MOV BL, AL
Ex: Write a piece of code to read data from two byte-wide input ports at
addresses AAH and A9H and output the data as a word to the word-wide
output port at address B000H.
IN AL, 0AAh
MOV AH, AL
IN AL, 0A9h
MOV DX, 0B000h
OUT DX, AX

Ex: An array of size 1 Kbyte is stored at addresses starting at 72000H, write

an ALP to send even parity bytes to port address 378H and odd parity bytes
to port 478H.
MOV AX , 7000H
MOV DS , AX
MOV CX , 400H
XOR BX , BX
AGAIN: MOV AL , [BX + 2000H]
OR AL , 00H
JP EVEN
MOV DX , 478H
OUT DX , AL
JMP NEXT
EVEN: MOV DX , 378H
OUT DX , AL
NEXT: INC BX
DEC CX
JNZ AGAIN
HLT

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Miscellaneous Instructions
 HLT (HALT PROCESSING)
The HLT instruction causes the 8086 to stop fetching and executing
instructions. The 8086 will enter a halt state. The different ways to get the
processor out of the halt state are with an interrupt signal on the INTR
pin, an interrupt signal on the NMI pin, or a reset signal on the RESET
input.

 NOP (PERFORM NO OPERATION)

This instruction simply takes three clock cycles (3T) and increments the
instruction pointer to point to the next instruction. The NOP instruction
can be used to increase the delay of a delay loop. A NOP can also be used
to hold a place in a program for an instruction that will be added later.
NOP does not affect any flag.

 ESC (ESCAPE)
This instruction is used to pass instructions to a coprocessor, such as the
8087 Math coprocessor, which shares the address and data bus with 8086.
Instructions for the coprocessor are represented by a 6-bit code embedded
in the ESC instruction. As the 8086 fetches instruction bytes, the
coprocessor also fetches these bytes from the data bus and puts them in its
queue. However, the coprocessor treats all the normal 8086 instructions as
NOPs. When 8086 fetches an ESC instruction, the coprocessor decodes
the instruction and carries out the action specified by the 6-bit code
specified in the instruction. In most cases, the 8086 treats the ESC
instruction as a NOP.

 INT – INT TYPE

The term TYPE in the instruction format refers to a number between 0
and 255, which identify the interrupt. When an 8086 executes an INT
instruction, it will
1. Decrement the stack pointer by 2 and push the flags on to the stack.
2. Decrement the stack pointer by 2 and push the content of CS onto the
stack.
3. Decrement the stack pointer by 2 and push the offset of the next
instruction after the INT number instruction on the stack.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

4. Get a new value for IP from an absolute memory address of 4 times the
type specified in the instruction. For an INT 8 instruction, for example,
the new IP will be read from address 00020H.
5. Get a new for value for CS from an absolute memory address of 4 times
the type specified in the instruction plus 2, for an INT 8 instruction, for
example, the new value of CS will be read from address 00022H.
6. Reset both IF and TF. Other flags are not affected.

 WAIT – WAIT FOR SIGNAL OR INTERRUPT SIGNAL

When this instruction is executed, the 8086 enters an idle state and is
doing no processing. The 8086 will stay in this idle state until the 8086
TEST input pin is made low(TEST=0) or until an interrupt signal is
received on the INTR or the NMI interrupt input pins. WAIT does not
affect any flag. The WAIT instruction is used to synchronize the 8086
with external hardware such as the 8087 Math coprocessor.

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Converting Assembly Language Instructions to Machine Code

The general instruction format for machine code is shown below :

BYTE 1 Specification
 OPCODE field (6-bits) : Specifies the operation to be performed such as
MOV , ADD , SUB …..etc.
 Register direction bit (D-bit):
D = 1 : the register operand specified by REG in byte 2 is a destination
operand.
D = 0 : the register operand specified by REG in byte 2 is a source
operand
 Data size bit (W-bit): Specifies whether the operation will be performed
on 8-bit or 16-bit data.
W = 1 : 16-bit data size
W = 0 : 8-bit data size

BYTE 2 Specification: byte 2 has three fields:

 Mode (MOD) field (2-bits) : Indicates whether the operand is in register
or memory.

MOD Explanation
00 Memory Mode no displacement
01 Memory Mode 8-bit displacement
10 Memory Mode 16-bit displacement
11 Register Mode (no displacement)

 Register (REG) field (3-bit) : Identifies the register for the first operand
 Register/Memory (R/M) field (3-bit): Together with MOD field to
specify the second operand.

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REG W=0 W=1

000 AL AX
001 CL CX
010 DL DX
011 BL BX
100 AH SP
101 CH BP
110 DH SI
111 BH DI

MOD = 11 Effective Address Calculation

Reg. W=0 W=1 R/M MOD=00 MOD=01 MOD=10
000 AL AX 000 (BX)+(SI) (BX)+(SI)+D8 (BX)+(SI)+D16
001 CL CX 001 (BX)+(DI) (BX)+(DI)+D8 (BX)+(DI)+D16
010 DL DX 010 (BP)+(SI) (BP)+(SI)+D8 (BP)+(SI)+D16
011 BL BX 011 (BP)+(DI) (BP)+(DI)+D8 (BP)+(DI)+D16
100 AH SP 100 (SI) (SI)+D8 (SI)+D16
101 CH BP 101 (DI) (DI)+D8 (DI)+D16
110 DH SI 110 Direct Address (BP)+D8 (BP)+D16
111 BH DI 111 (BX) (BX)+D8 (BX)+D16

Ex : Encode the following instruction in machine code. Assume that the

OPCODE for MOV instruction is 1000102.
MOV BL , AL
Ans.
OPCODE = 100010 (for MOV), D = 0 (source), W = 0 (8-bit) this leads to :
BYTE 1 = 100010002 = 8816
In byte 2 the source operand, specified by REG is AL , then:
REG = 000, MOD = 11, R/M = 011
Therefore:
BYTE 2 = 110000112 = C316
The machine code for the instruction is:
MOV BL , AL = 88C3H

Ex : Encode the following instruction in machine code. Assume that the

OPCODE for ADD instruction is 0000002.
ADD AX , [SI]
Ans.
OPCODE = 000000 (for ADD), D = 1 (destination), W = 1 (16-bit) this leads to
BYTE 1 = 000000112 = 0316
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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

In byte 2 the destination operand, specified by REG is AX , then:

REG = 000, MOD = 00, R/M = 100
Therefore:
BYTE 2 = 000001002 = 0416
The machine code for the instruction is:
ADD AX, [SI] = 030416

Ex: Encode the following instruction in machine code. Assume that the
OPCODE for XOR instruction is 0011002.
XOR CL , [1234H]
Ans.
OPCODE = 001100 (for XOR), D = 1 (destination), W = 0 (8-bit) this leads to:
BYTE 1 = 001100102 = 3216
In byte 2 the destination operand, specified by REG is CL , then:
REG = 001 , MOD = 00, R/M = 110
Therefore:
BYTE 2 = 000011102 = 0E16
BYTE 3 = 3416 and BYTE 4 = 1216
The machine code for the instruction is:
XOR CL , [1234H] = 320E341216

Ex: Encode the following instruction in machine code. Assume that the
OPCODE for ADD instruction is 0000002.
ADD [BX+DI+1234H] , AX
Ans.
OPCODE = 000000 (for ADD) , D = 0 (source), W = 1 (16-bit) This leads to :
BYTE 1 = 000000012 = 0116
In byte 2 the destination operand, specified by REG is AX, then :
REG = 000 , MOD = 10 , R/M = 001
Therefore :
BYTE 2 = 100000012 = 8116
BYTE 3 = 3416 and BYTE 4 = 1216
The machine code for the instruction is:
ADD [BX+DI+1234H] , AX = 0181341216

Ex: Encode the following instruction in machine code

MOV [BP+DI+1234H] , 0ABCDH
Ans.
This example does not follow the general format. The OPCODE of MOV
(immediate to memory) is 1100011W, and W = 1 for word-size data, then:

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BYTE 1 = 110001112 = C716

BYTE 2 = (MOD)000(R/M) = 100000112 = 8316
BYTE 3 = 3416 and BYTE 4 = 1216
BYTE 5 = CD16 and BYTE 6 = AB16
The machine code for the instruction is:
MOV [BP+DI+1234H] , 0ABCDH = C7833412CDAB16

Instructions Involve a Segment Register (SR-field)

Instructions that involve a segment register need a 2-bit field to encode which
register is to be affected, this field is called the SR field. The four segment
registers are encoded as shown in the following table.

Segment Register SR
ES 00
CS 01
SS 10
DS 11

Ex: Encode the above instruction in machine code:

MOV [BP+DI+1234H] , DS
Ans.
This example does not follow the general format. The OPCODE of MOV (Seg.
Reg. to memory) is 100011002, and the instruction is:
10001100(MOD)0(SR)(R/M)(DISP)
Then we find that for DS , the SR = 11 therefore, the instruction is coded as:
MOV [BP+DI+1234H] , DS =100011001001101100110100000100102
=8C9B341216

Encoding a Complete Program in Machine Code

The following steps have to be followed in encoding a complete assembly
program:
 Identify the general machine code format.
 Evaluate the bit fields.
 Express the binary-code instruction in hexadecimal form
 To execute the program, the machine code of the program must be stored
in the code segment of memory.
 The first byte of the program is stored at the lowest address.

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Ex: Encode the “block move” program and show how it would be stored in
memory starting at address 20016.
Ans.
MOV AX , 2000H
MOV DS , AX
MOV SI , 100H
MOV DI , 120H
MOV CX , 10H
NXTPT: MOV AH , [SI]
MOV [DI] , AH
INC SI
INC DI
DEC CX
JNZ NXTPT
HLT

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The 8086/8088Microprocessor Architecture and Pin-configuration

The 8086µP, announced in 1978, was the first 16-bit microprocessor
introduced by Intel Corporation.
The 8086 µP is internally a 16-bit µP and externally it has a 16-bit data bus.
The 8086 µP is internally a 16-bit µP and externally it has a 8-bit data bus.
It has the ability to address up to 1 Mbyte of memory via its 20-bit address
bus.
In addition, it can address up to 64K of byte-wide input/output ports.
It is manufactured using high-performance metal-oxide semiconductor
(HMOS) technology, and the circuitry on its chip is equivalent to
approximately 29000 transistors.
The 8086µP is housed in a 40-pin dual in-line package. The signals pinned
out to each lead are shown in Figure below.
The address bus lines A0 through A15 and data bus lines D0 through D15 are
multiplexed. For this reason, they are labeled AD0 through AD15. By
multiplexed we mean that the same physical pin carries an address bit at one
time and the data bit at another time.

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Minimum-Mode and Maximum-Mode System

The 8086µP and 8088µP microprocessors can be configured to work in
either of two modes:
1. Minimum Mode:
 The 8086µP operates in minimum mode by connecting its
pin to Vcc. ( ).
 In this mode, all the control signals are given out by the
microprocessor chip.
 It is typically used for single microprocessor systems.
2. Maximum Mode:
 The 8086µP operates in minimum mode by connecting its
pin to ground. ( ).
 In this mode, the processor derives the status signal S2, S1, S0 by
another chip called bus controller.
 In the maximum mode, there may be more than one microprocessor
in the system configuration.

Minimum-Mode Interface Signals

The minimum-mode signals can be divided into the following basic groups:
Address/Data bus
Status signals
Control signals
Interrupt signals
Interface Signals

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Address/Data Bus:
 The address bus is 20 bits long and consists of signal lines A0 (LSB)
through A19 (MSB). However, only address lines A0 through A15 are used
when accessing I/O.
 The data bus lines are multiplexed with address lines. For this reason,
they are denoted as AD0 through AD15. Data line D0 is the LSB.

Status Signals:
 The four most significant address lines A16 through A19 of the 8086µP are
multiplexed with status signals S3 through S6. These status bits are output
on the bus at the same time that data are transferred over the other bus
lines.
 Bit S4 and S3 together from a 2 bit binary code that identifies which of
the 8086 internal segment registers are used to generate the physical
address as shown in the table below.
 Status line S5 reflects the status of the IF. The last status bit S6 is always
at the logic 0 level.

Control Signals:
 When Address latch enable (ALE) is logic 1 it signals that a valid
address is on the bus. This address can be latched in external circuitry on
the 1-to-0 edge of the pulse at ALE.
 ̅̅̅ (memory/IO) tells external circuitry whether a memory or I/O
transfer is taking place over the bus. Logic 1 signals a memory operation
and logic 0 signals an I/O operation.
 ̅ (data transmit/receive) signals the direction of data transfer over
the bus. Logic 1 indicates that the bus is in the transmit mode (i.e., data
are either written into memory or to an I/O device). Logic 0 signals that

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the bus is in the receive mode (i.e., reading data from memory or from an
input port).
 The bank high enable (̅̅̅̅̅̅) signal is used as a memory enable signal for
the most significant byte half of the data bus, D8 through D15.
 ̅̅̅̅̅ (write) is switched to logic 0 to signal external devices that valid
output data are on the bus.
 ̅̅̅̅ (read) indicates that the MPU is performing a read of data off the bus.
During read operations, one other control signal, ̅̅̅̅̅̅ (data enable), is
also supplied. It enables external devices to supply data to the
microprocessor.
 The READY signal can be used to insert wait states into the bus cycle so
that it is extended by a number of clock periods. This signal is supplied
by a slow memory or I/O subsystem to signal the MPU when it is ready
to permit the data transfer to be completed.
Interrupt Signals:
 Interrupt request (INTR) is an input to the 8086µP that can be used by an
external device to signal that it needs to be serviced. Logic 1 at INTR
represents an active interrupt request.
 When the MPU recognizes an interrupt request, it indicates this fact to
external circuits with logic 0 at the interrupt acknowledge (INTA) output.
 On the 0-to-1 transition of non-maskable interrupt (NMI), control is
passed to a non-maskable interrupt service routine at completion of
execution of the current instruction. NMI is the interrupt request with
highest priority and cannot be masked by software.
 The RESET input is used to provide a hardware reset for the MPU.
Switching RESET to logic 0 initializes the internal registers of the MPU
and initiates a reset service routine.
DMA Interface Signals:
The Direct Memory Access (DMA) interface of the 8086 minimum mode
consist of the HOLD and HLDA signals.
 When an external device wants to take control of the system bus, it
signals the MPU by switching HOLD to the logic level 1.
 When in the hold state, lines AD0 through AD15, A16/S3 through
A19/S6, ̅̅̅̅̅̅ ̅̅̅ ̅ ̅̅̅̅̅ ̅̅̅̅ ̅̅̅̅̅̅ are all put in the
high-Z state. The MPU signals external devices that it is in this state by
switching HLDA to 1.

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Maximum-Mode Interface
The maximum-mode configuration is mainly used for implementing a
multiprocessor/coprocessor system environment which means that
multiple processor exist in the system and each processor execute its own
program.
8086µP does not directly provide all the signals that are required to
control the memory, I/O and interrupt interfaces.
̅̅̅ ̅̅̅ ̅̅̅ are input to the external bus controller device (8288 Bus
Controller) , the bus controller generates the timed command and control
signals.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

System Clock
 To synchronize the internal and external operations of the microprocessor
a clock (CLK) input signal is used. The CLK can be generated by the
8284 clock generator IC.
 The 8086µP is manufactured in three speeds: 5 MHz, 8 MHz and 10 MHz
 For 8086µP, we connect either a 15-, 24- or 30-MHz crystal between
inputs X1 and X2 inputs of the clock chip (see Fig. 8-11). The
fundamental crystal frequency is divided by 3 within the 8284 to give
either a 5-, 8- or 10-MHz
 clock signal, which is directly connected to the CLK input of the 8086µP.

Bus Cycle and Time States

A bus cycle defines the sequence of events when the MPU communicates with
an external device, which starts with an address being output on the system bus
followed by a read or write data transfer.
Types of bus cycles:
 Memory Read Bus Cycle
 Memory Write Bus Cycle
 Input / Output Read Bus Cycle
 Input / Output Write Bus Cycle
The bus cycle of the 8086µP microprocessor consists of at least four clock
periods. These four time states are called T1, T2, T3 and T4.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Two Basic Memory Operations

The memory unit supports two fundamental operations: Read and Write. The
read operation read a previously stored data and the write operation stores a
value in memory, see the figure below.

Memory Read and write Bus Cycles

The following steps have to be followed in a typical read cycle:
1. Place the address of the location to be read on the address bus.
2. Activate the memory read control signal on the control bus.
3. Wait for the memory to retrieve the data from the address memory
location.
4. Read the data from the data bus.
5. Drop the memory read control signal to terminate the read cycle.

The following steps have to be followed in a typical read cycle:

1. Place the address of the location to be written on the address bus.
2. Place the data to be written on the data bus.
3. Activate the memory write control signal on the control bus.
4. Wait for the memory to store the data at the address location..
5. Drop the memory write control signal to terminate the write cycle.

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Memory Read Bus Cycle

Memory Write Bus Cycle

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Hardware Organization of the Memory Address Space

The 8088µP's memory address space as shown in figure below is
implemented as single 1 Mbyte memory bank.
The 8086µP's 1 Mbyte memory address space as shown in figure below is
implemented as two independent 512 Kbyte banks:
 Data bytes associated with an even address (00000, 00002, …. , FFFFE)
reside in the low bank.
 Data bytes associated with an odd addresses (00001, 00003, ….. , FFFFF)
reside in the high bank.
Address bits A1 through A19 select the location that is to be accessed.
They are applied to both banks in parallel. A0 (BLE) and bank high
enable (BHE) are used as bank-select signals:
 A0 = 0 causes the low bank to be enabled.
 BHE = 0 causes the high bank to be enabled.
Each of the memory banks provides half of the 8086µP's 16-bit data bus.
The lower bank transfers bytes of data over data lines D0 through D7,
while data transfers for a high bank use D8 through D15.

The byte transfer operation and word transfer operation of the 8088µP is
as illustrated in figure below. The byte transfer operation needs one bus
cycle, while word transfer operation needs two bus cycles.

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8086/8088MP INSTRUCTOR: ABDULMUTTALIB A. H. ALDOURI

Figure below shows how a byte transfer operation is performed to address

X, an even-addressed storage location. A0 is set to logic 0 to enable the
low bank of memory and BHE to logic 1 to disable the high bank. Data
are transferred to or from the lower bank over data bus lines D0 - D7.

Figure below shows how a byte transfer operation is performed to an odd

addressed storage location such as X + 1. A0 is set to logic 1 and BHE to
logic 0. This enables the high bank of memory and disables the low bank.
Data are transferred over bus lines D8 through D15. D8 represents the LSB.

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Figure below illustrates how an aligned word (at even address X) is

accessed. Both the high and low banks are accessed at the same time.
Both A0 and BHE are set to 0. This 16-bit word is transferred over the
complete data bus D0 through D15 in just one bus cycle.

Figure below illustrates how a misaligned word (at address X + 1) is

accessed. Two bus cycles are needed. During the first bus cycle, the byte
of the word located at address X + 1 in the high bank is accessed over D8
through D15. Even though the data transfer uses data lines D8 through D15,
to the processor it is the low byte of the addressed data word. In the
second memory bus cycle, the even byte located at X + 2 in the low bank
is accessed over bus lines D0 through D7.
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Input /Output Interface

Input / Output (I/O) devices provide the means by which the computer system
can interact with the outside world. Computers use I/O devices (also called
peripheral devices) for two major purposes:
1- To communicate with the outside world and,
2- Store data.
Devices that are used to communicate like, printer, keyboard, modem. Devices
that are used to store data like disk drive. I/O devices are connected to the
system bus through I/O controller (interface) – which acts as interface between
the system bus and I/O devices.The 8086µP employs two different types of
input/output (I/O): Isolated I/O and Memory-mapped I/O. These I/O methods
differ in how I/O ports are mapped into the 8086's address spaces.

Isolated Input/Output:
The I/O devices are treated separate from memory. I/O ports are organized as
bytes of data; the memory address space contains 1M consecutive byte
addresses in the range 00000H, through FFFFFH; and the I/O address space
contains 64K consecutive byte addresses in the range 0000H through FFFFH as
shown in figure below.
The way in which the microprocessor deals with input/output devices is similar
to the way in which it deals with memory. The only difference is that just the 16
least significant lines of the bus, AD0 through AD15, are in use (because I/O
addresses are 16 bit long), and throughout the bus cycles, the M/IO control
signal is set to 0.

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Advantages of Isolated I/O

Complete memory address space available for use by memory.
I/O instructions maximizes the performance.
Disadvantage of Isolated I/O
All inputs/outputs must take place between an I/O port and accumulator
register.

Memory Mapped I/O

The address space dedicated to I/O devices is a part of the memory. Addresses
E0000H - E0FFFH → 4096 memory locations are assigned to I/O ports.
E0000H, E0001H, and E0002H correspond to byte-wide ports 0,1, and 2.
E0000H and E0001H correspond to word-wide port 0 at address E0000H.
Advantages of memory mapped I/O
I/O transfers can take place between I/O port and any of the registers.
Disadvantage of memory mapped I/O
Memory instructions perform slower.
Part of the memory address space cannot be used to implement memory.

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Minimum -Mode Interface

Maximum-Mode Interfaces

Input /Output Bus Cycles

 All the timing signals in the I/O read and write bus cycles are identical to
those already described in the memory read/write bus cycle except the
M/IO.
 Input/output data transfers in the 8086 microcomputers can be either
byte-wide or word-wide.
 Data transfers to byte-wide I/O ports always require one bus cycle.
 Word data transfers between the 8086 and I/O devices are accompanied
by the code A0=0 and BHE= 0 and are performed over the complete data
bus D0 through D15.

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Input Bus cycle

Output Bus cycle

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Memory Unit:
It is a collection of storage cells together with associated circuits needed to
transfer information in and out of storage device. The memory stores binary
information in groups of bits called bytes or words. The memory unit is mainly
divided into two main parts:
1. Main Memory (Primary Memory)
2. Secondary storage devices (Magnetic Memory)

Main Memory (Primary Memory)

Main memory (Semiconductor Memory) is faster, compact and lighter. It
consumes less power supply. It is static device i.e. there is no rotating part in it.
Semiconductor memory is employed as the Main Memory or Primary Memory
of the computer. It stores the program, which are currently needed by the CPU.
The main memory is divided into:
1. RAM (Random Access Memory)
2. ROM (Read Only Memory)

RAM (Random Access Memory)

RAM stands for Random Access Memory. It is called volatile memory because
it does not retain the data stored in it when the system's power is turned off.
RAM provides space for your computer to read and write data to be accessed by
the CPU (central processing unit). RAM can be both read and written, hold the
programs, operating system, and data required by the system.
There are two main types of RAM:
DRAM (Dynamic RAM) - each one-bit memory cell uses a capacitor for
data storage and a transistor to access the cell. typically has access times
of 50 to 70 nanoseconds(ns). DRAM is slower and less expensive than
SRAM.

Bit Select

Data In Data Out

DRAM Cell

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SRAM (Static RAM) - one-bit memory cells use bistable latches (flip-
flop) for data storage. It is faster with a typical assess time of 10
nanoseconds. It is more expensive and can only store a quarter of the data
that DRAM is able to in the same given area, however data will remain
stored as long as power is on. Fast SRAM can be found in most CPU's
called cache memory.

Bit Select

Data In D Q Data Out

Write En
RAM Cell

ROM (Read Only Memory)

ROM stands for Read-Only Memory. It refers to computer memory chips
containing permanent or semi-permanent data. Unlike RAM, ROM is non-
volatile; even after you turn off your computer, the contents of ROM will
remain. The types of ROM are:
Programmable read only memory (PROM) - are programmed during
manufacturing process. The contents of each memory cell is locked by a
fuse (diodes). PROMs are used for permanent data storage.
Erasable Programmable read only memory (EPROM) - there is a
possibility to erase EPROM with ultra-violet light (about 20 minutes)
what sets all bits in memory cells to 1. Programming requires higher
voltage. Memory cells are built with floating gate transistors. Data can be
stored in EPROMs for about 10 years.

Electrically erasable read only memory (EEPROM) - erasing does not

require ultra-violet light but higher voltage and can be applied not to the
whole circuit but to each memory cell separately.

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Magnetic Memory
The magnetic memory is cheaper than static memory. It is in the form of
magnetic disks {hard disk (HD) , compact disk (CD) and floppy disk} . It is
used as secondary memory or Auxiliary memory. The size is in G-Bytes but the
speed is very low compared with main memory.

Memory Unit

Main Secondary
Memory Memory

RAM ROM HD CD

SRAM DRAM PROM EPROM FD

EEPROM

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Memory and Memory Address Decoding

A memory device can be viewed as a single column table as shown
below. Table index (row number) refers to the address of the memory. Table
entries refer to the memory contents or data. Each table entry is referred as a
memory location. Both the memory address and the memory contents are
binary numbers, expressed in most cases in Hex format. The size of a memory
device is specified as the number of memory locations.
For example a 1Kbyte x 8 memory device has 1024 memory locations, with a
width of 8 bits.

A memory device must have three types of lines or connections: Address, Data,
and Enable & Control.

 Address Lines: The input lines that select a memory location within the
memory device. Decoders are used, inside the memory chip, to select a
specific location. The number of address pins on a memory chip specifies
the number of memory locations.
If a memory chip has 13 address pins (A0 - A12), then then the size is 213 =
23 x 210 = 8 Kbyte.
If a memory chip has 4Kbytes, then it has N pins:
2N = 4 Kbyte = 212 → N = 12 address pins (A0 - A11)
 Data Connections: All memory devices have a set of data output pins
(for ROM devices), or input/output pins (for RAM devices).

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 Enable and Control Connections: All memory devices have at least one
Chip Select CS or Chip Enable (CE) input, used to select or enable the
memory device. If a device is not selected or enabled then no data can be
read from, or written into it.
The CS or CE input is usually controlled by the microprocessor through
the higher address lines via an address decoding circuit. RAM chips
have two control input signals that specify the type of memory operation:
the Read (RD) and the Write (WR) signals. ROM chips can perform
only memory read operations, thus there is only read (RD) signal. In most
real ROM devices the Read signal is called the Output Enable (OE)
signal.

RAM ROM

Address Decoding
The physical address space, or memory map, of a microprocessor refers to
the range of addresses of memory locations that can be accessed by the
microprocessor. The size of the address space depends on the number of address
lines of the microprocessor.

At least two memory devices are required in a microprocessor system:

one for the ROM and one for the RAM. In an 8088/8086 the high addresses in
the memory map should always be occupied by a ROM, while the low addresses
in the memory map should always be occupied by a RAM.

Address decoding is required in order to enable the connection of more

than one memory devices on the microprocessor. More than one memory
devices can be used to expand (increase) the number of memory locations on the
system. The following steps have to be followed to design a memory map:

1. Determine the number of memory chips required, by dividing the required

memory size with the size of the memory devices to be used.

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2. Connect the data lines of each memory chip in parallel on the data lines of
the processor.
3. Connect the address lines of each memory chip in parallel with the low
address lines of the processor.
4. Connect the CS lines of each memory device with the high address lines
of the processor through an address decoding circuit..
5. Connect together all WR and RD lines of each memory device.

The following example is assumed that the processor has only 7 address lines
(A0 – A6) , thus it can address 27=128 memory locations . The data lines are 4
(D0 – D3) The size of the RAM used in the system is 32 locations (4 chips of 8
locations), then 3 address lines (A0 – A2) are used to address the 8 locations of
each RAM chip. There are 4 address lines (A3 – A6) used as chip select.
The memory block occupied by the memory module depends on the connection
of the address selection circuit (AND gate) that enables the decoder.
Two address lines are used to control the address selection circuit, thus the
circuit can be configured to occupy four different areas in the address space.

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Address Decoding Circuits Using Only NAND Gates

 A single NAND gate is used to decode each memory device. The inputs of
the NAND gate can be connected on the address lines either directly, or
through inverters, according to the required memory map.
 This method has the advantage that it adds a short time delay in the memory
path.
 The disadvantage of this circuit is that too many gates (NAND and NOT) are
needed for memory systems that have a few memory chips. This increases
the cost of the system, adds to the complexity of the PCB board (too many
chips and lines).
The figure below shows a memory map of two memory chips. Lines A0 – A14
are connected to each chip and lines A15 – A19 are connected to NAND gates to
generate the CS signal.

Address Decoding Circuits Using decoders and a NAND Gate

 One or more line decoders such as the 74LS139 (2 x 4 decoder) or the
74LS138 (3 x 8 decoder) are used to decode(enable) one out of a number
of memory device. The CS inputs of the decoders are enabled by a NAND
gate, according to the required memory map.
 This decoding circuit has the disadvantage that it adds at least three gate
delays in the memory path.
 The advantage of this circuit is that less gates (NAND, NOT and
decoders) are needed for memory systems that have a number memory
chips.
The figure below shows a memory map of 8 memory chips. The decoding
circuit has one decoder, one inverter and one NAND gate.

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Example: Show how a 128 Kbyte RAM module can be connected on an

8088µP using SRAM chips 32K x 8, occupying the address range starting from
the address C0000H. Use the following address decoding circuits:
1. NAND gates 2. Line decoders
Solution:
Number of chips needed: 128K / 32K = 4 chips
Number of address lines: 32K = 25 * 210 = 215 → 15 address lines (A0 - A14)
Lines A15 – A19 are used to generate the CS signals
The final address = the starting address + memory size - 1
RAM1 : final address=C0000H + 8000H - 1H=C7FFFH
RAM2 : final address=C8000H + 8000H - 1H=CFFFFH
RAM3 : final address=D0000H + 8000H - 1H=D7FFFH
RAM4 : final address=D8000H + 8000H - 1H=DFFFFH

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1. Using NAND gates

In this case the lines A15 – A19 are connected to four NAND gates with ̅
control signal sent by the 8088µP to generate the CS signal as shown below.
RAM4 RAM3 RAM2 RAM1

2. Using a line decoder and a NAND GATE

In this case, the lines A15 and A16 are input to the decoder to select one of
the four chips, while the lines A17 – A19 and ̅ signal are connected to
a NAND gate to enable the decoder.
RAM4 RAM3 RAM2 RAM1

H.W.
Show how a 32Kbyte ROM module can be connected on an 8088 system using
2764 EPROM chips (8K x 8), occupying the address range starting from the
address E0000H. Use the following address decoding circuits:
1. NAND gates
2. A line decoder and a NAND gate

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Example:
Design an 8K x 8 RAM module using 2K x 8 RAM chips. The module should
be connected on an 8-bit processor with a 16-bit address bus, and occupy the
address range starting from the address A000. Show the circuit and the memory
map.
Solution:
Number of memory devices needed = 8K / 2K = 4
Decoder needed = 2 x 4
Number of address lines on each 2K x 8 memory chip = 11
2m = 2K = 21 x 210 = 211 → (A0 - A10)

Two address lines are needed for the decoder → (A11 , A12)
Number of address lines needed for the address selection circuit
= 16 - 11 - 2 = 3 → (A13, A14 , A15)

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16-bit Microprocessors Memory Interfacing (8086µP)

To design memory interface circuit with the 8086µP, bank selection is

accomplished in two ways:
1. Separate decoders are used for each bank of the memory.
2. Separate write signal is generated to select a write signal to each bank of
the memory.

1. 16-bit Memory Interfacing Using Separate Bank Decoders

The figure below shows a memory map with 16-bit microprocessor
(8086µP). Four memory chips of 32k x 8 are used, two of them represent the
low bank and the other represent the high bank.
The first decoder (left side) is enabled when A0 is zero, thus it is enable with
even addresses. Thus the data lines of the memory devices decoded by this
decoder must be connected on the processor’s data lines D0 - D7.
The second decoder (right side) is enabled when ̅̅̅̅̅̅̅ is zero, thus it is enable
with odd addresses. Thus the data lines of the memory devices decoded by this
decoder must be connected on the processor’s data lines D8 - D15.

2. 16-bit Memory Interfacing Using Separate Write Signals

In this method the decoder always enables both banks. On a memory read
operation, the data from both banks is loaded on the data bus. The
microprocessor selects internally the appropriate bank, according to the
instruction being executed. On a memory write operation, only the ̅̅̅̅̅ signal of

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the appropriate bank is enabled, thus data is copied only in the appropriate
memory chip.
By providing separate write signals, we require
one decoder to select a 16-bit wide memory.
The signal ̅̅̅̅̅̅̅̅ is activated only when ̅̅̅̅̅̅̅
and ̅̅̅̅̅ both are activated, thus it is used with
memory chips from odd memory bank. The
signal ̅̅̅̅̅̅̅ is activated only when A0 and ̅̅̅̅̅ both are activated, thus it is
used with memory chip from even memory bank.
Note: It is not necessary to generate separate read signals for two memory
banks. Read memory signal always put 16-bit data on the data bus, but the CPU
reads data according to 8-bit read operation or 16-bit read operation.

Example: Design an 8086µP based system 128Kbyte memory (64 Kbyte

EPROM and 64 Kbyte RAM. Draw the complete schematic of the design
indicating the address map. Assume the starting Address of the EPROM is
30000H and for the RAM is 00000H.
Solution:
The design can be achieved by using two 32Kbyte EPROMs (one for odd bank
and another for the even bank ) and two 32Kbyte RAMs (one for odd bank and
another for the even bank).
Each RAM and EPROM chip needs 15 address lines A1 – A15 because
32Kbyte=25 * 210 = 215
A0 and ̅̅̅̅̅̅ are used to select even and odd memory banks respectively.
The memory map is as shown in the table below :

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̅̅̅̅̅̅̅ A19A18A17A16 A15A14A13A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A 1 A0 Address Memory

1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30000H Even(Low)
1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 3FFFEH EPROM1
0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 30001H Odd(High)
0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFFH EPROM2
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000H Even(Low)
1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0FFFEH RAM1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 00001H Odd(High)
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0FFFFH RAM2

The schematic diagram is as shown below.

RAM1 EPROM1 RAM2 EPROM2

Example: Design an 8086µP based system 128Kbyte memory (64 Kbyte

EPROM and 64 Kbyte RAM). Draw the complete schematic of the design
indicating the address map. Assume the starting Address of the EPROM is
F0000H and for the RAM is C0000H.
Solution:
Each RAM and EPROM chip needs 15 address lines A1 – A15 because
32Kbyte=25 * 210 = 215
A0 and ̅̅̅̅̅̅ are used to select even and odd memory banks respectively.
The memory map is as shown in the table below :

̅̅̅̅̅̅̅ A19A18A17A16 A15A14A13A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A 1 A0 Address Memory

1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 F0000H Even
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 FFFFEH EPROM1
0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 F0001H Odd
0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFFH EPROM2
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C0000H Even
1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 CFFFEH RAM1
0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 C0001H Odd
0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CFFFFH RAM2

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𝑊𝑅 D7 – D0 A14 – A0
RAM2
̅̅̅
CS
E ̅̅̅̅̅
̅̅̅̅ 𝑊𝑅 D7 – D0 A14 – A0
RAM1
̅̅̅
CS
E ̅̅̅̅̅
D7 – D0 A14 – A0 ̅̅̅̅
EPROM2
̅̅̅
CS
̅̅̅̅
E
D7 – D0 A14 – A0
EPROM1
̅̅̅
CS
̅̅̅̅
E

Y0 Y1 Y2 Y3
Decoder
A B E
A19 – A0
D15 – D0

̅̅̅̅
𝐑𝐃

̅̅̅̅̅̅̅
𝑩𝑯𝑬
̅̅̅̅̅
𝐖𝐑
8086µP

𝐈𝐎
𝐌 ̅̅̅

H.W: Design an 8086µP based system 256Kbyte memory (128 Kbyte EPROM
and 128 Kbyte RAM), the size of the RAM and EPROM chips is 32 Kbyte.
Draw the complete schematic of the design indicating the address map. Assume
the starting Address of the EPROM is F0000H and for the RAM is 30000H.

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