RTL Coding Guidelines

Trio Adiono

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 Objective
• Readable
• Modifiable
• Reusable
• Simple & regular structure
– Easy to design, code, verify, synthesize
• Meet performance and functional goal

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 Coding Guidelines
• Use simple constructs, basic types (for VHDL), and
simple clocking schemes.
• Use a consistent coding style, consistent naming
conventions, and a consistent structure for processes
and states machines.
• Use a regular partitioning scheme, with all module
outputs registered and with modules roughly of the
same size.
• Make RTL code easy to understand, by using
comments, meaningful names and consistent or
parameters instead of hard-coded numbers

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 General Naming Conventions
• Rule: Develop Naming Convention
– Consistent
– Documentation
• Guideline
– Lower case : signal, variable and port
– Uppercase : constant, user define type
• type BUS_BYTE is std_logic_vector( 7 downto 0)
• sig_A : BUS_BYTE;
– Short but descriptive names
– Clock : clk or clk1, clk_interface
– The same clock name for the same clk source
– Active low signal : _b or _n
– Reset : rst or rst_n
– Consistent Multibit description : (y downto x) and (x to y)
– Recommended : (y downto x) or (x:0)
– Use the same name or similar name for port and signals:
• (a=>a; a=>a_int)
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 Signal Naming Conventions
*_r Output of registers

*_a Async signal

*_pn Signal in n-th phase

*_nxt Data before being registered into a register

with the same name
*_z Tristate internal signal

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 Naming Convention for VITAL
Support
• VITAL : gate level model standard for VHDL (IEEE
1076.4)
– VITAL_Level0: interface spec (ports & generic spec in entity)
– VITAL_Level1: (Functional & Timing)
• Rule:
– Hard Macro & top level port : do not use (_) in entity port
(separator to construct name in SDF)
– Not in mode LINKAGE
– Type mark declared in std_logic_1164
– Cannot be a guarded port

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Architecture Naming Convention
Synthesis ARCITECTURE rtl OF my_syn_model IS
Model or
ARCITECTURE str OF my_structural_design IS
Simulation ARCITECTURE sim OF my_behave_model IS
Model or
ARCITECTURE tb OF my_test_bench IS

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 Include Header in Source Files
• Rule
– Filename, Author
– Function and key features
– Date created
– Modification History : date, name, desc of changes

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Example: Header in HDL source file

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 Use Comments
• Rule Contoh:
-- VHDL Code --
– Explain all process,
signal mySignal :std_logic;
function, declaration of
-- an example signal
types and subtypes
MYsignal <=
• Guidelines: ‘0',
-- start with '0'
'1' AFTER 10 ns,
– Use comments to -- and toggle after
'0' after 10 ns,
explains ports, signals, -- every 10 ns
'1' afTer 10 ns;
and variables, or groups
of signals

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 Keep Commands on Separate Lines
• Rule
– Use separate line for each VHDL statement
(readable and maintainable)

Line Length
• Guideline
– Keep line length to 72 char or less

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 Indention
• Rule
– Use indention to improve the readability of continued code
lines and nested loops
• if
• if
• end if;
• end if;
• Guidelines
– Use 2 space
• Guidelines
– Avoid using tabs

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 Do not Use HDL Reserved Words
• Rule
– Do not use nether VHDL or Verilog reserved word.
Because they are going to be translated

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 Port Ordering
• Rule:
– Declare ports in a logical order, and keep consistent
• Guideline
– Declare one port per line, with a comment following it
– Inputs:
• Clocks
• Resets
• Enables
• Other Control Signals
• Data and address lines
– Outputs:
• Clocks
• Resets
• Enables
• Other Control Signals
• Data

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 Port Maps and Generic Maps
• Rule:
– Use explicit mapping, using named association rather
than positional association
• Guideline
– Leave blank line between the input and output ports
to improve readibility

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 5.4 Guideline for Clocks & Reset
• Preferred : single global clock and positive edge-
triggered

D D Q D Q Q

Clock

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 5.4.1 Avoid Mixed Clock Edges
• Guideline: Avoid using both positive and negative-edge
triggered flip-flops
– Cautions in mixed clock edge:
• The duty cycle becomes a critical
• Scan-based testing methodologies require separate handling
• Separate them into different module. Put them in
different scan chains
• Rule:
– Be sure to model the worst case duty cycle (synth & timing
analysis)
– Document the assumed duty cycle

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 Avoid Mixed Clock Edge

D D Q D Q Q

Clock

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 5.4.2 Avoid Clock Buffers
• G: Avoid hand instantiating clock buffers in
RTL code.
– Part of physical design

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 Avoid Gated Clocks
• G: avoid coding gated clock.
– Technology specific and Timing dependent.
– Can generate a false clock & glitch
– Can generate hold time violations due to different clock
skew.
– Limited testability : cannot be part of scan chain
– Used for low-powered design
– Should not be coded in the RTL
– Should be inserted by a tool
•
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 5.4.4 Avoid Internally Generated Clocks

• G: Avoid using internally generated clocks

– Cause limited testability : cannot be part of scan
chain
– Difficult to put constrain for synthesis

• Alternative:
– Design synchronous design
– Use multiple clocks

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5.4.5 Gated Clock and Low Power Design

• Guideline:
– Keep the clock and/or reset generation circuitry as a separate
module at top level of the design.
– Partition the design so that all the logic in a single module use
a single clock and single reset.
– Gated clock should never occur within a macro.
– Gated clock should appear at top level of the design
hierarchy.
– Standard timing analysis and scan chain can be applied to
each module.
– See Example 5-17

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 5.4.6 Avoid Internally Generated Reset

• Make sure registers are controlled only by a simple reset

signal
• G: Avoid internally generated, conditional resets : make
analysis and design much simpler and easier
• G: if conditional reset required, create separate signal,
and isolate in saparate module (increase readable and
syntheisis result)
• See Example 5-18

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 5.5 Coding for Synthesis
• Best compile and synthesis result
• Testability
• Performance
• Simplification of static timing analysis
• Gate-level circuit behaviour that maches that of
the original RTL code

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 5.5.1 Infer Design
• G: Registers (flip-flop) are the preferred
mechanism for sequential logic.
– See template Example 5-19, 5-20
– Use the design’s reset signal to initialize registered
signals
– Do not initialize signal in the declaration: mismatch
between pre and post synthesis result.
–

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 5.5.2 Avoid Latches
• Exception: instantiate technology-independent GTECH.D.
Provide list of documentation and its special timing requirements
• Note: check latches = all_registers –level_sensitive
• VHDL code infers latches: example 5-21, 5-22
• G: avoid latch
– Assign default values at the beginning of a process (Example 5-24)
– Assign outputs for all input conditions (Example 5-25)
– Use else (instead of elsif) for the final priority branch (example 5-26)

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 5.5.3 If latch must be used
• Testability: Use a mux to provide either the
normal function or the input from an I/O pad
as data to mux
– See Figure 5-7

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 Avoid Combinational Feedback

D Q Q
A

C B

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 5.5.5 Specify Complete Sensitivity Lists

• Pre and post layout may differ

– See Figure 5-9
• Combinational block
– Must include all signals read by process
– Example 5-27
• Sequential block
– Include clock and reset signal
– Example 5-28
• Must not include unnecessary sensitivity list. It may
slow down simulation

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 2.2.10 Process
Contoh:

entity AND_OR_XOR is
port (A,B : in bit;
Z_OR, Z_AND, Z_XOR :
out bit);
end AND_OR_XOR;
architecture RTL of
AND_OR_XOR is

begin
A_O_X: process (A, B)
begin
Z_OR <= A or B;
Z_AND <= A and B;
Z_XOR <= A xor B;
end process A_O_X ;
end RTL;

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 Sequential Logic: D-Flip Flop

architecture
architecture rtl rtl of
of D_FF
D_FF is
is
begin
begin Flip-flop
process
process (Clock,
(Clock, Reset)
Reset) isis
begin
begin
if D D Q Q
if Reset
Reset == ‘‘11’’ then
then
QQ <= ‘ 0 ’
<= ‘0’;;
elsif
elsif ((Clock’
Clock’’event
Clock
Clock’ event and
and Clock=‘
Clock=‘‘11’’)) then
Clock=
Clock=‘ then
QQ <= D;
<= D; Clock
R
end if;
end if;
end
end process;
process;
end
end architecture rtl;
architecture rtl;;
rtl
rtl;
Reset
--
-- rising
rising edge
edge ff
ff
-- async reset
-- async reset

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 Blocking and Non-blocking
Assignments (Verilog)
• Blocking: execute in sequential order
• Non-Blocking : execute concurrently
• Use blocking statement inside always
@(posedge clk)
• Example 5-29, 5-30
•

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 Signal vs Variable
• Signal: scheduled to be executed in next
simulation clock cycle
• Variable: take effect immediately
• Guideline : use signal instead of variable
• See Example 5-31

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 Sequential Logic: D-Flip Flop
architecture
architecture rtl
rtl of
of D_FF
D_FF is
is
begin
begin
process
process (Clock)
(Clock) isis
begin
begin
if
if (Clock’event
(Clock’event and
and Clock=‘1’)
Clock=‘1’) then
then
if Reset = ‘1’ then
if Reset = ‘1’ then
Flip-flop Flip-flop Flip-flop

S1
S1 <=
<= ‘0’;
‘0’; S0 D QD Q D Q D Q D Q S3
S2
S2 <=
<= ‘0’;
‘0’;
S3 <= ‘0’;
S3 <= ‘0’; Clock Clock Clock
else
else R R R
S1
S1 <=
<= S0;
S0; Reset Reset Reset
S2 <= S1;
S2 <= S1;
S3
S3 <=
<= S2;
S2;
end if;
end if;
end
end if;
if;
end process;
end process;
end
end architecture
architecture rtl;
rtl;
--
-- rising
rising edge
edge ff
ff
-- sync reset
-- sync reset

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 Case vs. if then else
• Case : single level multiplexer
• If-then-else: priority encoded, cascaded
combination of mux
• See Figure 5-12, 5-13
• Guideline: multiplexer is faster circuit. Use case
statement rather than an if-then-else
• Conditional assignment also infer a mux
• See example 5-34
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 Coding State Machines
• Separate the state machine HDL desc into two
process, combination and sequential logic
• Create enumerated type for the state vector
• Keep FSM logic and non-FSM logic in separate
modules
• Assign a default state for the state machine.
Implement idle state. Assign a state for other
condition (Example 5-35, 5-36).

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 5.6 Partition for Synthesis
• Advantages:
– Better synthesis result
– Faster compile runtime
– Ability to use simpler synth strategy to meet timing

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 Register All Outputs
• Simplify the synthesis process
• Makes output drive strengths (flip-flop) and
input delay predictable
• All input of each block arrive the same relative
delay
• Figure 5-14 example of registered output

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