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Sec III, L 5-7: Wafer Preparation: MEL G611: Ic Fabrication Technology

This document discusses a course on IC fabrication technology. It covers topics like wafer preparation, oxidation, and modeling oxidation. Specifically: - Section IV of the course will cover oxidation processes on August 18, 23, and 25th. Topics will include oxidation growth mechanisms, techniques, properties, and defects. - Oxidation is important for protecting wafers and forming insulating oxides. It involves breaking silicon bonds and incorporating oxygen. Thermal oxidation is used to form oxides. - The Deal-Grove model from 1965 mathematically describes thermal oxidation kinetics and is used to predict and interpret oxidation of silicon. It is valid for temperatures of 700-1300C and oxygen partial pressures of 0.2

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Udai Valluru
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Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
86 views33 pages

Sec III, L 5-7: Wafer Preparation: MEL G611: Ic Fabrication Technology

This document discusses a course on IC fabrication technology. It covers topics like wafer preparation, oxidation, and modeling oxidation. Specifically: - Section IV of the course will cover oxidation processes on August 18, 23, and 25th. Topics will include oxidation growth mechanisms, techniques, properties, and defects. - Oxidation is important for protecting wafers and forming insulating oxides. It involves breaking silicon bonds and incorporating oxygen. Thermal oxidation is used to form oxides. - The Deal-Grove model from 1965 mathematically describes thermal oxidation kinetics and is used to predict and interpret oxidation of silicon. It is valid for temperatures of 700-1300C and oxygen partial pressures of 0.2

Uploaded by

Udai Valluru
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 33

29-08-2018

MEL G611 :
IC FABRICATION TECHNOLOGY
Section IV: Oxidation
Sat, 18 Aug; Thu, 23 Aug, Sat, 25 Aug;
BITS Pilani Tues, 28 Aug
Hyderabad Campus
Sanket Goel, EEE

Sec III, L 5-7: Wafer Preparation

• Sat, 11 Aug; Tues, 14 Aug & Thu, 16 Aug

• Learning Objectives
o To learn the art of wafer preparation and some of the
basic properties of these wafers

• Topics covered –
o Single crystal growth
o Wafer preparation
o Measurements

MEL G611 : IC FABRICATION TECHNOLOGY 2 BITS Pilani, Hyderabad Campus

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29-08-2018

Sec IV, L 8-10: Oxidation


• Sat, 18 Aug; Thu, 23 Aug; Sat, 25 Aug

• Learning Objectives
o To understand the Oxidation process during the IC
Fabrication

• Topics to be covered –
o Oxidation growth mechanisms
o Various techniques
o Properties
o Defects

MEL G611 : IC FABRICATION TECHNOLOGY 3 BITS Pilani, Hyderabad Campus

Basic VLSI Fabrication Steps

MEL G611 : IC FABRICATION TECHNOLOGY 4 BITS Pilani, Hyderabad Campus

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Oxidation: Outline

• Introduction
• Basic Concepts
• Thermal Oxidation Kinetics
• Solution of Deal-Grove Model
• Dopant Redistribution
• Oxide Quality Improvement

MEL G611 : IC FABRICATION TECHNOLOGY 5 BITS Pilani, Hyderabad Campus

BITS Pilani
Hyderabad Campus

Oxidation: Fundamentals

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Why SiO2?
• The interface between Si and SiO2 has very few mechanical
and electrical defects and it’s stable over time
• It is easily grown thermally on silicon or deposited on many
substrates.
• It acts as a resistant to most of the chemicals used in silicon
processing.
• Easily pattern and etched (both dry and wet)
• Very good etching selectivity between Si and SiO2 Act
as an excellent insulator
• SiO2 is a good diffusion mask for common dopants

MEL G611 : IC FABRICATION TECHNOLOGY 7 BITS Pilani, Hyderabad Campus

Wafer Oxidization : Role


• Protects wafer surface from scratches
• Prevents dust from interacting / Minimizes contamination
• Protects wafer from chemical impurities, electrically active
• Acts as a hard mask for doping and as an etch stop during
patterning
• Original gate oxide in MOSFET was made of SiO2
• Used as inter-layer dielectric separating different metallization
layers
• Used to prevent induced charge due to the metal layers
• Oxygen forms covalent bond with two silicon atoms, i.e., Si-O-
Si structure  oxygen atoms are neutral in this configuration
o yield strength improved by 25%

MEL G611 : IC FABRICATION TECHNOLOGY 8 BITS Pilani, Hyderabad Campus

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SiO2 Properties
• Conceptually, a silicon bond is broken and oxygen atoms are
incorporated into the silicon and finally Si-O bonds formed!
o Thermal SiO2  Amorphous
o Energy gap ∼ 9 eV
o Breakdown electric field > 10 MV/cm

MEL G611 : IC FABRICATION TECHNOLOGY 9 BITS Pilani, Hyderabad Campus

SiO2 usage

MEL G611 : IC FABRICATION TECHNOLOGY 10 BITS Pilani, Hyderabad Campus

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SiO2 – thickness requirement

SiO2
SiO2

Si
S Si
S
<Si> i i

MEL G611 : IC FABRICATION TECHNOLOGY 11 BITS Pilani, Hyderabad Campus

Wafer Oxidization: Type


• Dry oxidation (denser oxides: gate oxide)
o Si + O2 →SiO2
• Wet Oxidation (lower density: Thick masking, Field oxides)
o Si + 2H2O→ SiO2 + 2H2
• Done at high temperature (>900oC) in oxidizing gas
• Thickness control and density determine process
• Underlying Si is consumed, the Si/SiO2 interface moves
deeper into the wafer.

MEL G611 : IC FABRICATION TECHNOLOGY 12 BITS Pilani, Hyderabad Campus

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Wafer Oxidization: Impact (1/3)


• Si = 2.33 gcm-3, ZSi = 28.08 g/mol
• SiO2 = 2.35 gcm-3, ZSiO2 = 60.08 g/mol
• Volume expansion as Si  SiO2
• Final thickness is higher than the initial Si thickness

• d  thickness of the original Si layer that has been consumed


in forming the oxide layer of thickness d’.
• A  area of cross-section
• Law of molar conservancy
• d’ ~ 2.17 d
• d’ > dSi  For d’ = 100 nm of oxide, 46 nm of Si needs to be
consumed

MEL G611 : IC FABRICATION TECHNOLOGY 13 BITS Pilani, Hyderabad Campus

Wafer Oxidization: Impact (2/3)

MEL G611 : IC FABRICATION TECHNOLOGY 14 BITS Pilani, Hyderabad Campus

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Wafer Oxidization: Impact (3/3)


Volume change

MEL G611 : IC FABRICATION TECHNOLOGY 15 BITS Pilani, Hyderabad Campus

Oxidization: Equipment (1/3)

MEL G611 : IC FABRICATION TECHNOLOGY 16 BITS Pilani, Hyderabad Campus

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Oxidization: Equipment (2/3)

Dummy wafers
at the ends

MEL G611 : IC FABRICATION TECHNOLOGY 17 BITS Pilani, Hyderabad Campus

Oxidization: Equipment (3/3)

Oxidation
O2 + HCl

Ramp up Ramp down


N2 + 5% O2 N2
Push
N2 + 5% O2 Pull N2

MEL G611 : IC FABRICATION TECHNOLOGY 18 BITS Pilani, Hyderabad Campus

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Oxidization: Defects

MEL G611 : IC FABRICATION TECHNOLOGY 19 BITS Pilani, Hyderabad Campus

Oxidization: Defects
• Fixed oxide charge Qf
o Due to incompletely oxidized silicon atoms that had net
positive charge

• Interface trapped charge Qit


o Due to incompletely oxidizing silicon atom with an
unsatisfied or dangling bond located in the oxide but very
closed to the interface

• Mobile oxide charge Qm


o Due to Na and K ions

• Oxide trapped charge Qot


o Due to broken Si-O bonds during ion-implantation,
plasma etching, etc.
MEL G611 : IC FABRICATION TECHNOLOGY 20 BITS Pilani, Hyderabad Campus

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Quality Control

MEL G611 : IC FABRICATION TECHNOLOGY 21 BITS Pilani, Hyderabad Campus

BITS Pilani
Hyderabad Campus

Oxidation Modeling

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Deal-Grove Model
• Mathematically describes the growth of an oxide layer
• To predict and interpret thermal oxidation of silicon
• First published in 1965 by Bruce Deal and Andrew Grove, of
Fairchild Semiconductor
• Temp: 700 – 1300, partial pressure: 0.2 – 1 atm
• Thickness: 30 – 2000 nm

Deal, B. E.; A. S. Grove (1965). "General Relationship for the Thermal Oxidation of Silicon". Journal of Applied Physics. 36 (12): 3770–3778.

MEL G611 : IC FABRICATION TECHNOLOGY 23 BITS Pilani, Hyderabad Campus

Deal-Grove Model: Assumptions


• Oxidation reaction occurs at interface between oxide layer and
the substrate material, not between oxide and ambient gas.
• 3 phenomena that oxidizing species undergoes:
o Diffuses from the bulk of the ambient gas to the surface
 Henry’s Law
o Diffuses through the existing oxide layer to the oxide-
substrate interface
 Fick’s Law of Diffusion
o Reacts with the substrate  1st order reaction wrt oxidant
• Each of these stages proceeds at a rate proportional to the
oxidant's concentration.
• Steady state conditions  No transient effects

Deal, B. E.; A. S. Grove (1965). "General Relationship for the Thermal Oxidation of Silicon". Journal of Applied Physics. 36 (12): 3770–3778.

MEL G611 : IC FABRICATION TECHNOLOGY 24 BITS Pilani, Hyderabad Campus

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Deal-Grove Model: Flux

• hG  gas phase
mass transfer
coefficient
• D diffusion
coefficient
• x0  oxide
thickness
• kS  rate constant
of chemical surface
reaction for Si
oxidization
𝐷(𝐶𝑜 − 𝐶𝑖)
F1 = hG (CG – CS) 𝐹2 = F3 = ks Ci
𝑥0

For steady state, F1 = F2 = F3

MEL G611 : IC FABRICATION TECHNOLOGY 25 BITS Pilani, Hyderabad Campus

Deal-Grove Model: Solution (1/4)


F1 = hG (CG – CS) • hG  gas phase mass transfer
𝑃𝐺 𝑃𝑆 coefficient
= hG −
𝑘𝑇 𝑘𝑇 • D diffusion coefficient
= h (HPG – HPs) • x0 (or do) oxide thickness
= h (C* - Co) • kS  rate constant of chemical
surface reaction for Si oxidization
𝐷(𝐶𝑜 − 𝐶𝑖) F3 = ks Ci
𝐹2 = • PS  partial pressure at oxide
𝑥0 surface
For steady state, F1 = F2 = F3 • PG  partial pressure of bulk of gas
• h gas phase mass transfer
coefficient in terms of concentration
ℎ𝐺
• ℎ= >>> 1
𝐻𝑘𝑇
• H  Henry law constant
• C* eqm bulk conc in oxide
• C0  eqm conc in oxide at surface

MEL G611 : IC FABRICATION TECHNOLOGY 26 BITS Pilani, Hyderabad Campus

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Deal-Grove Model: Solution (2/4)


Grove's Law d0  thickness of the oxide layer at
time t
di  initial oxide thickness (at t = 0)
D  diffusion coefficient
ks  rate constant
C  concentration
h  mass transfer coefficient
N1  # of oxidant molecules
incorporated per unit volume of oxide
grown (for SiO2, N1 = 2.2 X1022 cm-3 for
dry oxidation)
  shift in the time coordinate to
account of the presence of initial oxide
layer di

MEL G611 : IC FABRICATION TECHNOLOGY 27 BITS Pilani, Hyderabad Campus

Deal-Grove Model: Solution (3/4)


d0  thickness of the oxide
layer at time t
di  initial oxide thickness
(at t = 0)
D  diffusion coefficient
ks  rate constant
C  concentration
• For thick oxide layer, or at long oxidation
time i.e. t >>  or t >> A2/4B h  mass transfer
coefficient
N1  # of oxidant
molecules incorporated per
unit volume of oxide grown
(for SiO2, N1 = 2.2 X1022
• When D is large or when the oxide cm-3 for dry oxidation)
thickness is small (t + τ ) << A2/4B 
  shift in the time
coordinate to account of the
presence of initial oxide
layer di

MEL G611 : IC FABRICATION TECHNOLOGY 28 BITS Pilani, Hyderabad Campus

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Deal-Grove Model: Solution (4/4)


• For thick oxide layer, or at long oxidation time i.e. t >> τ or t >> A2/4B

• When D is large or when the oxide thickness is small (t + τ ) << A2/4B

Xox

 t

t
t

Oxide Growth Rate slows down


http://cleanroom.byu.edu/OxideThickCalc with increase of oxide thickness
MEL G611 : IC FABRICATION TECHNOLOGY 29 BITS Pilani, Hyderabad Campus

Rate Constants: Wet & Dry


Experimentally, B/A & B are well described by the Arrhenius
expressions (E  activation energy and C  constant

For (111) Silicon at 1 Atm. For (100) Silicon all C2 value should be
divided by 1.68

MEL G611 : IC FABRICATION TECHNOLOGY 30 BITS Pilani, Hyderabad Campus

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Deal-Grove Model: Rates

MEL G611 : IC FABRICATION TECHNOLOGY 31 BITS Pilani, Hyderabad Campus

Rate Constants: Wet & Dry


Wet oxidation

Dry oxidation

MEL G611 : IC FABRICATION TECHNOLOGY 32 BITS Pilani, Hyderabad Campus

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Problem
Show the results obtained for wet oxidation at 10000C using the
following two are same for short and long time (assume  = 0)

t >>  t << 

For 10000C, A = 0.226 µm and B/A = 1.27 µm/h


B = 0.287 µm2/h
t = 100 h t = 0.01 h
Eqn 1 Eqn 2 Eqn 1 Eqn 3
d0 (µm ) 5.24 5.35 0.0121 0.0127

MEL G611 : IC FABRICATION TECHNOLOGY 33 BITS Pilani, Hyderabad Campus

Problem
Show the following equation can be used graphically to obtain the rate
constant (assume  = 0)

𝐵𝑡
𝑑0 = −𝐴
𝑑𝑜

MEL G611 : IC FABRICATION TECHNOLOGY 34 BITS Pilani, Hyderabad Campus

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Oxidation Rate: Experimental

MEL G611 : IC FABRICATION TECHNOLOGY 35 BITS Pilani, Hyderabad Campus

Rate Constants: Wet & Dry

Dry Wet

MEL G611 : IC FABRICATION TECHNOLOGY 36 BITS Pilani, Hyderabad Campus

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Oxidization: Orientation Dependence

MEL G611 : IC FABRICATION TECHNOLOGY 37 BITS Pilani, Hyderabad Campus

Oxidization: Orientation Dependence

Oxidation on the
<111> crystal plane
has a higher rate
because there are a
higher number of
surface atoms, i.e.
reaction sites or
chemical bonds,
when compared to a
<100> plane.

MEL G611 : IC FABRICATION TECHNOLOGY 38 BITS Pilani, Hyderabad Campus

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Problem

MEL G611 : IC FABRICATION TECHNOLOGY 39 BITS Pilani, Hyderabad Campus

Problem
If y  additional thickness of Si
consumed during the oxide growth

MEL G611 : IC FABRICATION TECHNOLOGY 40 BITS Pilani, Hyderabad Campus

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BITS Pilani
Hyderabad Campus

Effect of Impurities, Pressure and


Plasma

Wet Oxidation: B-doped Si


• Wet oxidation rate is >> than that of dry oxidation.
• Any unintentional moisture in the furnace accelerates oxidation
• Doping impurities are
redistributed at growing Si-
SiO2 interface.
• If the dopant segregates into
the oxide
o Bond structure in silica
weakens
o Enhanced incorporation &
diffusivity of oxidizing
species through the oxide Oxidation of boron-doped
o Larger oxidation rate silicon in wet oxygen
• Oxidation process  diffusion control predominant
MEL G611 : IC FABRICATION TECHNOLOGY 42 BITS Pilani, Hyderabad Campus

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Wet Oxidation: P-doped Si


• Impurities that segregate into oxide but then diffuse rapidly
through it (Ga, In, Al), have no effect on oxidation kinetics.
• For oxidation of P-doped silicon, a concentration dependence is
observed only at lower temperature, where the surface reaction
becomes important.

• This dependence may


be the result of
phosphorus being
segregated into the
silicon

Oxidation of P-doped silicon in wet oxygen


MEL G611 : IC FABRICATION TECHNOLOGY 43 BITS Pilani, Hyderabad Campus

Oxidation: Diffusion Constant


• SiO2  a selective mask against the diffusion of dopant atoms
at elevated temperature
• Dopant diffusion rate in the oxide must be slow with respect to
that in silicon, so that the dopant does not diffuse through the
oxide in the masked region into the silicon.
• The masking oxide thickness must also be large enough to
prevent it from reaching the silicon substrate.
• n-type impurities and B have very small diffusion coefficients in
oxide

MEL G611 : IC FABRICATION TECHNOLOGY 44 BITS Pilani, Hyderabad Campus

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Wet Oxidation: External impurities


• Oxidation rates are also influenced by adventitious impurities.
• Sodium  High concentrations influence the oxidation rate
by changing the bond structure in the oxide, thereby
enhancing the diffusion and concentration of the oxidizing
species in the oxide.

• Certain halogen species  intentionally introduced into the


oxidation ambient to improve both the oxide and the
underlying silicon properties.

• Chlorine is instrumental in converting certain impurities in


the silicon to volatile chlorides, resulting in a reduction in
oxidation-induced stacking faults.

MEL G611 : IC FABRICATION TECHNOLOGY 45 BITS Pilani, Hyderabad Campus

Oxidation: Pressure Effect


• Oxidation in high pressure produces a substantial acceleration
in the growth rate

For pyrogenic steam for <100> silicon oxidized in dry


at 900oC O2 at 900oC

MEL G611 : IC FABRICATION TECHNOLOGY 46 BITS Pilani, Hyderabad Campus

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Oxidation: Plasma
• Has all the advantages associated with the high-pressure
technique
• Offers possibility of growing high-quality oxides at even lower
temperatures.
• Plasma oxidation is a low-pressure process usually carried out
in a pure oxygen discharge.
• Plasma is sustained either by a high-frequency or DC
discharge.
• Placing the wafer in the uniform density region of the plasma
and biasing it slightly negatively against the plasma potential
allows it to collect active charged oxygen species.
• The oxidation rate typically increases with higher substrate
temperature, plasma density, and substrate dopant
concentration
MEL G611 : IC FABRICATION TECHNOLOGY 47 BITS Pilani, Hyderabad Campus

Color chart: Gown SiO2


Thickness (A) COLOR Color and Comments
500 Tan
750 Brown
1000 Dark Violet to red violet
1250 Royal blue
1500 Light blue to metallic blue
1750 Metallic to very light yellow-green
2000 Light gold or yellow slightly metallic
2250 Gold with slight yellow-orange
2500 Orange to Melon
2750 Red-Violet
3000 Blue to violet-blue
3100 Blue
3250 Blue to blue-green
3450 Light green
3500 Green to yellow-green
3650 Yellow-green
3750 Green-yellow
3900 Yellow.
4120 Light orange
4260 Carnation pink
4650 Red-violet
4760 Violet
MEL G611 : IC FABRICATION TECHNOLOGY 48 BITS Pilani, Hyderabad Campus

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Color chart: Gown SiO2


Thickness (A) COLOR Color and Comments
4800 Blue Violet
4930 Blue
5020 Blue-green
5200 Green (Broad)
5400 Yellow-green
5600 Green-yellow
5740 Yellow to Yellowish (not yellow but is in the position where
yellow is to be expected. At times is appears to be light creamy
gray or metallic)
5850 Light orange or yellow to pink borderline
6000 Carnation pink
6300 Violet-red
6800 Bluish (Not blue but borderline between violet and blue-green.
It appears more like a Mixture between violet-red and blue-
green and over-all looks grayish)
7200 Blue-green to green (quite broad)
7700 Yellowish
8000 Orange (rather broad for orange)
8200 Salmon
8500 Dull, light red-violet
8600 Violet
8700 Blue-violet
8900 Blue
MEL G611 : IC FABRICATION TECHNOLOGY 49 BITS Pilani, Hyderabad Campus

Color chart: Gown SiO2


9200 Blue-green
9500 Dull yellow-green
9700 Yellow to Yellowish
9900 Orange
10000 Carnation Pink
10200 Violet-red
10500 Red-violet
10600 Violet
10700 Blue-violet
11000 Green
11100 Yellow-green
11200 Green
11800 Violet
11900 Red-violet
12100 Violet-red
12400 Carnation Pink-Salmon
12500 Orange
12800 Yellowish
13200 Sky blue to green-blue
14000 Orange
14500 Violet
14500 Blue-violet
15000 Blue
15100 Dull Yellow-green
MEL G611 : IC FABRICATION TECHNOLOGY 50 BITS Pilani, Hyderabad Campus

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Deal-Grove Model: Approximation

• Diffusion process is not rate limiting • Diffusion process is rate limiting


• Oxidant is being supplied to Si/SiO2 • Oxidant is being supplied to Si/SiO2
surface faster than required surface at required rate
• For thin oxide • For thick oxide

How about ksx0/D ~ 1?


MEL G611 : IC FABRICATION TECHNOLOGY 51 BITS Pilani, Hyderabad Campus

Problem
According to the Deal Grove model, oxidation kinetics start out linear and
become parabolic as the oxidation proceeds. Calculate the oxide thickness at
which this transition takes place and plot this versus oxidation temperature.

MEL G611 : IC FABRICATION TECHNOLOGY 52 BITS Pilani, Hyderabad Campus

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Problem (Solution)

(µm)

Deg C

MEL G611 : IC FABRICATION TECHNOLOGY 53 BITS Pilani, Hyderabad Campus

Problem
A MOS device requires a gate oxide of 10nm ± 0.5nm. Assume the growth is
done at 900°C in dry O2 . Neglect any effect of the anomalous initial growth.
Derive a simple expression which gives the sensitivity of the oxide thickness to
growth temperature (dx/dT). Evaluate this expression to see how well controlled
the furnace T must be in order to obtain 10nm ± 0.5nm at 900°C.
Transition thickness at 900°C for dry
oxygen is > 10nm, so we can use the
(µm)

linear growth rate approximation.

Deg C

MEL G611 : IC FABRICATION TECHNOLOGY 54 BITS Pilani, Hyderabad Campus

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Solution

Thus, the growth rate is approximately constant and we are justified in using the
linear approximation

MEL G611 : IC FABRICATION TECHNOLOGY 55 BITS Pilani, Hyderabad Campus

Problem
A silicon wafer is covered by an SiO2 film 0.3 μm thick.
a. What is the time required to increase the thickness by 0.5 μm by oxidation
in H2O at 1200°C?
b. Repeat for oxidation in dry O2 at 1200°C.

MEL G611 : IC FABRICATION TECHNOLOGY 56 BITS Pilani, Hyderabad Campus

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Solution

MEL G611 : IC FABRICATION TECHNOLOGY 57 BITS Pilani, Hyderabad Campus

Problem
Suppose an oxidation process is used in which (100) wafers are oxidized in O2
for three hrs. at 1100°C, followed by two hrs. in H2O at 900°C, followed by two
hrs in O2 at 1200°C. Use Figs. in the text to estimate the resulting final oxide
thickness. Explain how you use these figures to calculate the results of a multi-
step oxidation like this.

(100) Si in Dry O2 (100) Si in H2O

MEL G611 : IC FABRICATION TECHNOLOGY 58 BITS Pilani, Hyderabad Campus

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Solution
• A  900°C ,
0.21 μm
• Move along the
900°C curve by
2 hours
• B  900°C, 0.4
μm

3 hours oxidation at 1100°C  0.21 μm

• A  1200°C, 0.4 μm
• Increment the time by 2 hrs
along the 1200°C curve
• B  1200°C, 0.5 μm.

MEL G611 : IC FABRICATION TECHNOLOGY 59 BITS Pilani, Hyderabad Campus

Problem
What is the approximate oxide thickness after a 100 minute dry O2 oxidation followed by
a 35 minute H2O oxidation at 900°C?

MEL G611 : IC FABRICATION TECHNOLOGY 60 BITS Pilani, Hyderabad Campus

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Solution
What is the approximate oxide thickness after a 100 minute dry O2 oxidation followed by
a 35 minute H2O oxidation at 900°C?

MEL G611 : IC FABRICATION TECHNOLOGY 61 BITS Pilani, Hyderabad Campus

Problem
A uniform oxide layer of 0.4μm thickness is selectively etched to expose the
silicon surface in some locations on a wafer surface. A second oxidation at
1000°C in H2O grows 0.2μm on the bare silicon.
(a) Sketch a cross-section of the SiO2 in all locations on the wafer and the
position of the Si/SiO2 interface.
(b) Would your picture be the same if the second oxidation grew the 0.2μm at a
different temperature? Explain.

MEL G611 : IC FABRICATION TECHNOLOGY 62 BITS Pilani, Hyderabad Campus

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Solution

MEL G611 : IC FABRICATION TECHNOLOGY 63 BITS Pilani, Hyderabad Campus

Sec IV, L 8-11: Oxidation


• Sat, 18 Aug; Thu, 23 Aug; Sat, 25 Aug; Tues, 28 Aug

• Learning Objectives
o To understand the Oxidation process during the IC
Fabrication

• Topics covered –
o Oxidation growth mechanisms
o Various techniques
o Properties
o Defects

MEL G611 : IC FABRICATION TECHNOLOGY 64 BITS Pilani, Hyderabad Campus

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Sec V, L 12-14: Lithography


• Thu, 30 Aug; Sat, 1 Sept; Tue, 4 Sept

• Learning Objectives
o Learn how to print the patterns on the wafer using
optical exposure systems

• Topics covered –
o Optical Lithography
o Electron Lithography
o X-ray Lithography
o Ion Lithography

MEL G611 : IC FABRICATION TECHNOLOGY 65 BITS Pilani, Hyderabad Campus

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