74HC4017
74HC4017
74HC4017
DATA SHEET
For a complete data sheet, please also download:
74HC/HCT4017
Johnson decade counter with 10
decoded outputs
Product specification December 1990
File under Integrated Circuits, IC06
Philips Semiconductors Product specification
TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
HC HCT
tPHL/ tPLH propagation delay CP0, CP1 to Qn CL = 15 pF; VCC = 5 V 20 21 ns
fmax maximum clock frequency 77 67 MHz
CI input capacitance 3.5 3.5 pF
CPD power dissipation capacitance per package notes 1 and 2 35 36 pF
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW):
PD = CPD × VCC2 × fi+∑ (CL × VCC2 × fo) where:
fi = input frequency in MHz
fo = output frequency in MHz
∑ (CL × VCC2 × fo) = sum of outputs
CL = output load capacitance in pF
VCC = supply voltage in V
2. For HC the condition is VI = GND to VCC
For HCT the condition is VI = GND to VCC − 1.5 V
ORDERING INFORMATION
See “74HC/HCT/HCU/HCMOS Logic Package Information”.
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Philips Semiconductors Product specification
PIN DESCRIPTION
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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Philips Semiconductors Product specification
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH clock transition
↓ = HIGH-to-LOW clock transition
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AC WAVEFORMS
Fig.7 Waveforms showing the hold and set-up times for CP0 to CP1 and CP1 to CP0.
Conditions:
CP1 = LOW while CP0 is triggered on a LOW-to-HIGH
transition and CP0 = HIGH, while CP1 is triggered on a
HIGH-to-LOW transition.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.8 Waveforms showing the minimum pulse widths for CP0, CP1 and MR inputs; the recovery time for MR and
the propagation delays for MR to Qn and Q5-9 outputs.
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Philips Semiconductors Product specification
Conditions:
CP1 = LOW while CP0 is triggered on a LOW-to-HIGH transition
and CP0 = HIGH, while CP1 is triggered on a HIGH-to-LOW
transition.
(1) HC : VM = 50%; VI = GND to VCC.
HCT: VM = 1.3 V; VI = GND to 3 V.
Fig.9 Waveforms showing the propagation delays for CP0, CP1 to Qn, Q5-9 outputs and the output transition times.
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Philips Semiconductors Product specification
APPLICATION INFORMATION
Some applications for the “4017” are:
• Decade counter with decimal decoding
• 1 out of n decoding counter (when cascaded)
• Sequential controller
• Timer
Figure 10 shows a technique for extending the number of decoded output states for the “4017”. Decoded outputs are
sequential within each stage and from stage to stage, with no dead time (except propagation delay).
Figure 11 shows an example of a divide-by 2 through divide-by 10 circuit using one “4017”. Since “4017” has an
asynchronous reset, the output pulse widths are narrow (minimum expected pulse width is 6 ns). The output pulse widths
can be enlarged by inserting a RC network at the MR input.
PACKAGE OUTLINES
See “74HC/HCT/HCU/HCMOS Logic Package Outlines”.
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