Features

• High-performance, Low-power AVR® 8-bit Microcontroller

– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 8 MIPS Throughput at 8 MHz
– On-chip 2-cycle Multiplier
• Nonvolatile Program and Data Memories
• Self-programming In-System Programmable Flash Memory
– 16K Bytes with Optional Boot Block (256 - 2K Bytes)
Endurance: 1,000 Write/Erase Cycles
– Boot Section Allows Reprogramming of Program Code without External
8-bit
Programmer
– Optional Boot Code Section with Independent Lock Bits
Microcontroller
– 512 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles with 16K Bytes
– 1024 Bytes Internal SRAM
– Programming Lock for Software Security In-System
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode Programmable
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Clock with Separate Oscillator and Counter Mode
Flash
– Three PWM Channels
– 8-channel, 10-bit ADC
– Byte-oriented Two-wire Serial Interface
– Programmable Serial UART
ATmega163
– Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
ATmega163L
– Analog Comparator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator Summary
– External and Internal Interrupt Sources
– Four Sleep Modes: Idle, ADC Noise Reduction, Power-save, and Power-down
• Power Consumption at 4 MHz, 3.0V, 25°C
– Active 5.0 mA
– Idle Mode 1.9 mA
– Power-down Mode < 1 µA
• I/O and Packages
Not Recommend for
– 32 Programmable I/O Lines New Designs. Use
– 40-pin PDIP and 44-pin TQFP
• Operating Voltages ATmega16.
– 2.7 - 5.5V for ATmega163L
– 4.0 - 5.5V for ATmega163
• Speed Grades
– 0 - 4 MHz for ATmega163L
– 0 - 8 MHz for ATmega163

Rev.1142ES–AVR–02/03

Note: This is a summary document. A complete document is

available on our web site at www.atmel.com . 1
Pin Configurations

(SDA)
(SCL)

(SDA)
(SCL)

2 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

Description The ATmega163 is a low-power CMOS 8-bit microcontroller based on the AVR architec-
ture. By executing powerful instructions in a single clock cycle, the ATmega163
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.

Block Diagram Figure 1. Block Diagram

PA0 - PA7 PC0 - PC7

VCC

PORTA DRIVERS PORTC DRIVERS

GND
DATA REGISTER DATA DIR. DATA REGISTER DATA DIR.
PORTA REG. PORTA PORTC REG. PORTC

8-BIT DATA BUS

AVCC

ANALOG MUX ADC

OSCILLATOR
AGND 2-WIRE SERIAL
XTAL1
AREF INTERFACE

INTERNAL
REFERENCE INTERNAL
OSCILLATOR
OSCILLATOR

XTAL2
PROGRAM STACK WATCHDOG TIMING AND
RESET
COUNTER POINTER TIMER CONTROL

PROGRAM MCU CONTROL

SRAM
FLASH REGISTER

INSTRUCTION GENERAL TIMER/

REGISTER PURPOSE COUNTERS
REGISTERS

X
INSTRUCTION INTERRUPT
Y
DECODER UNIT
Z

CONTROL
LINES ALU EEPROM

INTERNAL
STATUS CALIBRATED
REGISTER OSCILLATOR

PROGRAMMING
SPI UART
LOGIC
COMPARATOR
ANALOG

DATA REGISTER DATA DIR. DATA REGISTER DATA DIR.

PORTB REG. PORTB PORTD REG. PORTD
+
-

PORTB DRIVERS PORTD DRIVERS

PB0 - PB7 PD0 - PD7

The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock

3
1142ES–AVR–02/03
 cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATmega163 provides the following features: 16K bytes of In-System Self-Program-
mable Flash, 512 bytes EEPROM, 1024 bytes SRAM, 32 general purpose I/O lines, 32
general purpose working registers, three flexible Timer/Counters with compare modes,
internal and external interrupts, a byte oriented Two-wire Serial Interface, an 8-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, a programmable
serial UART, an SPI serial port, and four software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and inter-
rupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or
Hardware Reset. In Power-save mode, the asynchronous Timer Oscillator continues to
run, allowing the user to maintain a timer base while the rest of the device is sleeping.
The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchro-
nous timer and ADC, to minimize switching noise during ADC conversions.
The On-chip ISP Flash can be programmed through an SPI serial interface or a conven-
tional programmer. By installing a Self-Programming Boot Loader, the microcontroller
can be updated within the application without any external components. The Boot Pro-
gram can use any interface to download the application program in the Application Flash
memory. By combining an 8-bit CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega163 is a powerful microcontroller that provides a
highly flexible and cost effective solution to many embedded control applications.
The ATmega163 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, In-Cir-
cuit Emulators, and evaluation kits.

Pin Descriptions

VCC Digital supply voltage.

GND Digital ground.

Port A (PA7..PA0) Port A serves as the analog inputs to the A/D Converter.
Port A also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used.
Port pins can provide internal pull-up resistors (selected for each bit). The Port A output
buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are
used as inputs and are externally pulled low, they will source current if the internal pull-
up resistors are activated. The Port A pins are tristated when a reset condition becomes
active, even if the clock is not running.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally
pulled low will source current if the pull-up resistors are activated. Port B also serves the
functions of various special features of the ATmega83/163 as listed on page 117. The
Port B pins are tristated when a reset condition becomes active, even if the clock is not
running.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each
bit). The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally
pulled low will source current if the pull-up resistors are activated. The Port C pins are
tristated when a reset condition becomes active, even if the clock is not running.

4 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

Port C also serves the functions of various special features of the ATmega163 as listed
on page 124.

Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors (selected for each
bit). The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally
pulled low will source current if the pull-up resistors are activated. Port D also serves the
functions of various special features of the ATmega163 as listed on page 128. The Port
D pins are tristated when a reset condition becomes active, even if the clock is not
running.

RESET Reset input. A low level on this pin for more than 500 ns will generate a Reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a Reset.

XTAL1 Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

XTAL2 Output from the inverting Oscillator amplifier.

AVCC This is the supply voltage pin for Port A and the A/D Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be con-
nected to VCC through a low-pass filter. See page 105 for details on operation of the
ADC.

AREF AREF is the analog reference input pin for the A/D Converter. For ADC operations, a
voltage in the range 2.5V to AVCC can be applied to this pin.

AGND Analog ground. If the board has a separate analog ground plane, this pin should be con-
nected to this ground plane. Otherwise, connect to GND.

5
1142ES–AVR–02/03
Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
$3F ($5F) SREG I T H S V N Z C 20
$3E ($5E) SPH – – – – – SP10 SP9 SP8 21
$3D ($5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 21
$3C ($5C) Reserved
$3B ($5B) GIMSK INT1 INT0 – – – – – – 30
$3A ($5A) GIFR INTF1 INTF0 – – – – – – 31
$39 ($59) TIMSK OCIE2 TOIE2 TICIE1 OCIE1A OCIE1B TOIE1 – TOIE0 32
$38 ($58) TIFR OCF2 TOV2 ICF1 OCF1A OCF1B TOV1 – TOV0 32
$37 ($57) SPMCR – ASB – ASRE BLBSET PGWRT PGERS SPMEN 140
$36 ($56) TWCR TWINT TWEA TWSTA TWSTO TWWC TWEN – TWIE 82
$35 ($55) MCUCR – SE SM1 SM0 ISC11 ISC10 ISC01 ISC00 34
$34 ($54) MCUSR – – – – WDRF BORF EXTRF PORF 28
$33 ($53) TCCR0 – – – – – CS02 CS01 CS00 41
$32 ($52) TCNT0 Timer/Counter0 (8 Bits) 42
$31 ($51) OSCCAL Oscillator Calibration Register 37
$30 ($50) SFIOR – – – – ACME PUD PSR2 PSR10 40
$2F ($4F) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM11 PWM10 44
$2E ($4E) TCCR1B ICNC1 ICES1 – – CTC1 CS12 CS11 CS10 45
$2D ($4D) TCNT1H Timer/Counter1 – Counter Register High Byte 46
$2C ($4C) TCNT1L Timer/Counter1 – Counter Register Low Byte 46
$2B ($4B) OCR1AH Timer/Counter1 – Output Compare Register A High Byte 47
$2A ($4A) OCR1AL Timer/Counter1 – Output Compare Register A Low Byte 47
$29 ($49) OCR1BH Timer/Counter1 – Output Compare Register B High Byte 47
$28 ($48) OCR1BL Timer/Counter1 – Output Compare Register B Low Byte 47
$27 ($47) ICR1H Timer/Counter1 – Input Capture Register High Byte 48
$26 ($46) ICR1L Timer/Counter1 – Input Capture Register Low Byte 48
$25 ($45) TCCR2 FOC2 PWM2 COM21 COM20 CTC2 CS22 CS21 CS20 52
$24 ($44) TCNT2 Timer/Counter2 (8 Bits) 53
$23 ($43) OCR2 Timer/Counter2 Output Compare Register 54
$22 ($42) ASSR – – – – AS2 TCN2UB OCR2UB TCR2UB 57
$21 ($41) WDTCR – – – WDTOE WDE WDP2 WDP1 WDP0 60
$20 ($40) UBRRHI – – – – UBRR[11:8] 78
$1F ($3F) EEARH – – – – – – – EEAR8 62
$1E ($3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 62
$1D ($3D) EEDR EEPROM Data Register 62
$1C ($3C) EECR – – – – EERIE EEMWE EEWE EERE 63
$1B ($3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 115
$1A ($3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 115
$19 ($39) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 115
$18 ($38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 117
$17 ($37) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 117
$16 ($36) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 117
$15 ($35) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 123
$14 ($34) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 123
$13 ($33) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 123
$12 ($32) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 128
$11 ($31) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 128
$10 ($30) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 128
$0F ($2F) SPDR SPI Data Register 69
$0E ($2E) SPSR SPIF WCOL – – – – – SPI2X 68
$0D ($2D) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 67
$0C ($2C) UDR UART I/O Data Register 74
$0B ($2B) UCSRA RXC TXC UDRE FE OR – U2X MPCM 74
$0A ($2A) UCSRB RXCIE TXCIE UDRIE RXEN TXEN CHR9 RXB8 TXB8 76
$09 ($29) UBRR UART Baud Rate Register 78
$08 ($28) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 102
$07 ($27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 110
$06 ($26) ADCSR ADEN ADSC ADFR ADIF ADIE ADPS2 ADPS1 ADPS0 111
$05 ($25) ADCH ADC Data Register High Byte 112
$04 ($24) ADCL ADC Data Register Low Byte 112
$03 ($23) TWDR Two-wire Serial Interface Data Register 84
$02 ($22) TWAR TWA6 TWA5 TWA4 TWA3 TWA2 TWA1 TWA0 TWGCE 85
$01 ($21) TWSR TWS7 TWS6 TWS5 TWS4 TWS3 – – – 84

6 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

Register Summary (Continued)

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
$00 ($20) TWBR Two-wire Serial Interface Bit Rate Register 82
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.

7
1142ES–AVR–02/03
Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← $FF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← $00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • ($FF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← $FF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
BRANCH INSTRUCTIONS
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
JMP k Direct Jump PC ← k None 3
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
CALL k Direct Subroutine Call PC ← k None 4
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

8 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

Instruction Set Summary (Continued)

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
DATA TRANSFER INSTRUCTIONS
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr+1:Rr None 1
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (Z) ← R1:R0 None -
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
BIT AND BIT-TEST INSTRUCTIONS
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C←1 C 1
CLC Clear Carry C←0 C 1
SEN Set Negative Flag N←1 N 1
CLN Clear Negative Flag N←0 N 1
SEZ Set Zero Flag Z←1 Z 1
CLZ Clear Zero Flag Z←0 Z 1
SEI Global Interrupt Enable I←1 I 1
CLI Global Interrupt Disable I←0 I 1
SES Set Signed Test Flag S←1 S 1
CLS Clear Signed Test Flag S←0 S 1
SEV Set Twos Complement Overflow. V←1 V 1
CLV Clear Twos Complement Overflow V←0 V 1
SET Set T in SREG T←1 T 1
CLT Clear T in SREG T←0 T 1
SEH Set Half Carry Flag in SREG H←1 H 1

9
1142ES–AVR–02/03
Instruction Set Summary (Continued)
CLH Clear Half Carry Flag in SREG H←0 H 1
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1

10 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

Ordering Information
Speed (MHz) Power Supply Ordering Code Package Operation Range
4 2.7 - 5.5V ATmega163L-4AC 44A Commercial
ATmega163L-4PC 40P6 (0°C to 70°C)
ATmega163L-4AI 44A Industrial
ATmega163L-4PI 40P6 (-40°C to 85°C)
8 4.0 - 5.5V ATmega163-8AC 44A Commercial
ATmega163-8PC 40P6 (0°C to 70°C)
ATmega163-8AI 44A Industrial
ATmega163-8PI 40P6 (-40°C to 85°C)

Package Type
44A 44-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)
40P6 40-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP)

11
1142ES–AVR–02/03
Packaging Information

44A

PIN 1
B
PIN 1 IDENTIFIER

e E1 E

D1
D

C 0˚~7˚

A1 A2 A
L
COMMON DIMENSIONS
(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable E1 9.90 10.00 10.10 Note 2
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum B 0.30 – 0.45
plastic body size dimensions including mold mismatch.
C 0.09 – 0.20
3. Lead coplanarity is 0.10 mm maximum.
L 0.45 – 0.75
e 0.80 TYP

10/5/2001
TITLE DRAWING NO. REV.
2325 Orchard Parkway
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
R San Jose, CA 95131 44A B
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

12 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

40P6

D
PIN
1

E1

SEATING PLANE

A1
L
B
B1
e

COMMON DIMENSIONS
0º ~ 15º REF (Unit of Measure = mm)
C
SYMBOL MIN NOM MAX NOTE

eB A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559

Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC. B1 1.041 – 1.651
2. Dimensions D and E1 do not include mold Flash or Protrusion. L 3.048 – 3.556
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP

09/28/01
TITLE DRAWING NO. REV.
2325 Orchard Parkway
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual 40P6 B
R San Jose, CA 95131 Inline Package (PDIP)

13
1142ES–AVR–02/03
Erratas

ATmega163(L) Errata • Increased Interrupt Latency

Rev. F • Interrupts Abort TWI Power-down
• TWI Master Does not Accept Spikes on Bus Lines
• TWCR Write Operations Ignored
• PWM not Phase Correct
• TWI is Speed Limited in Slave Mode

6. Increased Interrupt Latency

In this device, some instructions are not interruptable, and will cause the interrupt
latency to increase. The only practical problem concerns a loop followed by a two-
word instruction while waiting for an interrupt. The loop may consist of a branch
instruction or an absolute or relative jump back to itself like this:
loop: rjmp loop
<Two-word instruction>
In this case, a dead-lock situation arises.
Problem Fix/Workaround
In assembly, insert a nop instruction immediately after a loop to itself. The problem
will normally be detected during development. In C, the only construct that will give
this problem is an empty “for” loop; “for(;;)”. Use “while(1)” or “do{} while (1)” to avoid
the problem.

5. Interrupts Abort TWI Power-down

TWI Power-down operation may be aborted by other interrupts. If an interrupt (e.g.,
INT0) occurs during TWI Power-down address watch and wakes the CPU up, the
TWI aborts operation and returns to its idle state.
Problem Fix/Workaround
Ensure that the TWI Address Match is the only enabled interrupt when entering
Power-down.

4. TWI Master Does not Accept Spikes on Bus Lines

When the part operates as Master, and the bus is idle (SDA = 1; SCL = 1), generat-
ing a short spike on SDA (SDA = 0 for a short interval), no interrupt is generated,
and the status code is still $F8 (idle). But when the software initiates a new start
condition and clears TWINT, nothing happens on SDA or SCL, and TWINT is never
set again.
Problem Fix/Workaround
Either of the following:
1. Ensure that no spikes occur on SDA or SCL lines.
2. Receiving a valid START condition followed by a STOP condition provokes a
bus error reported as a TWI interrupt with status code $00.
3. In a Single Master systems, the user should write the TWSTO bit immedi-
ately before writing the TWSTA bit.

3. TWCR Write Operation Ignored

Repeated write to TWCR must be delayed. If a write operation to TWCR is immedi-
ately followed by another write operation to TWCR, the first write operation may be
ignored.

14 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

Problem Fix/Workaround
Ensure at least one instruction (e.g., nop) is executed between two writes to TWCR.

2. PWM not Phase Correct

In Phase-correct PWM mode, a change from OCRx = TOP to anything less than
TOP does not change the OCx output. This gives a phase error in the following
period.
Problem Fix/Workaround
Make sure this issue is not harmful to the application.

1. TWI is Speed Limited in Slave Mode

When the two-wire Serial Interface operates in Slave mode, frames may be unde-
tected if the CPU frequency is less than 64 times the bus frequency.
Problem Fix/Workaround
Ensure that the CPU frequency is at least 64 times the TWI bus frequency.

15
1142ES–AVR–02/03
Change Log This section containes a log on the changes made to the data sheet for ATmega163. All
refereces to pages in Change Log, are referred to this document.

Changes from Rev. 1. Added “Not Recommend for New Designs. Use ATmega16.”.
1142C-09/01 to Rev.
1142D-09/02

Changes from Rev. 1. Updated Table 52, “Boot Reset Fuse,” on page 136.
1142D-09/09 to Rev.
1142E-02/03 2. Corrected pin numbers in Figure 62 on page 113.

3. Corrected a constant in the Boot Loader code example on page 141.

4. Changed max bit rate for the TWI from 400 kHz to 217 kHz.

5. Removed redundant and harmful loop in a code example for Slave Receiver
mode for the TWI on page 96.

6. Added AGND and AVCC in Figure 81 on page 145 and Figure 86 on page 154.

7. Updated the “Packaging Information” on page 12.

8. Added “Erratas” on page 14.

16 ATmega163(L)
1142ES–AVR–02/03
 ATmega163(L)

17
1142ES–AVR–02/03
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1142ES–AVR–02/03 0M