Pipelining: Dr. Souvik Sinha
Pipelining: Dr. Souvik Sinha
An inter-stage storage buffer, B1, is needed to hold the information being passed from
one stage to the next. New information is loaded into this buffer at the end of each
clock cycle.
How Pipelining Works ?
A 4-Stage Pipelining
• A pipelined processor may process each instruction in four
steps, as follows:
Fetch (F) : read the instruction from the memory.
Decode (D) : decode the instruction and fetch the source
operand(s).
Execute (E) : perform the operation specified by the
instruction.
Write (W) : store the result in the destination location.