INTERRUPT INTERFACE

OF THE 8088 AND 8086

MICROPROCESSOR

INTERRUPT INTERFACE OF THE

8088 AND 8086 MICROPROCESSOR

11.1 Interrupt Mechanism, Types and Priority

11.2 Interrupt Vector Table
11.3 Interrupt Instructions
11.4 Enabling/Disabling of Interrupts
11.5 External Hardware-Interrupt Interface
Signals
11.6 External Hardware-Interrupt Sequence

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1
INTERRUP INTERFACE OF THE 8088
AND 8086 MICROPROCESSOR

11.7 82C59A Programmable Interrupt

Controller
11.8 Interrupt Interface Circuits Using the
82C59A
11.9 Software Interrupts
11.10 Nonmaskable Interrupt
11.11 Reset
11.12 Internal Interrupt Function
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11.1 Interrupt Mechanism, Types and

Priority
„ Interrupts provide a mechanism for quickly changing
program environment. Transfer of program control is
initiated by the occurrence of either an event internal
to the MPU or an event in its external hardware.
„ The section of program to which control is passed is
called the interrupt service routine.
„ The 8088 and 8086 microprocessor are capable of
implementing any combination of up to 256 interrupts.
„ Interrupts are divided into five groups:
™ External hardware interrupts
™ Nonmaskable interrupts
™ Software interrupts
™ Internal interrupts
™ reset
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11.1 Interrupt Mechanism, Types and
Priority
„ Interrupt program context switching
mechanism

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11.1 Interrupt Mechanism, Types and

Priority
„ Hardware, software, and internal interrupts are
serviced on a priority basis.
„ Each interrupts is given a different priority level by
assigning it a type number. Type 0 identifies the
highest-priority interrupt, and type 255 identifies the
lowest-priority interrupt.
„ Tasks that must not be interrupted frequently are
usually assigned to higher-priority levels and those
that can be interrupted to lower-priority levels.
„ Once an interrupt service routine is initiated, it could
be interrupted only by a function that corresponds to
a higher-priority level.
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11.1 Interrupt Mechanism, Types and
Priority
„ Types of interrupts and their priority

Increasing priority

Reset
Internal interrupts and exceptions
Software interrupts
Nonmaskable interrupts
External hardware interrupts

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11.2 Interrupt Vector Table

„ An address pointer table is used to link the interrupt
type numbers to the locations of their service routines
in the program-storage memory.
„ The address pointer table contains 256 address
pointers (vectors), which are identified as vector 0
through vector 255. One pointer corresponds to each
of the interrupt types 0 through 255.
„ The address pointer table is located at the low-
address end of the memory address space. It starts
at 0000016 and ends at 003FE16. This represents the
first 1 Kbytes of memory.

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11.2 Interrupt Vector Table
„ Interrupt vector table of the 8088/8086

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11.2 Interrupt Vector Table

EXAMPLE
At what address are CS50 and IP50 stored in memory?
Solution:
Each vector requires four consecutive bytes of memory for
storage. Therefore, its address can be found by multiplying the type
number by 4. Since CS50 and IP50 represent the words of the type
50 interrupt pointer, we get
Address = 4 x 50 = 200
converting to binary form gives
Address = 110010002 = C816
Therefore, IP50 is stored at 000C816 and CS50 at 000CA16.

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11.3 Interrupt Instructions
Mnemonic Meaning Format Operation Flags affected
CLI Clear interrupt flag CLI 0 → (IF) IF
STI Set interrupt flag STI 1 → (IF) IF
INT n Type n software INT n (Flags) → ((SP)-2) TF, IF
interrupt 0 → TF, IF
(CS) → ((SP) – 4)
(2+4xn) → (CS)
(IP) → ((SP) – 6 )
(4xn) → (IP)
IRET Interrupt return IRET ((SP)) → (IP) All
((SP)+2) →(CS)
((SP)+4) →(Flags)
(SP) + 6 → (SP)
INTO Interrupt on overflow INTO INT 4 steps TF, IF
HLT Halt HLT Wait for an external None
interrupt or reset to occur
WAIT Wait WAIT Wait for TEST input to go
active

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11.4 Enabling/Disabling of Interrupts

„ An interrupt-enable flag bit (IF) is provided within
the 8088/8086 MPUs.
„ The ability to initiate an external hardware interrupt at
the INTR input is enabled by setting IF or masked out
by resetting it. Executing the STI or CLI instructions,
respectively, does this through software.
„ During the initiation sequence of a service routine for
an external hardware interrupt, the MPU
automatically clears IF. This masks out the
occurrence of any additional external hardware
interrupts.

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11.5 External Hardware-Interrupt
Interface Signals
„ Minimum-mode interrupt interface
™Key interrupt interface signals: INTR and INTA

Minimum-mode 8088 and 8086 system external hardware interrupt interface

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11.5 External Hardware-Interrupt

Interface Signals
„Maximum-mode interrupt interface
™ 8288 bus controller is added in the interface. The INTA and ALE
signals are produced by the 8288.
™ The bus priority lock signal LOCK is also added. This signal
ensures that no other device can take over control of the system
bus until the interrupt-acknowledge bus cycle is completed.

Maximum-mode 8088 and 8086 system external hardware interrupt interface

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11.5 External Hardware-Interrupt
Interface Signals
„Maximum-mode interrupt interface

Interrupt bus status code to the 8288 bus controller

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11.6 External Hardware-Interrupt

Sequence
COMPLETE CURRENT
INSTRUCTION

YES
INTERNAL
INTERRUPT?
NO
YES
NMI

NO
YES 1
ACKNOWLEDGE READ TYPE
INTR IF
INTERRUPT NUMBER
NO 0

1 COMPLET CURRENT
TF INSTRUCTION
0

EXECUTE NEXT LET TEMP = TF

INSTRUCTION

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11.6 External Hardware-Interrupt
Sequence
CLEAR IF & TF

PUSH CS & IP

CALL INTERRUPT
SERVICE ROUTINE

EXECUTE USER
INTERRUPT ROUTINE

POP IP & CS

POP FLAGS
Flow chart of the interrupt
processing sequence of the 8088 RESUME INTERRUPT
PROCEDURE
and 8086 microprocessor

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11.6 External Hardware-Interrupt

Sequence
„Interrupt-acknowledge bus cycle

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11.6 External Hardware-Interrupt
Sequence
„Interrupt service routine
PUSH XX
To save registers and PUSH YY
parameters on the stack
PUSH ZZ
.
.
Main body of the .
service routine .
.

To restore register and

POP ZZ
parameters from the stack POP YY
POP XX
Return to main program IRET
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11.6 External Hardware-Interrupt

Sequence
EXAMPLE
The circuit in the next slide is used to count interrupt requests.
The interrupting device interrupts the microprocessor each time the
interrupt-request input signal transitions from 0 to 1. The
corresponding interrupt type number generated by the 74LS244 is
60H.
a. Describe the hardware operation for an interrupt request.
b. What is the value of the type number sent to the microprocessor?
c. Assume that (CS)=(DS)=1000H and (SS)=4000H; the main
program is located at offsets of 200H; the count is held at 100H; the
interrupt-service routine starts at offset 1000H from the beginning
of another code segment at 2000H:0000H; and the stack starts at
an offset of 500H from the stack segment. Make a map showing
the memory address space.
d. Write the main program and the service routine.

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11.6 External Hardware-Interrupt
Sequence
EXAMPLE

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11.6 External Hardware-Interrupt

Sequence
Solution:
a. A positive transition at the CLK input of the flip-flop (interrupt
request) make the Q output of the flip-flop logic 1 and presents
a positive level signal at the INTR input of the 8088. When
8088 recognized this as an interrupt request, it responds by
generating the INTA signal. The logic 0 output on the line
clears the flip-flop and enables the 74LS244 buffer to present
the type number to the 8088. This number is read of the data
bus by the 8088 and is used to initiate the interrupt-service
routine.
b. From the inputs and outputs of the 74LS244, we see the type
number is
AD7…AD1AD0 = 2Y42Y32Y22Y11Y41Y31Y21Y1 = 011000002
AD7…AD1AD0 = 60H
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11.6 External Hardware-Interrupt
Sequence
Solution:
c. The memory organization is
in the right figure

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11.6 External Hardware-Interrupt

Sequence
Solution:
d. The flowcharts of the main program and interrupt-service routine
Main Program SRVRTN
Set up data segment,
Save processor
stack segment, and
status
stack pointer

Set up the Increment

interrupt vector the count

Enable Restore processor

interrupts status

Wait for
Return
interrupt

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11.6 External Hardware-Interrupt
Sequence
Solution:

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11.7 82C59A Programmable Interrupt

Controller
„ The 82C59A is an LSI peripheral IC that is designed
to simplify the implementation of the interrupt
interface in the 8088- and 8086-based
microcomputer system.
„ The 82C59A is known as a programmable interrupt
controller or PIC.
„ The operation of the PIC is programmable under
software control.
„ The 82C59A can be cascaded to expand from 8 to 64
interrupt inputs.

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11.7 82C59A Programmable Interrupt
Controller
„ Block diagram of the 82C59A

Block diagram and pin layout of the 82C59A

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11.7 82C59A Programmable Interrupt

Controller
„ Internal architecture of the 82C59A

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11.7 82C59A Programmable Interrupt
Controller
„ Internal architecture of the 82C59A
™Eight functional parts of the 82C59A
• The data bus buffer
• The read/write logic
• The control logic
• The in-service register
• The interrupt-request register
• The priority resolver
• The interrupt-mask register
• The cascade buffer/comparator

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11.7 82C59A Programmable Interrupt

Controller
„ Programming the 82C59A
™ Two types of command words are provided to program the
82C59A: the initialization command words (ICW) and the
operational command words (OCW).
™ ICW commands (ICW1, ICW2, ICW3, ICW4) are used to load
the internal control registers of the 82C59A to define the
basic configuration or mode in which it is used.
™ The OCW commands (OCW1, OCW2, OCW3) permit the
8088 or 8086 microprocessor to initiate variations in the
basic operating modes defined by the ICW commands.
™ The MPU issues commands to the 82C59A by initiating
output (I/O-mapped) or write (Memory-mapped) cycles.

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11.7 82C59A Programmable Interrupt
Controller
„ Programming the 82C59A
ICW1

ICW2

NO (SNGL=1)
IN CASCADE
MODE ?
YES (SNGL=0)

ICW3

NO (IC4=0) IS ICW4
NEEDED ?
YES (IC4=1)

ICW4
Initialization sequence of
the 82C59A
READY TO ACCEPT
INTERRUPT REQUESTS
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11.7 82C59A Programmable Interrupt

Controller
„ Initialization command words
™ICW1

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11.7 82C59A Programmable Interrupt
Controller
EXAMPLE
What value should be written into ICW1 in order to configure the
82C59A so that ICW4 is needed in the initialization sequence, the
system is going to use multiple 82C59As, and its inputs are to be
level sensitive? Assume that all unused bits are to be logic 0.
Solution:
Since ICW4 is to be initialized, D0 must be logic 1, D0 = 1
For cascaded mode of operation, D1 must be 0, D1 = 0
And for level-sensitive inputs, D3 must be 1, D3 = 1
Bits D2 and D5 through D7 are don’t-care states and are 0.
D2 = D5 = D6 = D7 = 0
Moreover, D4 must be fixed at the 1 logic level, D4 = 1
This gives the complete command word
D7D6D5D4D3D2D1D0 = 000110012 = 1916
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11.7 82C59A Programmable Interrupt

Controller
„ Initialization command words
™ICW2 is used for type number determination

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11.7 82C59A Programmable Interrupt
Controller
EXAMPLE
What should be programmed into register ICW2 if the type
numbers output on the bus by the device are to range from F016
through F716?

Solution:
To set the 82C59A up so that type numbers are in the range of F016
through F716, its device code bits must be
D7D6D5D4D3 = 111102
The lower three bits are don’t-care states and all can be 0s. This
gives the word
D7D6D5D4D3D2D1D0 = 111100002 = F016

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11.7 82C59A Programmable Interrupt

Controller
„ Initialization command words
™ICW3 is required only for cascaded mode of
operation

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11.7 82C59A Programmable Interrupt
Controller
EXAMPLE
Assume that a master PIC is to be configured so that its IR0
through IR3 inputs are to accept inputs directly from external devices,
but IR4 through IR7 are to be supplied by the INT outputs of slaves.
What code should be used for the initialization command word ICW3?
Solution:
For IR0 through IR3 to be configured to allow direct inputs from
external devices, bits D0 through D3 of ICW3 must be logic 0:
D3D2D1D0 = 00002
The other IR inputs of the master are to be supplied by INT outputs
of slaves. Therefore, their control bits must be all 1:
D7D6D5D4 = 11112
This gives the complete command word
D7D6D5D4D3D2D1D0 = 111100002 = F016

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11.7 82C59A Programmable Interrupt

Controller
„ Initialization command words
™ ICW4 is used to configure device for use with the 8088 or
8086 and selects various features in its operation.

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11.7 82C59A Programmable Interrupt
Controller
„ Operational command words
™OCW1 is used to access the contents of the
interrupt-mask register (IMR). Setting a bit to logic
1 masks out the associated interrupt input.

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11.7 82C59A Programmable Interrupt

Controller
EXAMPLE
What should be the OCW1 code if interrupt inputs IR0 through
IR3 are to be masked and IR4 through IR7 are to be unmasked?
Solution:
For IR0 through IR3 to be masked, their corresponding bits in the
mask register must be make logic 1:
D3D2D1D0 = 11112
On the other hand, for IR4 through IR7 to be unmasked, D4 through
D7 must be logic 0:
D7D6D5D4 = 00002
This gives the complete command word
D7D6D5D4D3D2D1D0 = 000011112 = 0F16

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11.7 82C59A Programmable Interrupt
Controller
„ Operational command words
™ OCW2 is used to select appropriate priority scheme and
assigns an IR level for the scheme.

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11.7 82C59A Programmable Interrupt

Controller
EXAMPLE
What OCW2 must be issued to the 82C59A if the priority
scheme rotate on nonspecific EOI command is to be selected?

Solution:
To enable the rotate on nonspecific EOI command priority scheme,
bits D7 through D5 must be set to 101. Since a specific level does
not have to be considered, the rest of the bits in the command word
can be 0. This gives OCW2 as

D7D6D5D4D3D2D1D0 = 101000002 = A016

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11.7 82C59A Programmable Interrupt
Controller
„ Operational command words
™ OCW3 permits reading of the contents of the ISR or IRR
registers through software.

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11.7 82C59A Programmable Interrupt

Controller
EXAMPLE
Write a program that will initialize an 82C59A with the
initialization command words ICW1, ICW2, ICW3 derived in the
previous examples, and ICW4 is equal to 1F16. Assume that the
82C59A resides at address A00016 in the memory address space.
Solution:
Since the 82C59A resides in the memory address space, we can
use a series of move instructions to write the initialization command
words into its registers. Note that the memory address for an ICW is
A00016 if A0 = 0, and it is A00116 if A0 = 1. However, before doing
this, we must first disable interrupts. This is done with the instruction

CLI ; Disable interrupts

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11.7 82C59A Programmable Interrupt
Controller
Next we will create a data segment starting at address 0000016:
MOV AX, 0 ;Create a data segment at 00000H
MOV DS, AX
Now we are ready to write the command words to the 82C59A:
MOV AL, 19H ;Load ICW1
MOV [0A000H], AL ;Write ICW1 to 82C59A
MOV AL, 0F0H ;Load ICW2
MOV [0A001H], AL ;Write ICW2 to 82C59A
MOV AL, 0F0H ;Load ICW3
MOV [0A001H], AL ;Write ICW3 to 82C59A
MOV AL, 1FH ;Load ICW4
MOV [0A001H], AL ;Write ICW4 to 82C59A
Initialization is now complete and the interrupts can be enabled
STI ;Enable interrupts
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11.8 Interrupt Interface Circuits Using

the 82C59A

Minimum-mode interrupt interface for the 8088 microcomputer using the 82C59A

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11.8 Interrupt Interface Circuits Using
the 82C59A

Minimum-mode interrupt interface for the 8086 microcomputer using the 82C59A

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11.8 Interrupt Interface Circuits Using

the 82C59A
„ For applications that require more than eight
interrupt-request inputs, several 82C59As are
connected into a master/slave configuration.

Master/slave connection of the 82C59A interface

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11.8 Interrupt Interface Circuits Using
the 82C59A

Maximum-mode interrupt interface for the 8088 microcomputer using the 82C59A

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11.8 Interrupt Interface Circuits Using

the 82C59A
EXAMPLE
Analyze the circuit in the following figure and write an
appropriate main program and a service routine that counts as a
decimal number the positive edges of the clock signal applied to the
IR0 input of the 82C59A.

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11.8 Interrupt Interface Circuits Using
the 82C59A
Solution:
Lets first determine the I/O addresses of the 82C59A registers:
A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1A0
= 11111111000000002 for A1 = 0, M/IO = 0 and
= 11111111000000102 for A1 = 1, M/IO = 0
These two I/O addresses are FF00H and FF02H, respectively. The
address FF00H is for the ICW1 and FF02H is for the ICW2, ICW3,
ICW4, and OCW1 command words.
The command words are:
ICW1 = 000100112 = 13H
ICW2 = 010010002 = 48H
ICW3 = not needed
ICW4 = 000000112 = 03H
OCW1 = 111111102 = FEH
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11.8 Interrupt Interface Circuits Using

the 82C59A
Software organization:

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11.8 Interrupt Interface Circuits Using
the 82C59A
Flowcharts of the main program and service routine:
Main Program SRV72
Set up data segment,
Save processor
stack segment, and
status
stack pointer

Set up the Increment

interrupt vector the count

Initialize Restore processor

82C59A status

Enable interrupts Return

Wait for
interrupt

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11.8 Interrupt Interface Circuits Using

the 82C59A
Program:
;MAIN PROGRAM
CLI ;Start with interrupt disabled
START: MOV AX, 0 ;Extra segment at 00000H
MOV ES, AX
MOV AX, 1000H ;Data segment at 01000H
MOV DS, AX
MOV AX, 0FF00H ;Stack segment at 0FF00H
MOV SS, AX
MOV SP, 100H ;Top of stack at 10000H

MOV AX, OFFSET SRV72 ;Get offset for SRV72

MOV [ES:120H], AX ;Set up the IP
MOV AX, SEG SRV72 ;Get CS for the service routine
MOV [ES:122H], AX ;Set up the CS

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11.8 Interrupt Interface Circuits Using
the 82C59A
Program:

MOV DX, 0FF00H ;ICW1 address

MOV AL, 13H ;Edge trig input, single 8259A
OUT DX, AL
MOV DX, 0FF02H ;ICW2, ICW4, OCW1 address
MOV AL, 48H ;ICW2, type 72
OUT DX, AL
MOV AL, 03H ;ICW4, AEOI, nonbuf mode
OUT DX, AL
MOV AL, 0FEH ;OCW1, mask all but IR0
OUT DX, AL
STI ;Enable the interrupts

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11.8 Interrupt Interface Circuits Using

the 82C59A
Program:

SRV72: PUSH AX ;Save register to be used

MOV AL, [COUNT] ;Get the count
INC AL ;Increment the count
DAA ;Decimal adjust the count
MOV [COUNT], AL ;Save the new count
POP AX ;Restore the register used
IRET ;Return from interrupt

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11.9 Software Interrupts
„ The 8088 and 8086 microcomputer systems are
capable of implementing up to 256 software
interrupts.
„ The INT n instruction is used to initiate a software
interrupt. The software interrupt service routine
vectors are also located in the memory locations in
the vector table.
„ Software interrupts are of higher priority than the
external interrupts and are not masked out by IF.
„ The software interrupts are actually vectored
subroutine calls.

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11.10 Nonmaskable Interrupt

„ The nonmaskable interrupt (NMI) is initiated from external
hardware.
„ Differences between NMI and other external interrupts:
™ NMI can not be masked out with the interrupt flag.
™ Request for NMI service are signaled to the 8088/8086
microprocessor by applying logic 1 at the NMI input, not the
INTR input.
™ NMI input is positive edge-triggered. Therefore, a request for
NMI is automatically latched internal to the MPU.
„ NMI automatically vectors from the type 2 vector location
in the pointer table (000816 ~000A16)
„ Typically, the NMI is assigned to hardware events that
must be responded to immediately, such power failure.
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11.11 Reset
„ The RESET input of the 8088 and 8086
microprocessors provides a hardware means for
initializing the microcomputer.

Reset interface and timing sequence of the 8088

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11.11 Reset
„ 　

8088 signal status 8086 signal status

Bus and control signal status of the 8088/8086 during system reset
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11.11 Reset
„ When the MPU recognizes the RESET input, it
initiates its internal initialization routine. At completion
of initialization, the flags are all cleared, the registers
are set to the values in the following table.
CPU COMPONENT CONTENT
Flags Clear
Instruction pointer 0000H
CS Register FFFFH
DS Register 0000H
SS Register 0000H
ES Register 0000H
Queue Empty
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11.11 Reset
„ The external hardware interrupts are disabled after
the initialization.
„ Program execution begins at address FFFF016 after
reset. This storage location contains an instruction
that will cause a jump to the startup (boot-strap)
program that is used to initialize the reset of the
microcomputer system’s resources, such as I/O ports,
the interrupt flag, and data memory.
„ After the system-level initialization is complete,
another jump can be performed to the starting point
of the microcomputer’s operating system or
application program.
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11.12 Internal Interrupt Functions
„ Four of the 256 interrupts of the 8088 and 8086 are
dedicated to internal interrupt functions.
„ Internal interrupts differ from external hardware
interrupts in that they occur due to the result of
executing an instruction, not an event that takes
place in external hardware.
„ Internal interrupts are not masked out with IF flag.
„ Internal interrupts of the 8088 and 8086 MPU:
™ Divide error (Type number 0)
™ Single step (Type number 1)
™ Breakpoint interrupt (Type number 3)
™ Overflow error (Type number 4)
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11.12 Internal Interrupt Functions

„ Internal interrupt vector locations

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